TI TPA3003D2

SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
FEATURES
D 3-W/Ch Into an 8-Ω Load From 12-V Supply
D Efficient, Class-D Operation Eliminates
Heatsinks and Reduces Power Supply
Requirements
32-Step DC Volume Control From −40 dB
to 36 dB
Third Generation Modulation Techniques
− Replaces Large LC Filter With Small
Low-Cost Ferrite Bead Filter
Thermal and Short-Circuit Protection
Stereo speaker volume is controlled with a dc voltage
applied to the volume control terminal offering a range
of gain from –40 dB to 36 dB.
D
APPLICATIONS
D LCD Monitors and TVs
D Powered Speakers
10 µF
Cs
0.1 µF
Cs
0.1 µF
PVCCR
PVCCR
PGNDR
ROUTN
PGNDR
PVCCR
NC
LINN
MUTE CONTROL
AVCC
Cs
0.1 µF
Cvcc
10 µF
NC
TPA3003D2
AVDDREF
FADE
AGND
COSC
AGND
ROSC
VOLUME
AGND
REFGND
VCLAMPL
Cs
Cbs
10 nF
PVCC
0.1 µF
PVCCL
AVDD
PVCCL
VREF
BSLN
VOLUME
LINP
LOUTP
1 µF
AVCC
LOUTP
LINN
1 µF Clinn
V2P5
PGNDL
LINP
Clinp 1 µF
1 µF
MUTE
RINP
PGNDL
C2p5
Ccpr
VCLAMPR
RINN
LOUTN
1 µF
Cbs
NC
LOUTN
Crinp 1 µF
10 nF
Cs
SD
PVCCL
RINP
ROUTN
BSRN
RINN
Crinn
PVCCL
SYSTEM CONTROL
PVCCR
Cs
PVCC
ROUTP
Cbs
10 µF
ROUTP
PVCC
10 nF
BSRP
D
The TPA3003D2 is a 3-W (per channel) efficient,
Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3003D2 can drive stereo speakers
as low as 8 Ω. The high efficiency of the TPA3003D2
eliminates the need for external heatsinks when playing
music.
BSLP
D
DESCRIPTION
AVDD
Cvdd
Cosc
100 nF
220 pF
SYSTEM CONTROL
Rosc
120 kΩ
Ccpl
1 µF
Cs
0.1 µF
Cs
Cs
10 µF
10 µF
Cbs
10 nF
PVCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
Copyright  2003, Texas Instruments Incorporated
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1
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
AVAILABLE OPTIONS
PACKAGED DEVICE
48-PIN TQFP (PFB)†
TA
−40°C to 85°C
TPA3003D2PFB
† The PFB package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3003D2PFBR).
PHP PACKAGE
2
PVCCR
41 40 39 38
37
ROUTP
BSRP
43 42
ROUTP
PGNDR
PGNDR
ROUTN
ROUTN
46 45 44
PVCCR
48 47
PVCCR
PVCCR
BSRN
(TOP VIEW)
SD
1
36
VCLAMPR
RINN
2
35
NC
RINP
3
34
MUTE
V2P5
4
33
AVCC
LINP
5
32
NC
LINN
6
31
NC
AVDDREF
7
30
FADE
VREF
8
29
AVDD
AGND
9
28
COSC
AGND
10
27
ROSC
VOLUME
11
26
AGND
REFGND
12
25
VCLAMPL
24
BSLP
PVCCL
LOUTP
PVCCL
PGNDL
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LOUTP
PVCCL
PGNDL
20 21 22 23
LOUTN
18 19
LOUTN
15 16 17
PVCCL
13 14
BSLN
TPA3003D2
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
functional block diagram
V2P5
PVCC
V2P5
VClamp
Gen
VCLAMPR
BSRN
PVCCR(2)
Gate
Drive
RINN
ROUTN(2)
PGNDR
BSRP
PVCCR(2)
Deglitch &
Gain
Adj.
Modulation
Logic
RINP
V2P5
Gate
Drive
VREF
VOLUME
Gain
Control
FADE
PGNDR
To Gain Adj.
Blocks
REFGND
Short Circuit
Detect
V2P5
ROSC
Ramp
Generator
Biases
Startup
Protection
Logic
&
COSC
References
AVDDREF
ROUTP(2)
Thermal
VDD
VDDok
AVCC
AVDD
VCCok
AVDD
5V LDO
PVCC
TTL Input
Buffer
SD
AVCC
AGND
VClamp
Gen
VCLAMPL
MUTE
BSLN
PVCCL(2)
Gate
Drive
Cint2
V2P5
LINN
Gain
Adj.
PGNDL
BSLP
PVCCL(2)
Deglitch &
Rfdbk2
Modulation
Logic
LINP
LOUTN(2)
Rfdbk2
Gate
Drive
Cint2
LOUTP(2)
PGNDL
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3
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
Terminal Functions
TERMINAL
NO.
NAME
AGND
9, 10, 26
AVCC
AVDD
AVDDREF
BSLN
BSLP
I/O
DESCRIPTION
−
Analog ground for digital/analog cells in core
33
−
High-voltage analog power supply (8.5 V to 14 V)
29
O
5-V Regulated output
7
O
5-V Reference output—provided for connection to adjacent VREF terminal.
13
I/O
Bootstrap I/O for left channel, negative high-side FET
24
I/O
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
I/O
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
I/O
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
FADE
30
I
Input for controlling volume ramp rate when cycling SD or during power-up. A logic low on this pin places
the amplifier in fade mode. A logic high on this pin allows a quick transition to the desired volume setting.
LINN
6
I
Negative differential audio input for left channel
LINP
5
I
Positive differential audio input for left channel
LOUTN
16, 17
O
Class-D 1/2-H-bridge negative output for left channel
LOUTP
20, 21
O
Class-D 1/2-H-bridge positive output for left channel
MUTE
34
I
A logic high on this pin disables the outputs. A low on this pin enables the outputs.
NC
31, 32,
35
−
Not internally connected
PGNDL
18, 19
−
Power ground for left channel H-bridge
PGNDR
42, 43
−
Power ground for right channel H-bridge
PVCCL
14, 15
−
Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or
AVCC.
PVCCL
22, 23
−
Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or
AVCC.
PVCCR
38,39
−
PVCCR
46, 47
−
REFGND
12
−
Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or
AVCC.
Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or
AVCC.
Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
RINP
3
I
Positive differential audio input for right channel
RINN
2
I
Negative differential audio input for right channel
ROSC
27
I/O
Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN
44, 45
O
Class-D 1/2-H-bridge negative output for right channel
ROUTP
40, 41
O
Class-D 1/2-H-bridge positive output for right channel
SD
1
I
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VCLAMPL
25
−
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
−
Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME
11
I
DC voltage that sets the gain of the amplifier.
VREF
8
I
Analog reference for gain control section.
V2P5
4
O
2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended
inputs.
4
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: AVCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V
Input voltage range, VI: MUTE, VREF, VOLUME, FADE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5.5 V
SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
RINN, RINP, LINN, LINP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Supply current,
AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
AVDDREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
PFB
TA ≤ 25°C
2.8 W
DERATING FACTOR
22.2 mW/°C
TA = 70°C
1.8 W
TA = 85°C
1.4 W
recommended operating conditions
Supply voltage, VCC
Volume reference voltage
PVCC, AVCC
VREF
Volume control pins, input voltage
VOLUME
SD
High-level input voltage, VIH
MIN
MAX
UNIT
8.5
14
V
3.0
5.5
V
5.5
V
2
MUTE
3.5
FADE
4
SD
Low-level input voltage, VIL
High-level input current, IIH
V
0.8
MUTE
2
FADE
2
MUTE, VI= 5 V, VCC = 14 V
1
SD, VI= 14 V, VCC = 14 V
50
FADE, VI= 5 V, VCC = 14 V
V
µA
150
1
A
µA
Oscillator frequency, fOSC
225
275
kHz
Operating free-air temperature, TA
−40
85
°C
Low-level input current, IIL
MUTE, SD, FADE, VI= 0 V, VCC = 14 V
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5
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
dc characteristics, TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Output offset voltage (measured
differentially)
INN and INP connected together,
Gain = 36 dB
V2P5 (terminal 4)
2.5-V Bias voltage
No load
PSRR
Power supply rejection ratio
ICC
ICC(MUTE)
Supply quiescent current
VCC = 11.5 V to 12.5 V
MUTE = 2 V, SD = 2 V
MUTE mode quiescent current
MUTE = 3.5 V, SD = 2 V
ICC(max power)
ICC(SD)
Supply current at max power
RL = 8 Ω, PO = 3 W
Supply current in shutdown mode
SD = 0.8 V
rds(on)
Drain-source on-state resistance
VCC = 12 V,
IO = 1 A,
TJ = 25°C
25 C
MIN
0.45x
AVDD
TYP
MAX
10
65
0.5x
AVDD
0.55x
AVDD
−80
UNIT
mV
V
dB
16
28.5
mA
7
9
mA
0.6
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1
10
High side
600
700
Low side
600
700
1200
1400
TYP
MAX
Total
µA
mΩ
m
ac characteristics, TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
kSVR
Supply ripple rejection ratio
PO(max)
Maximum continuous output power
Vn
Output integrated noise floor
SNR
6
TEST CONDITIONS
VCC = 11.5 V to 12.5 V from 10 Hz
to 1 kHz, Gain = 36 dB
MIN
UNITS
−67
dB
3
W
THD+N = 10%, f = 1 kHz, RL = 8 Ω
20 Hz to 22 kHz, No weighting filter,
Gain = 0.5 dB
3.75
W
−82
dBV
Crosstalk, Left → Right
Gain = 13.2 dB, PO = 1 W, RL = 8 Ω
−77
dB
Signal-to-noise ratio
Maximum output at THD+N < 0.5%,
f= 1 kHz, Gain = 0.5 dB
102
dB
Thermal trip point
150
°C
Thermal hystersis
20
°C
THD+N = 1%, f = 1 kHz, RL = 8 Ω
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
Table 1. DC Volume Control
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (INCREASING
VOLUME OR FIXED
GAIN)
VOLTAGE ON THE
VOLUME PIN AS A
PERCENTAGE OF
VREF (DECREASING
VOLUME)
GAIN OF AMPLIFIER
%
%
dB
0 − 4.5
0 − 2.9
−75†
4.5 − 6.7
2.9 − 5.1
−40.0
6.7 − 8.91
5.1 − 7.2
−37.5
8.9 − 11.1
7.2 − 9.4
−35.0
11.1 − 13.3
9.4 − 11.6
−32.4
13.3 − 15.5
11.6 − 13.8
−29.9
15.5 − 17.7
13.8 − 16.0
−27.4
17.7 − 19.9
16.0 − 18.2
−24.8
19.9 − 22.1
18.2 − 20.4
−22.3
22.1 − 24.3
20.4 − 22.6
−19.8
24.3 − 26.5
22.6 − 24.8
−17.2
26.5 − 28.7
24.8 − 27.0
−14.7
28.7 − 30.9
27.0 − 29.1
−12.2
30.9 − 33.1
29.1 − 31.3
−9.6
33.1 − 35.3
31.3 − 33.5
−7.1
35.3 − 37.5
33.5 − 35.7
−4.6
37.5 − 39.7
35.7 − 37.9
39.7 − 41.9
37.9 − 40.1
−2.0
0.5†
41.9 − 44.1
40.1 − 42.3
3.1
44.1 − 46.4
42.3 − 44.5
5.6
46.4 − 48.6
44.5 − 46.7
8.1
48.6 − 50.8
46.7 − 48.9
10.7
50.8 − 53.0
48.9 − 51.0
13.2
53.0 − 55.2
51.0 − 53.2
15.7
55.2 − 57.4
53.2 − 55.4
18.3
57.4 − 59.6
55.4 − 57.6
20.8
59.6 − 61.8
57.6 − 59.8
23.3
61.8 − 64.0
59.8 − 62.0
25.9
64.0 − 66.2
62.0 − 64.2
28.4
66.2 − 68.4
64.2 − 66.4
30.9
68.4 − 70.6
66.4 − 68.6
33.5
36.0†
> 70.6
>68.6
† Tested in production. Remaining steps are specified by design.
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7
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
PO
Efficiency
vs Output power
1
Output power
vs Load resistance
2
vs Supply voltage
3
IQ
ICC
Quiescent supply current
vs Supply voltage
4
Supply current
vs Output Power
5
IQ(sd)
Quiescent shutdown supply current
vs Supply voltage
6
Input impedance
vs Gain
vs Frequency
THD+N
Total harmonic distortion + noise
kSVR
Supply ripple rejection ratio
vs Output power
vs Frequency
Closed loop response
10, 11
12
13, 14
Intermodulation performance
15
Input offset voltage
vs Common-mode input voltage
16
Crosstalk
vs Frequency
17
Mute attenuation
Shutdown attenuation
Common-mode rejection ratio
8
7
8, 9
18
vs Frequency
vs Frequency
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19
20
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
EFFICIENCY
vs
OUTPUT POWER
OUTPUT POWER
vs
LOAD RESISTANCE
80
8
70
7
VCC = 12 V, RL = 8 Ω
60
PO − Output Power − W
6
Efficiency − %
VCC = 8.5 V, RL = 8 Ω
50
40
LC Filter
Resistive Load
30
20
10
VCC = 12 V,
THD = 10%
5
Thermally Limited
4
3
2
VCC = 8.5 V,
THD = 10%
1
0
0
0.5
1
1.5
2
PO − Output Power − W
2.5
VCC = 8.5 V,
THD = 1%
0
3
8
9
Figure 1
10
11
12
13
14
RL − Load Resistance − Ω
15
16
Figure 2
OUTPUT POWER
vs
SUPPLY VOLTAGE
QUIESCENT SUPPLY CURRENT
vs
SUPPLY VOLTAGE
6
I Q − Quiescent Supply Current − mA
18
5
PO − Output Power − W
VCC = 12 V,
THD = 1%
Thermally Limited
4
8 Ω, THD = 10%
8 Ω, THD = 1%
3
2
TA = 25°C
17
16
15
14
13
12
11
1
8.5
9
10
11
12
VDD − Supply Voltage − V
13
14
10
8.5
9
10
11
12
VCC − Supply Voltage − V
13
14
Figure 4
Figure 3
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9
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
OUTPUT POWER (TOTAL)
QUIESCENT SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.8
0.5
0.4
0.3
0.2
0
0.8
0.6
VSD = 0.8 V
0.4
0.2
VSD = 0 V
CC
0.1
1
0
1
2
3
4
5
PO − Output Power (Total) − W
6
I
− Supply Current − A
0.6
I
CC
− Quiescent Shutdown Supply Current − µ A
VCC = 12 V,
RL = 8 Ω
0.7
0
8.5
9
10
11
12
13
VCC − Supply Voltage − V
Figure 5
Figure 6
INPUT IMPEDANCE
vs
GAIN
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
120
THD+N − Total Harmonic Distortion + Noise − %
10
Z i − Input Impedance − k Ω
100
80
60
40
20
0
−50
−30
−10
10
Gain − dB
30
50
VCC = 12 V,
RL = 8 Ω,
TA = 25°C
5
2
1
0.5
PO = 1 W
0.2
0.1
0.05
0.02
0.01
20
50
100 200
500
Figure 8
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PO = 0.5 W
PO = 3 W
1k 2k
f − Frequency − Hz
Figure 7
10
14
5 k 10 k 20 k
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V,
RL = 8 Ω,
TA = 25°C
5
2
1
PO = 1 W
0.5
PO = 0.5 W
0.2
0.1
0.05
PO = 3.5 W
0.02
0.01
20
50
100 200 500 1 k 2 k
f − Frequency − Hz
VCC = 8.5 V,
RL = 8 Ω,
TA = 25°C
5
2
1
0.5
f = 1 kHz
f = 20 Hz
0.2
0.1
0.05
f = 20 KHz
0.02
0.01
5 k 10 k 20 k
20m
50m 100m 200m 500m 1
2
PO − Output Power − W
5
10
Figure 10
Figure 9
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY
5
−40
VCC = 12 V,
RL = 8 Ω,
TA = 25°C
k SVR − Supply Ripple Rejection Ratio − dB
THD+N − Total Harmonic Distortion + Noise − %
10
2
1
f = 1 kHz
0.5
f = 20 Hz
0.2
0.1
0.05
f = 20 kHz
0.02
0.01
20m
50m 100m 200m 500m 1
2
5
10
PO − Output Power − W
−45
VCC = 12 V,
RL = 8 Ω
−50
−55
−60
−65
−70
−75
−80
−85
−90
20
100
1k
10 k
100 k
f − Frequency − Hz
Figure 12
Figure 11
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11
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
CLOSED LOOP RESPONSE
CLOSED LOOP RESPONSE
100
50
Gain
0
Gain
50
0
Phase
50
0
−50
0
−50
−100
−100
Phase − Deg
Gain − dB
Gain − dB
100
Phase
−50
−50
−100
−100
−150
−150
−150
−200
VCC = 12 V,
Gain = +5.6 dB,
RL = 8 Ω
−250
10
100
−200
1k
10 k
100 k
−150
VCC = 12 V,
Gain = +36 dB,
RL = 8 Ω
−200
−250
10
−250
1M
100
Figure 13
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INTERMODULATION PERFORMANCE
6
5
VIO − Input Offset Voltage − mV
FFT − dBr
VCC = 12 V
VCC = 12 V, 19 kHz, 20 kHz,
1:1, PO = 1 W, RL = 8 Ω
Gain= +13.2 dB,
BW =20 Hz to 22 kHz,
Class-D
No Filter
−60
−80
−100
−120
−140
50
4
3
2
1
0
−1
100
1k
f − Frequency − Hz
1
10 k
1.5
2
2.5
3
3.5
4
4.5
VICM − Common-Mode Input Voltage − V
Figure 16
Figure 15
12
−250
1M
100 k
Figure 14
0
−40
−200
1k
10 k
f − Frequency − Hz
f − Frequency − Hz
−20
Phase − Deg
50
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5
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
MUTE ATTENUATION
vs
FREQUENCY
−30
−60
−50
−70
Crosstalk − dB
VCC = 12 V,
RL = 8 Ω,
VI = 1 Vrms
Class-D,
VOLUME = 0 V
−40
Mute Attenuation − dB
−65
VCC = 12 V,
Gain = +13.2 dB,
RL = 8 Ω,
PO = 1 W
−75
−80
−85
−60
−70
−80
−90
−100
−110
−90
−95
10
−120
−130
100
1k
10 k
f − Frequency − Hz
10
100 k
100
Figure 17
10 k
Figure 18
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
SHUTDOWN ATTENUATION
vs
FREQUENCY
−60
−80
−90
CMRR − Common-Mode Rejection Ratio − dB
VCC = 12 V,
RL = 8 Ω,
VI = 1 Vrms
Gain = +13.2 dB,
Class-D
−85
Shutdown Attenuation − dB
1k
f − Frequency − Hz
−95
−100
−105
−110
−115
−120
−125
100
1k
−70
−80
−90
−100
20
−130
10
VCC = 12 V
10 k
100
1k
10 k 20 k
f − Frequency − Hz
f − Frequency − Hz
Figure 20
Figure 19
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
VCC
ROUT+
GND
VCC
ROUT−
APPLICATION INFORMATION
C23
1 nF
C22
1 nF
L1
(Bead)
L2
(Bead)
10 µF
PGND
10 nF
10 nF
C15
0.1uF
0.1uF
C9
C10
1 µF
1 µF
P1
50 kΩ
BSRP
PVCCR
ROUTP
ROUTP
PGNDR
ROUTN
PGNDR
ROUTN
PVCCR
NC
RINP
MUTE
V2P5
AVCC
LINP
NC
LINN
NC
TPA3003D2
AVDDREF
GND
AVDD
AGND
COSC
AGND
ROSC
VOLUME
AGND
REFGND
VCLAMPL
PGND
1 µF
C13
0.1 µF
FADE
VREF
C11
220pF
100 nF
R1
120 kΩ
AGND
BSLP
PVCCL
PVCCL
PGND
L3
(Bead)
L4
(Bead)
C25
1nF
GND
C24
1nF
VCC
LOUTP
10 nF
10 µF
LOUT−
PGND
VCC
10 nF
GND
1 µF
C21
0.1 µF
Figure 21. Stereo Configuration With Single-Ended Inputs
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MUTE
CONTROL
VCC
AVDD
C14
C6
C12
0.1 µF
C17
LOUT+
C20
LOUTP
PGNDL
PGNDL
LOUTN
AGND
14
C16
10 µF
C8
GND
LOUTN
LIN−
1 µF
1 µF C4
RINN
PVCCL
C3
PVCCR
BSRN
C2
1 µF C5
AGND
C7
VCLAMPR
PVCCL
RIN−
SD
C1
BSLN
SHUTDOWN
PVCCR
C19
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
class-D operation
This section focuses on the class-D operation of the TPA3003D2.
traditional class-D modulation scheme
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 22. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is
high, causing high loss, thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
−12 V
Current
Figure 22. Traditional Class-D Modulation Scheme’s Output Voltage and
Current Waveforms Into an Inductive Load With No Input
TPA3003D2 modulation scheme
The TPA3003D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50%
and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout
most of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.
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APPLICATION INFORMATION
TPA3003D2 modulation scheme (continued)
OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
−12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
−12 V
Current
Figure 23. The TPA3003D2 Output Voltage and Current Waveforms Into an Inductive Load
efficiency: LC filter required with the traditional class-D modulation scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme, because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3003D2 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker, which results in less power
dissipation, therefore increasing efficiency.
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APPLICATION INFORMATION
effects of applying a square wave into a speaker
Audio specialists have advised for years not to apply a square wave to speakers. If the amplitude of the
waveform is high enough and the frequency of the square wave is within the bandwidth of the speaker, the
square wave could cause the voice coil to jump out of the air gap and/or scar the voice coil. A 250-kHz switching
frequency, however, does not significantly move the voice coil, as the cone movement is proportional to 1/f2 for
frequencies beyond the audio band.
Damage may occur if the voice coil cannot handle the additional heat generated from the high-frequency
switching current. The amount of power dissipated in the speaker may be estimated by first considering the
overall efficiency of the system. If the on-resistance (rds(on)) of the output transistors is considered to cause the
dominant loss in the system, then the maximum theoretical efficiency for the TPA3003D2 with an 8-Ω load is
as follows:
ǒ
Efficiency (theoretical, %) + R ń R ) r
L
L
ds(on)
Ǔ
100% + 8ń(8 ) 1.4)
100% + 85.11%
(1)
The maximum measured output power is approximately 3 W with an 12-V power supply. The total theoretical
power supplied (P(total)) for this worst-case condition would therefore be as follows:
P
(total)
+ P ńEfficiency + 3 W ń 0.8511 + 3.52 W
O
(2)
The efficiency measured in the lab using an 8-Ω speaker was 75%. The power not accounted for as dissipated
across the rds(on) may be calculated by simply subtracting the theoretical power from the measured power:
Other losses + P
(total)
(measured) * P
(total)
(theoretical) + 4 * 3.52 + 0.48 W
(3)
The quiescent supply current at 12 V is measured to be 28.5 mA. It can be assumed that the quiescent current
encapsulates all remaining losses in the device, i.e., biasing and switching losses. It may be assumed that any
remaining power is dissipated in the speaker and is calculated as follows:
P
(dis)
+ 0.48 W * (12 V
28.5 mA) + 0.14 W
(4)
Note that these calculations are for the worst-case condition of 3 W delivered to the speaker. Since the 0.14 W
is only 5% of the power delivered to the speaker, it may be concluded that the amount of power actually
dissipated in the speaker is relatively insignificant. Furthermore, this power dissipated is well within the
specifications of most loudspeaker drivers in a system, as the power rating is typically selected to handle the
power generated from a clipping waveform.
when to use an output filter
Design the TPA3003D2 without the filter if the traces from amplifier to speaker are short (< 1 inch). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies.
Use a LC output filter if there are low frequency (<1 MHz) EMI sensitive circuits and/or there are long wires from
the amplifier to the speaker.
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
when to use an output filter (continued)
33 µH
OUTP
L1
33 µH
C1
C2
0.1 µF
0.47 µF
OUTN
L2
C3
0.1 µF
Figure 24. Typical LC Output Filter, Cutoff Frequency of 41 kHz, Speaker Impedance = 8 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 25. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3)
volume control operation
The VOLUME terminal controls the internal amplifier gain. This pin is controlled with a dc voltage, which should
not exceed VREF. Table 1 lists the gain as determined by the voltage on the VOLUME pin in reference to the
voltage on VREF.
If using a resistor divider to fix the gain of the amplifier, the VREF terminal can be directly connected to
AVDDREF and a resistor divider can be connected across VREF and REFGND. (See Figure 21 in the
Application Information Section). For fixed gain, calculate the resistor divider values necessary to center the
voltage between the two percentage points given in the first column of Table 1. For example, if a gain of 10.7
dB is desired, the resistors in the divider network can both be 10 kΩ. With these resistor values, a voltage of
50%*VREF will be present at the VOLUME pin and result in a class-D gain of 10.7 dB.
If using a DAC to control the class-D gain, VREF and REFGND should be connected to the reference voltage
for the DAC and the GND terminal of the DAC, respectively. For the DAC application, AVDDREF would be left
unconnected. The reference voltage of the DAC provides the reference to the internal gain circuitry through the
VREF input and any fluctuations in the DAC output voltage will not affect the TPA3003D2 gain. The percentages
in the first column of Table 1 should be used for setting the voltages of the DAC when the voltage on the VOLUME
terminal is increased. The percentages in the second column should be used for the DAC voltages when
decreasing the voltage on the VOLUME terminal. Two lookup tables should be used in software to control the
gain based on an increase or decrease in the desired system volume. This is explained further in a section
below.
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
volume control operation (continued)
If using an analog potentiometer to control the gain, it should be connected between VREF and REFGND.
VREF can be connected to AVDDREF or an external voltage source, if desired. The first and second column
in Table 1 should be used to determine the point at which the gain changes depending on the direction that the
potentiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the first column in
Table 1 should be referenced to determine the trip points. If the voltage is decreasing, the trip points in the
second column should be referenced.
The trip point, where the gain actually changes, is different depending on whether the voltage on the VOLUME
terminal is increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that
the gain control is monotonic and does not oscillate from one gain step to another. A pictorial representation
of the volume control can be found in Figure 26. The graph focuses on three gain steps with the trip points
defined in the first and second columns of Table 1. The dotted lines represent the hysteresis about each gain
step.
The timing of the volume control circuitry is controlled by an internal 60-Hz clock. This clock determines the
rate at which the gain changes when adjusting the voltage on the external volume control pins. The gain updates
every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step until the final desired gain is
reached. For example, if the TPA3003D2 is currently in the +0.53 dB gain step and the VOLUME pin is adjusted
for maximum gain at +36 dB, the time required for the gain to reach +36 dB is 14 steps x 67ms/step = 0.938
seconds. Referencing Table 1, there are 14 steps between the +0.53 dB gain step and the maximum gain step
of +36 dB.
Decreasing Voltage on
VOLUME Terminal
Class-D Gain − dB
5.6
3.1
Increasing Voltage on
VOLUME Terminal
0.5
2.00
(40.1%*VREF)
2.21
2.10 2.11
(44.1%*VREF)
(41.9%*VREF) (42.3%*VREF)
Voltage on VOLUME Pin − V
Figure 26. DC Volume Control Operation, VREF = 5 V
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
FADE operation
The FADE terminal is a logic input that controls the operation of the volume control circuitry during transitions
to and from the shutdown state and during power-up.
A logic low on this terminal places the amplifier in the fade mode. During power-up or recovery from the
shutdown state (a logic high is applied to the SD terminal), the volume is smoothly ramped up from the mute
state, −75 dB, to the desired volume setting determined by the voltage on the volume control terminal.
Conversely, the volume is smoothly ramped down from the current state to the mute state when a logic low is
applied to the SD terminal. The timing of the volume control circuitry is controlled by an internal 60-Hz clock.
This clock determines the rate at which the gain changes when adjusting the voltage on the external volume
control pins. The gain updates every 4 clock cycles (nominally 67 ms based on a 60 Hz clock) to the next step
until the final desired gain is reached. For example, if the TPA3003D2 is currently in the +0.53 dB class-D gain
step and the VOLUME pin is adjusted for maximum gain at +36 dB, the time required for the gain to reach 36
dB is 14 steps x 67 ms/step = 0.938 seconds. Referencing Table 1, there are 14 steps between the +0.53 dB
gain step and the maximum gain step of +36 dB.
Figure 27 shows a scope capture of the differential output (measured across OUT+ and OUT−) with the amplifier
in the fade mode. A 1 Vpp dc voltage was applied across the differential inputs and a logic low was applied to
the SD terminal at the time defined in the figure. The figure depicts the outputs transitioning from one gain step
to the next lower step at approximately 67 ms/step.
A logic high on this pin disables the volume fade effect during transitions to and from the shutdown state and
during power-up. During power-up or recovery from the shutdown state (a logic high is applied to the SD
terminal), the transition from the mute state, −75 dB, to the desired volume setting is less than 1 ms. Conversely,
the volume ramps down from current state to the mute state within 1 ms when a logic low is applied to the SD
terminal.
Figure 28 shows a scope capture of the differential output with the fade effect disabled. The outputs transition
to the lowest gain state within 1ms of applying a logic low to the SD terminal.
SD = 0V
GND
Figure 27. Differential Output With FADE (Terminal 30) Held Low
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
SD = 0 V
GND
Figure 28. Differential Output With FADE Terminal Held High
MUTE operation
The MUTE pin is an input for controlling the output state of the TPA3003D2. A logic high on this pin disables
the outputs. A logic low on this pin enables the outputs. This pin may be used as a quick disable or enable of
the outputs without a volume fade. Quiescent current is listed in the dc characteristics specification table. The
MUTE pin should never be left floating.
For power conservation, the SD pin should be used to reduce the quiescent current to the absolute minimum
level. The volume will fade, slowly increase or decrease, when leaving or entering the shutdown state if the
FADE terminal is held low. If the FADE terminal is held high, the outputs will transition very quickly. Refer to the
FADE operation section.
SD operation
The TPA3003D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point)during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. SD should never be left unconnected, because
amplifier operation would be unpredictable.
For the best power-off pop performance, the amplifier should be placed in the shutdown mode prior to removing
the power supply voltage.
selection of COSC and ROSC
The switching frequency is determined using the values of the components connected to ROSC (pin 20) and
COSC (pin 21) and may be calculated with the following equation:
fOSC = 6.6 / (ROSC * COSC)
The frequency may be varied from 225 kHz to 275 kHz by adjusting the values chosen for ROSC and COSC.
The recommended values are COSC = 220 pF, ROSC=120 kΩ for a switching frequency of 250 kHz.
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
internal 2.5-V bias generator capacitor selection
The internal 2.5-V bias generator (V2P5) provides the internal bias for the preamplifier stage. The external input
capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of
the input preamplifiers.
The selection of the capacitor value on the V2P5 terminal is critical for achieving the best device performance.
During startup or recovery from the shutdown state, the V2P5 capacitor determines the rate at which the
amplifier starts up. When the voltage on the V2P5 capacitor equals 0.75 x V2P5, or 75% of its final value, the
device turns on and the class-D outputs start switching. The startup time is not critical for the best depop
performance since any pop sound that is heard is the result of the class-D outputs switching on and not the
startup time. However, at least a 0.47-µF capacitor is recommended for the V2P5 capacitor.
A secondary function of the V2P5 capacitor is to filter high frequency noise on the internal 2.5-V bias generator.
input resistance
Each gain setting is achieved by varying the input resistance of the amplifier, which can range from its smallest
value to over six times that value. As a result, if a single capacitor is used in the input high-pass filter, the −3 dB
or cutoff frequency also changes by over six times.
Zf
Ci
Input
Signal
Zi
IN
The −3-dB frequency can be calculated using equation 5.
f *3dB +
1
2p Z iC i
(5)
input capacitor, Ci
In the typical application an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level (V2P5) for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form
a high-pass filter with the corner frequency determined in equation 6.
−3 dB
(6)
1
fc +
2 p Zi Ci
fc
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
The value of Ci is important, as it directly affects the bass (low frequency) performance of the circuit. Consider
the example where Zi is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 6
is reconfigured as equation 7.
Ci +
1
2p Z i f c
(7)
In this example, Ci is 0.4 µF, so one would likely choose a value in the range of 0.47 µF to 1 µF. If the gain is
known and will be constant, use Zi to calculate Ci. Calculations for Ci should be based off the impedance at the
lowest gain step intended for use in the system. A further consideration for this capacitor is the leakage path
from the input source through the input network (Ci) and the feedback network to the load. This leakage current
creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain
applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized
capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as
the dc level there is held at 2.5 V, which is likely higher than the source dc level. Note that it is important to confirm
the capacitor polarity in the application.
power supply decoupling, CS
The TPA3003D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 µF placed as close as possible to the device VCC lead works best. For
filtering lower-frequency noise signals, a larger aluminum electrolytic capacitor of 10 µF or greater placed near
the audio power amplifier is recommended. The 10-µF capacitor also serves as a local storage capacitor for
supplying current during large signal transients on the amplifier outputs.
BSN and BSP capacitors
The full H-bridge output stages use only NMOS transistors. They therefore require bootstrap capacitors for the
high side of each output to turn on correctly. A 10-nF ceramic capacitor, rated for at least 25 V, must be connected
from each output to its corresponding bootstrap input. Specifically, one 10-nF capacitor must be connected from
xOUTP to xBSP, and one 10-nF capacitor must be connected from xOUTN to xBSN. (See the application circuit
diagram in Figure 21.)
VCLAMP capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-µF capacitors must be connected from VCLAMPL (pin 25)
and VCLAMPR (pin 36) to ground and must be rated for at least 25 V. The voltages at the VCLAMP terminals
vary with VCC and may not be used for powering any other circuitry.
internal regulated 5-V supply (AVDD)
The AVDD terminal (pin 29) is the output of an internally-generated 5-V supply, used for the oscillator,
preamplifier, and volume control circuitry. It requires a 0.1-µF to 1-µF capacitor, placed very close to the pin,
to ground to keep the regulator stable. The regulator may not be used to power any external circuitry.
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SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
differential input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel.
To use the TPA3003D2 with a differential source, connect the positive lead of the audio source to the INP input
and the negative lead from the audio source to the INN input. To use the TPA3003D2 with a single-ended source,
ac ground the INP input through a capacitor equal in value to the input capacitor on INN and apply the audio
source to the INN input. In a single-ended input application, the INP input should be ac-grounded at the audio
source instead of at the device input for best noise performance.
using low-ESR capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this
resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this
resistance the more the real capacitor behaves like an ideal capacitor.
short-circuit protection
The TPA3003D2 has short circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short-circuit is detected on
the outputs, the output drive is immediately disabled. This is a latched fault and must be reset by cycling the
voltage on the SD pin to a logic low and back to the logic high state for normal operation. This will clear the
short-circuit flag and allow for normal operation if the short was removed. If the short was not removed, the
protection circuitry will again activate.
thermal protection
Thermal protection on the TPA3003D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15 degree tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are
disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by
20°C. The device begins normal operation at this point with no external system interaction.
thermal considerations: output power and maximum ambient temperature
To calculate the maximum ambient temperature, the following equation may be used:
TAmax = TJ – ΘJAPDissipated
where: TJ = 150°C
ΘJA = 45°C/W
(8)
(The derating factor for the 48-pin PFB package is given in the dissipation rating table.)
To estimate the power dissipation, the following equation may be used:
PDissipated = PO(average) x ((1 / Efficiency) – 1)
(9)
Efficiency = ~75% for an 8-Ω load
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APPLICATION INFORMATION
thermal considerations: output power and maximum ambient temperature (continued)
Example. What is the maximum ambient temperature for an application that requires the TPA3003D2 to drive
3 W into an 8-Ω speaker (stereo)?
PDissipated = 6 W x ((1 / 0.75) – 1) = 2 W
(PO = 3 W * 2)
TAmax = 150°C – (45°C/W x 2 W) = 60°C
This calculation shows that the TPA3003D2 can drive 3 W of continuous RMS power per channel into an 8-Ω
speaker up to an ambient temperature of 60°C.
printed circuit board (PCB) layout
Because the TPA3003D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
D Decoupling capacitors — As described on page 23, the high-frequency 0.1-uF decoupling capacitors
should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC (pin 33) terminals as
possible. The V2P5 (pin 4) capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should
also be placed as close to the device as possible. Large (10 uF or greater) bulk power supply decoupling
capacitors should be placed near the TPA3003D2 on the PVCCL, PVCCR, and AVCC terminals.
D Grounding — The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor,
COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND,
pin 26. The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power ground
(PGND, pins 18, 19, 42, 43). Basically, an AGND island should be created with a single connection to PGND.
D Output filter — The ferrite EMI filter (Figure 25, page 18) should be placed as close to the output terminals
as possible for the best EMI performance. The LC filter (Figure 24, page 18 should be placed close to the
outputs. The capacitors used in both the ferrite and LC filters should be grounded to PGND.
For an example layout, please refer to the TPA3003D2 Evaluation Module (TPA3003D2EVM) User Manual, TI
literature number SLOU159. The EVM user manual is available on the TI web site at http://www.ti.com.
basic measurement system
This section focuses on methods that use the basic equipment listed below:
D
D
D
D
D
D
D
D
D
Audio analyzer or spectrum analyzer
Digital multimeter (DMM)
Oscilloscope
Twisted pair wires
Signal generator
Power resistor(s)
Linear regulated power supply
Filter components
EVM or other complete audio circuit
www.ti.com
25
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
Figure 29 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal since it consists of the fundamental frequency only (no other harmonics
are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must
be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise
and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II)
(Reference 1) by Audio Precision includes the signal generator and analyzer in one package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important since the input resistance of APAs is not very high (about 10 kΩ).
Conversely the analyzer-input impedance should be high. The output impedance, ROUT, of the APA is normally
in the hundreds of milliohms and can be ignored for all but the power-related calculations.
Figure 29(a) shows a class-AB amplifier system, which is relatively simple because these amplifiers are linear
their output signal is a linear representation of the input signal. They take analog signal input and produce analog
signal output. These amplifier circuits can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 29(b), which requires low pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
26
www.ti.com
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
Power Supply
Signal
Generator
APA
RL
Analyzer
20 Hz − 20 kHz
(a) Basic Class−AB
Power Supply
Low−Pass RC
Filter
Signal
Generator
Class−D APA
RL
Low−Pass RC
Filter
Analyzer
20 Hz − 20 kHz
(b) Filter−Free and Traditional Class−D
Figure 29. Audio Measurement Systems
The TPA3003D2 uses a modulation scheme that does not require an output filter for operation, but they do
sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs
cannot accurately process the rapidly changing square-wave output and therefore record an extremely high
level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the
analyzer can measure the output sine wave.
www.ti.com
27
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
differential input and BTL output
All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling
the output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 30. The differential input is a balanced input,
meaning the positive (+) and negative (−) pins will have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
Evaluation Module
Audio Power
Amplifier
Generator
Analyzer
Low−Pass
RC Filter
CIN
VGEN
RGEN
RIN
ROUT
RIN
ROUT
CIN
RGEN
RL
Twisted−Pair Wire
Low−Pass
RC Filter
RANA
CANA
RANA
CANA
Twisted−Pair Wire
Figure 30. Differential Input—BTL Output Measurement Circuit
The generator should have balanced outputs and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that will affect the measurement accuracy. The analyzer
must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common mode
noise in the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL
outputs:
D
D
D
D
D
Use a balanced source to supply the input signal.
Use an analyzer with balanced inputs.
Use twisted-pair wire for all connections.
Use shielding when the system environment is noisy.
Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 2).
Table 2 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
28
www.ti.com
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
Table 2. Recommended Minimum Wire Size for Power Cables
POUT
(W)
RL
(Ω)
AWG SIZE
DC POWER LOSS
(mW)
AC POWER LOSS
(mW)
1
8
22 to 28
2.0
8.0
2.1
8.1
< 0.75
8
22 to 28
1.5
6.1
1.6
6.2
Class-D RC low-pass filter
A RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 31.
RL is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should
be available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived
for the system. The filter should be grounded to the APA near the output ground pins or at the power supply
ground pin to minimize ground loops.
Load
RC Low−Pass Filters
RFILT
CFILT
RL
VL= VIN
AP Analyzer Input
CANA
RANA
CANA
RANA
VOUT
RFILT
CFILT
To APA
GND
Figure 31. Measurement Low-Pass Filter Derivation Circuit—Class-D APAs
www.ti.com
29
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
APPLICATION INFORMATION
The transfer function for this circuit is shown in equation (10) where ωO = REQCEQ, REQ = RFILTRANA and CEQ
= (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation (11) provides this cutoff frequency, fC. The value of
RFILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to
minimize the attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA.
A rule of thumb is that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement
error to less than 1% for RANA ≥ 10 kΩ.
ǒ Ǔ
V
OUT
V
IN
f
C
+ Ǹ2
ǒ
R
R
+
f
ANA
)R
ANA
FILT
Ǔ
ǒ Ǔ
1 ) j ww
O
(10)
MAX
(11)
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 3 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated using equation (12). When the
calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum
desired value calculated in equation (11).
C
FILT
+
1
2p
f
C
R
FILT
(12)
Table 3 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57000 pF,
but the nearest values of 56000 pF and 51000 pF were not available. A 47000 pF capacitor was used instead,
and fC is 34 kHz, which is above the desired value of 28 kHz.
Table 3. Typical RC Measurement Filter Values
MEASUREMENT
RFILT
Efficiency
All other measurements
30
CFILT
1 000 Ω
5 600 pF
100 Ω
56 000 pF
www.ti.com
SLOS406A − FEBRUARY 2003 − REVISED MARCH 2003
MECHANICAL DATA
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°−ā 7°
1,05
0,95
Seating Plane
1,20 MAX
0,75
0,45
0,08
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
www.ti.com
31
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA3003D2PFB
ACTIVE
TQFP
PFB
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA3003D2PFBG4
ACTIVE
TQFP
PFB
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA3003D2PFBR
ACTIVE
TQFP
PFB
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPA3003D2PFBRG4
ACTIVE
TQFP
PFB
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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