ADS ADS ADS823 ADS826 826 823 SBAS070B – OCTOBER 1995 – REVISED AUGUST 2002 10-Bit, 60MHz Sampling ANALOG-TO-DIGITAL CONVERTER ● +3V/+5V LOGIC I/O COMPATIBLE (ADS826) ● POWER DOWN: 20mW ● SSOP-28 PACKAGE FEATURES ● ● ● ● ● HIGH SNR: 60dB HIGH SFDR: 74dBFS LOW POWER: 265mW INTERNAL/EXTERNAL REFERENCE OPTION SINGLE-ENDED OR DIFFERENTIAL ANALOG INPUT ● PROGRAMMABLE INPUT RANGE ● LOW DNL: 0.25LSB ● SINGLE +5V SUPPLY OPERATION APPLICATIONS ● ● ● ● ● The ADS823 and ADS826 employ digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Their low distortion and high SNR give the extra margin needed for medical imaging, communications, video, and test instrumentation. The ADS823 and ADS826 offer power dissipation of 265mW and also provide a power-down mode, thus reducing power dissipation to only 20mW. DESCRIPTION The ADS823 and ADS826 are pipeline, CMOS Analog-toDigital Converters (ADCs) that operate from a single +5V power supply. These converters provide excellent performance with a single-ended input and can be operated with a differential input for added spurious performance. These high-performance converters include a 10-bit quantizer, highbandwidth track-and-hold, and a high-accuracy internal reference. They also allow for disabling the internal reference and utilizing external references. This external reference option provides excellent gain and offset matching when used in multi-channel applications or in applications where full-scale range adjustment is required. +VS IN IN T/H The ADS823 and ADS826 are specified at a maximum sampling frequency of 60MHz and a single-ended input range of 1.5V to 3.5V. The ADS823 and ADS826 are available in an SSOP-28 package and are pin-compatible with the 10-bit, 40MHz ADS822 and ADS825, and the 10-bit, 75MHz ADS828. CLK ADS823 ADS826 VIN MEDICAL IMAGING COMMUNICATIONS CCD IMAGING VIDEO DIGITIZING TEST EQUIPMENT VDRV Timing Circuitry 10-Bit Pipelined A/D Core Error Correction Logic 3-State Outputs D0 • • • D9 Internal Reference CM Optional External Reference Int/Ext PD OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (+VS + 0.3V) Logic Input ............................................................... –0.3V to (+VS + 0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +150°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximumrated conditions of extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. EVALUATION MODULE ORDERING INFORMATION PRODUCT EVALUATION MODULE ADS823E DEM-ADS823E PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) ADS823E " ADS826E " SSOP-28 " SSOP-28 " DB " DB " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA, QUANTITY –40°C to +85°C " –40°C to +85°C " ADS823E " ADS826E " ADS823E ADS823E/1K ADS826E ADS826E/1K Rails Tape and Reel, 1000 Rails Tape and Reel, 1000 NOTE: (1) Fot the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of ADS823E/1K” will get a single 1000-piece Tape and Reel. ELECTRICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. ADS826E(1) ADS823E MIN RESOLUTION SPECIFIED TEMPERATURE RANGE ANALOG INPUT Standard Single-Ended Input Range Optional Single-Ended Input Range Common-Mode Voltage Optional Differential Input Range Analog Input Bias Current Input Impedance Track-Mode Input Bandwidth Ambient Air 2Vp-p 1Vp-p 1.5 2 2Vp-p 2 2 MAX MIN UNITS Bits –40 to +85 °C 10k 3.5 3 ✻ ✻ 3 ✻ 74 74 ✻ ✻ ✻ ✻ 60M ±0.25 ±0.25 Tested ±0.5 ✻ ✻ ✻ ✻ ±1.0 ✻ ✻ Tested ✻ ±2.0 65 64 V V V V µA MΩ || pF MHz ✻ Samples/s Clk Cyc ✻ LSB LSB ✻ LSBs ✻ 5 67 MAX –40 to +85 1 1.25 || 5 300 –3dBFS Input TYP 10 Tested 2.5 CONVERSION CHARACTERISTICS Sample Rate Data Latency DYNAMIC CHARACTERISTICS Differential Linearity Error (largest code error) f = 1MHz f = 10MHz No Missing Codes Integral Nonlinearity Error, f = 1MHz Spurious-Free Dynamic Range(2) f = 1MHz f = 10MHz 2-Tone Intermodulation Distortion(4) f = 9.5MHz and 9.9MHz (–7dB each tone) Signal-to-Noise Ratio (SNR) f = 1MHz f = 10MHz Signal-to-(Noise + Distortion) (SINAD) f = 1MHz f = 10MHz Effective Number of Bits(5), f = 1MHz Output Noise Aperture Delay Time Aperture Jitter Over Voltage Recovery Time(5) Full-Scale Step Acquisition Time TYP 10 Tested 73 73 dBFS(3) dBFS ✻ dBc 59 59 dB dB 58 58 ✻ ✻ ✻ ✻ ✻ ✻ dB dB Bits LSBs rms ns ps rms ns ns Referred to Full-Scale Sinewave 57 60 60 56 Referred to Full-Scale Sinewave 56 Input Grounded 59 59 9.5 0.2 3 1.2 2 5 55 ADS823, ADS826 www.ti.com SBAS070B ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. ADS826E(1) ADS823E MIN DIGITAL INPUTS Logic Family Convert Command High Level Input Current(6) (VIN = 5V) Low Level Input Current (VIN = 0V) High Level Input Voltage Low Level Input Voltage Input Capacitance DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) Low Output Voltage, (IOL = 50µA to 1.6mA) High Output Voltage, (IOH = 50µA to 0.5mA) 3-State Enable Time 3-State Disable Time Output Capacitance ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted) Zero Error (referred to –FS) Zero Error Drift (referred to –FS) Midscale Offset Error Gain Error(7) Gain Error Drift(7) Gain Error(8) Gain Error Drift(8) Power-Supply Rejection of Gain REFT Tolerance REFB Tolerance(9) External REFT Voltage Range External REFB Voltage Range Reference Input Resistance POWER-SUPPLY REQUIREMENTS Supply Voltage: +VS Supply Current: +IS Power Dissipation: VDRV = 5V VDRV = 3V VDRV = 5V VDRV = 3V Power-Down Thermal Resistance, θJA SSOP-28 Start Conversion VDRV = 5V VDRV = 3V OE = H to L OE = L to H TYP MAX MIN TYP MAX CMOS-Compatible Rising Edge of Convert Clock +100 +10 +3.5 +1.0 5 TTL, +3V/+5V CMOS-Compatible Rising Edge of Convert Clock ✻ ✻ +2.0 +0.8 ✻ CMOS Straight Offset Binary +0.1 +4.9 +0.1 +2.8 2 40 2 10 5 CMOS Straight Offset Binary ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±0.29 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ UNITS µA µA V V pF V V V V ns ns pF fS = 2.5Mhz At 25°C At 25°C At 25°C At 25°C ∆VS = ±5% Deviation From Ideal 3.5V Deviation From Ideal 1.5V REFB + 0.8 1.25 REFT to REFB Operating Operating External Reference External Reference Internal Reference Internal Reference Operating +4.75 ±1.0 16 ±3.0 ±1.5 66 ±1.0 23 70 ±10 ±10 3.5 1.5 1.6 ±3.5 +5.0 55 275 265 295 285 20 89 ±2.5 ±25 ±25 VS – 1.25 REFT – 0.8 ✻ ✻ +5.25 ✻ 335 350 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ % FS ppm/°C % FS % FS ppm/°C % FS ppm/°C dB mV mV V V kΩ V mA mW mW mW mW mW °C/W ✻ Indicates the same specifications as the ADS823E. NOTES: (1) ADS826 accepts a +3V clock input. (2) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full-Scale. (4) 2-tone intermodulation distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (6) A 50kΩ pull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference. (9) Ensured by design. ADS823, ADS826 SBAS070B www.ti.com 3 PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP GND 1 28 VDRV Bit 1 (MSB) 2 27 +VS Bit 2 3 26 GND Bit 3 4 25 IN Bit 4 5 24 IN Bit 5 6 23 CM Bit 6 7 22 REFT Bit 7 8 21 ByT Bit 8 9 20 ByB Bit 9 10 19 REFB Bit 10 (LSB) 11 18 INT/EXT OE 12 17 RSEL PD 13 16 GND CLK 14 15 +VS ADS823 ADS826 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 GND Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 OE 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD CLK +VS GND RSEL INT/EXT REFB ByB ByT REFT CM IN IN GND +VS VDRV DESCRIPTION Ground Data Bit 1 (D9) (MSB) Data Bit 2 (D8) Data Bit 3 (D7) Data Bit 4 (D6) Data Bit 5 (D5) Data Bit 6 (D4) Data Bit 7 (D3) Data Bit 8 (D2) Data Bit 9 (D1) Data Bit 10 (D0) (LSB) Output Enable. HI: High Impedance State. LO: Normal Operation (Internal Pull-Down Resistor) Power Down: HI = Power Down; LO = Normal Convert Clock Input +5V Supply Ground Input Range Select: HI = 2V; LO = 1V Reference Select: HI = External; LO = Internal Bottom Reference Bottom Ladder Bypass Top Ladder Bypass Top Reference Common-Mode Voltage Output Complementary Input (–) Analog Input (+) Ground +5V Supply Output Logic Driver Supply Voltage TIMING DIAGRAM N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+7 N+6 tH Clock 5 Clock Cycles t2 Data Out N–5 N–4 N–3 N–2 N–1 N Data Invalid SYMBOL tCONV tL tH tD t1 t2 4 N+1 N+2 t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 16.6 7.9 7.9 TYP MAX UNITS 100µs ns ns ns ns ns ns 8.3 8.3 3 3.9 12 ADS823, ADS826 www.ti.com SBAS070B TYPICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 1MHz SNR = 60dBFS SFDR = 77dBFS –20 Magnitude (dB) Magnitude (dB) –20 –40 –60 –40 –60 –80 –80 –100 –100 0 7.5 15 22.5 0 30 7.5 22.5 Frequency (MHz) SPECTRAL PERFORMANCE (Single-Ended, 1Vp-p) SPECTRAL PERFORMANCE (Differential Input, 2Vp-p) 30 0 fIN = 10MHz SNR = 56.6dBFS SFDR = 74dBFS fIN = 10MHz SNR = 60dBFS SFDR = 73dBFS –20 Magnitude (dB) –20 –40 –60 –40 –60 –80 –80 –100 –100 0 7.5 15 22.5 0 30 7.5 15 22.5 30 Frequency (MHz) Frequency (MHz) SPECTRAL PERFORMANCE (Differential Input, 2Vp-p) SPECTRAL PERFORMANCE 0 0 fIN = 20MHz SNR = 60.4dBFS SFDR = 72dBFS –40 –60 fIN = 20MHz SNR = 58.7dBFS SFDR = 70dBFS –20 Magnitude (dB) –20 Magnitude (dB) 15 Frequency (MHz) 0 Magnitude (dB) fIN = 10MHz SNR = 60dBFS SFDR = 76dBFS –80 –40 –60 –80 –100 –100 0 7.5 15 22.5 30 0 Frequency (MHz) 15 22.5 30 Frequency (MHz) ADS823, ADS826 SBAS070B 7.5 www.ti.com 5 TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. UNDERSAMPLING (Differential Input, 2Vp-p) 2-TONE INTERMODULATION DISTORTION 0 0 fIN = 41MHz fS = 56MHz SNR = 59.8dBFS SFDR = 78dBFS –20 Magnitude (dB) Magnitude (dB) –20 f1 = 9.5MHz at –7dBFS f2 = 9.9MHz at –7dBFS IMD(3) = –64.4dBc –40 –60 –40 –60 –80 –80 –100 –100 0 7 14 21 0 28 7.50 15 22.50 DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR 1.0 1.0 fIN = 10MHz fIN = 20MHz 0.5 0.5 DLE (LSB) DLE (LSB) 30 Frequency (MHz) Frequency (MHz) 0 –0.5 0 –0.5 –1.0 –1.0 0 256 512 768 1024 0 256 512 Output Code 768 1024 Output Code SWEPT POWER SFDR INTEGRAL LINEARITY ERROR 100 2.0 fIN = 1MHz fIN = 10MHz 80 SFDR (dB) ILE (LSB) 1.0 0 –1.0 dBc 40 20 0 –2.0 0 256 512 768 1024 –60 –50 –40 –30 –20 –10 0 Input Amplitude (dBFS) Output Code 6 dBFS 60 ADS823, ADS826 www.ti.com SBAS070B TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V single-ended input range = 1.5V to 3.5V, sampling rate = 60MHz, external reference, unless otherwise noted. DYNAMIC PERFORMANCE vs TEMPERATURE DYNAMIC PERFORMANCE vs INPUT FREQUENCY 80 80 SFDR SFDR, SNR (dBFS) SFDR, SNR (dBFS) 75 70 SNR 60 SFDR (fIN = 10MHz) 70 SFDR (fIN = 20MHz) 65 SNR (fIN = 10MHz) 60 SNR (fIN = 20MHz) 55 50 0.1 1 10 –50 100 –25 0 25 50 75 Frequency (MHz) Temperature (°C) SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 100 .40 65 60 DLE (LSB) SINAD (dBFS) fIN = 1MHz fIN = 10MHz fIN = 20MHz .30 fIN = 20MHz fIN = 1MHz .20 55 fIN = 10MHz .10 50 –50 –25 0 25 50 75 –50 100 –25 0 25 50 75 100 Temperature (°C) Temperature (°C) POWER DISSIPATION vs TEMPERATURE OUTPUT NOISE HISTOGRAM (DC Input) 290 800k VDRV = +5V Counts Power (mW) 600k 280 400k 270 200k 260 –50 –25 0 25 50 75 0 N–2 100 Temperature (°C) N N+1 N+2 Code ADS823, ADS826 SBAS070B N–1 www.ti.com 7 APPLICATION INFORMATION THEORY OF OPERATION The ADS823 and ADS826 are high-speed CMOS ADCs which employ a pipelined converter architecture consisting of 9 internal stages. Each stage feeds its data into the digital error correction logic ensuring excellent differential linearity and no missing codes at the 10-bit level. The output data becomes valid on the rising clock edge (see Timing Diagram on page 4). The pipeline architecture results in a data latency of 5 clock cycles. The analog input of the ADS823 and the ADS826 is a differential track-and-hold, as shown in Figure 1. The differential topology along with tightly matched capacitors produce a high level of AC-performance while sampling at very high rates. The ADS823 and ADS826 allows its analog inputs to be driven either single-ended or differentially. The typical configuration for the ADS823 and the ADS826 is for the singleended mode in which the input track-and-hold performs a single-ended to differential conversion of the analog input signal. Both inputs (IN, IN) require external biasing using a commonmode voltage that is typically at the mid-supply level (+VS/2). The following application discussion focuses on the singleended configuration. Typically, its implementation is easier to achieve and the rated specifications for the ADS823 and ADS826 are characterized using the single-ended mode of operation. DRIVING THE ANALOG INPUT The ADS823 and ADS826 achieve excellent AC performance either in the single-ended or differential mode of operation. The selection for the optimum interface configuration will depend Op Amp Bias φ1 VCM φ1 CH φ2 CI IN IN φ1 φ2 φ1 φ1 φ1 See Figure 2 for the typical circuit for an AC-coupled analog input configuration of the ADS823 and ADS826 while all components are powered from a single +5V supply. With the RSEL pin connected HIGH, the full-scale input range is set to 2Vp-p. In this configuration, the top and bottom references (REFT, REFB) provide an output voltage of +3.5V and +1.5V, respectively. Two resistors ( 2x 1.62kΩ) are used to create a common-mode voltage (VCM) of approximately +2.5V to bias the inputs of the driving amplifier A1. Using the OPA680 on a single +5V supply, its ideal commonmode point is at +2.5V, which coincides with the recommended common-mode input level for the ADS823 and ADS826, thus obviating the need of a coupling capacitor between the amplifier and the converter. Even though the OPA680 has an AC gain of +2, the DC gain is only +1 due to the blocking capacitor at resistor RG. The addition of a small series resistor (RS) between the output of the op amp and the input of the ADS823 and ADS826 will be beneficial in almost all interface configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor in combination with the 10pF capacitor establishes a passive low-pass filter limiting the bandwidth for the wideband noise, thus helping improve the SNR performance. AC-Coupled, Dual-Supply Interface OUT See The circuit provided in Figure 3 for typical connections of the analog input in case the selected amplifier operates on dual supplies. This might be necessary to take full advantage of very low distortion operational amplifiers, like the OPA642. The advantage is that the driving amplifier can be operated with a ground referenced bipolar signal swing. This will keep the distortion performance at its lowest since the signal range stays within the linear region of the op amp and sufficient headroom to the supply rails can be maintained. By capacitively coupling the single-ended signal to the input of the ADS823 and ADS826, their common-mode requirements can easily be satisfied with two resistors connected between the top and bottom reference. φ2 φ1 Input Clock (50%) Op Amp Bias INPUT CONFIGURATIONS AC-Coupled, Single-Supply Interface OUT CI CH on the individual application requirements and system structure. For example, communications applications often process a band of frequencies that does not include DC, whereas in imaging applications, the previously restored DC level must be maintained correctly up to the ADC. Features on the ADS823 and ADS826 like the input range select (RSEL pin) or the option for an external reference, provide the needed flexibility to accommodate a wide range of applications. In any case, the ADS823 and ADS826 should be configured such that the application objectives are met while observing the headroom requirements of the driving amplifier in order to yield the best overall performance. VCM Internal Non-overlapping Clock φ1 φ2 φ1 FIGURE 1. Simplified Circuit of Input Track-and-Hold with Timing Diagram. 8 ADS823, ADS826 www.ti.com SBAS070B 1.62kΩ +5V VCM +2.5V 1.62kΩ +5V 0.1µF 50Ω REFB +1.5V RS 50Ω VIN REFT +3.5V RSEL +VS IN OPA690 10pF +VIN 0V ADS823 ADS826 RF 402Ω –VIN CM IN RG 402Ω 0.1µF INT/EXT 0.1µF GND FIGURE 2. AC-Coupled Input Configuration for a 2Vp-p Full-Scale Range and a Common-Mode Voltage, VCM, at +2.5V Derived from the Internal Top (REFT) and Bottom Reference (REFB). +5V 1.62kΩ +5V RS 24.9Ω VIN REFT +3.5V 0.1µF RSEL +VS IN OPA642 100pF ADS823 ADS826 –5V RF 402Ω 1.62kΩ CM IN 0.1µF RG 402Ω REFB +1.5V INT/EXT GND FIGURE 3. AC-Coupling the Dual-Supply Amplifier OPA642 to the ADS823 and ADS826 for a 2Vp-p Full-Scale Input Range. For applications requiring the driving amplifier to provide a signal amplification, with a gain ≥ 5, consider using decompensated voltage-feedback op amps, like the OPA686, or current-feedback op amps like the OPA6901. DC-Coupled with Level Shift Several applications may require that the bandwidth of the signal path includes DC, in which case the signal has to be DC-coupled to the ADC. In order to accomplish this, the interface circuit has to provide a DC level shift to the analog input signal. The circuit of in Figure 4 employs a dual op amp, A1, to drive the input of the ADS823 and ADS826, and level shift the signal to be compatible with the selected input range. With the RSEL pin tied to the supply and the INT/EXT pin to ground, the ADS823 and ADS826 are configured for a 2Vp-p input range and uses the internal references. The complementary input (IN) may be appropriately biased using the +2.5V common-mode voltage available at the CM pin. One half of amplifier A1 buffers the REFB pin and drives the voltage divider R1, R2. Due to the op amp’s noise gain of +2V/V, assuming RF = RIN, the common-mode voltage (VCM) has to be re-scaled to +1.25V. This results in the correct DC level of +2.5V for the signal input (IN). Any DC voltage differences between the IN and IN inputs of the ADS823 and ADS826 effectively produce an offset, which can be corrected for by adjusting the resistor values of the divider, R1 and R2. The selection criteria for a suitable op amp should include the supply voltage, input bias current, output voltage swing, distortion, and noise specification. Note that in this example the overall signal phase is inverted. To re-establish the original signal polarity, it is always possible to interchange the IN and IN connections. ADS823, ADS826 SBAS070B www.ti.com 9 +5V RF 499Ω RIN 499Ω VIN 1/2 OPA2681 +VS RSEL RS 50Ω IN 2Vp-p 10pF ADS823 ADS826 NOTE: RF = RIN, G = –1 CM (+2.5V) IN 0.1µF +5V REFB (+1.5V) REFT (+3.5V) INT/EXT 50Ω R2 200Ω 0.1µF 1/2 OPA2681 VCM = +1.25V 0.1µF R1 1kΩ RF 1kΩ FIGURE 4. DC-Coupled Interface Circuit with Level-Shifting, Dual Current-Feedback Amplifier OPA2681. SINGLE-ENDED TO DIFFERENTIAL CONFIGURATION (Transformer Coupled) If the application requires a signal conversion from a singleended source to feed the ADS823 and ADS826 differentially, a RF transformer might be a good solution. The selected transformer must have a center tap in order to apply the common-mode DC voltage necessary to bias the converter inputs. AC grounding the center tap will generate the differential signal swing across the secondary winding. Consider a step-up transformer to take advantage of a signal amplification without the introduction of another noise source. Furthermore, the reduced signal swing from the source may lead to an improved distortion performance. The component values of the R-C low-pass may be optimized depending on the desired roll-off frequency. The resistor across the secondary side (RT) should be calculated using the equation RT = n2 • RG to match the source impedance (RG) for good power transfer and VSWR. REFERENCE OPERATION Figure 6 depicts the simplified model of the internal reference circuit. The internal blocks are the bandgap voltage reference, the drivers for the top and bottom reference, and the RSEL The differential input configuration may provide a noticeable advantage of achieving good SFDR performance over a wide range of input frequencies. In this mode, both inputs of the ADS823 and ADS826 see matched impedances, and the differential signal swing can be reduced to half of the swing required for single-ended drive. Figure 5 shows the schematic for the suggested transformer-coupled interface circuit. ADS823 ADS826 50kΩ +VS INT/EXT 50kΩ Bandgap Reference and Logic VREF +1 +1 RG 0.1µF 1:n 22Ω VIN IN 400Ω 47pF 400Ω 400Ω 400Ω ADS823 ADS826 RT REFT 22Ω IN CM ByT CM ByB REFB RSEL INT/EXT 47pF +5V + 10µF FIGURE 5. Transformer-Coupled Input. 10 Bypass Capacitors: 0.1µF each (optionally, 2.2µF tantalum capacitors maybe added to ByT and ByB pins for the best results). 0.1µF FIGURE 6. Equivalent Reference Circuit with Recommended Reference Bypassing. ADS823, ADS826 www.ti.com SBAS070B resistive reference ladder. The bandgap reference circuit includes logic functions that allow to set the analog input swing of the ADS823 and ADS826 to either a 1Vp-p or 2Vp-p full-scale range simply by tying the RSEL pin to a LOW or HIGH potential, respectively. While operating the ADS823 and ADS826 in the external reference mode, the buffer amplifiers for the REFT and REFB are disconnected from the reference ladder. As shown, the ADS823 and ADS826 have internal 50kΩ pullup resistors at the range select pin (RSEL) and reference select pin (INT/EXT). Leaving those pins open configures the ADS823 for a 2Vp-p input range and external reference operation. Setting the ADS823 up for internal reference mode requires bringing the INT/EXT pin LOW. The reference buffers can be utilized to supply up to 1mA (sink and source) to external circuitry. The resistor ladders of the ADS823 and ADS826 are divided into several segments and have two additional nodes, ByT and ByB, which are brought out for external bypassing only (See Figure 6). To ensure proper operation with any reference configurations, it is necessary to provide solid bypassing at all reference pins in order to keep the clock feedthrough to a minimum. All bypassing capacitors should be located as close to their respective pins as possible. ADS823 ADS826 REFT +3.5V R1 1.6kΩ REFB +1.5V For even more design flexibility, the internal reference can be disabled and an external reference voltage be used. The utilization of an external reference may be considered for applications requiring higher accuracy, improved temperature performance, or a wide adjustment range of the converter’s full-scale range. Especially in multichannel applications, the use of a common external reference has the benefit of obtaining better matching of the full-scale range between converters. The external references can vary as long as the value of the external top reference REFTEXT stays within the range of (VS – 1.25V) and (REFB + 0.8V), and the external bottom reference REFBEXT stays within 1.25V and (REFT – 0.8V), as shown in Figure 8. Clock jitter is critical to the SNR performance of high-speed, high-resolution ADCs. Clock jitter leads to aperture jitter (tA), which adds noise to the signal being converted. The ADS823 and ADS826 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by 0.1µF VCM +2.5V EXTERNAL REFERENCE OPERATION DIGITAL INPUTS AND OUTPUTS Clock Input Requirements R2 1.6kΩ 0.1µF The common-mode voltage available at the CM pin may be used as a bias voltage to provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this node, which is not buffered and has a high impedance. An alternative way of generating a common-mode voltage is given in Figure 7. Here, two external precision resistors (tolerance 1% or better) are located between the top and bottom reference pins. The commonmode voltage, VCM, will appear at the midpoint. FIGURE 7. Alternative Circuit to Generate CM Voltage. +5V B A - Short for 1Vp-p Input Range B - Short for 2Vp-p Input Range (Default) +VS A RSEL INT/EXT GND IN VIN ADS823 ADS826 VCM +2.5VDC IN REFT External Top Reference REFT = REFB +0.8V to +3.75V ByT GND 4 x 0.1µF ByB REFB External Bottom Reference REFB = REFT –0.8V to +1.25V FIGURE 8. Configuration Example for External Reference Operation. ADS823, ADS826 SBAS070B www.ti.com 11 the following equation. If this value is near your system requirements, input clock jitter must be reduced. Jitter SNR = 20 log Particularly in undersampling applications, special consideration should be given to clock jitter. The clock input should be treated as an analog input in order to achieve the highest level of performance. Any overshoot or undershoot of the clock signal may cause degradation of the performance. When digitizing at high sampling rates, the clock should have 50% duty cycle (tH = tL), along with fast rise and fall times of 2ns or less. To estimate the typical performance deviation for clock duty cycles in the range of 50% ±7.5%, refer to Figure 9. The clock input of the ADS826 can be driven with either 3V or 5V logic levels. Using low-voltage logic (3V) may lead to improved AC performance of the converters. 1111111111 1100000000 1000000000 0100000000 0000000000 TABLE I. Coding Table for Single-Ended Input Configuration with IN tied to the Common-Mode Voltage (VCM). DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY (SOB) +FS –1LSB (IN = +3V, IN = +2V) +1/2 Full-Scale Bipolar Zero (IN = IN = VCM) –1/2 Full-Scale –FS (IN = +2V, IN = +3V) TABLE II. 1111111111 1100000000 1000000000 0100000000 0000000000 Coding Table for Differential Input Configuration and 2Vp-p Full-Scale Range. 60 It is recommended to keep the capacitive loading on the data lines as low as possible (≤ 15pF). Higher capacitive loading will cause larger dynamic currents as the digital outputs are changing. Those high current surges can feed back to the analog portion of the ADS823 and ADS826 and affect performance. If necessary, external buffers or latches close to the converter’s output pins may be used to minimize the capacitive loading. They also provide the added benefit of isolating the ADS823 and ADS826 from any digital noise activities on the bus coupling back high frequency noise. 55 Digital Output Driver (VDRV) 80 SFDR 75 SFDR, SNR (dBFS) STRAIGHT OFFSET BINARY (SOB) +FS –1LSB (IN = REFT) +1/2 Full-Scale Bipolar Zero (IN = VCM) –1/2 Full-Scale –FS (IN = REFB) 1 rms signal to rms noise 2π ƒ IN t A where: ƒIN is input signal frequency tA is rms clock jitter 70 65 SNR 50 57.5 55 52.5 50 47.5 45 42.5 Clock Duty Cycle (tH/tL x 100%) FIGURE 9. ADS823 and ADS826 Duty Cycle Sensitivity. Digital Outputs The output data format of the ADS823 and ADS826 is in positive Straight Offset Binary code as shown in Tables I and II. This format can easily be converted into the Binary Two’s Complement code by inverting the MSB. 12 SINGLE-ENDED INPUT (IN = CMV) The ADS823 and ADS826 feature a dedicated supply pin for the output logic drivers, VDRV, which is not internally connected to the other supply pins. Setting the voltage at VDRV to +5V or +3V, the ADS823 and ADS826 produce corresponding logic levels and can directly interface to the selected logic family. The output stages are designed to supply sufficient current to drive a variety of logic families. However, it is recommended to use the ADS823 and ADS826 with +3V logic supply. This will lower the power dissipation in the output stages due to the lower output swing and reduce current glitches on the supply line which may affect the ACperformance of the converter. In some applications, it might be advantageous to decouple the VDRV pin with additional capacitors or a pi-filter. ADS823, ADS826 www.ti.com SBAS070B GROUNDING AND DECOUPLING Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for highfrequency designs. Multilayer PC boards are recommended for best performance since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. The ADS823 and ADS826 should be treated as analog components. Whenever possible, the supply pins should be powered by the analog supply. This will ensure the most consistent results, since digital supply lines often carry high levels of noise which otherwise would be coupled into the converter and degrade the achievable performance. All ground connections on the ADS823 and ADS826 are internally joined together, obviating the design of split ground planes. The ground pins (1, 16, 26) should directly connect to an analog ground plane which covers the PC board area around the converter. While designing the layout, it is important to keep the analog signal traces separated from any digital lines to prevent noise coupling onto the analog signal path. Due to the high sampling rate, the ADS823 and ADS826 generate high frequency current transients and noise (clock feedthrough) that are fed back into the supply and reference lines. This requires that all supply and reference pins are sufficiently bypassed. Figure 10 shows the recommended decoupling scheme for the ADS823 and ADS826. In most cases 0.1µF ceramic chip capacitors at each pin are adequate to keep the impedance low over a wide frequency range. Their effectiveness largely depends on the proximity to the individual supply pin. Therefore, they should be located as close to the supply pins as possible. In addition, a larger bipolar capacitor (1µF to 22µF) should be placed on the PC board in proximity of the converter circuit. ADS823 ADS826 +VS 27 +VS 15 0.1µF GND 16 0.1µF VDRV 28 0.1µF 10µF + +5V +3/+5V FIGURE 10. Recommended Bypassing for the Supply Pins. ADS823, ADS826 SBAS070B GND 26 www.ti.com 13 PACKAGE DRAWING MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°– 8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 ADS823, ADS826 www.ti.com SBAS070B PACKAGE OPTION ADDENDUM www.ti.com 17-Apr-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS823E ACTIVE SSOP DB 28 ADS823E/1K ACTIVE SSOP DB ADS823E/1KG4 ACTIVE SSOP ADS823EG4 ACTIVE ADS826E 48 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DB 28 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SSOP DB 28 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS826E/1K ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS826E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ADS826EG4 ACTIVE SSOP DB 28 CU NIPDAU Level-1-260C-UNLIM 48 Green (RoHS & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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