HD151011 Dual BCD Programmable Counter with Synchronous Preset Enable ADE-205-100(Z) Rev 0 April 1995 The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider. Features • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) • High output current Fanout of 10 LS TTL Loads • Wide operating voltage Vcc = 2 to 6 V • Low supply current (Ta = 25°C) Icc (Static) = 4 µA (max) HD151011 Function Table Control Inputs CLR PR SPE C/T Mode Operation Description H H H X Generally count Down count at the rise edge of clock (CLK), Down count at the fall edge of clock (CLK) X X L X Synchronous preset Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) — — — H — Clock inputs (CLK, CLK) is CMOS level — — — L — Clock inputs (CLK, CLK) is TTL level L H — — Initialize of Q output Initialize of Q = "L" H L — — Initialize of Q output Initialize of Q = "H" H: High level L: Low level Z: Immaterial —: Irrespective of condition 1. Synchronous preset (SPE) input can set max 99 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. 4. Clock inputs (CLK, CLK) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB) 2 HD151011 Pin Arrangement CO 1 20 VCC J0 2 19 (Test 1)* J1 3 18 (Test 2)* J2 4 17 C / T J3 5 16 CLK J4 6 15 CLK J5 7 14 Q J6 8 13 PR J7 9 12 SPE GND 10 11 CLR (Top view) * Pins 18 and 19 are for function test only and should be open. Pin Description Pin Name Input pins Pin Description J0 to J7 Count data input for option C/T Level change input for CLK, CLK (CMOS level or TTL level) CLK, CLK Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger Output pins SPE Preset input for Jn data PR Preset input for D-type Flip Flop (Initialize "L" at Q output) CLR Clear input for D-type Flip Flop (Initialize "H" at Q output) CO Output for BCD decimal counter Q Output for D-type Flip Flop 3 HD151011 Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC –0.5 to 7.0 V Input / output voltage VIN / V OUT –0.5 to VCC +0.5 V VCC, GND current I CC, I GND ±50 mA Output current / pin I OUT ±25 mA Power dissipation PT 757 mW Storage temperature Tstg –65 to 150 °C Input diode current I IK ±20 mA Output diode current I OK ±20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage VCC 2 — 6 V Input / output voltage VIN / 0 — VCC V Operating temperature Topr –40 — +85 °C tr, tf 0 — 1000 ns VCC = 4.5 V 0 — 500 VCC = 5.5 V 0 — 400 Input rise / fall time Note: 4 *1 VCC = 2.5 V OUT 1. This item guarantees maximum limit when one input switches. HD151011 Logic Diagram C/T J0 J1 J1 J2 J2 J3 J3 J4 J4 J5 J5 J6 J6 J7 J7 CLK CLK BCD decimal counter J0 CLK CO PR PR D CO SPE Q CK Q Q CLR SPE CLR 5 HD151011 Electrical Characteristics Ta = 25°C Ta = –40 to 85°C Item Symbol VCC Min Typ Max Min Max Unit Test Conditions High level input VIH 2.0 1.5 — — 1.5 — V J0 to J7 4.5 3.15 — — 3.15 — C/T, SPE 6.0 4.2 — — 4.2 — PR, CLR 2.0 1.5 — — 1.5 — CLK, CLK C/T = VIH 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 4.5 to 5.5 2.0 — — 2.0 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 C/T, SPE 6.0 — — 1.8 — 1.8 PR, CLR 2.0 — — 0.5 — 0.5 CLK, CLK C/T = VIH 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 4.5 to 5.5 — — 0.8 — 0.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 4.31 — 4.13 — I OH = –4 mA 6.0 5.68 5.80 — 5.63 — I OH = –5.2 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — 0.17 0.26 — 0.33 I OL = 4 mA 6.0 — 0.18 0.26 — 0.33 I OL = 5.2 mA Input capacitance IIN 6.0 — — ±0.1 — ±1.0 mA VIN = VCC or GND Supply current 6.0 — — 4.0 — 40.0 mA VIN = VCC or GND voltage Low level input VIL voltage High level output voltage Low level output voltage 6 VOH VOL I CC C/T = VIL V J0 to J7 C/T = VIL V V VIN = VIH or VIL VIN = VIH or VIL I OH = –20 µA I OL = 20 µA HD151011 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) Ta = 25°C Ta = –40 to 85°C Item Symbol VCC Min Typ Max Min Max Unit Maximum clock frequency fmax 2.0 — — 4 — 3 MHz 4.5 — 36 20 — 16 6.0 — — 24 — 19 t TLH 2.0 — 30 75 — 95 t THL 4.5 — 8 15 — 19 6.0 — 7 13 — 16 t PLH 2.0 — — 250 — 318 t PHL 4.5 — 30 50 — 63 6.0 — — 45 — 53 t PLH 2.0 — — 300 — 380 t PHL 4.5 — 35 60 — 75 6.0 — — 53 — 65 t PLH 2.0 — — 150 — 185 t PHL 4.5 — 18 30 — 38 6.0 — — 25 — 32 2.0 80 — — 100 — 4.5 16 — — 20 — 6.0 14 — — 17 — 2.0 100 — — 125 — (Jn - CLK, CLK) 4.5 20 — — 25 — (SPE, CLK, CLK) 6.0 17 — — 21 — 2.0 15 — — 15 — (Jn - CLK, CLK) 4.5 10 — — 10 — (SPE, CLK, CLK) 6.0 5 — — 5 — Output rise / fall time Propagation delay time Pulse width tw (CLK, CLK, PR, CLR) Setup time Hold time ts th ns ns CLK or CLK to CO CLK or CLK to Q PR or CLR to Q ns ns ns Input capacitance CIN — — 5 10 — 10 pF Power dissipation capacitance CPD — — 48 — — — pF Note: Test Conditions 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD V CC • fIN + ICC 7 HD151011 • Test Circuit VCC VCC Input J0 J1 Pulse generator See Function Table Zout = 50 Ω Input Pulse generator Zout = 50 Ω Output Q Output J7 CO C/T CLK CLK CL SPE CL PR CLR Note: 1. CL includes probe and jig capacitance. • Waveforms – 1 tw tw 6 ns 6 ns CLK CLK VIH 90 % 90 % *1 *1 V ref V ref 10 % 10 % t PLH GND t PHL 90 % 50 % 10 % 10 % t THL t TLH t PLH 50 % 10 % t TLH Note: 8 1. VOL t PHL 90 % CO VOH 90 % 50 % Q *1 In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC × 50% VOH 90 % 50 % 10 % t THL VOL HD151011 • Waveforms – 2 6 ns 90 % Jn VCC 90 % 50 % 10 % 10 % GND ts CLK *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output VOL Internal delay Notes: 1. 2. In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC × 50% F/F output is internal signal of IC. • Waveforms – 3 6 ns 90 % Jn 90 % VCC 50 % 10 % 10 % th CLK GND *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output Internal delay Notes: 1. 2. VOL In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC × 50% F/F output is internal signal of IC. 9 HD151011 • Waveforms – 4 6 ns 90 % SPE VCC 90 % 50 % 10 % 10 % GND ts CLK *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output VOL Internal delay Notes: 1. 2. In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC × 50% F/F output is internal signal of IC. • Waveforms – 5 6 ns 90 % SPE 90 % VCC 50 % 10 % 10 % th CLK GND *1 90 % VIH 10 % 6 ns GND *1 V ref 10 % CLK VOH *2 50 % F/F Output Internal delay Notes: 1. 2. 10 In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC × 50% F/F output is internal signal of IC. VOL HD151011 • Waveforms – 6 tf tr VCC 90 % 90 % CLR 50 % 50 % 10 % 10 % GND tw tf tr 90 % 90 % VCC PR 50 % 50 % 10 % 10 % GND tw t PHL t PLH VOH Q 50 % 50 % VOL 11 HD151011 Timing Chart CLK SPE J0 J1 J2 J3 J4 J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 12 5 4 3 2 1 0 3 2 1 0 23 22 HD151011 Example of Application Circuit • AC Signal Generator for STN Type Liquid Crystal Panel CLK (CLK) : CMOS level input Initialize counter : 32 CO V CC J0 (Test 1) NC J1 (Test 2) NC J2 C/T J3 CLK J4 CLK J5 Q J6 PR J7 SPE GND CLR * * *When initializing output D-F/F apply "L" 13 HD151011 Timing Chart • Example of AC Signal Generator 1 2 3 31 32 33 34 35 65 66 67 68 CLK SPE J0 J1 1digit=2 J2 J3 J4 J5 2digits=3 J6 J7 (CO=SPE) CLR Q PR Q Count 14 32 31 30 2 1 0 32 31 1 0 32 31 HD151011 Package Dimensions Unit : mm Unit: mm 6.50 6.80 Max 11 1 10 4.40 20 0.65 0.22 +0.08 –0.07 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 Dimension including the plating thickness Base material dimension 0.07 +0.03 –0.04 0.10 0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.65 Max 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-20DA — — 0.07 g 15 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Stra§e 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.