HD404849 Series 4-Bit Single-Chip Microcomputer Rev. 6.0 Sept. 1998 Description The HD404849 series of HMCS400-series microcomputers is designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D converter, input capture circuit, 32-kHz oscillator for clock use, and four low-power dissipation modes. The HD404849 series includes the HD404848 with an 8-kword on-chip ROM, the HD4048412 with a 12kword on-chip ROM, the HD404849 with a 16-kword on-chip ROM, and the HD4074849 with a 16-kword on-chip PROM. On-chip ROM is available in a PROM (ZTAT microcomputer) version and a mask ROM version. A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. PROM programming specifications are the same as for the 27256. ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features • 35 I/O pins, including nine high-current pins (15 mA, max.), eight pins multiplexed with LCD segment pins, and four pins multiplexed with analog input pins • Four timer/counters • Eight-bit input capture circuit • Three timer outputs (including two PWM outputs) • Two event counter inputs (including one in which the detection edge is programmable) • Clock-synchronous 8-bit serial interface • A/D converter (8 channels × 8 bits) Operation voltage 2.7 V to 6.0 V • LCD driver (32 segments × 4 commons) • Built-in oscillators Main clock: Can be driven by ceramic oscillator, crystal oscillator, or external clock. Subclock: 32.768-kHz crystal • Ten interrupt sources Four by external sources, including two in which the detection edge is programmable HD404849 Series • • • • • • Six by internal sources Subroutine stack up to 16 levels, including interrupts Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode One external input for transition from stop mode to active mode Instruction cycle time: 0.89 µs (fOSC = 4.5 MHz) Operation voltage VCC = 2.7 V to 6.0 V (subactive mode: 2.2 V to 6.0 V) (HD404848, HD404849) VCC = 2.7 V to 5.5 V (HD4074849) Two operating modes MCU mode (HD404848, HD4048412, HD404849) MCU/PROM mode (HD4074849 only) Ordering Information Type Product Name Model Name ROM (words) RAM (digits) Package Mask ROM HD404848 HD404848H 8,192 512 80-pin plastic QFP (FP-80A) HD4048412 HD404849 ZTAT 2 HD4074849 HD404848FS 80-pin plastic QFP (FP-80B) HD404848TF 80-pin plastic TQFP (TFP-80C) HD4048412H 12,288 1,184 80-pin plastic QFP (FP-80A) HD4048412FS 80-pin plastic QFP (FP-80B) HD4048412TF 80-pin plastic TQFP (TFP-80C) HD404849H 16,384 1,184 80-pin plastic QFP (FP-80A) HD404849FS 80-pin plastic QFP (FP-80B) HD404849TF 80-pin plastic TQFP (TFP-80C) HD4074849H 16,384 1,184 80-pin plastic QFP (FP-80A) HD4074849FS 80-pin plastic QFP (FP-80B) HD4074849TF 80-pin plastic TQFP (TFP-80C) HD404849 Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 R31/AN5 R30/AN4 AN3 AN2 AN1 AN0 AVCC VCC V3 V2 V1 COM4 COM3 COM2 COM1 SEG44 SEG43 SEG42 SEG41 SEG40 Pin Arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 FP-80A TFP-80C (top view) SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73/SEG20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AN3 AN2 AN1 AN0 AVCC VCC V3 V2 V1 COM4 COM3 COM2 COM1 SEG44 SEG43 SEG42 D11/INT0 R00/INT1 R01/INT2 R02/INT3 R03 R10/TOB R11/TOC R12/TOD R13/EVNB R20/EVND R21/SCK R22/SI R23/SO R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 R70/SEG17 R71/SEG18 R72/SEG19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R32/AN6 R33/AN7 AVSS TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D10/STOPC FP-80B (top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73/SEG20 R72/SEG19 R71/SEG18 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 R01/INT2 R02/INT3 R03 R10/TOB R11/TOC R12/TOD R13/EVNB R20/EVND R21/SCK R22/SI R23/SO R60/SEG13 R61/SEG14 R62/SEG15 R63/SEG16 R70/SEG17 R30/AN4 R31/AN5 R32/AN6 R33/AN7 AVSS TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D10/STOPC D11/INT0 R00/INT1 3 HD404849 Series Pin Description Pin Number Item Symbol FP-80A ,TFP-80C FP-80B Power supply VCC 73 75 Applies power voltage GND 10 12 Connected to ground Test TEST 4 6 I Used for factory testing only: Connect this pin to GND Reset RESET 7 9 I Resets the MCU Oscillator OSC 1 5 7 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator or connect OSC1 to an external oscillator circuit. OSC 2 6 8 O X1 8 10 I X2 9 11 O D0–D 8 11–19 13–21 I/O Input/output pins addressed by individual bits; pins D 0–D 8 are highcurrent pins that can each supply up to 15 mA D10, D11 20, 21 22, 23 I R0–R3, R6, 22–33, 79, 80, R7 1, 2, 34–41 24–35, 1–4, 36–43 I/O Input/output pins addressable in 4-bit units Interrupt INT0, INT1, INT2, INT3 21–24 23–26 I Input pins for external interrupts Stop clear STOPC 20 22 I Input pin for transition from stop mode to active mode Serial SCK 31 33 I/O Serial clock input/output pin SI 32 34 I Serial receive data input pin SO 33 35 O Serial transmit data output pin TOB, TOC, TOD 26–28 28–30 O Timer output pins EVNB, EVND 29, 30 31, 32 I Event count input pins Port Timer 4 I/O Function Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to VCC and leave the X2 pin open. Input pins addressable by individual bits HD404849 Series Pin Number Item Symbol FP-80A, TFP-80C FP-80B LCD V1, V2, V3 70–72 72–74 COM1– COM4 66–69 68–71 O Common signal pins for LCD SEG13– SEG44 34–65 36–67 O Segment signal pins for LCD AVCC 74 76 Power pin for A/D converter: Connect it to the same potential as VCC, as physically close to the VCC pin as possible AVSS 3 5 Ground for AV CC: Connect it to the same potential as GND, as physically close to the GND pin as possible AN 0–AN 7 75–80, 1, 2 77–80, 1–4 A/D converter I/O Function Power pins for LCD driver. The LCD power supply division resistors can be connected and disconnected as controlled by software. Voltage conditions are: VCC ≥ V 1 ≥ V 2 ≥ V 3 ≥ GND I Analog input pins for A/D converter 5 HD404849 Series V CC GND RESET TEST STOPC OSC 1 OSC 2 X1 X2 Block Diagram System control circuit 512 × 4-bit, 1,184 × 4-bit RAM External interrupt control cricuit D D11/ INT 0 R00/ INT 1 R01/ INT 2 R02/ INT 3 W (2) Timer A X (4) R10/ TOB R13/ EVNB Timer B R11/ TOC Timer C R12/ TOD R20/ EVND Timer D R21/ SCK R22/ SI R23/ SO Serial interface AVCC AVSS AN0 AN1 AN2 AN3 R30/ AN4 R31/ AN5 R32/ AN6 R33/ AN7 A/D converter D10 /STOPC D11 /INT0 R0 ST (1) R1 ALU R10 /TOB R11 /TOC R12 /TOD R13 /EVNB R2 SPY (4) Internal data bus Internal address bus Internal data bus Y (4) R00 /INT1 R01 /INT2 R02 /INT3 R03 R20 /EVND R21 /SCK R22 /SI R23 /SO R3 SPX (4) R30 /AN4 R31 /AN5 R32 /AN6 R33 /AN7 R6 to R60 /SEG13 R61 /SEG14 R62 /SEG15 R63 /SEG16 R70 /SEG17 R71 /SEG18 R72 /SEG19 R73 /SEG20 CA (1) A (4) B (4) SP (10) LCD display circuit Instruction decoder Program counter (14) 8,192 × 10-bit, 12,288 × 10-bit, 16,384 × 10-bit ROM SEG44 : Data bus : Signal lines 6 Highcurrent pins R7 V1 V2 V3 COM1 COM2 COM3 COM4 R60/ SEG13 D0 D1 D2 D3 D4 D5 D6 D7 D8 HD404849 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$1FFF: HD404848; $0000–$2FFF: HD4048412; $0000–$3FFF: HD404849, HD4074849): Used for program coding. 0 15 63 Vector address area (16 words) Zero-page subroutine area (64 words) $0000 $000F $003F Pattern area (4,096 words) $0FFF 4095 HD404848 program area (8,192 words) $1FFF 8191 HD4048412 program area (12,288 words) $2FFF 12287 0 JMPL instruction $0000 1 (jump to RESET, STOPC routine) $0001 2 JMPL instruction $0002 3 (jump to INT0 routine) $0003 4 JMPL instruction $0004 5 (jump to INT1 routine) $0005 6 JMPL instruction $0006 7 (jump to timer A routine) $0007 8 JMPL instruction $0008 9 (jump to timer B, INT 2 routine) $0009 10 JMPL instruction $000A 11 (jump to timer C, INT3 routine) $000B 12 JMPL instruction $000C 13 (jump to timer D routine) $000D 14 JMPL instruction $000E 15 (jump to A/D, serial routine) $000F HD404849/ HD4074849 program area (16,384 words) 16383 $3FFF Figure 1 ROM Memory Map 7 HD404849 Series RAM Memory Map The MCU contains a RAM area consisting of a memory register area, an LCD data area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000–$03F): • Interrupt Control Bits Area ($000–$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. • Special Function Register Area ($004–$01F, $024–$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, LCD, and A/D converter, and is used as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for the LCD control register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other registers. • Register Flag Area ($020–$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. LCD Data Area ($05C–$07B): Used for storing 32-digit LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to the LCD description for details. Data Area ($090–$21F: HD404848; $090–$2EF: HD4048412, HD404849, HD4074849): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $2EF is accessed without setting the bank register. Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 8 HD404849 Series HD404848 HD4048412, HD404849, HD4074849 $000 0 0 RAM mapped register 64 80 92 124 Memory register (16 digits) Not used LCD display area (32 digits) Not used 144 $040 64 $050 80 $05C 92 $07C 124 $090 144 Memory register (16 digits) $040 $050 Not used LCD display area (32 digits) $05C $07C Not used $090 Data (464 digits × 2) * 1 V = 0 (bank 0) V = 1 (bank 1) Data (400 digits) 544 $000 RAM mapped register $220 Not used 608 $260 Data (144 digits) 752 $2F0 Not used 960 $3C0 960 $3C0 Stack (64 digits) 1023 Stack (64 digits) $3FF 1023 $3FF $000 0 Interrupt control bits area 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (PMRA) Port mode register A (SMRA) Serial mode register A (SRL) Serial data register lower Serial data register upper (SRU) (TMA) Timer mode register A (TMB1) Timer mode register B1 (TRBL/TWBL) Timer-B (TRBU/TWBU) (MIS) Miscellaneous register (TMC1) Timer mode register C1 (TRCL/TWCL) Timer-C (TRCU/TWCU) Timer mode register D1 (TMD1) (TRDL/TWDL) Timer-D (TRDU/TWDU) (TMB2) Timer mode register B2 Timer mode register C2 (TMC2) (TMD2) Timer mode register D2 (AMR) A/D mode register (ADRL) A/D data register lower (ADRU) A/D data register upper W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R R $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 27 28 LCD control register LCD mode register (LCR) (LMR) W W $01B $01C 31 32 LCD output register 3 (LOR3) W $01F $020 *2 Not used Notes: R: Read only W: Write only R/W: Read/write Not used 1. The data area has two banks: bank 0 (V = 0) and bank 1 (V = 1) $090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) 35 36 37 38 39 40 41 Register flag area Port mode register B Port mode register C Edge sense select register 1 Edge sense select register 2 Serial mode register B System clock select register (PMRB) (PMRC) (ESR1) (ESR2) (SMRB) (SSR) W W W W W W $023 $024 $025 $026 $027 $028 $029 (DCD0) (DCD1) (DCD2) W W W $02C $02D $02E (DCR0) (DCR1) (DCR2) (DCR3) W W W W $030 $031 $032 $033 (DCR6) (DCR7) W W $036 $037 (V) W $03F Not used $25F 2. Two registers are mapped to the same address (at $00A, $00B, $00E, $00F, $011, and $012) 44 45 46 48 49 50 51 Port D0 to D3 DCR Port D4 to D7 DCR Port D8 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR 54 55 Port R6 DCR Port R7 DCR 63 V register Not used Not used 10 11 Timer read register B lower (TRBL) Timer read register B upper (TRBU) R R Timer write register B lower (TWBL) Timer write register B upper (TWBU) W W $00A $00B 14 15 Timer read register C lower (TRCL) Timer read register C upper (TRCU) R R Timer write register C lower (TWCL) Timer write register C upper (TWCU) W W $00E $00F 17 18 Timer read register D lower (TRDL) Timer read register D upper (TRDU) R R Timer write register D lower (TWDL) Timer write register D upper (TWDU) W W $011 $012 Figure 2 RAM Memory Map 9 HD404849 Series Bit 3 Bit 2 Bit 1 Bit 0 0 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $000 1 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $001 2 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $002 3 IMAD (IM of A/D) IFAD (IF of A/D) IMTD (IM of timer D) IFTD (IF of timer D) $003 (a) Interrupt control bits area Bit 3 Bit 2 Bit 1 Bit 0 32 DTON (Direct transfer on flag) ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $020 33 RAME (RAM enable flag) IAOF (A/D current off flag) ICEF (Input capture error flag) ICSF (Input capture status flag) $021 34 IM3 (IM of INT3) IF3 (IF of INT3) IM2 (IM of INT2) IF2 (IF of INT2) $022 35 IMS (IM of serial interface) IFS (IF of serial interface) Not used Not used $023 IF: IM: IE: SP: Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer (b) Register flag area Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 10 HD404849 Series Bits in the interrupt control bits area and register flag area can be set and reset by the SEM/SEMD and REM/REMD instructions, and tested with the TM/TMD instructions. Other instructions have no effect on these bits. Note the following restrictions for each bit. IE IM LSON IAOF IF ICSF ICEF RAME RSP WDON ADSF DTON Not used SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Inhibited Allowed Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST cannot be guaranteed. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 11 HD404849 Series $000 $003 PMRA $004 SMRA $005 SRL $006 SRU $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 bit3 bit2 bit1 bit0 Interrupt control bits area Not used R21/ SCK Timer A/time base Auto reload on/off Pull-up MOS control Auto reload on/off R22/SI Not used R23/SO Serial transmit clock speed selection 1 Serial data register (lower digit) Serial data register (upper digit) Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) Timer B register (upper digit) PMOS SO control Interrupt frame period selection Clock source selection (timer C) Timer C register (lower digit) Timer C register (upper digit) Auto reload on/off Not used Not used Input capture selection AMR $016 ADRL $017 ADRU $018 Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer B output mode selection Not used Timer C output mode selection Timer D output mode selection Analog channel selection A/D data register (lower digit) A/D data register (upper digit) A/D conversion period Not used LCR $01B LMR $01C LCD power switch LCD display on/off LCD duty cycle selection *1 *2 LCD input clock source selection Not used LOR3 $01F $020 Not used R7/SEG17–20 R6/SEG13–16 Not used Register flag area $023 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SMRB $028 SSR $029 R0 2/INT3 Not used D11/INT0 D10/STOPC INT3 detection edge selection EVND detection edge selection Not used Not used 32-kHz oscillation stop *5 R0 1/INT2 R0 0 /INT1 R20/EVND R13/EVNB INT2 detection edge selection Not used Not used *3 *4 *6 Not used Not used DCD0 $02C DCD1 $02D DCD2 $02E Port D3 DCR Port D7 DCR Not used Port D2 DCR Port D6 DCR Not used Port D1 DCR Port D5 DCR Not used Port D0 DCR Port D4 DCR Port D8 DCR DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 Port R03 DCR Port R13 DCR Port R23 DCR Port R33 DCR Not used Port R02 DCR Port R01 DCR Port R12 DCR Port R11 DCR Port R22 DCR Port R21 DCR Port R32 DCR Port R31 DCR Port R00 DCR Port R10 DCR Port R20 DCR Port R30 DCR DCR6 $036 DCR7 $037 Port R63 DCR Port R73 DCR Port R62 DCR Port R72 DCR Not used Not used Not used Port R61 DCR Port R71 DCR Port R60 DCR Port R70 DCR Not used V $03F Notes: 1. LCD display division resistor switch 2. Display on/off in watch mode 3. SO output level control in idle states Not used 4. Transmit clock source selection 5. 32-kHz oscillation division ratio 6. System oscillation frequency selection Figure 5 Special Function Register Area 12 Bank selection HD404849 Series Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC 12 PC11 $3FC 1021 PC 10 PC9 PC 8 PC7 $3FD 1022 CA PC6 PC 5 PC4 $3FE 1023 PC 3 PC2 PC 1 PC0 $3FF PC13 –PC0 : Program counter ST: Status flag CA: Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position Bank register (V: $03F) Bit 3 2 1 0 Initial value — — — 0 — — — R/W Read/Write Bit name Not used Not used Not used V0 V0 Bank area selection 0 Bank 0 is selected 1 Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Figure 7 Bank Register (V) 13 HD404849 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator Initial value: Undefined, R/W B register Initial value: Undefined, R/W W register Initial value: Undefined, R/W 0 (A) 3 0 (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W 0 (SPX) 3 0 (SPY) 0 Carry Initial value: Undefined, R/W (CA) Status Initial value: 1, no R/W (ST) 0 13 Program counter Initial value: 0, no R/W 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 8 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing. 14 HD404849 Series SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a low-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be low for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be low for at least two instruction cycles. Initial values after MCU reset are listed in table 1. 15 HD404849 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Program counter (PC) $0000 Indicates program execution point from start address of ROM area Status flag (ST) 1 Enables conditional branching Stack pointer (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask (IM) 1 Prevents (masks) interrupt requests Port data register (PDR) All bits 1 Enables output at level 1 Data control register (DCD0, DCD1) All bits 0 Turns output buffer off (to high impedance) Interrupt flags/mask I/O Timer/ counters, serial interface 16 Contents (DCD2) ---0 (DCR0– DCR3, DCR6, DCR7) All bits 0 Port mode register A (PMRA) - - 00 Refer to description of port mode register A Port mode register B (PMRB) - 000 Refer to description of port mode register B Port mode register C bits 3, 1, 0 (PMRC3, PMRC1, PMRC0) 000 Refer to description of port mode register C Detection edge select register 1 (ESR1) 0000 Disables edge detection Detection edge select register 2 (ESR2) 00 - - Disables edge detection Timer mode register A (TMA) 0000 Refer to description of timer mode register A Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1 Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2 Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 HD404849 Series Item Abbr. Initial Value Contents Timer/ Serial mode register A (SMRA) 0000 Refer to description of serial mode register A counters, Serial mode register B (SMRB) - - X0 Refer to description of serial mode register B serial Prescaler S (PSS) $000 — interface Prescaler W (PSW) $00 — Timer counter A (TCA) $00 — Timer counter B (TCB) $00 — Timer counter C (TCC) $00 — Timer counter D (TCD) $00 — Timer write register B (TWBU, TWBL) $X0 — Timer write register C (TWCU, TWCL) $X0 — Timer write register D (TWDU, TWDL) $X0 — 000 — Octal counter A/D LCD Bit registers Others A/D mode register (AMR) 0000 Refer to description of A/D mode register A/D data register (ADRU, ADRL) $80 Refer to description of A/D mode register LCD control register (LCR) 0000 Refer to description of LCD control register LCD mode register (LMR) 0000 Refer to description of LCD duty-cycle/clock control register LCD output register 3 (LOR3) - 00 - Sets R-port/LCD segment pins to R port mode Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C A/D start flag (ADSF) 0 Refer to description of A/D converter A/D current off flag (IAOF) 0 Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes, I/O, and serial interface System clock select register bits 2, 1 (SSR2, SSR1) 00 - Refer to description of operating modes and oscillation circuits Bank register (V) ---0 Refer to description of RAM memory map Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist. 17 HD404849 Series Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) Y/SPX register (Y/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) A/D data register (ADRU, L) RAM Status After all Status After Status After Cancellation of Stop Cancellation of Stop Other Types of Modeby STOPC Input Mode by MCU Reset Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 0 Port mode register C bit 2 (PMRC2) Pre-stop-mode values are retained 0 0 System clock select register bit 3 (SSR3) 18 HD404849 Series Interrupts The MCU has ten interrupt sources: four external signals (INT0, INT1, INT 2, INT3), four timer/counters (timers A, B, C, and D), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT 2, timer C and INT 3, and A/D converter and serial interface interrupts. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the ten interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* — $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 Timer B, INT2 4 $0008 Timer C, INT3 5 $000A Timer D 6 $000C A/D, Serial 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 19 HD404849 Series Interrupt enable flag INT0 interrupt $ 000,0 IE Sequence control • Push PC/CA/ST • Reset IE • Jump to vector address $ 000,2 IF0 $ 000,3 IM0 Vector address Priority control logic INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 Timer A interrupt $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt Timer C interrupt Timer D interrupt $ 002,0 IFTB $ 022,0 IF2 INT2 interrupt $ 002,1 IMTB $ 022,1 IM2 $ 002,2 IFTC $ 022,2 IF3 INT3 interrupt $ 002,3 IMTC $ 022,3 IM3 $ 003,0 IFTD $ 003,1 IMTD A/D interrupt $ 003,2 IFAD $ 023,2 Serial interrupt IFS $ 003,3 IMAD $ 023,3 IMS Note: $m,n is RAM address $m, bit number n. Figure 9 Interrupt Control Circuit 20 HD404849 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit INT0 INT1 Timer A Timer B or INT2 Timer C or INT3 Timer D A/D or Serial IE 1 1 1 1 1 1 1 IF0 • IM0 1 0 0 0 0 0 0 IF1 • IM1 * 1 0 0 0 0 0 IFTA • IMTA * * 1 0 0 0 0 IFTB • IMTB + IF2 • IM2 * * * 1 0 0 0 IFTC • IMTC + IF3 • IM3 * * * * 1 0 0 IFTD • IMTD * * * * * 1 0 IFAD • IMAD + IFS • IMS * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Execution of instruction at start address of interrupt routine Figure 10 Interrupt Processing Sequence 21 HD404849 Series Power on RESET = 0? Yes No Interrupt request? No Yes No IE = 1? Yes Reset MCU Accept interrupt Execute instruction IE ← 0 Stack ← (PC) Stack ← (CA) Stack ← (ST) PC ←(PC) + 1 PC← $0002 Yes INT0 interrupt? No PC← $0004 Yes INT1 interrupt? No PC← $0006 Yes Timer A interrupt? No PC← $0008 Yes Timer B/INT 2 interrupt? No PC ← $000A Yes Timer C/INT 3 interrupt? No PC ← $000C Yes Timer D interrupt? No PC ← $000E (A/D, serial interrupt) Figure 11 Interrupt Processing Flowchart 22 HD404849 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupts (INT0, INT1, INT2, INT3): There are four external interrupt signals. External Interrupt Request Flags (IF0–IF3: $000, $001, $022): IF0 and IF1 are set when the signals input to INT0 and INT1 are falling, and IF2 and IF3 are set when the signals input to INT2 and INT3 are rising or falling, as listed in table 5. The INT2 and INT3 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0–IF3: $000, $001, $022) IF0–IF3 Interrupt Request 0 No 1 Yes Detection edge selection register 1 (ESR1: $026) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W ESR13 ESR12 ESR11 ESR10 INT3 detection edge ESR13 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection * 1 INT2 detection edge ESR11 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 Note: * Both falling and rising edges are detected. Figure 12 Detection Edge Selection Register 1 (ESR1) 23 HD404849 Series Detection edge selection register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 — — Read/Write W W — — Bit name ESR23 ESR22 Not used Not used ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection * 1 EVND detection edge Note: * Both falling and rising edges are detected. Figure 13 Detection Edge Selection Register 2 (ESR2) External Interrupt Masks (IM0–IM3: $000, $001, $022): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0–IM3: $000, $001, $022) IM0–IM3 Interrupt Request 0 Enabled 1 Disabled (masked) Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2) IFTA Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. 24 HD404849 Series Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt Request 0 Enabled 1 Disabled (masked) Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9. Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0) IFTB Interrupt Request 0 No 1 Yes Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10. Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1) IMTB Interrupt Request 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11. Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2) IFTC Interrupt Request 0 No 1 Yes Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 Enabled 1 Disabled (masked) 25 HD404849 Series Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used, as listed in table 13. Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0) IFTD Interrupt Request 0 No 1 Yes Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 14. Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1) IMTD Interrupt Request 0 Enabled 1 Disabled (masked) Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 15. Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 2) IFS Interrupt Request 0 No 1 Yes Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS: $023, Bit 3) IMS Interrupt Request 0 Enabled 1 Disabled (masked) A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in table 17. 26 HD404849 Series Table 17 A/D Interrupt Request Flag (IFAD: $003, Bit 2) IFAD Interrupt Request 0 No 1 Yes A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 18. Table 18 A/D Interrupt Mask (IMAD: $003, Bit 3) IMAD Interrupt Request 0 Enabled 1 Disabled (masked) 27 HD404849 Series Operating Modes The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables 20 and 21. Transitions between operating modes are shown in figure 14. Table 19 Operating Modes and Clock Status Mode Name Stop Watch Subactive*2 SBY Reset instruction cancellation, interrupt request STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0 or timer A interrupt request from watch mode OP OP Stopped Stopped Stopped Subsystem OP oscillator OP OP *1 OP OP RESET input, interrupt request RESET input, STOPC input in stop mode RESET input RESET input, INT0 or timer A STOP/SBY instruction interrupt request Active Activation method Status Cancellation method System oscillator RESET input, STOP/SBY instruction Standby Notes: OP implies in operation. 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 28 HD404849 Series Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained OP RAM Retained Retained Retained OP Timer A Reset OP OP OP Timer B Reset Stopped OP OP Timer C Reset Stopped OP OP Timer D Reset Stopped OP OP OP OP OP Stopped OP OP Retained OP Serial Reset Stopped* A/D Reset Stopped LCD Reset I/O Reset* OP* 1 3 4 Retained Notes: OP implies in operation. 1. Output pins are at high impedance. 2. Subactive mode is an optional function specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. However, interrupts stop. 4. When a 32-kHz clock source is used. Table 21 I/O Status in Low-Power Dissipation Modes Output Input Standby Mode, Watch Mode Stop Mode Active Mode, Subactive Mode D0–D 8 Retained High impedance Input enabled D10, D11 — — Input enabled R0–R3, R6, R7 Retained or output of peripheral High impedance functions Input enabled 29 HD404849 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR3 = 0) RAME = 0 RAME = 1 RESET1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: ø CPU: ø CLK: ø PER: fOSC: fX: ø CPU: ø CLK: ø PER: SBY Interrupt fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR3 = 1) STOP fOSC: fX: ø CPU: ø CLK: ø PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A*1 fOSC: fX: ø CPU: ø CLK: ø PER: Stop Oscillate Stop fW Stop *3 fOSC: fX: Main oscillation frequency Suboscillation frequency for time-base fOSC/4 fcyc: fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 ø CPU: System clock ø CLK: Clock for time-base ø PER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag *2 Subactive mode fOSC: fX: ø CPU: ø CLK: ø PER: STOP Stop Oscillate fSUB fW fSUB Notes: 1. 2. 3. 4. *4 INT0, timer A*1 fOSC: fX: ø CPU: ø CLK: ø PER: Stop Oscillate Stop fW Stop Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don’t care, LSON = 1) Figure 14 MCU Status Transitions 30 (TMA3 = 1, LSON = 1) HD404849 Series Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15. 31 HD404849 Series Stop Standby Watch Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Oscillator: Active Peripheral clocks: Active All other clocks: Stop Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop No RESET = 0? Yes No RESET = 0? Yes IF0 • IM0 = 1? No No STOPC = 0? Yes IF1 • IM1 = 1? No Yes Yes IFTA • IMTA = 1? Yes RAME = 1 No IFTB • IMTB + IF2 • IM2 = 1? RAME = 0 No Yes IFTC • IMTC + IF3 • IM3 = 1? Yes No IFTD • IMTD = 1? Yes (SBY only) Restart processor clocks (SBY only) (SBY only) (SBY only) No IFAD • IMAD + IFS • IMS = 1? (SBY only) No Yes Restart processor clocks Execute next instruction No Reset MCU IF = 1, IM = 0, and IE = 1? Execute next instruction Yes Accept interrupt Figure 15 MCU Operation Flowchart Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC 2 oscillator stops. The X1 and X2 oscillator can be selected to operate by setting bit 3 of the system clock select register (SSR: $029; operating: SSR3 = 0, stop: SSR3 = 1) (figure 26). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 41). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, 32 , HD404849 Series but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed. Stop mode Oscillator Internal clock RESET or STOPC tres STOP instruction execution tres ≥ tRC (stabilization period) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD function operate, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0 interrupt, as shown in figures 17 and 18. Operation during mode transition is the same as that at standby mode cancellation (figure 15). 33 HD404849 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation T (During the transition from watch mode to active mode only) T t RC Tx Interrupt frame length T: t RC : Oscillation stabilization period Figure 17 Interrupt Frame Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 38. MIS1 MIS0 0 0 T*1 tRC * 1 0.24414 ms 0.12207 ms Oscillation circuit conditions External clock input 0.24414 ms* 2 0 1 15.625 ms 7.8125 ms 1 0 62.5 ms 1 1 Not used 31.25 ms Ceramic oscillator Crystal oscillator — Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the operating clock slows down, power dissipation is reduced, next least to watch mode. 34 HD404849 Series The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR2) of the system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Interrupt Frame: In watch and subactive modes, φCLK is applied to timer A and theINT0 circuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, a timer-A/INT0 interrupt is generated synchronously with the interrupt frame. An interrupt request is generated synchronously with an interrupt strobe except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe. Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: • Set LSON to 0 and DTON to 1 in subactive mode. • Execute the STOP or SBY instruction. • The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T t RC Interrupt frame length T: t RC : Oscillation stabilization period Figure 19 Direct Transition Timing 35 HD404849 Series Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by inputting STOPC or RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program needs to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power on RESET = 0 ? No Yes RAME = 0 MCU operation cycle Reset MCU Figure 20 MCU Operating Sequence (Power On) 36 HD404849 Series MCU operation cycle IF = 1? No Instruction execution Yes SBY/STOP instruction? Yes No IM = 0 and IE = 1? Yes IE ← 0 Stack ← (PC), (CA), (ST) No Low-power mode operation cycle IF: IM: IE: PC: CA: ST: PC ← Next location PC ← Vector address Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag Figure 21 MCU Operating Sequence (MCU Operation Cycle) 37 HD404849 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Standby/watch mode No IF = 1 and IM = 0? Yes Stop mode No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC ← Next Iocation PC ← Next Iocation Reset MCU Instruction execution MCU operation cycle For IF and IM operation, refer to figure 15. Figure 22 MCU Operating Sequence (Low-Power Mode Operation) Notes on Use: • When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 is shorter than the interrupt frame, INT 0 will not be detected. Also, if the low level period after the falling edge of INT 0 is shorter than the interrupt frame, INT 0 will not be detected. Edge detection is shown in figure 23. The level of the INT 0 signal is sampled by a sampling clock. When this sampled value changes from high to low, a falling edge is detected. 38 HD404849 Series In figure 24, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge will not be detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge will not be detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than the interrupt frame. INT0 Sampling High Low Low Figure 23 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low a. High level period A: High B: High b. Low level period Figure 24 Sampling Example 39 HD404849 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 25. As shown in table 22, a ceramic or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock select register (SSR: $029) must be set according to the fre quency of the oscillator connected to OSC1 and OSC2 (figure 26). Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency, subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 1/4 System fOSC division oscillator circuit fcyc tcyc Timing generator circuit OSC1 fX X1 Subsystem oscillator øCPU CPU with ROM, RAM, registers, flags, and I/O øPER Peripheral function interrupt System clock selection fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit * circuit TMA3 X2 1/8 division circuit fW tWcyc Timing generator circuit Time-base clock øCLK selection Note: * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (SSR: $029). Figure 25 Clock Generation Circuit 40 Time-base interrupt HD404849 Series System clock select register (SSR: $029) Bit 3 2 1 0 Initial value 0 0 0 — Read/Write W W W — SSR3* SSR2 SSR1 Not used Bit name SSR3 32-kHz oscillation stop SSR1 System oscillation frequency selection 0 Oscillation operates in stop mode 0 0.4 MHz – 1.0 MHz 1 Oscillation stops in stop mode 1 1.6 MHz – 4.5 MHz SSR2 32-kHz oscillation division ratio selection 0 fSUB = fX/8 1 fSUB = fX/4 Note: * SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode. Figure 26 System Clock Select Register 41 HD404849 Series GND X2 X1 RESET OSC2 OSC1 TEST GND Figure 27 Typical Layout of Crystal and Ceramic Oscillators 42 HD404849 Series Table 22 Oscillator Circuit Examples Circuit Configuration External clock operation Ceramic oscillator (OSC1, OSC 2) Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 MΩ ± 20% C1 = C2 = 30 pF ± 20% C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND Crystal oscillator (OSC1,OSC2) Rf = 1 MΩ ± 20% C1 = C2 = 10 to 22 pF ± 20% Equivalent circuit of crystal oscillator shown at left. C0: 7 pF max RS: 100 Ω max C1 OSC1 Crystal oscillator Rf OSC2 C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Crystal: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF ± 20% RS: 14 kΩ C0: 1.5 pF X1 Crystal oscillator X2 C2 GND L CS RS X1 X2 C0 Notes: 1. Circuit constants differ by the different types of crystal oscillators and ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1 and OSC 2 pins (X1 and X2 pins) and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 27. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. 43 HD404849 Series Input/Output The MCU has 33 input/output pins (D0–D 8, R0–R3, R6, and R7) and two input pins (D10 , D11 ). The features are described below. • Nine pins (D 0–D8) are high-current input/output pins. • The D10, D11, R00–R0 2, R1–R3, R6, and R7 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. • Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. • Peripheral function output pins are CMOS output pins. Only the R23/SO pin can be set to NMOS opendrain output by software. • In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. The data control register (DCD, DCR) is also reset, so input/output pins go to the high-impedance state. • Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 28, programmable I/O circuits are listed in table 23, and I/O pin circuit types are shown in table 24. Table 23 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD, DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS — — — On — — — On NMOS — — On — — — On — — — — — — On — On CMOS buffer Pull-up MOS Note: — indicates off status. 44 1 1 0 1 HD404849 Series VCC Pull-up MOS MIS3 VCC PMOS DCD, DCR PDR NMOS CPU input Input control signal Figure 28 I/O Buffer Configuration 45 HD404849 Series Table 24 Circuit Configurations of I/O Pins I/O Pin Type Circuit VCC Input/output pins Pins VCC Pull-up control signal Buffer control signal Output data MIS3 DCD, DCR PDR Input data D0–D 8 R0 0–R0 3 R1 0–R1 3 R2 0–R2 2 R3 0–R3 3 R6 0–R6 3 R7 0–R7 3 Input control signal VCC VCC Pull-up control signal Buffer control signal Output data MIS3 R2 3 DCR MIS2 PDR Input data Input control signal Input data Input pins D10, D11 Input control signal Peripheral Input/ function pins output pins VCC VCC Pull-up control signal Output data Input data Output pins VCC VCC Pull-up control signal Output data VCC SCK Pull-up control signal MIS3 SO MIS2 SO MIS3 Output data TOB, TOC, TOD 46 SCK SCK PMOS control signal VCC MIS3 TOB, TOC, TOD HD404849 Series I/O Pin Type Circuit Pins Input data Peripheral Input function pins pins INT0, STOPC VCC HLT MIS3 PDR INT0, STOPC SI, INT1, INT2, INT3, EVNB, EVND SI, etc. AN 0–AN 3 A/D input Input control VCC HLT AN 4–AN 7 MIS3 PDR A/D input Input control Note: The MCU is reset in stop mode, and an peripheral function selections are cancelled. The I/O control register is reset, so the input/output pins enter high-impedance state. D Port: Consist of nine input/output pins and two input pins addressed by one bit. D 0–D8 are high-current I/O pins, and D 10 and D 11 are input-only pins. Pins D 0–D 8 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins of the D port are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D port data control registers (DCD0–DCD2: $02C–$02E) that are mapped to memory addresses (figure 29). Pins D10 and D 11 are multiplexed with peripheral function pins STOPC and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 34). R Ports: 24 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R port data control registers (DCR0–DCR3, DCR6, DCR7: $030–$033, $036, $037) that are mapped to memory addresses (figure 29). 47 HD404849 Series Pins R00–R02 are multiplexed with peripheral pins INT1–INT 3, respectively. The peripheral function modes of these pins are selected by bits 0–2 (PMRB0–PMRB2) of port mode register B (PMRB: $024) (figure 30). Pins R10–R12 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3 (TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 31, and 33). Pins R13 and R20 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 34). Pins R21–R23 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36. Ports R6 and R7 are multiplexed with segment pins SEG13–SEG20, respectively. The function modes of these pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 37). 48 HD404849 Series Data control register DCD0, DCD1 Bit (DCD0 to DCD2: $02C to $02E) (DCR0 to DCR7: $030 to $037) 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 DCD2 Bit 3 2 1 Initial value — — — 0 Read/Write — — — W Bit name 0 Not used Not used Not used DCD20 DCR0 to DCR3, DCR6, DCR7 Bit 3 2 1 0 Initial value Read/Write 0 0 0 0 W W W W Bit name DCR03– DCR02– DCR01– DCR00– DCR33 DCR32 DCR31 DCR30 DCR63– DCR62– DCR61– DCR60– DCR73 DCR72 DCR71 DCR70 All Bits CMOS Buffer On/Off Selection 0 Off (high-impedance) 1 On Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 DCD2 — — — D8 DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR6 R63 R62 R61 R60 DCR7 R73 R72 R71 R70 Figure 29 Data Control Registers (DCD, DCR) 49 HD404849 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value — 0 0 0 — W W W Read/Write Bit name PMRB2 Not used PMRB2 PMRB1 PMRB0 PMRB0 R02/INT3 mode selection R00/INT1 mode selection 0 R02 0 R00 1 INT3 1 INT1 PMRB1 R01/INT2 mode selection 0 R01 1 INT2 Figure 30 Port Mode Register B (PMRB) Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — R/W R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R11 R11 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Inhibited TOC PWM output Bit name 1 1 0 R11/TOC mode selection 1 1 0 1 Figure 31 Timer Mode Register C2 (TMC2) 50 HD404849 Series Timer mode register B2 (TMB2: $013) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — R/W R/W Bit name Not used Not used TMB21 TMB20 TMB21 TMB20 0 0 R10 R10 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output 1 R10/TOB mode selection Figure 32 Timer Mode Register B2 (TMB2) Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R12 R12 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Inhibited TOD PWM output R12 Input capture (R12 port) 1 1 0 R12/TOD mode selection 1 1 0 1 1 Don’t care Don’t care Don’t care Figure 33 Timer Mode Register D2 (TMD2) 51 HD404849 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 W W Read/Write W Bit name PMRC3 PMRC3 W PMRC2 * PMRC1 D11/INT0 mode selection PMRC0 PMRC1 R20/EVND mode selection 0 D11 0 R20 1 INT0 1 EVND PMRC2 D10/STOPC mode selection PMRC0 R13/EVNB mode selection 0 D10 0 R13 1 STOPC 1 EVNB Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value. Figure 34 Port Mode Register C (PMRC) Serial mode register A (SMRA: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name SMRA3 SMRA3 SMRA2 SMRA1 SMRA0 R21/SCK mode selection 0 R21 1 SCK SMRA2 0 SMRA1 SMRA0 0 1 1 0 1 SCK 0 Output Prescaler ÷2048 1 Output Prescaler ÷512 0 Output Prescaler ÷128 1 Output Prescaler ÷32 0 Output Prescaler ÷8 1 Output Prescaler ÷2 0 Output System clock — 1 Input External clock — Figure 35 Serial Mode Register A (SMRA) 52 Clock source Prescaler division ratio HD404849 Series Port mode register A (PMRA: $004) Bit 3 2 Initial value — — 0 0 Read/Write — — W W Bit name 0 1 Not used Not used PMRA1 PMRA0 PMRA1 R22/SI mode selection PMRA0 R23/SO mode selection 0 R22 0 R23 1 SI 1 SO Figure 36 Port Mode Register A (PMRA) LCD output register 3 (LOR3: $01F) Bit 3 2 1 0 Initial value — 0 0 — — W W — Read/Write Bit name LOR32 Not used LOR32 LOR31 Not used R7/SEG17–SEG20 mode selection LOR31 R6/SEG13–SEG16 mode selection 0 R7 0 R6 1 SEG17–SEG20 1 SEG13–SEG16 Figure 37 LCD Output Register 3 (LOR3) Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 10 and D11 . The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 23 and figure 38). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. 53 HD404849 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R23/SO Bit name MIS3 Pull-up MOS on/off selection 0 Off 0 On 1 On 1 Off MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 38 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ. 54 HD404849 Series Prescalers The MCU has two prescalers, S and W. The prescaler operating conditions are listed in table 25, and the prescalers output supply is shown in figure 39. The timer A–D input clocks except external events, the serial transmit clock except the external clock, and the LCD controller/driver operating clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the divided X1 input clock signal (32-kHz crystal oscillation). After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W 32-kHz crystal oscillation MCU reset, software MCU reset, stop mode LCD Subsystem clock fX/8 Prescaler W Timer A Timer B fX/4 or fX/8 Timer C System clock Clock selector Prescaler S Timer D Serial interface Figure 39 Prescaler Output Supply 55 HD404849 Series Timers The MCU has four timer/counters (A to D). • • • • Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer Timer A is an 8-bit free-running timer. Timers B–D are 8-bit multifunction timers, whose functions are listed in table 26. The operating modes are selected by software. Table 26 Timer Functions Functions Clock source Timer functions Timer outputs Timer A Timer B Timer C Timer D Prescaler S Available Available Available Available Prescaler W Available — — — External event — Available — Available Free-running Available Available Available Available Time-base Available — — — Event counter — Available — Available Reload — Available Available Available Watchdog — — Available — Input capture — — — Available Toggle — Available Available Available 0 output — Available Available Available 1 output — Available Available Available PWM — — Available Available Note: — implies not available. Timer A Timer A Functions: Timer A has the following functions. • Free-running timer • Clock time-base The block diagram of timer A is shown in figure 40. 56 HD404849 Series 1/4 1/2 2 fW fW twcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow System clock ø PER ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 40 Block Diagram of Timer A Timer A Operations: • Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. • Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. • Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode and input clock source as shown in figure 41. 57 HD404849 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TMA3 TMA2 TMA1 TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 PSS 2048tcyc 1 PSS 1024tcyc 0 PSS 512tcyc 1 PSS 128tcyc 0 PSS 32tcyc 1 PSS 8tcyc 0 PSS 4tcyc 1 PSS 2tcyc 0 PSW 32tWcyc 1 PSW 16tWcyc 0 PSW 8tWcyc 1 PSW 2tWcyc 0 PSW 1/2tWcyc 1 Inhibited Don’t care Timer A mode Time-base mode PSW and TCA reset Note: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) 256. 3. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts × (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the program to the minimum. 4. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 41 Timer Mode Register A (TMA) 58 HD404849 Series Timer B Timer B Functions: Timer B has the following functions. • Free-running/reload timer • External event counter • Timer output operation (toggle, 0, and 1 outputs) The block diagram of timer B is shown in figure 42. Timer B interrupt request flag (IFTB) Timer output control logic TOB Timer read register BU (TRBU) Timer output control Timer read register BL (TRBL) Clock System clock ø PER ÷ 2048 EVNB ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 Selector Timer write register BU (TWBU) Prescaler S (PSS) Free-running/ Reload control Timer write register BL (TWBL) Internal data bus Timer counter B (TCB) Overflow 3 Timer mode register B1 (TMB1) 2 Timer mode register B2 (TMB2) Figure 42 Block Diagram of Timer B 59 HD404849 Series Timer B Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R13/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operations are basically the same as the free-running/reload timer operation. • Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R10/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 43 (1). 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low. 60 HD404849 Series (1) Toggle output waveform (timers B, C, and D) Free-running timer 256 clock cycles 256 clock cycles (256 – N) clock cycles (256 – N) clock cycles Reload timer (2) PWM output waveform (timers C and D) T × (N + 1) TMC13 = 0 TMD13 = 0 (free-running timer setting) T T × 256 TMC13 = 1 TMD13 = 1 (reload timer setting) T × (256 – N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (the clock source and frequency division ratio are controlled in timer mode registers B1, C1, and D1) N: The value in timer write registers C and D Figure 43 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) • Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 44. It is reset to $0 by MCU reset. 61 HD404849 Series Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-running/reload timer selection TMB12 TMB11 TMB10 0 Free-running timer 0 0 0 2048tcyc 1 Reload timer 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R13/EVNB (external event input) 1 1 0 1 Input clock period and input clock source Figure 44 Timer Mode Register B1 (TMB1) Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. A timer B initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be programmed to occur after a mode change becomes valid. • Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 45. It is reset to $0 by MCU reset. Timer mode register B2 (TMB2: $013) Bit 3 2 1 0 Initial value — — 0 0 TMB21 TMB20 Read/Write — — R/W R/W 0 0 R10 R10 port 1 TOB Toggle output 0 TOB 0 output 1 TOB 1 output Bit name Not used Not used TMB21 TMB20 1 R10/TOB mode selection Figure 45 Timer Mode Register B2 (TMB2) • Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit (TWBL) and upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit value cannot be guaranteed. See figures 46 and 47. 62 HD404849 Series Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B. Timer write register B (lower digit) (TWBL: $00A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWBL3 TWBL2 TWBL1 TWBL0 Bit name Figure 46 Timer Write Register B Lower Digit (TWBL) Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWBU3 TWBU2 TWBU1 TWBU0 Figure 47 Timer Write Register B Upper Digit (TWBU) • Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of a lower digit (TRBL) and upper digit (TRBU) that holds the count of the timer B upper digit. See figures 48 and 49. The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU was read can be obtained. Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBL3 TRBL2 TRBL1 TRBL0 Figure 48 Timer Read Register B Lower Digit (TRBL) 63 HD404849 Series Timer read register B (upper digit) (TRBU: $00B) Bit 3 Initial value Read/Write Bit name 2 1 0 Undefined Undefined Undefined Undefined R R R R TRBU3 TRBU2 TRBU1 TRBU0 Figure 49 Timer Read Register B Upper Digit (TRBU) • Port mode register C (PMRC: $025): Write-only register that selects R13/EVNB pin function as shown in figure 50. It is reset to $0 by MCU reset. Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write Bit name PMRC3 W PMRC3 PMRC2 PMRC1 PMRC0 D11/INT0 mode selection PMRC1 R20/EVND mode selection 0 D11 0 R20 1 INT0 1 EVND PMRC2 D10/STOPC mode selection PMRC0 R13/EVNB mode selection 0 D10 0 R13 1 STOPC 1 EVNB Figure 50 Port Mode Register C (PMRC) Timer C Timer C Functions: Timer C has the following functions. • Free-running/reload timer • Watchdog timer • Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 51. 64 HD404849 Series System reset signal Watchdog on flag (WDON) TOC Timer C interrupt request flag (IFTC) Watchdog timer control logic Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Timer counter C (TCC) Timer write register CU (TWCU) ÷2 ÷4 ÷8 ÷32 ÷128 ÷512 ÷1024 ÷2048 Selector System ø PER clock Prescaler S (PSS) Overflow Free-running /Reload control Timer write register CL (TWCL) Internal data bus Clock 3 Timer mode register C1 (TMC1) 3 Timer mode register C2 (TMC2) Figure 51 Block Diagram of Timer C 65 HD404849 Series Timer C Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program runaway can be controlled by initializing timer C by software before it reaches $FF. • Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R11/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B’s toggle output. 0 output: The operation is basically the same as that of timer-B’s 0 output. 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 43 (2). Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) • Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 52. It is reset to $0 by MCU reset. 66 HD404849 Series Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. A timer C initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be programmed to occur after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name TMC13 W W W W TMC13 TMC12 TMC11 TMC10 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period TMC12 TMC11 TMC10 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Figure 52 Timer Mode Register C1 (TMC1) • Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 53. It is reset to $0 by MCU reset. 67 HD404849 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value — 0 0 0 Read/Write — R/W R/W R/W Not used TMC22 TMC21 TMC20 TMC22 TMC21 TMC20 0 0 0 R11 R11 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 — Inhibited TOC PWM output Bit name 1 1 0 R11/TOC mode selection 1 0 1 1 Figure 53 Timer Mode Register C2 (TMC2) • Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and upper digit (TWCU). See figures 54 and 55. The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 54 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 55 Timer Write Register C Upper Digit (TWCU) 68 HD404849 Series • Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and upper digit (TRCU) that holds the count of the timer C upper digit. See figures 56 and 57. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 56 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 57 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. • • • • Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 58-1 and 58-2. 69 HD404849 Series Timer D interrupt request flag (IFTD) Timer output control logic TOD Timer read register DU (TRDU) Timer output control Timer read register DL (TRDL) Clock Timer write register DU (TWDU) System clock ø PER ÷2048 Edge detection logic ÷2 ÷4 ÷8 ÷32 ÷128 ÷512 Selector EVND Overflow Free-running/ reload control Timer write register DL (TWDL) 3 Prescaler S (PSS) Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 58-1 Block Diagram of Timer D (in Reload Timer and Event Counter Mode) 70 Internal data bus Timer counter D (TCD) HD404849 Series Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD) Error control logic Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Timer counter D (TCD) Overflow Selector System clock ÷2048 ÷2 ÷4 ÷8 ÷32 ÷128 ÷512 3 Timer mode register D1 (TMD1) Internal data bus Input capture timer control ø PER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2) Figure 58-2 Block Diagram of Timer D (in Input Capture Timer Mode) 71 HD404849 Series Timer D Operations: • Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. • External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R20/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operations are basically the same as the free-running/reload timer operation. • Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R12/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B’s toggle output. 0 output: The operation is basically the same as that of timer-B’s 0 output. 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: The operation is basically the same as that of timer-C’s PWM output. • Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. 72 HD404849 Series By selecting the input capture operation, pin R1 2/TOD is set to R1 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) • Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and prescaler division ratio as shown in figure 59. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. A timer D initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be programmed to occur after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source. 73 HD404849 Series Timer mode register D1 (TMD1: $010) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMD13 TMD12 TMD11 TMD10 Bit name TMD13 Free-running/reload timer selection 0 Free-running timer 1 Reload timer Input clock period and input clock source TMD12 TMD11 TMD10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 R20/EVND (external event input) 1 1 0 1 Figure 59 Timer Mode Register D1 (TMD1) • Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset. 74 HD404849 Series Timer mode register D2 (TMD2: $015) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD22 TMD21 TMD20 TMD23 TMD22 TMD21 TMD20 0 0 0 0 R12 R12 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 — Inhibited TOD PWM output R12 Input capture (R12 port) Bit name 1 1 0 R12/TOD mode selection 1 1 0 1 1 Don’t care Don’t care Don’t care Figure 60 Timer Mode Register D2 (TMD2) • Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and upper digit (TWDU). See figures 61 and 62. The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). Timer write register D (lower digit) (TWDL: $011) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W TWDL3 TWDL2 TWDL1 TWDL0 Figure 61 Timer Write Register D Lower Digit (TWDL) Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWDU3 TWDU2 TWDU1 TWDU0 Figure 62 Timer Write Register D Upper Digit (TWDU) 75 HD404849 Series • Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and upper digit (TRDU). See figures 63 and 64. The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDL3 TRDL2 TRDL1 TRDL0 Figure 63 Timer Read Register D Lower Digit (TRDL) Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRDU3 TRDU2 TRDU1 TRDU0 Figure 64 Timer Read Register D Upper Digit (TRDU) • Port mode register C (PMRC: $025): Write-only register that selects R20/EVND pin function as shown in figure 50. It is reset to $0 by MCU reset. • Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset. 76 HD404849 Series Detection edge register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 — — W — — Read/Write Bit name W ESR23 ESR22 Not used Not used ESR23 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Double-edge detection* 1 EVND detection edge Note: * Both falling and rising edges are detected. Figure 65 Detection Edge Select Register 2 (ESR2) Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. 77 HD404849 Series Table 27 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T × (255 – N) T × (N + 1) Interrupt request T × (N' + 1) T × (255 – N) Reload Timer write register updated to value N T Interrupt request T × (255 – N) T Timer write register updated to value N Interrupt request T T × (255 – N) 78 T × (N + 1) T HD404849 Series Serial Interface The serial interface serially transfers and receives 8-bit data, and includes the following features. • Multiple transmit clock sources External clock Internal prescaler output clock System clock • Output level control in idle states Five registers, an octal counter are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 66. 79 HD404849 Series Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Transfer control signal Selector 1/2 Internal data bus Serial data register (SR) Selector ÷2 ÷8 ÷32 ÷128 ÷512 ÷2048 3 System clock øPER Serial mode register A (SMRA) Prescaler S (PSS) Serial mode register B (SMRB) Figure 66 Block Diagram of Serial Interface Serial Interface Operation Selecting and Changing the Operating Mode: Table 28 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register A. Note that the serial interface is initialized by writing data to serial mode register A. Refer to the following Serial Mode Register A section for details. Table 28 Serial Interface Operating Modes SMRA PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Clock continuous output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 80 HD404849 Series Pin Setting: The R21/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The R2 2/SI and R23/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Serial data is set by writing data to the serial data register (SRL: $006, SRU, $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO pin remains unsettled until the first data is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SMRA0– SMRA2) of serial mode register A (SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) as listed in table 29. Table 29 Serial Transmit Clock (Prescaler Output) SMRB SMRA Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency 0 0 0 0 ÷ 2048 4096t cyc 1 ÷ 512 1024t cyc 0 ÷ 128 256t cyc 1 ÷ 32 64t cyc 0 ÷8 16t cyc 1 ÷2 4t cyc 0 ÷ 4096 8192t cyc 1 ÷ 1024 2048t cyc 0 ÷ 256 512t cyc 1 ÷ 64 128t cyc 0 ÷ 16 32t cyc 1 ÷4 8t cyc 1 1 1 0 0 0 1 1 0 81 HD404849 Series Operating States: The serial interface has the following operating states; transitions between them are shown in figure 67. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode) • STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. • Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state. However, note that if clock continuous output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters clock continuous output state (17). The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04, 14) in transmit clock wait state. • Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set by the octal counter that is reset to 000. • Clock continuous output state (only in internal clock mode): Clock continuous output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters clock continuous output state. If serial mode register A (SMRA: $005) is written to in clock continuous output mode (18), STS wait state is entered. 82 HD404849 Series External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMRA write 00 MCU reset 06 SMRA write (IFS ← 1) 04 01 STS instruction 02 Transmit clock Transmit clock wait state (Octal counter = 000) 03 8 transmit clocks Transfer state (Octal counter = 000) 05 STS instruction (IFS ← 1) Internal clock mode SMRA write 18 Clock continuous output state (PMRA 0, 1 = 00) STS wait state (Octal counter = 000, transmit clock disabled) 13 SMRA write 14 11 Transmit clock 10 STS instruction MCU reset 8 transmit clocks 16 SMRA write (IFS ←1) 17 12 Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 15 STS instruction (IFS ← 1) Note: Refer to the Operating States section for the corresponding encircled numbers. Figure 67 Serial Interface State Transitions Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB: $028) to 0 or 1. The output level control example is shown in figure 68. Note that the output level cannot be controlled in transfer state. 83 , HD404849 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMRA write Output level control in idle states Dummy write for state transition Output level control in idle states SMRB write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMRA write Output level control in idle states SMRB write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 68 Example of Serial Interface Operation Sequence 84 HD404849 Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 69. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. 85 HD404849 Series Transfer completion (IFS1 ← 1) Interrupts inhibited IFS1 ← 0 SM1A write Yes IFS1 = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State SCK pin (input) 1 2 Transfer state Noise 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMRA is written, IFS is set. SMRA write IFS Flag set because octal counter reaches 000 Transmit clock error detection procedures Figure 69 Transmit Clock Error Detection 86 Flag reset at transfer completion HD404849 Series Notes on Use: • Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register A (SMRA: $005) again. • Setting the serial interrupt request flag (IFS: $023, bit 2): If the state is changed from transfer to another by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register A write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R2. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register A (SMRA: $005) Serial Mode Register B (SMRB: $028) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register A (SMRA: $005): This register has the following functions (figure 70). • • • • R2 1/SCK pin function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the data transfer is discontinued and the serial interrupt request flag (IFS: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after a write operation, so the STS instruction must be executed at least two cycles after a write operation. 87 HD404849 Series Serial mode register A (SMRA: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name SMRA3 SMRA3 SMRA2 SMRA1 SMRA0 R21/SCK mode selection 0 R21 1 SCK SMRA2 0 SMRA1 SMRA0 0 SCK Clock source Output Prescaler Refer to table 29 0 Output System clock — 1 Input External clock — 0 1 1 Prescaler division ratio 0 1 1 0 0 1 1 Figure 70 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: $028): This register has the following functions (figure 71). • Prescaler division ratio selection • Output level control in idle states Serial mode register B (SMRB: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can be reset to 0 by MCU reset. Bit 1 (SMRB1) is used to control the output level of the SO pin in idle states. The output level changes at the same time that SMRB1 is written to. 88 HD404849 Series Serial mode register B (SMRB: $028) Bit 3 2 1 0 Initial value — — Undefined 0 Read/Write — — W W Bit name Not used Not used SMRB1 SMRB1 Output level control in idle states SMRB0 SMRB0 Transmit clock division ratio 0 Low level 0 Prescaler output divided by 2 1 High level 1 Prescaler output divided by 4 Figure 71 Serial Mode Register B (SMRB) Serial Data Register (SRL: $006, SRU: $007): The serial data register configuration is shown in figures 72 and 73. This register has the following functions. • Transmission data write and shift • Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 74. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed. Serial data register (lower digit) (SRL: $006) Bit 3 Initial value 2 1 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR3 SR2 SR1 SR0 Figure 72 Serial Data Register (SRL) 89 HD404849 Series Serial data register (upper digit) (SRU: $007) Bit Initial value 1 2 3 0 Undefined Undefined Undefined Undefined Read/Write R/W R/W R/W R/W Bit name SR7 SR6 SR5 SR4 Figure 73 Serial Data Register (SRU) Transmit clock 1 Serial output data 2 3 4 5 6 LSB 7 8 MSB Serial input data latch timing Figure 74 Serial Interface Input/Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 75). • R2 2/SI pin function selection • R2 3/SO pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset. Port mode register A (PMRA: $004) Bit 3 2 Initial value — — 0 0 Read/Write — — W W Bit name PMRA1 1 0 Not used Not used PMRA1 PMRA0 R22/SI mode selection PMRA0 R23/SO mode selection 0 R22 0 R23 1 SI 1 SO Figure 75 Port Mode Register A (PMRA) 90 HD404849 Series Miscellaneous Register (MIS: $00C): This register has the following function (figure 76). • R2 3/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 Pull-up MOS on/off selection 0 Off 1 On MIS2 On 1 Off MIS0 0 0 tRC* 0.12207 ms 0.24414 ms R23/SO PMOS on/off selection 0 MIS1 1 1 7.8125 ms 0 31.25 ms 1 Not used Note: * Refer to figure 18. Figure 76 Miscellaneous Register (MIS) 91 HD404849 Series A/D Converter The MCU has a built-in A/D converter that uses successive approximations with a resistor ladder. It can measure eight analog inputs with 8-bit resolution. As shown in the block diagram of figure 77, the A/D converter has a 4-bit A/D mode register, a 4-bit plus 4-bit A/D data register, a 1-bit A/D start flag, and a 1bit A/D current off flag. Interrupt flag (IFAD) A/D data register (ADRU, ADRL) Encoder 3 AN1 A/D mode register (AMR) AN3 R30 /AN4 Selector AN2 + R31 /AN5 COMP R32 /AN6 A/D control logic – R33 /AN7 Conversion time control Reference voltage AVCC A/D start flag (ADSF) Reference voltage control AVSS D/A HLT (1 in stop, watch, and subactive modes) A/D current off flag (IAOF) Figure 77 Block Diagram of A/D Converter 92 Internal data bus AN0 HD404849 Series A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 1 to 3 select a channel, as shown in figure 78. A/D mode register (AMR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W AMR3 AMR2 AMR1 AMR0 Analog input selection AMR3 AMR2 AMR1 0 0 0 AN0 0 34tcyc 0 1 0 AN1 1 67tcyc 1 0 0 AN2 1 1 0 AN3 0 0 1 AN4 0 1 1 AN5 1 0 1 AN6 1 1 1 AN7 AMR0 Conversion time Figure 78 A/D Mode Register (AMR) 93 HD404849 Series A/D Data Register (ADRL: $017, ADRU: $018): 8-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. Any data read during A/D conversion is not guaranteed. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 79, 80, and 81). ADRU: $018 3 2 ADRL: $017 1 0 3 2 1 MSB LSB Bit 7 Bit 0 Figure 79 A/D Data Registers A/D data register (lower digit) (ADRL: $017) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name R R R R ADRL3 ADRL2 ADRL1 ADRL0 Figure 80 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit 3 2 1 0 Initial value 1 0 0 0 Read/Write R R R R ADRU3 ADRU2 Bit name ADRU1 ADRU0 Figure 81 A/D Data Register Upper Digit (ADRU) 94 0 RESULT HD404849 Series A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 82. A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W DTON ADSF WDON LSON Bit name DTON WDON Refer to the description of operating modes Refer to the description of timers LSON ADSF (A/D start flag) 1 A/D conversion started 0 A/D conversion completed Refer to the description of operating modes Figure 82 A/D Start Flag (ADSF) A/D Current Off Flag (IAOF: $021, Bit 2): By setting this 1-bit flag to 1, the current flowing through the ladder resistor of the A/D converter is cut off during standby and active modes. See figure 83. 95 HD404849 Series A/D current off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name RAME Refer to description of operating modes IAOF (A/D current off flag) 1 Current IAD is cut off. 0 Current IAD flows. ICEF Refer to description of timers ICSF Refer to description of timers Figure 83 A/D Current Off Flag (IAOF) Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed. The A/D converter does not operate in the stop, watch, and subactive modes because it relies on the clock from OSC, which is stopped in these modes. During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input. The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up. 96 HD404849 Series LCD Controller/Driver The MCU has an LCD controller and driver which drive 4 common signal pins and 32 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR: $01B), and a duty-cycle/clock-control register (LMR: $01C) (figure 84). Four duty cycles and the LCD clock are programmable, and a built-in dual-port RAM ensures that display data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz oscillation clock is selected as the LCD clock source, the LCD can even be used in watch mode, in which the system clock stops. 97 HD404849 Series VCC LCD power switch V1 V2 LCD power control circuit LCD control register (LCR) V3 LCD output register 3 (LCR3) COM1 LCD common driver COM2 COM3 COM4 R60/SEG13 R61/SEG14 R73/SEG20 SEG21 Pin function control circuit 2 Pin control Display 2 control 32 Display data 2 Duty cycle selection Display dual-port RAM (32 digits) LCD segment driver Selector 2 SEG43 SEG44 LCD input clock LCD mode register (LMR) Figure 84 Block Diagram of LCD Controller/Driver 98 Internal data bus GND HD404849 Series LCD Data Area and Segment Data ($05C–$07B): As shown in figure 85, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data. Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 92 SEG13 SEG13 SEG13 SEG13 $05C 108 SEG29 SEG29 SEG29 SEG29 $06C 93 SEG14 SEG14 SEG14 SEG14 $05D 109 SEG30 SEG30 SEG30 SEG30 $06D 94 SEG15 SEG15 SEG15 SEG15 $05E 110 SEG31 SEG31 SEG31 SEG31 $06E 95 SEG16 SEG16 SEG16 SEG16 $05F 111 SEG32 SEG32 SEG32 SEG32 $06F 96 SEG17 SEG17 SEG17 SEG17 $060 112 SEG33 SEG33 SEG33 SEG33 $070 97 SEG18 SEG18 SEG18 SEG18 $061 113 SEG34 SEG34 SEG34 SEG34 $071 98 SEG19 SEG19 SEG19 SEG19 $062 114 SEG35 SEG35 SEG35 SEG35 $072 99 SEG20 SEG20 SEG20 SEG20 $063 115 SEG36 SEG36 SEG36 SEG36 $073 100 SEG21 SEG21 SEG21 SEG21 $064 116 SEG37 SEG37 SEG37 SEG37 $074 101 SEG22 SEG22 SEG22 SEG22 $065 117 SEG38 SEG38 SEG38 SEG38 $075 102 SEG23 SEG23 SEG23 SEG23 $066 118 SEG39 SEG39 SEG39 SEG39 $076 103 SEG24 SEG24 SEG24 SEG24 $067 119 SEG40 SEG40 SEG40 SEG40 $077 104 SEG25 SEG25 SEG25 SEG25 $068 120 SEG41 SEG41 SEG41 SEG41 $078 105 SEG26 SEG26 SEG26 SEG26 $069 121 SEG42 SEG42 SEG42 SEG42 $079 106 SEG27 SEG27 SEG27 SEG27 $06A 122 SEG43 SEG43 SEG43 SEG43 $07A 107 SEG28 SEG28 SEG28 SEG28 $06B 123 SEG44 SEG44 SEG44 SEG44 $07B COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1 Figure 85 Configuration of LCD RAM Area (for Dual-Port RAM) 99 HD404849 Series LCD Control Register (LCR: $01B): Four-bit write-only register which controls LCD blanking, on/off switching of the liquid-crystal display’s power supply division resistor, display in watch and subactive modes, and connection of the LCD division resistor, as shown in figure 86. • Blank/display Blank: Segment signals are turned off, regardless of LCD RAM data setting. Display: LCD RAM data is output as segment signals. • Power switch on/off Off: The power switch is off. On: The power switch is on and V1 is VCC. • Watch/subactive mode display Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. On: In watch and subactive modes, LCD RAM data is output as segment signals. • LCD power supply division resistor switch Off: Division resistor is disconnected. On: Division resistor is connected. LCD display control register (LCR: $01B) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W LCR3 LCR2 LCR1 LCR0 Bit name LCR3 LCD power supply division resistor switch 0 On 1 Off LCR2 Display on/off selection in watch and subactive modes 0 Off 1 On LCR1 Power switch on/off 0 Off 1 On LCR0 Blank/display 0 Blank 1 Display Figure 86 LCD Control Register (LCR) 100 HD404849 Series LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in figure 87. The dependence of frame frequency on duty cycle is listed in table 30. LCD duty cycle/clock control register (LMR: $01C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W LMR3 LMR2 LMR1 LMR0 LMR3 LMR2 0 0 CL0 (32.768 × duty/64: when 32.768-kHz oscillation is used) 0 1 CL1 (fOSC × duty cycle/1024) 1 0 CL2 (fOSC × duty cycle/8192) 1 1 CL3 (refer to table 29) LMR1 LMR0 Duty cycle selection 0 0 1/4 duty 0 1 1/3 duty 1 0 1/2 duty 1 1 Static Bit name Input clock source selection Figure 87 LCD Duty-Cycle/Clock Control Register (LMR) 101 HD404849 Series Table 30 LCD Frame Frequencies for Different Duty Cycles Frame Frequencies fOSC = 400 kHz fOSC = 800 kHZ fOSC = 2 MHz fOSC = 4 MHz CL0 512 Hz 512 Hz 512 Hz 512 Hz 1 CL1 390.6 Hz 781.3 Hz 1953 Hz 3906 Hz 0 CL2 48.8 Hz 97.7 Hz 244.1 Hz 488.3 Hz 1 CL3* 24.4 Hz 48.8 Hz 122.1 Hz 244.1 Hz 64 Hz 64 Hz 64 Hz 64 Hz Duty Cycle LMR3 LMR2 Static 0 0 1 1/2 0 1 1/3 0 1 1/4 0 1 0 CL0 256 Hz 256 Hz 256 Hz 256 Hz 1 CL1 195.3 Hz 390.6 Hz 976.6 Hz 1953 Hz 0 CL2 24.4 Hz 48.8 Hz 122.1 Hz 244.1 Hz 1 CL3* 12.2 Hz 24.4 Hz 61 Hz 122.1 Hz 32 Hz 32 Hz 32 Hz 32 Hz 0 CL0 170.7 Hz 170.7 Hz 170.7 Hz 170.7 Hz 1 CL1 130.2 Hz 260.4 Hz 651 Hz 1302 Hz 0 CL2 16.3 Hz 32.6 Hz 81.4 Hz 162.8 Hz 1 CL3* 8.1 Hz 16.3 Hz 40.7 Hz 81.4 Hz 21.3 Hz 21.3 Hz 21.3 Hz 21.3 Hz 0 CL0 128 Hz 128 Hz 128 Hz 128 Hz 1 CL1 97.7 Hz 195.3 Hz 488.3 Hz 976.6 Hz 0 CL2 12.2 Hz 24.4 Hz 61 Hz 122.1 Hz 1 CL3* 6.1 Hz 12.2 Hz 30.5 Hz 61 Hz 16 Hz 16 Hz 16 Hz 16 Hz Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA). Upper value: When TMA3 = 0, CL3 = f OSC × duty cycle/16384. Lower value: When TMA3 = 1, CL3 = 32.768 kHz × duty cycle/512. LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R6 and R7 as pins SEG13–SEG20 in 4-pin units (figure 88). 102 HD404849 Series LCD output register 3 (LOR3: $01F) Bit 3 2 1 0 Initial value — 0 0 — — W W — Read/Write Bit name LOR32 Not used LOR32 LOR31 Not used R7/SEG17–SEG20 mode selection LOR31 R6/SEG13–SEG16 mode selection 0 R7 0 R6 1 SEG17–SEG20 1 SEG13–SEG16 Figure 88 LCD Output Register 3 (LOR3) Large Liquid-Crystal Panel Drive and VLCD: If the capacitance of the LCD is very large while being driven, decrease the capacitance by attaching external resistors in parallel, as shown in figure 89. The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix configuration of the LCD complicates the paths of charge/discharge currents flowing through the capacitors—the resistance will also vary with lighting conditions. This size must be determined by trialand-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10 kΩ is usually suitable. (Another effective method is to attach capacitors of 0.1 to 0.3 µF.) Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (VLCD). 103 HD404849 Series VCC (V 1 ) VCC (V 1 ) R R C V2 V2 R R V3 V3 C C R R GND GND VCC VCC VLCD COM1 1 . V1 V2 SEG13 to V3 SEG44 GND 4-digit LCD 32 Static drive VCC VCC VLCD COM1 COM2 2 . V1 V2 SEG13 to V3 SEG44 GND 8-digit LCD 32 1/2 duty, 1/2 bias drive VCC VLCD VCC COM1 to COM3 V1 V2 SEG13 to V3 GND SEG44 3 . 10-digit LCD with sign 32 1/3 duty, 1/3 bias drive VCC VCC ≥ V LCD ≥ GND VLCD VCC COM1 to COM4 V1 V2 SEG13 to V3 GND SEG44 4 . 32 1/4 duty, 1/3 bias drive Figure 89 LCD Connection Examples 104 16-digit LCD HD404849 Series Programmable ROM (HD4074849) The HD4074849 is a ZTAT ™ microcomputer with built-in PROM that can be programmed in PROM mode. Pin Description by Mode Pin No. MCU Mode PROM Mode Pin No MCU Mode PROM Mode FP-80A, TFP- 80C FP-80B Pin Name I/O FP- 80A, Pin Name I/O TFP-80C FP-80B Pin Name I/O Pin Name I/O 1 3 R3 2/AN6 I/O A3 I 28 30 R1 2/TOD I/O A7 I 2 4 R3 3/AN7 I/O A4 I 29 31 R1 3/EVNB I/O A8 I 3 5 AVSS 30 32 R2 0/EVND I/O A0 I 4 6 TEST I TEST 31 33 R2 1/SCK I/O O0 I/O 5 7 OSC 1 I VCC 32 34 R2 2/SI I/O O1 I/O 6 8 OSC 2 O 33 35 R2 3/SO I/O O2 I/O 7 9 RESET I RESET 34 36 R6 0/SEG13 I/O O3 I/O 8 10 X1 I GND 35 37 R6 1/SEG14 I/O O4 I/O 9 11 X2 O 36 38 R6 2/SEG15 I/O O4 I/O 10 12 GND 37 39 R6 3/SEG16 I/O O3 I/O 11 13 D0 I/O CE I 38 40 R7 0/SEG17 I/O O2 I/O 12 14 D1 I/O OE I 39 41 R7 1/SEG18 I/O O1 I/O 13 15 D2 I/O VCC 40 42 R7 2/SEG19 I/O O0 I/O 14 16 D3 I/O VCC 41 43 R7 3/SEG20 I/O VCC 15 17 D4 I/O A10 I 42 44 SEG21 O 16 18 D5 I/O A11 I 43 45 SEG22 O 17 19 D6 I/O A12 I 44 46 SEG23 O 18 20 D7 I/O A13 I 45 47 SEG24 O 19 21 D8 I/O A14 I 46 48 SEG25 O 20 22 D10/STOPC I A9 I 47 49 SEG26 O 21 23 D11/INT0 I VPP 48 50 SEG27 O 22 24 R0 0/INT1 I/O M0 I 49 51 SEG28 O 23 25 R0 1/INT2 I/O M1 I 50 52 SEG29 O 24 26 R0 2/INT3 I/O 51 53 SEG30 O 25 27 R0 3 I/O 52 54 SEG31 O 26 28 R1 0/TOB I/O A5 I 53 55 SEG32 O 27 29 R1 1/TOC I/O A6 I 54 56 SEG33 O GND I I GND 105 HD404849 Series Pin No. MCU Mode PROM Mode FP-80A, TFP- 80C FP-80B Pin Name I/O Pin No FP- 80A, Pin Name I/O TFP-80C MCU Mode PROM Mode FP-80B Pin Name I/O Pin Name I/O 55 57 SEG34 O 68 70 COM3 O 56 58 SEG35 O 69 71 COM4 O 57 59 SEG36 O 70 72 V1 58 60 SEG37 O 71 73 V2 59 61 SEG38 O 72 74 V3 60 62 SEG39 O 73 75 VCC VCC 61 63 SEG40 O 74 76 AVCC VCC 62 64 SEG41 O 75 77 AN0 I 63 65 SEG42 O 76 78 AN1 I 64 66 SEG43 O 77 79 AN2 I 65 67 SEG44 O 78 80 AN3 I 66 68 COM1 O 79 1 R3 0/AN4 I/O A1 I 67 69 COM2 O 80 2 R3 1/AN5 I/O A2 I Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0–O4 has two pins; before using, each pair must be connected together. PROM Mode Pin Functions VPP: Applies the programming voltage (12.5 V ± 0.3 V) to the built-in PROM. CE : Inputs a control signal to enable PROM programming and verification. OE : Inputs a data output control signal for verification. A0–A14: Act as address input pins of the built-in PROM. O0–O4: Act as data bus input pins of the built-in PROM. Each of O0–O4 has two pins; before using these pins, connect each pair together. M0, M1, RESET, TEST: Used to set PROM mode. The MCU is set to PROM mode by pulling M0, M1, and RESET low, and TEST high. Other Pins: Connect pins AVCC, OSC 1, D2, D3, R73/SEG20, and V CC to VCC. Connect pins AVSS and X1 to GND. Leave other pins open. Programming the Built-In PROM The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0, and M1 low, and TEST high. In PROM mode, the MCU does not operate, but it can be programmed in the 106 HD404849 Series same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 80-to28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 31. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. As shown in figure 90, this circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000–$7FFF) must be specified. Table 31 Recommended PROM Programmers and Socket Adapters PROM Programmer Manufacturer Model name DATA I/O Corp. 121B 29B AVAL Corp. PKW–1000 Socket Adapter Package Model Name Manufacturer FP-80A HS4849ESH01H Hitachi FP-80B HS4849ESF01H TFP-80C HS4849ESN01H Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package version cannot be erased and reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP ): 12.5 V and 21 V. Remember that Hitachi devices require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage to data reliability. 107 HD404849 Series Programming and verification modes are selected as listed in table 32, the memory map in PROM mode is shown in figure 90. Table 32 PROM Mode Selection Pin Mode CE OE VPP O0–O4 Programming Low High VPP Data input Verification High Low VPP Data output Programming inhibited High High VPP High impedance $0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 $1FFF $2000 Program (16,384 words) $3FFF $7FFF Upper three bits are not to be used (fill them with 111) Figure 90 Memory Map in PROM Mode 108 HD404849 Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 91 and described below. W register W1 W0 RAM address X register X3 X2 X1 Y register X0 Y3 Y2 Y1 Y0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Register Indirect Addressing 1st word of Instruction Opcode 2nd word of Instruction d RAM address 9 d8 d7 d6 d5 d4 d3 d2 d1 d0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Direct Addressing Instruction Opcode 0 RAM address 0 0 1 m3 m2 0 m1 m0 0 AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0 Memory Register Addressing Figure 91 RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register (V: $03F). Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. 109 HD404849 Series Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 92 and described below. 1st word of instruction [JMPL] [BRL] [CALL] Opcode p3 Program counter 2nd word of instruction p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Program counter Opcode b7 b6 b5 b4 b3 b2 b1 b0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 Program counter 0 0 0 d5 Opcode 0 0 0 d4 d3 d2 d1 d0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction [TBR] Opcode p3 p2 p1 p0 B register B3 0 Program counter B0 A3 A2 A1 A0 0 PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Table Data Addressing Figure 92 ROM Addressing Modes 110 B2 B1 Accumulator HD404849 Series Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 94. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Instruction [P] Opcode p3 p2 p1 p0 B register B3 0 B2 B1 Accumulator B0 A3 A2 A1 A0 0 Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Accumulator, B register ROM data B3 B2 B1 B0 A3 A 2 A1 A 0 If RO 8 = 1 RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0 Output registers R1, R2 R2 3 R22 R21 R20 R13 R12 R11 R1 0 If RO 9 = 1 Pattern Output Figure 93 P Instruction 111 HD404849 Series 256 (n – 1) + 255 BR AAA 256n AAA BBB 256n + 254 256n + 255 256 (n + 1) NOP BR BR BBB AAA NOP Figure 94 Branching when the Branch Destination is on a Page Boundary Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000– $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC 5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of fourbit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 93. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter. 112 HD404849 Series Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V Pin voltage VT –0.3 to VCC + 0.3 V Total permissible input current ∑Io 100 mA 2 Total permissible output current –∑Io 50 mA 3 Maximum input current Io 4 mA 4, 5 30 mA 4, 6 7, 8 Maximum output current –I o 4 mA Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes 1 Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 11 (VPP) of the HD4074849. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to R0–R3, R6, and R7. 6. Applies to D 0–D 8. 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 0–D 8, R0–3, R6, and R7. 113 HD404849 Series Electrical Characteristics DC Characteristics (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, T a = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH RESET, SCK, SI, INT0, INT1, INT2, INT3, STOPC, EVNB, EVND 0.9V CC — VCC + 0.3 V — OSC 1 VCC – 0.3 — VCC + 0.3 V External clock operation RESET, SCK, SI, INT0, INT1, INT2, INT3, STOPC, EVNB, EVND –0.3 — 0.1V CC V — OSC 1 –0.3 — 0.3 V External clock operation Input low voltage VIL Notes Output high voltage VOH SCK, SO, TOB, TOC, TOD VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL SCK, SO, TOB, TOC, TOD — — 0.4 V I OL = 0.4 mA I/O leakage current |IIL| RESET, SCK, SI, INT0, INT1, INT2, INT3, STOPC, EVNB, EVND, OSC 1, TOB, TOC, TOD, SO — — 1.0 µA Vin = 0 V to VCC 1 Current I CC1 dissipation in active mode VCC — 3 6 mA VCC = 5.0 V, f OSC = 4 MHz 2 I CC2 VCC — 0.6 1.8 mA VCC = 3.0 V, f OSC = 800 kHz 2 I SBY1 Current dissipation in standby mode VCC — 1.0 2.0 mA VCC = 5.0 V, f OSC = 4 MHz, 3 I SBY2 VCC 114 LCD on — 0.2 0.7 mA VCC = 3.0 V, f OSC = 800 kHz LCD on 3 HD404849 Series Item Symbol I SUB Current dissipation in subactive mode Pin(s) Min Typ Max Unit Test Condition Notes VCC — 25 50 µA VCC = 3.0 V, LCD on 4, 7, 8 — 35 70 µA VCC = 3.0 V, LCD on 5, 7, 8 — 70 150 µA VCC = 3.0 V, LCD on 6, 7, 8 Current I WTC1 dissipation in watch mode VCC — 15 40 µA VCC = 3.0 V, LCD on 8 I WTC2 VCC — 5 10 µA VCC = 3.0 V, LCD off 8 Current I STOP dissipation in stop mode VCC — — 5 µA VCC = 3.0 V 8 no 32-kHz oscillator Stop mode retaining voltage VCC 1.5 — — V No 32-kHz oscillator 9 VSTOP Notes: 1. Output buffer current is excluded. 2. I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET and TEST at GND 3. I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at V CC TEST at GND D0–D 8, D10, D11, R0–R3, R6, R7 at V CC 4. Applies to HD404848. 5. Applies to HD4048412 and HD404849. 6. Applies to HD4074849. 7. When the LCD power supply division resistor is connected (LCR3 = 0). 8. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at V CC TEST at GND D0–D 8, D10, D11, R0–R3, R6, R7 at V CC 9. Test condition voltage necessary for RAM data retention. 115 HD404849 Series I/O Characteristics for Standard Pins (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074849: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Input high voltage VIH D10, D11, R0–R3, R6, R7 0.7V CC — VCC + 0.3 V — Input low voltage VIL D10, D11, R0–R3, R6, R7 –0.3 — 0.3V CC V — Output high voltage VOH R0–R3, R6, R7 VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL R0–R3, R6, R7 — — 0.4 V I OL = 0.4 mA I/O leakage current |IIL| D10, R0–R3, R6, R7 — — 1 µA Vin = 0 V to VCC 1 D11 — — 1 µA Vin = 0 V to VCC 1, 2 — — 1 µA Vin = VCC – 0.3 V to VCC 1, 3 — — 20 µA Vin = 0 V to 0.3 V 10 50 150 µA VCC = 3.0 V, Pull-up MOS –I PU current R0–R3, R6, R7 Notes: 1. Output buffer current is excluded. 2. Applies to HD404848, HD4048412, and HD404849. 3. Applies to HD4074849. 116 Unit Test Condition Vin = 0 V Notes 1, 3 HD404849 Series I/O Characteristics for High-Current Pins (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Input high voltage VIH D0–D 8 0.7V CC — VCC + 0.3 V — Input low voltage VIL D0–D 8 –0.3 — 0.3V CC V — Output high voltage VOH D0–D 8 VCC – 1.0 — — V –I OH = 0.5 mA Output low voltage VOL D0–D 8 — — 0.4 V I OL = 0.4 mA — — 2.0 V I OL = 15 mA, Note 1 VCC = 4.5 V to 6.0 V I/O leakage current |IIL| Pull-up MOS –I PU current Note: D0–D 8 — — 1 µA Vin = 0 V to VCC D0–D 8 10 50 150 µA VCC = 3 V, 2 Vin = 0 V 1. The test condition of HD4074849 is VCC = 4.5 V to 5.5 V. 2. Output buffer current is excluded. LCD Circuit Characteristics (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Note Segment VDS driver voltage drop SEG13–SEG44 — — 0.6 V I d = 3 µA 1 Common VDC driver voltage drop COM1–COM4 — — 0.3 V I d = 3 µA 1 50 300 900 kΩ Between V 1 and GND 2.7 — VCC V LCD power supply division resistance RW LCD voltage VLCD V1 2 Notes: 1. VDS and VDC are the voltage drops from power supply pins V1, V2, V3, and GND to each segment pin and each common pin, respectively. 2. When VLCD is supplied from an external source, the following relations must be retained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND 117 HD404849 Series A/D Converter Characteristics (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Analog power voltage AVCC AVCC VCC – 0.3 VCC Analog input voltage AVin AN 0–AN 7 AVSS Current between AVCC and AVSS I AD — Analog input capacitance CA in Resolution Number of inputs Max Test Condition Note VCC + 0.3 V — 1 — AVCC V — — — 200 µA VCC = AVCC = 5.0 V AN 0–AN 7 — 15 — pF — — — 8 8 8 Bit — — 0 — 8 Channel Absolute accuracy — — — — ± 2.0 LSB Conversion time — — 34 — 67 t cyc Input impedance — AN 0–AN 7 1 — — MΩ Note: 1. Connect to VCC when the A/D converter is not used. 118 Unit — — HD404849 Series AC Characteristics (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) Item Symbol Pin(s) Min Typ Max Unit Test Condition Note Clock oscillation frequency f OSC OSC 1, OSC 2 0.4 — 4.5 MHz 1/4 division 1 X1, X2 — 32.768 — kHz — t cyc — 0.89 — t subcyc — Instruction cycle time 10 µs — 244.14 — µs 32-kHz oscillator, 1/8 division 2 — 122.07 — µs 32-kHz oscillator, 1/4 division 2 Oscillation stabilization time (ceramic oscillator) t RC OSC 1, OSC 2 — — 7.5 ms Oscillation stabilization time (crystal oscillator) t RC OSC 1, OSC 2 — — 30 ms — X1, X2 — — 2 s Ta = –10°C to+60°C 3 t CPH OSC 1 105 — — ns f OSC = 4 MHz 4 External clock low width t CPL OSC 1 105 — — ns f OSC = 4 MHz 4 External clock rise time t CPr OSC 1 — — 20 ns f OSC = 4 MHz 4 External clock fall time t CPf OSC 1 — — 20 ns f OSC = 4 MHz 4 INT0–INT3, EVNB, EVND high widths t IH INT0–INT3, 2 EVNB, EVND — — t cyc / t subcyc — 5 INT0–INT3, EVNB, EVND low widths t IL INT0–INT3, 2 EVNB, EVND — — t cyc / t subcyc — 5 RESET low width t RSTL RESET 2 — — t cyc — 6 STOPC low width t STPL STOPC 1 — — t RC — 7 RESET rise time t RSTr RESET — — 20 ms — 6 STOPC rise time t STPr STOPC — — 20 ms — 7 Input capacitance Cin All pins except — D11 — 15 pF f = 1 MHz, Vin = 0 V D11 — 180 pF f = 1 MHz, Vin = 0 V 8 External clock high width — 3 3 Notes: 1. When the subsystem oscillator (32.768-kHz crystal oscillator) is used, f OSC must operate under one of the following conditions: 0.4 MHz ≤ fOSC ≤ 1.0 MHz or 1.6 MHz ≤ fOSC ≤ 4.5 MHz. Set bit 1 of the system clock select register (SSR: $029) to 0 for the former, and 1 for the latter. 2. For the HD404848, HD4048412, and HD404849, instructions can be executed during subactive mode if VCC = 2.2 V to 6.0 V. 3. The oscillation stabilization time is defined as the time required for the oscillator to stabilize in the following three cases: • After VCC reaches 2.7 V at power-on • After RESET input goes low when stop mode is cancelled 119 HD404849 Series 4. 5. 6. 7. 8. • After STOPC input goes low when stop mode is cancelled At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic or crystal oscillator, contact its manufacturer to determine what stabilization time is required since it will depend on the circuit constants and stray capacitances. See figure 95. See figure 96. See figure 97. See figure 98. The max value for the HD404848, HD4048412, HD404849 is 15 pF. Serial Interface Timing Characteristics (HD404848/HD4048412/HD404849: VCC = 2.7 to 6.0 V, GND = 0 V, T a = –20°C to +75°C; HD4074849: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20°C to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1.0 — — t cyc Load shown in figure 100 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 100 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 100 1 Transmit clock rise time t SCKr SCK — — 100 ns Load shown in figure 100 1 Transmit clock fall time t SCKf SCK — — 100 ns Load shown in figure 100 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 100 1 Serial input data setup time t SSI SI 200 — — ns — 1 Serial input data hold time t HSI SI 200 — — ns — 1 Note: 1. Refer to figure 99. 120 HD404849 Series During Transmit Clock Input Item Symbol Pin Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1.0 — — t cyc — 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc — 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc — 1 Transmit clock rise time t SCKr SCK — — 100 ns — 1 Transmit clock fall time t SCKf SCK — — 100 ns — 1 Transmit output data delay time t DSO SO — — 300 ns Load shown in figure 100 1 Serial input data setup time t SSI SI 200 — — ns — 1 Serial input data hold time t HSI SI 200 — — ns — 1 Note: 1. Refer to figure 99. 1/fCP VCC – 0.3 V 0.3 V tCPL tCPH OSC1 tCPr tCPf Figure 95 External Clock Timing 0.9VCC 0.1VCC tIL tIH INT0 to INT3, EVNB, EVND Figure 96 Interrupt Timing RESET 0.9VCC tRSTL 0.1VCC tRSTr Figure 97 STOPC Reset Timing 0.9VCC tSTPL 0.1VCC tSTPr Figure 98 STOPC Timing 121 HD404849 Series t Scyc t SCKf SCK VCC – 2.0 V (0.9VCC )* 0.4 V (0.1VCC)* t SCKr t SCKL t SCKH t DSO VCC – 0.5 V 0.4 V SO t SSI t HSI 0.9V CC 0.1VCC SI Note: * VCC – 2.0 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input. Figure 99 Serial Interface Timing VCC RL = 2.6 kΩ Test point C= 30 pF R= 12 kΩ 1S2074 H or equivalent Figure 100 Timing Load Circuit 122 HD404849 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404849). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base. 12-kword ROM version: HD4048412 Write all-1 data to addresses $3000 to $3FFF 8-kword ROM version: HD404848 Write all-1 data to addresses $2000 to $3FFF $0000 $0000 Vector address Vector address $000F $0010 $000F $0010 Zero-page subroutine (64 words) Zero-page subroutine (64 words) $003F $0040 $003F $0040 Pattern & program (8,192 words) Pattern & program (12,288 words) $2FFF $3000 $1FFF $2000 Not used $3FFF Not used $3FFF Write all-1 data in shaded areas 123 HD404849 Series HD404848/HD4048412/HD404849 Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department 1. ROM Size Name HD404848 8-kword HD4048412 12-kword ROM code name HD404849 16-kword LSI number 2. Optional Functions * With 32-kHz CPU operation, with time-base for clock * Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs. 4. Oscillator for OSC1 and OSC2 Ceramic oscillator f= MHz Crystal oscillator f= MHz External clock f= MHz 5. Stop mode Used Not used 6. Package FP-80A FP-80B TFP-80C 124 HD404849 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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