TPA4411 www.ti.com SLOS430 – AUGUST 2004 80-mW CAPLESS STEREO HEADPHONE DRIVER FEATURES APPLICATIONS • • • • • • • • • • • • Ground-Referenced Outputs Eliminate DC-Bias Voltages on Headphone Ground Pin – No Output DC-Blocking Capacitors • Reduced Board Area • Reduced Component Cost • Improved THD+N Performance • No Degradation of Low-Frequency Response Due to Output Capacitors Wide Power Supply Range: 1.8 V to 4.5 V 80-mW/Ch Output Power into 16-Ω at 4.5 V Independent Right and Left Channel Shutdown Control Short-Circuit and Thermal Protection Pop Reduction Circuitry Space Saving Pb-Free Packages – 20-pin, 4 mm × 4 mm ThinQFN – 16-ball, 2 mm × 2 mm WCSP (Product Preview) Notebook Computers CD / MP3 Players Smart Phones Cellular Phones PDAs DESCRIPTION The TPA4411 is a stereo headphone driver designed to allow the removal of the output dc-blocking capacitors for reduced component count and cost. The TPA4411 is ideal for small portable electronics where size and cost are critical design parameters. The TPA4411 is capable of driving 80 mW into a 16-Ω load at 4.5 V. The TPA4411 has a fixed gain of -1.5 V/V and headphone outputs have ±8-kV IEC ESD protection. The TPA4411 has independent shutdown control for the right and left audio channels. The TPA4411 is available in a 20-pin, 4 mm × 4 mm ThinQFN package. . TLV320AIC26 or TLV320AIC28 HPL or SPK1 TPA2012D2 HPR or SPK2 Shutdown Control SDL SDR PGND SGND TPA4411 OUTL INR OUTR INL 1.8 − 4.5 V PVSS SVSS PVDD SVDD C1P C1N Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TPA4411 www.ti.com SLOS430 – AUGUST 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. YZH (WCSP) PACKAGE (TOP VIEW) 16 2 14 SDR C1N 3 13 INL NC 4 12 NC PVSS 5 11 OUTR A4 A1 INR SGND PVDD C1P B1 SDR SDL NC PGND C1 INL OUTR NC C1N D1 SVDD OUTL SVSS PVSS NC − No internal connection SVDD OUTL NC SVSS A3 10 PGND 9 INR 8 15 7 1 6 C1P NC A2 NC SGND 17 SDL 18 PVDD 19 20 NC RTJ (QFN) PACKAGE (TOP VIEW) NC − No internal connection TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION A4 I/O Charge pump flying capacitor positive terminal B4 I 3 C4 I/O 4, 6, 8, 12, 16, 20 B3, C3 QFN WCSP (1) C1P 1 PGND 2 C1N NC PVSS 5 D4 O Output from charge pump. SVSS 7 D3 I Amplifier negative supply, connect to PVSS via star connection. OUTL 9 D2 O Left audio channel output signal SVDD 10 D1 I Amplifier positive supply, connect to PVDD via star connection. OUTR 11 C2 O Right audio channel output signal INL 13 C1 I Left audio channel input signal SDR 14 B1 I Right channel shutdown, active low logic. INR 15 A1 I Right audio channel input signal SGND 17 A2 I Signal ground, connect to ground. SDL 18 B2 I Left channel shutdown, active low logic. PVDD 19 A3 I Supply voltage, connect to positive supply. NAME Exposed Pad (1) 2 Package not yet available - Power ground, connect to ground. Charge pump flying capacitor negative terminal No connection Exposed pad must be soldered to a floating plane. Do NOT connect to power or ground. TPA4411 www.ti.com SLOS430 – AUGUST 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range, TA = 25°C (unless otherwise noted) UNIT Supply voltage, AVDD, PVDD VI Input voltage -0.3 to 5.5 V -0.3 to VDD + 0.3 V Output Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range - 40 to 85 °C TJ Operating junction temperature range - 40 to 150 °C Tstg Storage temperature range -65 to 85 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS TABLE PACKAGE TA≤ 25°C POWER RATING RTJ YZH (2) (1) (2) DERATING FACTOR (1) TA = 70°C POWER RATING TA = 85°C POWER RATING 3450 mW 34.5 mW/°C 1898 mW 1380 mW TBD TBD mW/°C TBD TBD Derating factor measured with High K board. Product preview AVAILABLE OPTIONS TA -40°C to 85°C (1) PACKAGED DEVICES PART NUMBER SYMBOL 20-pin, 4 mm × 4 mm QFN TPA4411RTJ (1) AKQ 16-ball, 2 mm × 2mm WSCP TPA4411YZH AKT The RTJ package is only available taped and reeled. To order, add the suffix “R” to the end of the part number for a reel of 3000, or add the suffix “T” to the end of the part number for a reel of 250 (e.g., TPA4411RTJR). RECOMMENDED OPERATING CONDITIONS Supply voltage, AVDD, PVDD VIH High-level input voltage SDL, SDR VIL Low-level input voltage SDL, SDR TA Operating free-air temperature (1) MIN MAX UNIT 1.8 4.5 (1) V 1.5 - 40 V 0.5 V 85 °C Device can shut down for VDD > 4.5 V to prevent damage to the device. 3 TPA4411 www.ti.com SLOS430 – AUGUST 2004 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP -80 MAX |VOS| Output offset voltage VDD = 1.8 V to 4.5 V, Inputs grounded PSRR Power Supply Rejection Ratio VDD = 1.8 V to 4.5 V -69 VOH High-level output voltage VDD = 3 V, RL = 16 Ω 2.2 VOL Low-level output voltage VDD = 3 V, RL = 16 Ω -1.1 V |IIH| High-level input current (SDL, SDR) VDD = 4.5 V, VI = VDD 1 µA |IIL| Low-level input current (SDL, SDR) VDD = 4.5 V, VI = 0 V 1 µA IDD Supply Current 8 UNIT mV dB V VDD = 1.8 V, No load, SDL= SDR = VDD 5.3 VDD = 3 V, No load, SDL = SDR = VDD 6.5 8.0 VDD = 4.5 V, No load, SDL = SDR = VDD 8.0 10.0 Shutdown mode, VDD = 1.8 V to 4.5 V 6.5 1 mA µA OPERATING CHARACTERISTICS VDD = 3 V , TA = 25°C, RL = 16 Ω (unless otherwise noted) PARAMETER PO THD+N Output power (Outputs In Phase) Total harmonic distortion plus noise Crosstallk kSVR Supply ripple rejection ratio Closed-loop voltage gain ∆Av Gain matching 50 THD = 1%, VDD = 4.5 V, f = 1 kHz 80 THD = 1%, VDD = 3 V, f = 1 kHz, RL = 32 Ω 40 PO = 25 mW, f = 1 kHz 0.054% PO = 25 mW, f = 20 kHz 0.010% -82.5 200-mVpp ripple, f = 1 kHz -70.4 200-mVpp ripple, f = 20 kHz -45.1 -1.45 -1.5 UNIT mW dB dB -1.55 V/V 1% 2.2 V/µs Maximum capacitive load 400 pF 10 µVRMS Noise output voltage ±8 OUTR, OUTL Charge pump switching frequency 280 Signal-to-noise ratio Thermal shutdown 320 kV 420 450 Input impedance 4 MAX -83 200-mVpp ripple, f = 217 Hz Start-up time from shutdown SNR TYP Slew rate Electrostatic discharge, IEC fosc MIN PO = 20 mW, f = 1 kHz Av Vn TEST CONDITIONS THD = 1%, VDD = 3 V, f = 1 kHz 12 Po = 40 mW (THD+N = 0.1%) Threshold Hysteresis 15 µs 18 98 150 kΩ dB 170 15 kHz °C °C TPA4411 www.ti.com SLOS430 – AUGUST 2004 Functional Block Diagram TPA4411 SVDD Audio In − R _ Audio Out − R + Short Circuit Protection SVSS SVDD SGND + _ Audio In − L Audio Out − L SVSS C1P Av = −1.5 V/V SDx Bias Circuitry Charge Pump C1N PVSS TYPICAL CHARACTERISTICS C(PUMP) = C(PVSS) = 2.2 µF , CIN = 1 µF (unless otherwise noted) Table of Graphs FIGURE Total harmonic distortion + noise vs Output power 1 - 24 Total harmonic distortion + noise vs Frequency 25 - 32 Supply voltage rejection ratio vs Frequency 33, 34 Power dissipation vs Output power 35 - 42 Crosstalk vs Frequency 43 - 46 Output power vs Supply voltage 47 - 50 Quiescent supply current vs Supply voltage 51 Output power vs Load resistance 52 - 60 Output spectrum Gain and phase 61 vs Frequency 62, 63 5 TPA4411 www.ti.com SLOS430 – AUGUST 2004 10 In Phase 1 Single Channel 0.1 0.01 180° Out of Phase 0.001 0.001 0.01 100 VDD = 1.8 V, RL = 16 Ω, fIN = 1 kHz 180° Out of Phase 10 1 In Phase 0.1 Single Channel 0.01 0.001 VDD = 1.8 V, RL = 16 Ω, fIN = 10 kHz In Phase 10 180° Out of Phase 1 0.1 Single Channel 0.01 0.001 0.01 0.01 PO − Output Power − mW Figure 1. Figure 2. Figure 3. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER VDD = 1.8 V, RL = 32 Ω, fIN = 20 Hz 10 In Phase 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.001 0.01 100 VDD = 1.8 V, RL = 32 Ω, fIN = 1 kHz In Phase 10 180° Out of Phase Single Channel 1 0.1 0.01 0.001 0.01 PO − Output Power − mW THD+N − Total Harmonic Distortion + Noise − % 100 100 VDD = 1.8 V, RL = 32 Ω, fIN = 10 kHz In Phase 10 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 PO − Output Power − mW 0.01 PO − Output Power − mW Figure 5. Figure 6. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 10 VDD = 3 V, RL = 16 Ω, fIN = 20 Hz In Phase 1 0.1 180° Out of Phase 0.01 Single Channel 0.001 0.001 0.01 0.1 100 VDD = 3 V, RL = 16 Ω, fIN = 1 kHz In Phase 10 1 180° Out of Phase 0.1 Single Channel 0.01 0.001 PO − Output Power − mW 0.01 0.1 PO − Output Power − mW Figure 7. Figure 8. THD+N − Total Harmonic Distortion + Noise − % Figure 4. THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 100 PO − Output Power − mW PO − Output Power − mW 6 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % VDD = 1.8 V, RL = 16 Ω, fIN = 20 Hz THD+N − Total Harmonic Distortion + Noise − % 100 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 3 V, RL = 16 Ω, fIN = 10 kHz In Phase 10 1 180° Out of Phase 0.1 Single Channel 0.01 0.001 0.01 0.1 PO − Output Power − mW Figure 9. TPA4411 www.ti.com SLOS430 – AUGUST 2004 10 In Phase 180° Out of Phase 1 0.1 Single Channel 0.01 0.001 0.001 0.01 0.1 PO − Output Power − mW 100 VDD = 3 V, RL = 32 Ω, fIN = 1 kHz 10 Single Channel 1 180° Out of Phase 0.1 0.01 0.001 0.01 0.1 100 VDD = 3 V, RL = 32 Ω, fIN = 10 kHz 10 In Phase 1 0.1 Single Channel 0.01 180° Out of Phase 0.001 0.001 0.01 0.1 PO − Output Power − mW Figure 10. Figure 11. Figure 12. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 3.6 V, RL = 16 Ω, fIN = 20 Hz 10 In Phase 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.001 0.01 0.1 100 VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHz 10 In Phase 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.01 0.1 THD+N − Total Harmonic Distortion + Noise − % PO − Output Power − mW 100 VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHz 10 In Phase 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.01 0.1 PO − Output Power − mW Figure 13. Figure 14. Figure 15. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 VDD = 3.6 V, RL = 32 Ω, fIN = 20 Hz In Phase 180° Out of Phase 1 0.1 Single Channel 0.01 0.001 0.001 0.01 0.1 PO − Output Power − mW Figure 16. THD+N − Total Harmonic Distortion + Noise − % 100 100 VDD = 3.6 V, RL = 32 Ω, fIN = 1 kHz In Phase 10 180° Out of Phase 1 0.1 0.01 0.001 Single Channel 0.01 0.1 PO − Output Power − mW Figure 17. THD+N − Total Harmonic Distortion + Noise − % PO − Output Power − mW PO − Output Power − mW THD+N − Total Harmonic Distortion + Noise − % In Phase TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % VDD = 3 V, RL = 32 Ω, fIN = 20 Hz THD+N − Total Harmonic Distortion + Noise − % 100 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 10 VDD = 3.6 V, RL = 32 Ω, fIN = 10 kHz In Phase 180° Out of Phase 1 0.1 0.01 Single Channel 0.001 0.001 0.01 0.1 PO − Output Power − mW Figure 18. 7 TPA4411 www.ti.com SLOS430 – AUGUST 2004 1 Single Channel 0.1 0.01 0.001 0.001 0.01 0.1 In Phase 10 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.01 0.1 100 VDD = 4.5 V, RL = 16 Ω, fIN = 10 k Hz In Phase 10 180° Out of Phase 1 0.1 Single Channel 0.01 0.001 0.1 0.01 PO − Output Power − mW PO − Output Power − mW Figure 19. Figure 20. Figure 21. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 4.5 V, RL = 32 Ω, fIN = 20 Hz 10 In Phase 1 Single Channel 0.1 180° Out of Phase 0.01 0.001 0.001 0.01 0.1 100 VDD = 4.5 V, RL = 32 Ω, fIN = 1 kHz THD+N − Total Harmonic Distortion + Noise − % PO − Output Power − mW THD+N − Total Harmonic Distortion + Noise − % In Phase 10 1 180° Out of Phase Single Channel 0.1 0.01 0.001 0.1 0.01 100 VDD = 4.5 V, RL = 32 Ω, fIN = 10 kHz 10 In Phase 1 180° Out of Phase 0.1 Single Channel 0.01 0.001 0.01 0.1 PO − Output Power − mW PO − Output Power − mW PO − Output Power − mW Figure 22. Figure 23. Figure 24. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 VDD = 1.8 V RL = 16 Ω PO = 1 mW 0.1 PO = 3 mW 0.01 PO = 2 mW 0.001 10 100 1k 10 k Figure 25. 100 k 1 VDD = 1.8 V RL = 32 Ω PO = 2 mW 0.1 PO = 6 mW 0.01 PO = 5 mW 0.001 10 100 1k 10 k f − Frequency − Hz Figure 26. 100 k THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 180° Out of Phase 100 VDD = 4.5 V, RL = 16 Ω, fIN = 1 k Hz TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % 10 In Phase f − Frequency − Hz 8 THD+N − Total Harmonic Distortion + Noise − % 100 VDD = 4.5 V, RL = 16 Ω, fIN = 20 Hz TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 1 VDD = 3 V RL = 16 Ω PO = 5 mW 0.1 PO = 40 mW PO = 25 mW 0.01 0.001 10 100 1k 10 k f − Frequency − Hz Figure 27. 100 k TPA4411 www.ti.com SLOS430 – AUGUST 2004 VDD = 3 V RL = 32 Ω PO = 5 mW PO = 25 mW 0.1 0.01 PO = 45 mW 0.001 10 100 1k 10 k 100 k 1 VDD = 3.6 V RL = 16 Ω PO = 5 mW PO = 40 mW 0.1 0.01 PO = 20 mW 0.001 10 100 PO = 70 mW 0.01 0.001 10 100 1k 10 k SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY 0.01 PO = 25 mW PO = 5 mW 0.001 100 1k 10 k 100 k VDD = 4.5 V RL = 32 Ω PO = 5 mW 0.1 PO = 80 mW PO = 25 mW 0.01 PO = 50 mW 0.001 10 100 1k 10 k 100 k 0 RL = 16 Ω −10 −20 −30 3V −40 4.5 V −50 −60 1.8 V −70 3.6 V −80 −90 −100 10 100 1k 10 k Figure 31. Figure 32. Figure 33. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY POWER DISSIPATION vs OUTPUT POWER POWER DISSIPATION vs OUTPUT POWER 60 80 P D − Power Dissipation − mW RL = 32 Ω −20 −30 −40 −50 −60 3V 1.8 V 4.5 V −80 −90 3.6 V 100 70 f − Frequency − Hz Figure 34. 10 k 100 k In Phase 60 180° Out of Phase 50 40 30 20 VDD = 1.8 V, RL = 16 Ω 10 0 1k 100 k f − Frequency − Hz f − Frequency − Hz P D − Power Dissipation − mW 10 1 k SVR − Supply Voltage Rejection Ratio − V PO = 50 mW 100 k f − Frequency − Hz TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY f − Frequency − Hz k SVR − Supply Voltage Rejection Ratio − V PO = 35 mW 0.1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.1 −100 10 PO = 5 mW Figure 30. PO = 35 mW −70 VDD = 3.6 V RL = 32 Ω Figure 29. VDD = 4.5 V RL = 16 Ω 0 100 k 1 Figure 28. 1 −10 10 k f − Frequency − Hz THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % f − Frequency − Hz 1k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N − Total Harmonic Distortion + Noise − % 1 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0 5 10 15 20 PO − Output Power − mW Figure 35. 25 30 In Phase 50 40 180° Out of Phase 30 20 VDD = 1.8 V, RL = 32 Ω 10 0 0 5 10 15 20 25 30 35 40 PO − Output Power − mW Figure 36. 9 TPA4411 www.ti.com SLOS430 – AUGUST 2004 POWER DISSIPATION vs OUTPUT POWER POWER DISSIPATION vs OUTPUT POWER 300 POWER DISSIPATION vs OUTPUT POWER 400 160 In Phase 250 200 180° Out of Phase 150 100 VDD = 3 V, RL = 16 Ω 50 120 180° Out of Phase 100 80 60 40 VDD = 3 V, RL = 32 Ω 20 50 100 150 200 0 PO − Output Power − mW 150 0 200 50 100 150 200 250 PO − Output Power − mW POWER DISSIPATION vs OUTPUT POWER 350 180° Out of Phase 100 50 VDD = 3.6 V, RL = 32 Ω VDD = 4.5 V, RL = 16 Ω 500 In Phase 400 180° Out of Phase 300 200 100 100 150 200 250 300 350 In Phase 250 180° Out of Phase 200 150 100 0 0 50 100 150 200 0 250 PO − Output Power − mW 50 100 150 200 250 PO − Output Power − mW Figure 40. Figure 41. Figure 42. CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 0 VDD = 3 V, PO = 1.6 mW RL = 16 Ω 0 VDD = 3 V, PO = 20 mW RL = 16 Ω Crosstalk − dB −20 −40 Left to Right −80 −20 −40 −60 Left to Right −80 −100 Right to Left 1k 10 k f − Frequency − Hz Figure 43. 100 k 10 100 1k 10 k f − Frequency − Hz Figure 44. 100 k 300 VDD = 3.6 V, PO = 1.6 mW RL = 16 Ω −40 −60 Left to Right −80 −100 Right to Left −120 100 VDD = 4.5 V, RL = 32 Ω 300 300 50 0 50 P D − Power Dissipation − mW PD − Power Dissipation − mW PD − Power Dissipation − mW 100 POWER DISSIPATION vs OUTPUT POWER PO − Output Power − mW Crosstalk − dB VDD = 3.6 V, RL = 16 Ω POWER DISSIPATION vs OUTPUT POWER 150 −120 10 100 Figure 39. 200 −100 150 Figure 38. 0 10 50 600 −60 200 Figure 37. In Phase −20 180° Out of Phase 250 PO − Output Power − mW 250 0 300 0 0 0 350 50 Crosstalk − dB 0 140 P D − Power Dissipation − mW In Phase P D − Power Dissipation − mW P D − Power Dissipation − mW In Phase −120 10 Right to Left 100 1k 10 k f − Frequency − Hz Figure 45. 100 k TPA4411 www.ti.com SLOS430 – AUGUST 2004 CROSSTALK vs FREQUENCY OUTPUT POWER vs SUPPLY VOLTAGE 0 120 VDD = 3.6 V, PO = 20 mW RL = 16 Ω −80 80 60 In Phase 40 20 Right to Left 100 PO − Output Power − mW Left to Right 180° Out of Phase 1k 10 k 0 100 k 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V 4.3 QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 10 PO − Output Power − mW THD = 10 % RL = 32 Ω 100 80 60 In Phase 40 200 180° Out of Phase 150 100 In Phase 50 2.3 2.8 3.3 3.8 4.3 1.8 VDD − Supply Voltage − V 7 6 5 4 3 2 1 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V 4.3 0 1 1.5 2 2.5 3 3.5 4 Figure 51. OUTPUT POWER vs LOAD RESISTANCE OUTPUT POWER vs LOAD RESISTANCE OUTPUT POWER vs LOAD RESISTANCE 100 0.47 µF 80 70 60 In Phase, VDD = 3 V, THD = 1%, Vary C(PUMP) 25 20 50 Out of Phase 15 10 In Phase 0 10 VDD = 1.8 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR 35 5 30 Figure 52. VDD = 1.8 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR PO − Output Power − mW PO − Output Power − mW 0.68 µF 10 20 30 40 RL − Load Resistance − Ω 40 30 2.2 µF 4.5 5 VDD − Supply Voltage − V Figure 50. 1 µF 0 8 Figure 49. 120 40 9 0 0 50 4.3 OUTPUT POWER vs SUPPLY VOLTAGE 180° Out of Phase 90 2.3 2.8 3.3 3.8 VDD − Supply Voltage − V OUTPUT POWER vs SUPPLY VOLTAGE 20 PO − Output Power − mW 1.8 250 110 In Phase 50 Figure 48. THD = 1 % RL = 32 Ω 1.8 100 Figure 47. 120 0 180° Out of Phase 150 Figure 46. 160 140 200 0 1.8 f − Frequency − Hz I DD − Quiescent Supply Current − mA Crosstalk − dB −60 −120 10 THD = 10 % RL = 16 Ω 100 −40 −100 250 THD = 1 % RL = 16 Ω PO − Output Power − mW −20 PO − Output Power − mW OUTPUT POWER vs SUPPLY VOLTAGE 30 Out of Phase 25 20 15 In Phase 10 5 100 1000 RL − Load Resistance − Ω Figure 53. 10000 0 10 100 1000 10000 RL − Load Resistance − Ω Figure 54. 11 TPA4411 www.ti.com SLOS430 – AUGUST 2004 OUTPUT POWER vs LOAD RESISTANCE 120 Out of Phase 100 80 In Phase 60 40 250 VDD = 3 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR 200 PO − Output Power − mW 140 PO − Output Power − mW 250 VDD = 3 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR OUTPUT POWER vs LOAD RESISTANCE PO − Output Power − mW 160 OUTPUT POWER vs LOAD RESISTANCE Out of Phase 150 100 In Phase 50 VDD = 3.6 V, THD = 1%, fIN = 1 kHz, PO = POUTL + POUTR 200 Out of Phase 150 100 In Phase 50 20 0 10 0 100 1000 RL − Load Resistance − Ω 10 10000 1000 0 10 10000 100 RL − Load Resistance − Ω 1000 Figure 56. Figure 57. OUTPUT POWER vs LOAD RESISTANCE OUTPUT POWER vs LOAD RESISTANCE OUTPUT POWER vs LOAD RESISTANCE 500 350 300 PO − Output Power − mW 300 VDD = 4.5 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR 250 Out of Phase 200 150 In Phase 100 250 Out of Phase 200 150 In Phase 100 50 50 0 0 VDD = 4.5 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR 450 PO − Output Power − mW VDD = 3.6 V, THD = 10%, fIN = 1 kHz, PO = POUTL + POUTR 10000 RL − Load Resistance − Ω Figure 55. 350 PO − Output Power − mW 100 400 350 Out of Phase 300 250 200 In Phase 150 100 50 1000 10000 0 10 100 RL − Load Resistance − Ω Figure 59. Figure 60. OUTPUT SPECTRUM GAIN AND PHASE vs FREQUENCY GAIN AND PHASE vs FREQUENCY 90 3.5 Gain 3 3 70 Gain 50 2.5 −40 −60 −80 30 2 10 Phase 1.5 −100 −10 −30 1 50 2.5 30 2 10 1.5 −10 Phase −30 1 −50 0.5 −140 −160 10 100 1k f − Frequency − Hz Figure 61. 10 k 100 k 0 10 VCC = 3.6 V, RL = 16 Ω 100 1k 10 k 100 k f − Frequency − Hz Figure 62. 10000 90 3.5 70 −120 12 1000 RL − Load Resistance − Ω Figure 58. Gain − dB Output Spectrum − dBv −20 100 RL − Load Resistance − Ω VO = 1 VRMS VDD = 3 V fIN = 1 kHz RL = 32 Ω 0 10 10000 Gain − dB 20 1000 −70 −90 1G −50 0.5 0 VCC = 3 V, RL = 16 Ω 10 100 1k 10 k 100 k f − Frequency − Hz Figure 63. −70 −90 1G Phase − Degrees 100 Phase − Degrees 10 TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION Headphone Amplifiers For single-supply headphone amplifiers, the output architecture typically require dc-blocking capacitors to remove the mid-rail bias required to obtain symmetrical output voltage swing. These capacitors are required because most headphone jacks are ground-referenced, with respect to the shield pin. Without the capacitors, there would be a dc bias voltage across the headphone speakers. In Figure 64, the first block diagram and waveform illustrate the traditional headphone amplifier connection to the headphone jack and output signal. These capacitors are typically large in value in order to prevent the filtering of the output audio signal. The dc-blocking capacitors form a high-pass filter with the load impedance of the headphone speakers. Treating the headphone speakers as a resistive load, typically either 16Ω or 32 Ω, the dc-blocking capacitors form a high-pass filter with the load impedance. Equation 1 shows the relationship between the load impedance (R), the capacitor (C), and the cutoff frequency. 1 f 2 R C (1) Substituting for the values in the circuit, the dc-blocking capacitors can be determined using Equation 2, where the load impedance and the cutoff frequency are known. 1 CO 2 RL fc OUT (2) From Equation 2, the capacitor must have a large value because the resistance value is small. Large capacitance values require large package sizes which consume board area, increase cost of the assembly, and can reduce the fidelity of the audio output signal. Two different capless headphone amplifier applications are available that allow for the removal of the output dc-blocking capacitors. The first amplifier architecture is implemented in the same manner as the traditional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is typically half of the amplifier power supply because this allows symmetrical swing of the output voltages. The second block diagram and waveform shows the mid-supply biased capless headphone architecture. The second amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Using this negative supply, the headphone amplifier is now a split supply amplifier (internally) and can be considered a ground-reference amplifier. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The bottom block diagram and waveform of Figure 64 illustrate the ground-referenced capless headphone architecture. Input-Blocking Capacitors DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the TPA4411. These capacitors block the dc portion of the audio source and allow the TPA4411 inputs to be properly biased to provide maximum performace. These capacitors form a high-pass filter with the input impedance of the TPA4411. The cutoff frequency is calculated using Equation 1. For this calculation, the capacitance used is input-blocking capacitor and the resistance is the input impedance of the TPA4411. Because the gain of the TPA4411 is fixed, the input impedance remains a constant value. Using the input impedance value from the operating characteristics table and Equation 2, the frequency and/or capacitance can be determined when one of the two values are given. 1 1 fc IN or C IN 2 fc R 2 RIN C IN IN IN (3) • Where RIN = 15 kΩ. 13 TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION (continued) Conventional VDD CO VOUT CO VDD/2 GND VDD VOUT VDD/2 GND VBIAS VBIAS VDD/2 GND VDD GND −VSS Figure 64. Amplifier Applications Charge Pump Flying Capacitor and PVSS Capacitor The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge pump capacitor in order to allow maximum charge transfer. Low ESR capacitors are an ideal selection, and a value of 2.2 µF is typical. Capacitor values that are smaller than 2.2 µF can be used, but the maximum output power is reduced and the device may not operate to specifications. Figures 65 through 75 compare the performance of the TPA4411 with the recommended 2.2-µF capacitors and 1-µF capacitors. 14 TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION (continued) THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 1 VDD = 3.6 V, RL = 32 Ω, PO = 35 mW, 0.1 C = 1 µF 0.01 C = 2.2 µF 0.001 10 100 1k 10 k 100 k f − Frequency − Hz Figure 65. 100 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER VDD = 3.6 V, RL = 16 Ω, fIN = 20 HZ C = 1 µF 180° Out of Phase 10 In Phase 1 Single Channel 0.1 0.0001 0.001 0.01 0.1 1 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 3.6 V, RL = 16 Ω, fIN = 20 Hz C = 2.2 µF 10 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.001 0.01 0.1 PO − Output Power − mW Figure 66. Figure 67. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHZ C = 1 µF Single Channel In Phase 10 1 180° Out of Phase 0.1 0.01 0.0001 0.001 0.01 0.1 PO − Output Power − mW Figure 68. 1 THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % PO − Output Power − mW 100 In Phase 100 VDD = 3.6 V, RL = 16 Ω, fIN = 1 kHz C = 2.2 µF 10 In Phase 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.01 0.1 PO − Output Power − mW Figure 69. 15 TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION (continued) 100 VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHZ C = 1 µF 10 In Phase 1 180° Out of Phase 0.1 0.01 Single Channel 0.001 0.0001 0.001 0.01 0.1 1 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 3.6 V, RL = 16 Ω, fIN = 10 kHz C = 2.2 µF 10 180° Out of Phase 1 Single Channel 0.1 0.01 0.001 0.1 Figure 71. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 100 VDD = 3.6 V, RL = 32 Ω, fIN = 20 HZ C = 1 µF In Phase 10 Single Channel 1 180° Out of Phase 0.1 0.0001 0.001 0.01 0.1 PO − Output Power − mW 1 In Phase 180° Out of Phase 1 0.1 Single Channel 0.01 0.001 0.001 0.01 0.1 Figure 73. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY −30 −40 −50 −60 −70 −80 −90 −100 10 10 VDD = 3.6 V, RL = 32 Ω, fIN = 20 Hz C = 2.2 µF Figure 72. VDD = 3.6 V, RL = 32 Ω, C = 1 µF −20 100 PO − Output Power − mW 0 −10 THD+N − Total Harmonic Distortion + Noise − % Figure 70. k SVR − Supply Voltage Rejection Ratio − V THD+N − Total Harmonic Distortion + Noise − % k SVR − Supply Voltage Rejection Ratio − V 0.01 PO − Output Power − mW PO − Output Power − mW 16 In Phase 100 1k 10 k 100 k 0 −10 RL = 32 Ω C = 2.2 µF −20 −30 −40 −50 −60 −70 3V 1.8 V 4.5 V −80 −90 −100 10 3.6 V 100 1k f − Frequency − Hz f − Frequency − Hz Figure 74. Figure 75. 10 k 100 k TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION (continued) Decoupling Capacitors The TPA4411 is a capless headphone amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 2.2 µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the TPA4411 is important for the performance of the amplifier. For filtering lower frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. Supply Voltage Limiting At 4.5 V The TPA4411 has a built-in charge pump which serves to generate a negative rail for the headphone amplifier. Because the headphone amplifier operates from a positive voltage and negative voltage supply, circuitry has been implemented to protect the devices in the amplifier from an overvoltage condition. Once the supply is above 4.5 V, the TPA4411 can shut down in an overvoltage protection mode to prevent damage to the device. The TPA4411 resumes normal operation once the supply is reduced to 4.5 V or lower. Layout Recommendations Exposed Pad On TPA4411RTJ Package Option The exposed metal pad on the TPA4411RTJ package must be soldered down to a pad on the PCB in order to maintain reliability. The pad on the PCB should be allowed to float and not be connected to ground or power. Connecting this pad to power or ground prevents the device from working properly because it is connected internally to PVSS. SGND and PGND Connections The SGND and PGND pins of the TPA4411 must be routed separately back to the decoupling capacitor in order to provide proper device operation. If the SGND and PGND pins are connected directly to each other, the part functions without risk of failure, but the noise and THD performance do not meet the specifications. 17 TPA4411 www.ti.com SLOS430 – AUGUST 2004 APPLICATION INFORMATION (continued) PVDD INL− INL+ CODEC TLV320AIC26 or TLV320AIC28 HPL or SPK1 AVDD PGND TPA2012D2 HPR or SPK2 INR− INR+ AGND SDR SDL Gain0 Gain1 Control SDL SDR PGND SGND TPA4411 OUTL 1 F INR OUTR 1 F VCC INL PVSS SVSS PVDD SVDD 2.2 F C1P 2.2 F C1N 2.2 F Figure 76. Application Circuit Shutdown Control 16 17 18 C1 2.2 F 19 20 1.8 − 4.5 V C5 1 15 C2 2.2 F 2 14 Shutdown Control 1 F 3 13 − C3 2.2 F Right Audio Input 1 F + + − 4 Left Audio Input C4 12 5 10 9 8 7 6 11 No Output DC-Blocking Capacitors Note: PowerPAD must be soldered down and plane must be floating. Figure 77. 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