HD74AC74 Dual D-Type Positive Edge-Triggered Flip-Flop Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to SD (Set) sets Q to High level Low input to CD (Clear) sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High • Outputs Source/Sink 24 mA HD74AC74 Pin Arrangement CD1 1 14 VCC CP1 D1 D1 2 SD1 CP1 3 13 CD2 CD1 12 D2 Q1 Q1 SD1 4 11 CP2 Q1 5 D2 CP2 Q1 6 CD2 SD2 10 SD2 9 Q2 Q2 Q2 8 Q2 GND 7 (Top view) Logic Symbol SD1 D1 SD2 Q1 CP1 CD1 Pin Names D1, D2 CP1, CP2 C D1, CD2 S D1, SD2 Q1, Q1, Q2, Q 2 2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs D2 Q2 CP2 Q1 CD2 Q2 HD74AC74 Truth Table (Each Half) Inputs Outputs SD CD CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H X Q0 Q0 H H H L X : : : : Q0 (Q0) : L High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Previous Q (Q) before Low-to-High Transition of Clock Logic Diagram SD D Q CP Q CD Please note that this diagram is provised only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 40 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 4.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C 3 HD74AC74 AC Characteristics Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock f max 3.3 100 125 — 95 — MHz 5.0 140 160 — 125 — 3.3 1.0 8.0 12.0 1.0 13.0 5.0 1.0 6.0 9.0 1.0 10.0 3.3 1.0 10.5 12.0 1.0 13.5 5.0 1.0 8.0 9.5 1.0 10.5 3.3 1.0 8.0 13.5 1.0 16.0 5.0 1.0 6.0 10.0 1.0 10.5 3.3 1.0 8.0 14.0 1.0 14.5 5.0 1.0 6.0 10.0 1.0 10.5 frequency Propagation delay t PLH CDn or SDn to Qn or Qn Propagation delay t PHL CDn or SDn to Qn or Qn Propagation delay t PLH CP n to Q n or Qn Propagation delay t PHL CP n to Q n or Qn Note: ns ns ns ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74AC74 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Set-up time, HIGH or LOW t su 3.3 1.5 4.0 4.5 ns 5.0 1.0 3.0 3.0 3.3 –2.0 0 0 5.0 –1.5 0 0 3.3 3.0 5.5 7.0 5.0 2.5 4.5 5.0 3.3 –2.5 0 0 5.0 –2.0 0 0 Dn to CPn Hold time, HIGH or LOW th Dn to CPn CP n or CDn or SDn tw Pulse width Recovery time CDn or SDn to CP Note: 4 t rec 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V ns ns ns HD74AC74 Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 35.0 pF VCC = 5.0 V 5 Unit: mm 19.20 20.32 Max 8 6.30 7.40 Max 14 1.30 7 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.39 Max 2.54 Min 5.06 Max 1 7.62 + 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 8 5.5 14 1 0.10 ± 0.10 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7 + 0.20 7.80 – 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 *0.40 ± 0.06 0.11 0.14 +– 0.04 0° – 8° 1.27 0.67 0.60 +– 0.20 0.15 0.25 M *Pd plating Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 0.20 ± 0.06 1.0 0.13 M 6.40 ± 0.20 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 1.10 Max 0.83 Max 0.07 +0.03 –0.04 *0.22+0.08 –0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-14D — — 0.05 g Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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