SCLS600 − NOVEMBER 2004 D Qualification in Accordance With DW OR PW PACKAGE (TOP VIEW) AEC-Q100† D Qualified for Automotive Applications D Customer-Specific Configuration Control D D D D D D D OE 1D 2D 3D 4D 5D 6D 7D 8D GND Can Be Supported Along With Major-Change Approval Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 21 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Bus-Structured Pinout 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE † Contact factory for details. Q100 qualification data available on request. description/ordering information This octal transparent D-type latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. ORDERING INFORMATION −40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA SOIC − DW Reel of 2500 SN74HC573AQDWRQ1 TSSOP − PW Reel of 2000 SN74HC573AQPWRQ1 TOP-SIDE MARKING HC573AQ HC573AQ ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS600 − NOVEMBER 2004 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS600 − NOVEMBER 2004 recommended operating conditions (see Note 3) VCC VIH VI VO tt NOM MAX 2 5 6 Supply voltage VCC = 2 V VCC = 4.5 V High-level input voltage 3.15 V 0.5 1.35 V 1.8 Input voltage 0 Output voltage VCC VCC 0 VCC = 2 V VCC = 4.5 V Input transition (rise and fall) time V 4.2 VCC = 4.5 V VCC = 6 V Low-level input voltage UNIT 1.5 VCC = 6 V VCC = 2 V VIL MIN V V 1000 500 ns VCC = 6 V 400 TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −6 mA IOH = −7.8 mA VOL VI = VCC or 0 VO = VCC or 0 ICC Ci VI = VCC or 0, MAX TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 MAX 5.2 UNIT MAX V 5.34 2V 0.002 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 IOL = 6 mA IOL = 7.8 mA 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 6V ±0.01 ±0.5 ±10 ±5 µA 8 160 80 µA 3 10 10 10 pF VI = VIH or VIL II IOZ TA = 25°C VCC IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 3 SCLS600 − NOVEMBER 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC tw Pulse duration, LE high tsu Setup time, data before LE↓ th Hold time, data after LE↓ TA = 25°C TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN MIN MAX MAX 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 50 75 63 4.5 V 10 15 13 6V 9 13 11 2V 20 24 24 4.5 V 5 5 5 6V 5 5 5 UNIT MAX ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) D TO (OUTPUT) Q tpd LE ten tdis tt 4 OE OE Any Q Any Q Any Q Any Q TA = 25°C VCC MIN TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN TYP MAX MAX 2V 77 175 265 220 4.5 V 26 35 53 44 6V 23 30 45 38 2V 87 175 265 260 4.5 V 27 35 53 44 6V 23 30 45 38 2V 68 150 225 190 4.5 V 24 30 45 38 6V 21 26 38 32 2V 47 150 225 190 4.5 V 23 30 45 38 6V 21 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns ns SCLS600 − NOVEMBER 2004 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) D Q tpd LE ten Any Q OE Any Q tt Any Q TA = 25°C VCC MIN TA = −40°C TO 125°C TA = −40°C TO 85°C MIN MIN TYP MAX MAX 2V 95 200 300 250 4.5 V 33 40 60 50 6V 21 34 51 43 2V 103 225 335 285 4.5 V 33 45 67 57 6V 29 38 57 48 2V 85 200 300 250 4.5 V 29 40 60 50 6V 26 34 51 43 UNIT MAX 2V 60 210 315 265 4.5 V 17 42 63 53 6V 14 36 53 45 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per latch No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 50 UNIT pF 5 SCLS600 − NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER S1 Test Point From Output Under Test ten RL tPZH RL CL 50 pF or 150 pF 1 kΩ tPZL tdis S2 tPLZ 1 kΩ 50 pF −− 50 pF or 150 pF tpd or tt LOAD CIRCUIT 50% Closed Closed Open Open Closed Closed Open Open Open 50% 0V 50% tsu 0V tw Data 50% Input 10% VCC Low-Level Pulse 50% 50% 50% 0V tPLH 50% 10% tPHL 90% 90% tr tPHL 90% tf 50% 10% Output Control (Low-Level Enabling) 50% 10% V OL tf tPZL Output Waveform 1 (See Note B) VOH tPZH VOH tPLH 50% 10% 90% 90% VCC 50% 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC 50% th tr 0V VOLTAGE WAVEFORMS PULSE DURATIONS Out-ofPhase Output Open VCC Reference Input VCC High-Level Pulse In-Phase Output S2 tPHZ CL (see Note A) Input S1 90% VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VCC 50% Output Waveform 2 (See Note B) 50% 0V tPLZ ≈VCC 50% 10% ≈VCC VOL tPHZ 50% 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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