HD74LV2G74A Single D–type Flip Flops with Preset and Clear ADE-205-346C (Z) Rev.3 July 2001 Description The HD74LV2G74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 8 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as hitachi uni logic series. • Supplied on emboss taping for high speed automatic mounting. • Electrical characteristics equivalent to the HD74LV74A Supply voltage range : 1.65 to 5.5 V Operating temperature range : –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. HD74LV2G74A Outline and Article Indication • HD74LV2G74A Index band Lot No. Y M W L 7 4 Y : Year code (the last digit of year) M : Month code W : Week code SSOP–8 Type No. Function Table Inputs Outputs PRE CLR CLK D Q Q L H X X H L H L X X L H *1 H *1 L L X X H H H ↑ H H L H H ↑ L L H H H ↓ X Q0 Q0 H : High level L : Low level X : Immaterial ↑ : Low to high transition ↓ : High to low transition Q0 : The level of Q immediately before the input conditions shown in the above table are determined. Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if preset and clear go high simultaneously. Rev.3, Jul. 2001, page 2 of 12 HD74LV2G74A Pin Arrangement CLK 1 8 VCC D 2 7 PRE Q 3 6 CLR GND 4 5 Q (Top view) Rev.3, Jul. 2001, page 3 of 12 HD74LV2G74A Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol Ratings Unit VCC –0.5 to 7.0 V VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Test Conditions Output : H or L VCC : OFF Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3, Jul. 2001, page 4 of 12 HD74LV2G74A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC 1.65 5.5 V Input voltage range VI 0 5.5 V Output voltage range VO 0 VCC V Output current IOL — 1 mA — 2 VCC = 2.3 to 2.7 V — 6 VCC = 3.0 to 3.6 V — 12 VCC = 4.5 to 5.5 V — –1 VCC = 1.65 to 1.95 V — –2 VCC = 2.3 to 2.7 V — –6 VCC = 3.0 to 3.6 V — –12 VCC = 4.5 to 5.5 V 0 300 0 200 VCC = 2.3 to 2.7 V 0 100 VCC = 3.0 to 3.6 V 0 20 VCC = 4.5 to 5.5 V –40 85 IOH Input transition rise or fall rate ∆t / ∆v Operating free-air temperature Ta ns / V Conditions VCC = 1.65 to 1.95 V VCC = 1.65 to 1.95 V °C Note: Unused or floating inputs must be held high or low. Logic Diagram PRE C CLK C C Q TG D C C TG TG TG C C C C C Q CLR Rev.3, Jul. 2001, page 5 of 12 HD74LV2G74A Electrical Characteristic • Ta = –40 to 85°C Item Symbol VCC (V) * Input voltage VIH VIL Hysteresis voltage VH Output voltage VOH VOL Min Typ 1.65 to 1.95 VCC×0.75 — Max Unit — V 2.3 to 2.7 VCC×0.7 — — 3.0 to 3.6 VCC×0.7 — — 4.5 to 5.5 VCC×0.7 — — 1.65 to 1.95 — — VCC×0.25 2.3 to 2.7 — — VCC×0.3 3.0 to 3.6 — — VCC×0.3 4.5 to 5.5 — — VCC×0.3 1.8 — 0.25 — 2.5 — 0.30 — 3.3 — 0.35 — 5.0 — 0.45 — Min to Max VCC–0.1 — — Test condition + – V VT – VT V IOH = –50 µA 1.65 1.4 — — IOH = –1 mA 2.3 2.0 — — IOH = –2 mA 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 1.65 — — 0.3 IOL = 1 mA 2.3 — — 0.4 IOL = 2 mA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 Output leakage current IOFF 0 — — 5 µA VIN or VO = 0 to 5.5 V 3.3 — 2.5 — pF VIN = VCC or GND Input capacitance CIN Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3, Jul. 2001, page 6 of 12 HD74LV2G74A Switching Characteristics • VCC = 1.8 ± 0.15 V Item Symbol Ta = 25°C Ta = –40 to 85°C Unit Test FROM Min Typ Max Min Max Maximum clock fmax 30 60 — 20 — MHz CL = 15 pF frequency 20 40 — 15 — CL = 50 pF Propagation tPLH — 16.3 27.0 1.0 29.0 delay time tPHL — 17.9 29.0 1.0 32.0 — 21.6 34.0 1.0 36.5 — 24.5 39.5 1.0 42.5 13.0 — — 14.0 — Conditions (Input) ns CL = 15 pF TO (Output) PRE/CLR Q or Q CLK CL = 50 pF PRE/CLR Q or Q CLK Setup time tsu ns 9.0 — — 9.0 — Hold time th 0.5 — — 0.5 — ns Pulse width tw 12.0 — — 13.0 — ns 12.0 — — 13.0 — D PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” • VCC = 2.5 ± 0.2 V Item Symbol Ta = 25°C Ta = –40 to 85°C Unit Test FROM Min Typ Max Min Max Maximum clock fmax 50 100 — 40 — MHz CL = 15 pF frequency 30 70 — 25 — CL = 50 pF Propagation tPLH — 9.8 14.8 1.0 17.0 delay time tPHL — 11.1 16.4 1.0 19.0 — 13.0 17.4 1.0 20.0 — 14.2 20.0 1.0 23.0 8.0 — — 9.0 — Conditions (Input) ns CL = 15 pF TO (Output) PRE/CLR Q or Q CLK CL = 50 pF PRE/CLR Q or Q CLK Setup time tsu ns 7.0 — — 7.0 — Hold time th 0.5 — — 0.5 — ns Pulse width tw 8.0 — — 9.0 — ns 8.0 — — 9.0 — D PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” Rev.3, Jul. 2001, page 7 of 12 HD74LV2G74A Switching Characteristics (cont) • VCC = 3.3 ± 0.3 V Item Symbol Ta = 25°C Ta = –40 to 85°C Unit Test Min Typ Max Min Max Maximum clock fmax 80 140 — 70 — MHz CL = 15 pF frequency 50 90 — 45 — CL = 50 pF Propagation tPLH — 6.9 12.3 1.0 14.5 delay time tPHL — 7.9 11.9 1.0 14.0 — 9.2 15.8 1.0 18.0 — 10.2 15.4 1.0 17.5 6.0 — — 7.0 — FROM Conditions (Input) ns CL = 15 pF TO (Output) PRE/CLR Q or Q CLK CL = 50 pF PRE/CLR Q or Q CLK Setup time tsu ns 5.0 — — 5.0 — Hold time th 0.5 — — 0.5 — ns Pulse width tw 6.0 — — 7.0 — ns 6.0 — — 7.0 — D PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” • VCC = 5.0 ± 0.5 V Item Symbol Ta = 25°C Ta = –40 to 85°C Unit Test Min Typ Max Min Max Maximum clock fmax 130 180 — 110 — MHz CL = 15 pF frequency 90 140 — 75 — CL = 50 pF Propagation tPLH — 5.0 7.7 1.0 9.0 delay time tPHL — 5.6 7.3 1.0 8.5 — 6.6 9.7 1.0 11.0 — 7.2 9.3 1.0 10.5 5.0 — — 5.0 — Conditions (Input) ns CL = 15 pF TO (Output) PRE/CLR Q or Q CLK CL = 50 pF PRE/CLR Q or Q CLK Setup time tsu 3.0 — — 3.0 — Hold time th 0.5 — — 0.5 — ns Pulse width tw 5.0 — — 5.0 — ns 5.0 — — 5.0 — Rev.3, Jul. 2001, page 8 of 12 FROM ns D PRE or CLR inactive PRE or CLR “L” CLK “H” or “L” HD74LV2G74A Operating Characteristics • CL = 50 pF Item Symbol Power dissipation CPD capacitance VCC (V) Ta = 25°C Min Typ Max 3.3 — 13.0 — 5.0 — 14.0 — Unit Test Conditions pF f = 10 MHz Test Circuit VCC VCC Input PRE Pulse Generator Zout = 50 Ω D CL Input Pulse Generator Zout = 50 Ω Output Q Q CLK CLR Output Q Q CL Notes: 1. C L includes probe and jig capacitance. 2. Test is put into the each flip flops. Rev.3, Jul. 2001, page 9 of 12 HD74LV2G74A • Waveform – 1 tr tf 90 % 50 % Timming input 10 % t su VCC 90 % 10 % th 0V VCC Data input 50 % 50 % 0V tw VCC Input 50 % 50 % 0V • Waveform – 2 tr tf 90 % 50 % Input VCC 90 % 50 % 10 % 10 % 0V t PHL t PLH VOH Same-phase output 50 % 50 % VOL t PHL t PLH VOH Opposite-phase output 50 % 50 % VOL Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. 2. The output are measured one at a time with one transition per measurement. Rev.3, Jul. 2001, page 10 of 12 HD74LV2G74A Package Dimensions As of January, 2001 (0.4) 1.50 0.5 0.5 0.5 Unit: mm + 0.05 0.13 − 0.03 3.1 ± 0.1 (0.4) 2.3 ± 0.1 0 − 0.1 + 0.05 8 − 0.2 − 0.04 0.7 ± 0.1 (0.17) 2.0 ± 0.1 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-8DB 0.25 g Rev.3, Jul. 2001, page 11 of 12 HD74LV2G74A Disclaimer 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan. Colophon 4.0 Rev.3, Jul. 2001, page 12 of 12