HN58V1001 Series 1M EEPROM (128-kword × 8-bit) Ready/Busy and RES function ADE-203-314G (Z) Rev. 7.0 Oct. 31, 1997 Description The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word × 8bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the write operations faster. Features • Single 3 V supply: 2.7 V to 5.5 V • Access time: 250 ns (max) • Power dissipation Active: 20 mW/MHz, (typ) Standby: 110 µW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 15 ms (max) • Automatic page write (128 bytes): 15 ms (max) • Data polling and RDY/Busy • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology • 104 erase/write cycles (in page mode) • 10 years data retention • Software data protection • Write protection by RES pin HN58V1001 Series Ordering Information Type No. Access time Package HN58V1001P-25 250 ns 600 mil 32-pin plastic DIP (DP-32) HN58V1001FP-25 250 ns 525 mil 32-pin plastic SOP (FP-32D) HN58V1001T-25 250 ns 8 × 14 mm 32-pin plastic TSOP (TFP-32DA) Pin Arrangement HN58V1001P/FP Series RDY/Busy A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 RES WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 (Top view) Pin Description Pin name Function A0 to A16 Address input I/O0 to I/O7 Data input/output OE Output enable CE Chip enable WE Write enable VCC Power supply VSS Ground RDY/Busy Ready busy RES Reset 2 HN58V1001T Series A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) A4 A5 A6 A7 A12 A14 A16 RDY/Busy VCC A15 RES WE A13 A8 A9 A11 HN58V1001 Series Block Diagram I/O0to VCC I/O7 RDY/Busy High voltage generator VSS RES I/O buffer and input latch OE CE Control logic and timing WE RES A0 to Y decoder Y gating X decoder Memory array A6 Address buffer and latch A7 to A16 Data latch Operation Table Operation CE OE WE RES 1 RDY/Busy I/O High-Z Dout VIL VIL VIH VH * Standby VIH ×* × × High-Z High-Z Write VIL VIH VIL VH High-Z to V OL Din Deselect VIL VIH VIH VH High-Z High-Z Write Inhibit × × VIH × — — × VIL × × — — Data Polling VIL VIL VIH VH VOL Dout (I/O7) Program reset × × × VIL High-Z High-Z Read 2 Notes: 1. Refer to the recommended DC operating conditions. 2. × : Don’t care 3 HN58V1001 Series Absolute Maximum Ratings Parameter Symbol Value Unit Supply voltage relative to VSS VCC –0.6 to +7.0 V Vin 1 –0.5* to +7.0 V Topr 0 to +70 °C Tstg –55 to +125 °C Input voltage relative to V SS Operating temperature range* 2 Storage temperature range Notes: 1. Vin min = –3.0 V for pulse width ≤ 50 ns 2. Including electrical characteristics and data retention Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 5.5 V VSS 0 0 0 V Input voltage 1 VIL Operating temperature –0.3* — 0.8 V VIH 2 1.9* — VCC + 0.3 V VH Vcc – 0.5 — VCC + 1.0 V Topr 0 — 70 °C Notes: 1. VIL (min): –1.0 V for pulse width ≤ 50 ns 2. VIH (min): 2.2 V for VCC = 3.6 to 5.5 V DC Characteristics (Ta = 0 to +70 °C, VCC = 2.7 V to 5.5 V) Parameter Symbol Min Typ Max 1 Unit Test conditions µA VCC = 3.6 V, Vin =3.6 V Input leakage current I LI — — 2* Output leakage current I LO — — 2 µA VCC = 3.6 V, Vout = 3.6/0.4 V Standby V CC current I CC1 — — 20 µA CE = VCC I CC2 — — 1 mA CE = VIH I CC3 — — 6 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs at VCC = 3.3 V — — 15 mA Iout = 0 mA, Duty = 100%, Cycle = 250 ns at VCC = 3.3 V Operating VCC current Output low voltage VOL — — 0.4 V I OL = 2.1 mA Output high voltage VOH VCC × 0.8 — — V I OH = –400 µA Notes: 1. I LI on RES: 100 µA (max) 4 HN58V1001 Series Capacitance (Ta = 25°C, f = 1 MHz) Parameter 1 Input capacitance* 1 Output capacitance* Note: Symbol Min Typ Max Unit Test conditions Cin — — 6 pF Vin = 0 V Cout — — 12 pF Vout = 0 V 1. This parameter is periodically sampled and not 100% tested. AC Characteristics (Ta = 0 to +70 °C, VCC = 2.7 V to 5.5 V) Test Conditions • Input pulse levels: 0.4 V to 2.4 V 0 V to VCC (RES pin) • Input rise and fall time: 20 ns • Output load: 1TTL Gate +100 pF • Reference levels for measuring timing: 0.8 V, 1.8 V Read Cycle HN58V1001-25 Parameter Symbol Min Max Unit Test conditions Address to output delay t ACC — 250 ns CE = OE = VIL, WE = VIH CE to output delay t CE — 250 ns OE = VIL, WE = VIH OE to output delay t OE 10 120 ns CE = VIL, WE = VIH t OH 0 — ns CE = OE = VIL, WE = VIH t DF 0 50 ns CE = VIL, WE = VIH RES low to output float t DFR 0 350 ns CE = OE = VIL, WE = VIH RES to output delay t RR 0 600 ns CE = OE = VIL, WE = VIH Address to output hold 1 OE (CE) high to output float* *1 5 HN58V1001 Series Write Cycle Parameter Symbol Min*2 Typ Max Unit Address setup time t AS 0 — — ns Address hold time t AH 150 — — ns CE to write setup time (WE controlled) t CS 0 — — ns CE hold time (WE controlled) t CH 0 — — ns WE to write setup time (CE controlled) t WS 0 — — ns WE hold time (CE controlled) t WH 0 — — ns OE to write setup time t OES 0 — — ns OE hold time t OEH 0 — — ns Data setup time t DS 100 — — ns Data hold time t DH 10 — — ns WE pulse width (WE controlled) t WP 250 — — ns CE pulse width (CE controlled) t CW 250 — — ns Data latch time t DL 750 — — ns Byte load cycle t BLC 1.0 — 30 µs Byte load window t BL 100 — — Write cycle time t WC — Time to device busy t DB 120 Write start time Reset protect time 5 Reset high time* 4 Test conditions µs 3 — 15* ms — — ns — — ns t DW 250* t RP 100 — — µs t RES 1 — — µs Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. t WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy are used. 5. This parameter is sampled and not 100% tested. 6. A7 to A16 are page addresses and must be same within the page write operation. 7. See AC read characteristics. 6 HN58V1001 Series Timing Waveforms Read Timing Waveform Address tACC CE tOH tCE OE tDF tOE WE High Data Out Data out valid tRR tDFR RES 7 HN58V1001 Series Byte Write Timing Waveform (1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tBL tWP WE tOES tOEH OE tDS tDH Din tDW High-Z RDY/Busy tRP tRES RES VCC 8 tDB High-Z HN58V1001 Series Byte Write Timing Waveform (2) (CE Controlled) Address tWS tAH tBL tWC tCW CE tAS tWH WE tOES tOEH OE tDS tDH Din tDW RDY/Busy tDB High-Z High-Z tRP tRES RES VCC 9 HN58V1001 Series Page Write Timing Waveform (1) (WE Controlled) *6 Address A0 to A16 tAS tAH tBL tWP WE tDL tCS tBLC tWC tCH CE tOEH tOES OE tDH tDS Din RDY/Busy High-Z tRP RES VCC 10 tRES tDB tDW High-Z HN58V1001 Series Page Write Timing Waveform (2) (CE Controlled) *6 Address A0 to A16 tAS CE tAH tBL tCW tDL tWS tBLC tWC tWH WE tOEH tOES OE tDH tDS Din RDY/Busy High-Z tDB tDW High-Z tRP RES tRES VCC 11 HN58V1001 Series Data Polling Timing Waveform Address An An CE WE tOEH tCE *7 tOES OE tDW tOE*7 I/O7 12 Din X Dout X Dout X tWC HN58V1001 Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Notes: 1. 2. 3. 4. I/O6 beginning state is “1”. I/O6 ending state will vary. See AC read characteristics. Any location can be used, but the address must be fixed. Toggle bit Waveform Next mode *4 Address tCE *3 CE WE *3 tOE OE tOES tOEH *1 I/O6 Din Dout Dout tWC *2 *2 Dout Dout tDW 13 HN58V1001 Series Software Data Protection Timing Waveform (1) (in protection mode) VCC CE WE tBLC Address 5555 Data AA 5555 AAAA or 2AAA 55 A0 tWC Write address Write data Software Data Protection Timing Waveform (2) (in non-protection mode) VCC tWC CE WE Address Data 14 5555 AAAA or 2AAA 5555 5555 AAAA or 2AAA 5555 AA 55 80 AA 55 20 Normal active mode HN58V1001 Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or W E is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to V OL after the first write signal. At the end of write cycle, the RDY/Busy signal changes state to high impedance. RES Signal When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch function. VCC Read inhibit Read inhibit RES Program inhibit Program inhibit WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. 15 HN58V1001 Series Write/Erase Endurance and Data Retention Time The endurance is 10 4 cycles in case of the page programming and 103 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is pageprogrammed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less in program mode. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE VIH 0V VIH OE 0V 20 ns max 16 HN58V1001 Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during V CC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable (1) Protection by RES The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM brakes off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 15 ms after the last data input. VCC RES Program inhibit WE or CE 1 µs min 100 µs min Program inhibit 15 ms min 17 HN58V1001 Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. Address Data 5555 AA ↓ ↓ AAAA or 2AAA 55 ↓ ↓ 5555 A0 ↓ ↓ Write address Write data } Normal data input The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written. Address Data 5555 ↓ AAAA or 2AAA ↓ 5555 ↓ 5555 ↓ AAAA or 2AAA ↓ 5555 AA ↓ 55 ↓ 80 ↓ AA ↓ 55 ↓ 20 The software data protection is not enabled at the shipment. Note: There are some differences between Hitachi’s and other company’s for enable/disable sequence of software data protection. If there are any questions , please contact with Hitachi sales offices. 18 HN58V1001 Series Package Dimensions HN58V1001P Series (DP-32) Unit: mm 41.90 42.50 Max 17 13.4 13.7 Max 32 16 5.08 Max 1.20 2.30 Max 2.54 ± 0.25 0.48 ± 0.10 0.51 Min 2.54 Min 1 15.24 + 0.11 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-32 — Conforms 5.1 g 19 HN58V1001 Series Package Dimensions (cont.) HN58V1001FP Series (FP-32D) Unit: mm 20.45 20.95 Max 17 11.30 32 1 1.27 0.40 ± 0.08 0.38 ± 0.06 0.10 0.15 M Dimension including the plating thickness Base material dimension 20 0.12 0.15 +– 0.10 1.00 Max 0.22 ± 0.05 0.20 ± 0.04 3.00 Max 16 14.14 ± 0.30 1.42 0° – 8° 0.80 ± 0.20 Hitachi Code JEDEC EIAJ Weight (reference value) FP-32D Conforms — 1.3 g HN58V1001 Series Package Dimensions (cont.) HN58V1001T Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M Dimension including the plating thickness Base material dimension 0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.10 0.80 14.00 ± 0.20 0.45 Max 0.13 ± 0.05 0.22 ± 0.08 0.20 ± 0.06 0° – 5° Hitachi Code JEDEC EIAJ Weight (reference value) 0.50 ± 0.10 TFP-32DA Conforms Conforms 0.26 g 21 HN58V1001 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 22