HOLTEK HT23B60

HT23B60
60´11 Pixel Data Bank 8-Bit Mask MCU
Features
· Operating voltage range: 2.4V~5.5V
· Build-in Low Battery detector
· Program ROM: 32K´16 bits
· 14 bidirectional I/O lines, 16 bidirectional I/O lines are
share pin with segments
· Data RAM: 2.3K´8 bits
· LCD driver:
· 16-bit table read instructions
- Up to a max. of 60 segments and 11 common
- 660 dots, 1/4 or 1/5 bias capability, 1/10 or 1/11
· Eight-level subroutine nesting
· Timer
duty, R type
- Two 16-bit programmable timer counters
- Real time clock (RTC)
- Watchdog Timer (WDT)
- LCD com/seg driving strength can be adjusted to
compromise the display quality and current
consumption, adjustable 16-level VLCD
- Segment 0~15 supports Key Scan function
· Build-in a serial-parallel-interface hardware circuit
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
· Built-in 32768Hz x¢tal oscillator circuit
· Build-in a 8-bit PWM D/A hardware circuit
· Build-in circuit dual system clock 32768Hz, 3.58MHz
· 100-pin QFP package
General Description
HT23B60 is an 8-bit CMOS microcontroller with various
functionalities in a compact package such as SRAM,
ROM I/Os, interrupt controller, timer and LCD control-
ler/driver. It¢s suitable for use as electrical data bank,
LCD game, calendar and speech products.
Block Diagram
S T A
S T A
S T A
S T A
S T A
S T A
S T A
S T A
R E S
P ro g ra m
C o u n te r
P ro g ra m
R O M
C K 0
C K 1 3 2 7 6 8 H z IN T /P B 3
C K 2
C K 3
In te rru p t
C ir c u it
C K 4
C K 5
R
T
C
C K 6
IN T C
C K 7
T M R 0
T M R 0 C
S Y S C L K /4
M
T M R 2
3 .5 8 M H z /4
U
X
In s tr u c tio n
R e g is te r
M P 0
M P 1
M
U
X
D A T A
M e m o ry
T M R 2 C
A L U
O S C
C ir c u it
3 .5 8 M H z
V L C D
C O M 0
C O M 1
C O M 9
C O M 1 0
M
A C C
S T A T U S
Rev. 1.10
X
U
P W M 2
X
L C D
M e m o ry
L C D D r
6 0 ´ 1
1 /4 , 1 /5
1 /1 0 , 1 /1 1
P A
P A C
P A 0 ~ P A 7
P B
P B C
P B 0 ~ P B 5
S h ifte r
1
W D T S
W D T P r e s c a le r
3 2 7 6 8 H z
W D T O S C
S y s te m C lo c k /4
L o w
L B IN
iv e r
B ia s
D u ty
S E G 0
S E G 1
S E G 5 8
S E G 5 9
P W M 1
U
M U X
In s tr u c tio n
D e c o d e r
X IN
X O U T
X C
M
P F D
P W M D A C 2
T im in g
G e n e ra to r
3 2 7 6 8 H z
P W M D A C 1
V o lta g e D e te c to r
S e r ia l
In te rfa c e
S E G 0 ~ 1 5
K e y S c a n S tro b e
1
S C L K /P B 0
D I/P B 2
D O /P B 1
March 1, 2004
HT23B60
Pin Assignment
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
3 2
1
3 1
8 0
2
7 9
3
7 8
4
7 7
5
7 6
6
7 5
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
G 9
G 8
G 7
G 6
G 5
G 4
G 3
3 5
3 4
3 3
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E
S E
S E
S E
S E
S E
S E
7
7 4
8
7 3
9
7 2
1 0
7 1
1 1
7 0
1 2
6 9
1 3
6 8
1 4
6 7
H T 2 3 B 6 0
1 0 0 Q F P -A
1 5
1 6
1 7
6 6
6 5
6 4
1 8
6 3
1 9
6 2
2 0
6 1
2 1
6 0
2 2
5 9
2 3
5 8
2 4
5 7
2 5
5 6
2 6
5 5
2 7
5 4
2 8
5 3
2 9
3 0
5 2
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
5 1
S E G
S E G
N C
N C
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
C O M
C O M
C O M
C O M
C O M
C O M
C O M
N C
V L C
L B IN
X C
X IN
X O U
P W M
P W M
N C
N C
5 3
5 4
5 5
5 6
5 7
5 8
5 9
0
1
2
3
4
5
6
7
8
9
1 0
D
T
2
1
5
0
1
2
3
4
5
6
7
G 0
G 1
G 2
G N D
V C C
R E S
0 /S
1 /D
2 /D
3 /IN
4
P B
P B
P B
P B
P B
P B
P A
P A
P A
P A
P A
P A
P A
P A
S E
S E
S E
C L K
O
I
T
Rev. 1.10
2
March 1, 2004
HT23B60
Pad Assignment
8 8
8 7
8 6
8 5
8 4
S E G 2 9
8 9
S E G 2 8
9 0
S E G 2 7
S E G 1 9
9 1
S E G 2 6
S E G 1 8
9 2
S E G 2 5
S E G 1 7
9 3
S E G 2 3
S E G 1 6
9 4
S E G 2 4
S E G 1 5
9 5
S E G 2 2
S E G 1 4
9 6
S E G 2 0
S E G 1 3
9 7
S E G 2 1
S E G 1 2
9 8
S E G 1 1
9 9
S E G 9
1 0 0
S E G 1 0
S E G 8
1 0 1
S E G 7
1 0 2
S E G 6
1
S E G 5
S E G 4
S E G 3
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
S E G 3 0
7 5
S E G 3 1
3
7 4
S E G 3 2
S E G 0
4
7 3
S E G 3 3
P A 7
5
7 2
S E G 3 4
P A 6
6
7 1
S E G 3 5
P A 5
7
7 0
S E G 3 6
P A 4
8
6 9
S E G 3 7
P A 3
9
6 8
S E G 3 8
6 7
S E G 3 9
6 6
S E G 4 0
6 5
S E G 4 1
6 4
S E G 4 2
6 3
S E G 4 3
6 2
S E G 4 4
6 1
S E G 4 5
6 0
S E G 4 6
5 9
S E G 4 7
S E G 2
2
S E G 1
P A 2
1 0
P A 1
1 1
P A 0
1 2
P B 5
1 3
P B 4
1 4
P B 3 /IN T
1 5
P B 2 /D I
(0 ,0 )
1 6
3 5
3 7
3 8
C O M 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
S E G 5 6
3 6
C O M 1 0
V L C D
3 4
C O M 9
3 2
L B IN
X C
X O U T
X IN
P W M 1
P W M 2
G N D
3 0
S E G 5 7
S E G 5 5
2 4
3 3
S E G 5 8
S E G 5 4
5 1
2 5
2 3
2 7
3 1
S E G 5 9
S E G 5 3
5 2
2 8
2 6
2 9
C O M 0
5 3
2 2
C O M 1
S E G 5 2
G N D
2 1
C O M 2
S E G 5 1
5 4
V C C
C O M 3
S E G 5 0
5 5
C O M 4
2 0
V C C
C O M 5
S E G 4 9
5 6
C O M 6
5 7
C O M 7
S E G 4 8
1 9
T R IM 4
5 8
R E S
T R IM 3
1 8
T R IM 2
P B 0 /S C L K
T R IM 0
1 7
T R IM 1
P B 1 /D O
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.10
3
March 1, 2004
HT23B60
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
-1348.345
-1334.345
-1334.345
-1334.345
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1330.600
-1323.500
-1282.800
-1323.500
-1323.500
-1191.900
-1083.800
-945.113
-835.109
-683.945
-519.280
-477.416
-425.640
-373.864
-312.995
-257.745
-207.745
-157.745
-107.745
-57.745
42.255
142.255
242.255
342.255
442.255
542.255
642.255
742.255
842.255
942.255
1042.255
1142.255
11314.745
1337.600
1076.850
966.250
866.250
746.150
635.550
535.550
424.950
324.950
214.350
114.350
3.750
-96.250
-206.850
-306.850
-417.450
-517.450
-628.050
-729.826
-863.400
-970.900
-1110.150
-1305.950
-1307.450
-1307.450
-1293.950
-1293.950
-1217.385
-1153.900
-1321.600
-1153.900
-1321.600
-1153.860
-1320.790
-1153.861
-1320.790
-1153.821
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1320.790
-1352.900
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1314.745
1346.855
1246.855
1146.855
1046.855
946.855
846.855
746.855
646.855
546.855
446.855
346.855
246.855
146.855
46.855
-84.745
-184.745
-295.345
-395.345
-505.945
-605.945
-716.545
-816.545
-927.145
-1027.145
-1137.745
-1237.745
-1252.900
-1152.900
-1052.900
-952.900
-852.900
-752.900
-652.900
-552.900
-452.900
-352.900
-252.900
-152.900
-52.900
47.100
147.100
247.100
347.100
447.100
547.100
647.100
747.100
847.100
947.100
1047.100
1147.100
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1319.590
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
1337.600
Rev. 1.10
4
March 1, 2004
HT23B60
Pad Description
Pad No.
Pad Name
I/O
Mask
Option
Description
¾
Selectable as LCD segment signal output or keyscan strobe signal.
4~1
SEG0~3
O
12~5
PA0~PA7
I/O
14~13
PB4~PB5
I/O
15
Bidirectional 8-bit input/output port. Each bit can be configured as
Wake-up wake-up input by mask option. Software instructions determine the
or None CMOS output or Schmitt trigger input with or without pull-high register by register [35H].
¾
Bidirectional 2-bit input/output port
Schmitt trigger input with or without pull-high register by software option or CMOS output
¾
Software instructions determine the bidirectional input/output pin or
external interrupt Schmitt trigger input or CMOS output. When the
[INTC0].1 is set to ²1² the PB3 will used to external interrupt input pin.
For I/O pin: Schmitt trigger input with or without pull-high register by
software option or CMOS output
For INT: Edge trigger activated on a falling edge.
PB3/INT
I/O
16
PB2/DI
Can be optioned as bidirectional input/output or serial data input.
I/O
Serial For I/O pin: Schmitt trigger input or CMOS output, see mask option
or
Data Input table for pull-high function
I
For serial data input: serial data input without pull-high resistor
17
PB1/DO
I/O
or
O
Serial
Data
Output
Can be optioned as bidirectional input/output or serial data output.
For I/O pin: Schmitt trigger input or CMOS output, see mask option
table for pull-high function
For serial data output: SK is a CMOS output
I/O
SCLK
Signal
Can be optioned as bidirectional input/output or serial interface clock
signal.
For I/O pin: Schmitt trigger input with or without pull-high resistor by
register [36H] or CMOS output
For serial interface clock signal: Use as serial I/O interface clock
signal
SCLK should be set as serial clock output and after 8 clocks from the
SCLK terminal, clock output is automatically suspended.
18
PB0/SCLK
19
RES
I
¾
Schmitt trigger reset input. Active low.
20, 21
VDD
¾
¾
Positive power supply
22, 23
VSS
¾
¾
Negative power supply, ground
24
PWM1
O
¾
Positive PWM CMOS output
25
PWM2
O
¾
Negative PWM CMOS output
26
XOUT
O
¾
A 32768Hz crystal (or resonator) should be connected to this pin and
XIN
27
XIN
I
¾
A 32768Hz crystal (or resonator) should be connected to this pin and
XOUT
28
XC
I
¾
External low pass filter used for frequency up conversion circuit
29
31
33
35
37
TRIM0
TRIM1
TRIM2
TRIM3
TRIM4
¾
¾
Test pin only
30
LBIN
I
¾
This pin detects battery low through external R1/R2 to determine
threshold, when the low voltage detect function is disabled, the
²LBIN² pin should be connected to VDD.
32
VLCD
I
¾
LCD voltage input
Rev. 1.10
5
March 1, 2004
HT23B60
Pad No.
Pad Name
I/O
Mask
Option
Description
46~38,
36
34
COM0~8
COM9
COM10
O
¾
LCD common signal output
102~47
SEG4~59
O
¾
LCD segment signal output
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Storage Temperature ...........................-55°C to 150°C
Input Voltage ............................ VSS-0.5V to VDD+0.5V
Operating Temperature ..........................-10°C to 70°C
Current Drain Per Pin Excluding VDD and VSS ...................................................................................................10mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
VDD
Operating Voltage
¾ 3V application
2.4
3.0
5.5
V
IDD1
Operating Current (In Normal Mode)
32768Hz on, 3.58MHz on,
3V CPU on, LCD on, WDT on,
no load
¾
1
1.5
mA
IDD2
Operating Current (In Green Mode)
32768Hz on, 3.58MHz off
3V CPU on, LCD off, WDT off,
no load
¾
8
15
mA
ISTB1
Standby Current 1 (In Sleep Mode)
32768Hz on, 3.58MHz off,
3V CPU off, LCD off, WDT off,
no load
¾
2.5
3
mA
ISTB2
Standby Current 2 (In Idle Mode)
32768Hz off, 3.58MHz off,
3V CPU off, LCD off, WDT off,
no load
¾
¾
1
mA
VIL
Input Low Voltage for I/O Port
3V
¾
0
¾
1.0
V
VIH
Input High Voltage for I/O Port
3V
¾
2.0
¾
VDD
V
VOL
Output Low Voltage
3V
¾
¾
¾
0.4
V
VOH
Output High Voltage
3V
¾
2.3
¾
VDD
V
IOL1
I/O Port Sink Current
3V VOL=0.3V
8
13
¾
mA
IOH1
I/O Port Source Current
3V VOH=2.7V
-4
-8
¾
mA
IOL2
Segment, Common Output Sink Current
3V VOL=0.3V
270
480
¾
mA
IOH2
Segment, Common Output Source Current
3V VOH=2.7V
-100 -140
¾
mA
IOL3
PWM Sink Current
3V VOL=0.3V
16
26
¾
mA
IOH3
PWM Source Current
3V VOH=2.7V
-16
-26
¾
mA
RPH
Pull-high Resistance of I/O Ports
3V
¾
30
60
90
kW
LBIN
Low Battery Detection Reference Voltage
3V
¾
Rev. 1.10
6
1.10 1.15 1.20
V
March 1, 2004
HT23B60
A.C. Characteristics
Symbol
Ta=25°C
Parameter
Test Conditions
VDD
Conditions
Min. Typ. Max. Unit
fSYS1
Operating System Clock (In Green Mode)
3V
¾
¾
32
¾
kHz
fSYS2
Operating System Clock (In Normal Mode)
3V
¾
¾
3.58
¾
MHz
tSTB
Green Mode to Normal Mode System
Frequency Stable Time
3V
¾
¾
¾
20
ms
tWDTOSC1 Watchdog Oscillator Period
3V
¾
45
90
180
ms
tWDTOSC2 Watchdog Time-out Period (WDT OSC)
3V Without WDT prescaler
23
45
90
ms
tWDT2
Watchdog Time-out Period (System Clock)
3V Without WDT prescaler
¾
512
¾
tSYS
tWDT3
Watchdog Time-out Period (32kHz OSC)
3V Without WDT prescaler
¾
15.6
¾
ms
tRESET
RESET Input Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up timer Period
¾
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Rev. 1.10
7
March 1, 2004
HT23B60
Functional Description
Execution Flow
Program Counter - PC
The system clock for the HT23B60 is derived from a
32768Hz crystal oscillator. A built-in frequency up conversion circuit provides dual system clock, namely
32768Hz and 3.58MHz. The system clock is internally
divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are executed.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by 1. The program counter then points to
the memory word containing the next instruction code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
T 3
T 4
C lo c k
O S C 2 (R C
B a n k 0
1 3 b its
P ro g ra m
C o u n te r
o n ly )
P C
P C
P C + 1
0 0 0 0 H
P C + 2
1 F F F H
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
S ta c k
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
B a n k 1
2 0 0 0 H
3 F F F H
B a n k 2
8 1 9 2 ´ 1 6
B its
B a n k 3
4 0 0 0 H
5 F F F H
6 0 0 0 H
7 F F F H
B a n k P o in te r
R e g is te r
B it6 ,B it5
A 1 4 ,A 1 3
B u ffe r
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n
3 2 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution Flow
Mode
Program ROM Address
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer Counter 0 Overflow
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer Counter 2 Overflow
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Keyscan Overflow
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
RTC Overflow
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
PWM Interrupt
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Initial Reset
External or Serial Input
Interrupt
Skip
PC+2
Loading PCL
*14
*13
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
BP.6 BP.5 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S14 S13 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program ROM Address
Note: *14~*0: Program ROM address
S14~S0: Stack register bits
@7~@0: PCL bits
BP.5, BP.6: Bit 5, 6 of bank pointer (04H)
#12~#0: Instruction code bits
Rev. 1.10
8
March 1, 2004
HT23B60
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is obtained.
0 0 0 0 H
0 0 0 4 H
0 0 0 8 H
0 0 0 C H
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256
locations.
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l o r S e r ia l In p u t In te r r u p t S u b r o u tin e
T im e r C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r 2 In te r r u p t S u b r o u tin e
0 0 1 0 H
0 0 1 4 H
0 0 1 8 H
0 0 2 0 H
When a control transfer takes place, an additional
dummy cycle is required.
K e y s c a n In te rru p t
R T C
P W M
In te r r u p t S u b r o u tin e
D /A In te r r u p t S u b r o u tin e
P ro g ra m
R O M
Program Memory - ROM
The program memory, which contains executable program instructions, data and table information, is composed of a 32768´16 bit format. However as the PC
(program counter) is comprised of only 13 bits, the remaining 2 ROM address bits are managed by dividing
the program memory into 4 banks, each bank having a
range between 0000H and 1FFFH. To move from the
present ROM bank to a different ROM bank, the higher 2
bits of the ROM address are set by the BP (Bank
Pointer), while the remaining 13 bits of the PC are set in
the usual way by executing the appropriate jump or call
instruction. As the full 15 address bits are latched during
the execution of a call or jump instruction, the correct
value of the BP must first be setup before a jump or call
is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank
the program is in the program will always jump to the appropriate interrupt service address in Bank 0. The original full 15 bit address will be stored on the stack and
restored when the relevant RET/RETI instruction is executed, automatically returning the program to the original ROM bank. This eliminates the need for
programmers to manage the BP when interrupts occur.
7 F F F H
1 6 b its
Program Memory
· Location 00CH
This area is reserved for the timer 2 interrupt service
program. If a timer interrupt resulting from a timer 2
overflow, and if the interrupt is enabled and the stack
is not full, the program will jump to location 00CH and
begins execution.
· Location 010H
This area is reserved for the keyscan interrupt
When the keyscan function is enabled and the stack is
not full, the program begins execution a location 010H
on each common clock.
· Location 014H
This location is reserved for real time clock (RTC) interrupt service program. When the RTC generator is
enabled and time-out occurs, the RTC interrupt is enabled and the stack is not full, the program begins execution at location 014H.
Certain locations in Bank 0 of program memory are reserved for special usage:
· Location 018H
This area is reserved for the PWM D/A buffer empty
interrupt service program. After the system latch a D/A
code at RAM address 28H, if the interrupt is enabled
and the stack is not full, the program begins execution
at location 018H.
· ROM Bank 0 (BP5~BP6=00B)
The ROM bank 0 ranges from 0000H to 1FFFH.
· Location 000H
This area is reserved for the initialization program. After a chip reset, the program always begins execution
at location 000H.
· Location 020H
For best condition, this location is reserved at the beginning when writing a program.
· Location 004H
· ROM Bank 1~3 (BP5~BP6=01B~11B)
This area is reserved for the external interrupt or serial
input interrupt service routine. If the INT input pin is
activated, and the interrupt is enabled and the stack is
not full, the program will jump to location 004H and begins execution.
The range of the ROM starts from n000H to (n+1)
FFFH. (n=2,4,6)
· Table location
Any location in the ROM space can be used as look up
table. The instructions ²TABRDC [m]² (use for any
bank) and² TABRDL [m]² (only used for last page of
program ROM) transfers the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is
· Location 008H
This area is reserved for the timer counter 0 interrupt
service program. If a timer interrupt results from a timer
counter 0 overflow, and if the interrupt is enabled and
the stack is not full, the program will jump to location
008H and begins execution.
Rev. 1.10
9
March 1, 2004
HT23B60
Data Memory - RAM
well-defined, the higher-order byte of the table word
are transferred to the TBLH. The Table Higher-order
byte register (TBLH) is read only. The Table Pointer
(TBHP, TBLP) is a read/write register (1FH, 07H),
used to indicate the table location. Before accessing
the table, the location must be placed in TBLP. The
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR. If this happens, errors can occur. In other words, using the table
read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table
read instruction has to be applied in both the main routine and the ISR, the interrupts should be disabled
prior to the table read instruction. It should not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the
operation. These areas may function as normal program memory depending upon requirements.
The data memory is designed with (192´12)´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory. Most are read/write, but some are read only.
· Bank 0 (BP4~BP0=0000H)
The Bank 0 data memory includes special purpose
and general purpose memory. The special purpose
memory is addressed from 00H to 3FH. The special
function registers include the indirect addressing registers (IAR0:00H, IAR1:02H), timer counter 0 higher
order byte register (TMR0H: 0CH), timer counter 0
lower order byte register (TMR0L: 0DH), timer counter
0 control register (TMR0C: 0EH), timer 2 lower-order
byte register (TMR2L:2BH), timer 2 higher-order byte
register (TMR2H:2AH), timer 2 control register
(TMR2C:2CH), real timer clock control register (RTC:
24H), program counter lower-order byte register
(PCL: 06H), memory pointer registers (MP0: 01H,
MP1:03H), accumulator (ACC:05H), table pointer
lower-order byte register (TBLP: 07H), table pointer
higher-order byte register (TBHP:1FH), table
higher-order byte register(TBLH:08H), status register
(STATUS:0AH), interrupt control register 0
( I N T C 0 : 0 B H ) , i n t e r r u p t co n t r o l r e g i st e r 1
(INTC1:1EH), watchdog timer option setting register
(WDTS:09H), PLL control register (OPMODE:26H),
LCD control register (LCDC:2DH), LCD bright control
register (VLCDC:34H), LCD segment output port 0
data register (LCDPC: 37H), LCD segment output
port 0 control register (LCDPCC: 38H), LCD segment
output port 1 data register (LCDPD:39H), LCD segment output port 1 control register (LCDPDC:3AH),
PFD control register (PFDC:2FH), PWM data register
(PWM:31H), PWM control register (PWMC:30H), serial data register (SRD:33H), serial control register
(SRC:32H), I/O registers (PA:12H, PB:14H) , I/O control registers (PAC:13H, PBC:15H) and pull-high control register (PAPHC:35H, PBPHC:36H).
The general purpose data memory, addressed from
40H to FFH, is used for data and control information
under instruction commands. All data memory areas
can handle arithmetic, logic, increment, decrement
and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and
reset by the ²SET [m].i² and ²CLR [m].i² instructions,
respectively. They are also indirectly accessible
Stack Register - STACK
This is a special part of memory which is used to save
the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction (²RET² or ²RETI²), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
If the stack is full and a non-masked interrupt takes place,
the interrupt request flag will be recorded but the acknowledge will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced.
This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address
are stored).
Instruction
Table Location
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#6
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: @7~@0: TBLP register bit7~bit0
*14~*0: Current program ROM table address bit14~bit0
#6~#0: TBHP register bit6~bit0
Rev. 1.10
10
March 1, 2004
HT23B60
0 0 H
IA R 0
0 1 H
M P 0
M e m o r y P o in te r 0
0 2 H
IA R 1
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
M e m o r y P o in te r 1
0 4 H
B P
B a n k P o in te r
0 5 H
A C C
A c c u m u la to r
0 6 H
P C L
0 3 H
0 7 H
T B L P
through the memory pointer registers (MP0;01H,
MP1;03H).
In d ir e c t A d d r e s s in g R e g is te r 0
P ro g ra m
· Bank 1~11(BP4~PB0=0001B~1011B)
The range of RAM starting from 40H to FFH are for
general purpose. Only MP1 can deal with the memory
of this range.
C o u n te r L o w e r - b y te R e g is te r
T a b le P o in te r L o w e r - o r d e r B y te R e g is te r
0 8 H
T B L H
T a b le H ig h e r - o r d e r B y te R e g is te r
0 9 H
W D T S
W a tc h d o g T im e r O p tio n S e ttin g R e g is te r
0 A H
S T A T U S
· Bank 15 (BP4~BP0=1111B)
S ta tu s R e g is te r
0 B H
IN T C 0
In te r r u p t C o n tr o l R e g is te r 0
0 C H
T M R 0 H
T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r
0 D H
T M R 0 L
T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r
0 E H
T M R 0 C
T im e r C o u n te r 0 C o n tr o l R e g is te r
The range of RAM starts from 80H to FBH (BCH~BFH
can¢t be used). Every bit stands for one dot on the
LCD. If the bit is ²1², the light of the dot on the LCD will
be turned on. If the bit is ²0², then it will be turned off.
Only MP1 can deal with the memory of this range.
The contrast form of RAM location, COMMON, and
SEGMENT is as follows.
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
P A I/O
P A I/O
P B I/O
D a ta R e g is te r
C o n tr o l R e g is te r
P B I/O
D a ta R e g is te r
C o n tr o l R e g is te r
1 6 H
1 7 H
LCD Driver Output
1 8 H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 9 H
The maximum output number of the HT23B60 LCD
driver is 11´60. The Common output signal can be selected as 11 com or 10 com and 1/4 or 1/5 bias by mask
option. The LCD driver used the voltage of VLCD pin to
the power source. To adjust the view angle, the programmer can select the real LCD power by the register
34H. Some of the Segment outputs share pins with
keyscan outputs (seg0~15). Whether segment output or
keyscan outputs can be determined by software option.
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
IN T C 1
T B H P
In te r r u p t C o n tr o l B y te R e g is te r 1
T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
R T C
R e a l T im e C lo c k C o n tr o l R e g is te r
O P M O D E
O P M o d e ( P L L C o n tr o l)
T M R 2 H
T im e r C o u n te r 2 H ig h e r - o r d e r B y te R e g is te r
T M R 2 L
T im e r C o u n te r 2 L o w e r - o r d e r B y te R e g is te r
T M R 2 C
T im e r C o u n te r 2 C o n tr o l R e g is te r
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
L C D C
L C D
D r iv e r C o n tr o l R e g is te r
P F D C
P F D
C o n tr o l R e g is te r
P W M C
P W M
C o n tr o l R e g is te r
P W M
P W M
S e r ia l C o n tr o l R e g is te r
S e r ia l D a ta R e g is te r
L C D
P A P H C
3 6 H
P B P H C
P o r t B P u ll- h ig h C o n tr o l R e g is te r
3 7 H
L C D P C
S e g m e n t O u tp u t P o r t 0 D a ta R e g is te r
3 8 H
L C D P C C
S e g m e n t O u tp u t P o r t 0 C o n tr o l R e g is te r
3 9 H
L C D P D
S e g m e n t O u tp u t P o r t 1 D a ta R e g is te r
3 A H
3 B H
L C D P D C
S e g m e n t O u tp u t P o r t 1 C o n tr o l R e g is te r
F F H
4 0 H
F F H
4 0 H
F F H
8 0 H
F B H
¾
B r ig h t C o n tr o l R e g is te r
G e n e ra l P u rp o s e
B a n k 0 D a ta M e m o ry
(1 9 2 B y te )
: U n u s e d
LCDC
(2DH)
2
¾
3
4
G e n e ra l P u rp o s e
B a n k 1 1 D a ta M e m o ry
(1 9 2 B y te )
¾
5, 6
B a n k 1 5 D a ta M e m o ry
(1 2 0 B y te )
LCDON
7
RAM Mapping
Rev. 1.10
LVEN
LVFG
G e n e ra l P u rp o s e
B a n k 1 D a ta M e m o ry
(1 9 2 B y te )
Function
0~1 RO Unused bit, read as ²0²
P o r t A P u ll- h ig h C o n tr o l R e g is te r
3 5 H
3 F H
4 0 H
Register Label Bits R/W
D a ta R e g is te r
S R C
S R D
V L C D C
LCD driver output can be enabled or disabled by setting
the LCD (bit7 of LCDC; 2DH) without the influence of the
related memory condition. Only MP1 can deal with the
memory of this range. The contrast form of RAM location, COMMON and SEGMENT is as follows:
To enable/disable the low
RW voltage detection function
(0: disable; 1: enable)
R
Unused bit, read as ²0²
1: LBIN pin voltage is less
than low voltage
detection level
RO
0: LBIN voltage is not less
than low voltage
detection level
R
Unused bit, read as ²0²
To enable/disable the
RW LCD output
(0: disable; 1: enable)
LCDC Register
11
March 1, 2004
HT23B60
VLCDC register (34H)
LCD Level
Bit7
Bit6
Bit5
Bit4
1
0
0
0
0
0.66´VLCD
2
0
0
0
1
0.68´VLCD
3
0
0
1
0
0.70´VLCD
4
0
0
1
1
0.72´VLCD
5
0
1
0
0
0.74´VLCD
6
0
1
0
1
0.77´VLCD
7
0
1
1
0
0.80´VLCD
8
0
1
1
1
0.83´VLCD
9
1
0
0
0
0.86´VLCD
10
1
0
0
1
0.88´VLCD
11
1
0
1
0
0.90´VLCD
12
1
0
1
1
0.92´VLCD
13
1
1
0
0
0.94´VLCD
14
1
1
0
1
0.96´VLCD
15
1
1
1
0
0.98´VLCD
16
1
1
1
1
1.00´VLCD
Note: VLCD=2.4V~5.5V
The range of RAM starts from 80H to FBH
Address 80H
COM0
Bit0
COM1
Bit1
COM2
Bit2
COM3
Bit3
COM4
Bit4
COM5
Bit5
COM6
Bit6
COM7
Bit7
Address C0H
COM8
Bit0
COM9
Bit1
COM10
Bit2
81H
82H
83H
84H
85H 86H- - - - B4H B5H
B6H
B8H
B9H
BAH
BBH
C1H
C2H
C3H
C4H
C5H C6H - - - F5H F6H
F7H
F8H
F9H
FAH
FBH
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6-SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59
LCD Display Memory: (Bank15)
Note:
C0~FB, bit3~7, R=0
BCH~BFH, R=0; FC~FFH, R=0
1: LCD pixels on
0: LCD pixels off
Rev. 1.10
12
March 1, 2004
HT23B60
An example of an LCD driving waveform is shown below:
1/11 duty, 1/5 bias
4 6 .5 4 H z
3
2
1
4
6
5
8
7
9
1 0
1 1
1
3
2
4
5
8
7
6
9
1 0
1 1
1 0
1
2
1
2
3
1 0 2 4 H z
C O M 0
C O M 1
S E G 0
4 /5
3 /5
2 /5
1 /5
V D
V D
V D
V D
V D
G N
4 /5
3 /5
2 /5
1 /5
V D
V D
V D
V D
V D
G N
4 /5
3 /5
2 /5
1 /5
V D D
V D D
V D D
V D D
V D D
G N D
D
D
D
D
D
D
D
D
D
D
D
D
1/10 duty, 1/5 bias
5 1 .2 H z
1
2
3
4
5
6
7
8
9
1 0
1
2
3
4
5
6
7
8
9
3
1 0 2 4 H z
C O M 0
C O M 1
S E G 0
4 /5
3 /5
2 /5
1 /5
V D
V D
V D
V D
V D
G N
4 /5
3 /5
2 /5
1 /5
V D
V D
V D
V D
V D
G N
4 /5
3 /5
2 /5
1 /5
V D D
V D D
V D D
V D D
V D D
G N D
Rev. 1.10
D
D
D
D
D
D
D
D
D
D
D
D
13
March 1, 2004
HT23B60
1/11 duty, 1/4 bias
4 6 .5 4 H z
3
2
1
4
6
5
8
7
1 0
9
1 1
1
3
2
4
5
8
7
6
9
1 0
1 1
1 0
1
2
1
2
3
1 0 2 4 H z
C O M 0
C O M 1
S E G 0
V D D
D D
D D
D D
N D
3 /4 V
2 /4 V
1 /4 V
G
V
3 /4 V
2 /4 V
1 /4 V
G
D D
D D
D D
D D
N D
V D D
D D
D D
D D
N D
3 /4 V
2 /4 V
1 /4 V
G
1/10 duty, 1/4 bias
5 1 .2 H z
1
2
3
4
5
6
7
8
9
1 0
1
2
3
4
5
6
7
8
9
3
1 0 2 4 H z
C O M 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
C O M 1
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
S E G 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
Rev. 1.10
14
March 1, 2004
HT23B60
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition, operations related to the status register may give different results from those intended. The TO and PDF flags can
only be changed by a system power up, Watchdog
Timer overflow, executing the ²HALT² instruction and
clearing the Watchdog Timer.
Indirect Addressing Register
Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write
operation of [00H] and [02H] access data memory
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly returns the result
00H, while writing to it results in no operation.
The data movement function between two indirect addressing registers is not supported. The memory pointer
registers MP0 and MP1, are 8-bit registers used to access the data memory by combining corresponding indirect addressing registers, Bank1~Bank11 and Bank15
can use MP1 only.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status register are important and the subroutine can
corrupt the status register, the programmer must take
precautions to save it properly.
Accumulator
The accumulator is closely related to ALU operations. It
is mapped to location 05H of the data memory and can
also operate with immediate data. The data movement
between two data memory must pass through the accumulator.
Interrupt
The HT23B60 provides external and a D/A interrupt and
internal timer counter interrupts. The interrupt control
register (INTC;0BH, INTCH;1EH) contains the interrupt
control bits to set the enable/disable and the interrupt request flags.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt
needs servicing within the service routine, the EMI bit and
the corresponding INTC bit may be set to allow interrupt
nesting. If the stack is full, the interrupt request will not be
acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
can also change the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag
(TO). It also records the status information and controls the
operation sequence.
Register
STATUS
(0AH)
Labels
Bits
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow
does not take place during a subtraction operation; otherwise C is cleared. It is also
affected by a rotate through carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is
cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry
out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.
TO
5
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.
¾
Rev. 1.10
All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter and A14~A13 bits onto the
6,7
Unused bit, read as ²0²
15
March 1, 2004
HT23B60
stack and then branching to subroutines at specified locations in the program memory. Only the program counter are pushed and A14~A13 bits onto the stack. If the
contents of the register and Status register (STATUS)
are altered by the interrupt service program which corrupt the desired control sequence, the contents must be
saved first.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction
is executed or the EMI bit and the related interrupt control bit
are set to 1 (of course, if the stack is not full). To return from
the interrupt subroutine, the ²RET² or ²RETI² instruction
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
External interrupt is triggered by a high to low transition
of INT which sets the related interrupt request flag (EIF;
bit 4 of INTC0). When the interrupt is enabled, and the
stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt request flag (T0F; bit 5
of INTC0), caused by a timer counter 0 overflow. When
the interrupt is enabled, and the stack is not full and the
T0F bit is set, a subroutine call to location 08H will occur.
The related interrupt request flag (T0F) will be reset and
the EMI bit cleared to disable further interrupts.
The timer counter 2 interrupt is operated in the same
manner as Timer counter 0. The related interrupt control
bits ET2I and T2F of timer counter 2 are bit 3 and bit 6 of
INTC0 respectively.
Interrupt Source
INTC0
(0BH)
Rev. 1.10
Bit No.
EMI
0
External interrupt
1
04H
Timer counter 0 overflow
2
08H
Timer counter 2 overflow
3
0CH
Keyscan interrupt
4
10H
RTC interrupt
5
14H
PWM D/A interrupt
6
18H
It is recommended that application programs do not use
CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and the interrupt enable is not well controlled, once a CALL subroutine, if used in the interrupt
subroutine, will corrupt the original control sequence.
The keyscan interrupt is generated by LCD enable function. When the bit7 of the LCDC (2DH) is set ²1², for every frame, each have a common signal all of which can
generate a single interrupt. And the keyscan function
have to be completed in the period of interrupt time.
Label
Vector
EMI, EEI, ET0I, ET2I, EKSI, ERTCI, EPWMI are used to
control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the
interrupt request flags (EIF, T0F, T2F, KSF, RTCF, PWMF)
are set by hardware or software, they will remain in the
INTC0 or INTC1 registers until the interrupts are serviced or cleared by a software instruction.
The real time clock interrupt is generated by a 2Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a subroutine call to location 14H will occur. The interrupt request flag RTCF and EMI bits will be cleared to disable
other interrupts.
Register
Priority
Function
Master (Global) interrupt (1=enable; 0=disable)
EEI
1
External interrupt (1=enable; 0=disable)
ET0I
2
Timer counter 0 interrupt (1=enable; 0=disable)
ET2I
3
Timer counter 2 interrupt (1=enable; 0=disable)
EIF
4
External interrupt request flag (1=active; 0=inactive)
T0F
5
Internal timer counter 0 request flag. (1=active; 0=inactive)
T2F
6
Internal timer counter 2 request flag. (1=active; 0=inactive)
¾
7
Unused bit, read as ²0²
16
March 1, 2004
INTCH register
HT23B60
Register
INTC1
(1EH)
Label
Bit No.
Function
EKSI
0
Controls the keyscan interrupt. (1=enable; 0=disable)
ERTCI
1
Controls the RTC interrupt. (1=enable; 0=disable)
EPWMI
2
PWM D/A interrupt (1=enable; 0=disable)
¾
3
Should be set ²0² always.
KSF
4
Keyscan interrupt request flag. (1=active; 0=inactive)
RTCF
5
RTC interrupt request flag. (1=active; 0=inactive)
PWMF
6
PWM D/A flag (1=enable; 0=disable)
¾
7
Should be set ²0² always.
Oscillator Configuration
Watchdog Timer - WDT
There are two oscillator circuits in the controller, the external 32768Hz crystal oscillator and internal WDT RC
oscillator.
The WDT clock source is implemented by a WDT OSC
or external 32768Hz or an instruction clock (system
clock divided by 4), determined by mask option. This
timer is designed to prevent software malfunction or
protect the sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer
can be disabled by mask option. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation.
The 32768Hz crystal oscillator and frequency-up conversion circuit (32768Hz to 3.58MHz) are designed for
dual system clock source. It is necessary for the frequency conversion circuit to add external RC components to make up the low pass filter that stabilize the
output frequency 3.58MHz (see the oscillator circuit).
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
The WDT RC oscillator is a free running on-chip RC oscillator, and no external components are required. Even
if the system enters the Idle mode (the system clock is
stopped), the WDT RC oscillator still works within a period of 65ms~78ms. When the WDT is disabled or the
WDT source is not this RC oscillator, the WDT RC
oscillator will be disabled.
When the WDT clock source is selected, it will be first divided by 512 (9-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
3 2 7 6 8
X 1
X 2
The WDT OSC period is 78ms. This time-out period may
vary with temperature, VDD and process variations. The
WDT OSC always works for any operation mode.
1 5 k W
X C
3 n F
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except
in the Sleep mode or Idle mode. In these two modes, the
WDT stops counting and lose its protecting purpose. In
this situation the logic can only be re-started by external
logic.
5 0 n F
System Oscillator Circuit
Register
WDTS
(09H)
Rev. 1.10
Label
Bits
R/W
Function
WS0
WS1
WS2
0
1
2
RW
Watchdog Timer division ratio selection bits
Bit 2, 1, 0=000, Division ratio=1:1
Bit 2, 1, 0=001, Division ratio=1:2
Bit 2, 1, 0=010, Division ratio=1:4
Bit 2, 1, 0=011, Division ratio=1:8
Bit 2, 1, 0=100, Division ratio=1:16
Bit 2, 1, 0=101, Division ratio=1:32
Bit 2, 1, 0=110, Division ratio=1:64
Bit 2, 1, 0=111, Division ratio=1:128
¾
7~3
RW
Unused bit. These bits are read/write-able.
17
March 1, 2004
HT23B60
3 2 7 6 8 H z
W D T O S C
S y s te m
C lo c k /4
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
7 - b it C o u n te r
9 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Controller Operation Mode
The high nibble and bit3 of the WDTS are reserved for
user defined flags, which can be used to indicate some
specified status.
Data bank controllers support two system clocks and
four operation modes. The system clock could be
32768Hz or 3.58MHz and the operation mode could be
Normal, Green, Sleep or Idle mode. There are all selected by the software.
The WDT time-out under Normal mode or Green mode
will initialize ²chip reset² and set the status bit ²TO². But
in the Sleep mode or Idle mode, the time-out will initialize a ²warm reset² and only the program counter and
stack pointer are reset to 0. To clear the WDT contents
(including the WDT prescaler), three methods are
adopted; external reset (a low level to RES pin), software instruction and ²HALT² instruction.
The following conditions will force the operation mode to
change to Green mode:
· Any reset condition from any operation mode
· Any interrupt from Sleep mode or Idle mode
· A falling edge on any pin of Port A from Sleep mode or
Idle mode
The software instruction include ²CLR WDT² and the
other set ²CLR WDT1² and ²CLR WDT2². Of these two
types of instruction, only one can be active depending
on the mask option ²WDT instr². If the ²CLR WDT² is selected (i.e. One clear instruction), any execution of the
²CLR WDT² instruction will clear the WDT. In the case
wherein ²CLR WDT1² and ²CLR WDT2² are chosen
(i.e. two clear instructions), these two instructions must
be executed to clear the WDT; otherwise, the WDT may
reset the chip as a result of time-out.
Register
How to change the Operation Mode
· Normal mode to Green mode:
Step 1: Clear MODE1 to 0
After step 1, operation mode is changed to Green
mode but the PLLEN status has no change.
However, PLLEN can be cleared by software.
Label
Bits
R/W
Function
¾
4~0
RO
Unused bit, read as ²0²
PLLEN
5
RW
1: Enable the frequency up conversion function to generate 3.58MHz
0: Disable the frequency up conversion function to generate 3.58MHz
OPMODE
(26H)
MODE0
6
RW
0: Enable the 32768Hz oscillator while the ²HALT² instruction is executed
1: Disable the 32768Hz oscillator while the ²HALT² instruction is executed
MODE1
7
RW
1: Select 3.58MHz as CPU system clock
0: Select 32768Hz as CPU system clock
Operation Mode Description
HALT
Instruction
MODE1
MODE0
PLLEN
Operation
Mode
32768Hz
3.58MHz
System
Clock
Not Execute
1
X
1
Normal
ON
ON
3.58MHz
Not Execute
0
X
0
Green
ON
OFF
32768Hz
Executed
0
0
0
Sleep
ON
OFF
HALT
Executed
0
1
0
Idle
OFF
OFF
HALT
Note: ²X² means don¢t care
Rev. 1.10
18
March 1, 2004
HT23B60
· Normal mode or Green mode to Sleep mode:
can be independently selected to wake-up the device by
mask option. Awakening from Port A stimulus, the program will resume execution of the next instruction.
Step 1: Clear MODE0 to 0
Step 2: Execute the ²HALT² instruction
After Step 2, the operation mode is changed to Sleep
mode, the PLLEN and MODE1 are cleared to 0 by
hardware.
· Normal mode or Green mode to Idle mode:
The interrupts from the Sleep mode or Idle mode may
cause two sequences to occur in the controller. One is if
the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. The other is if the interrupt
is enabled and the stack is not full, the regular interrupt
response takes place. It is necessary to mention that if
an interrupt request flag is set to ²1² before entering the
Sleep mode or Idle mode, the wake-up function of the
related interrupt will be disabled.
Step 1: Set MODE0 to 1
Step 2: Execute the ²HALT² instruction
After Step 2, the operation mode is changed to Idle
mode, the PLLEN and MODE1 are cleared to 0 by
hardware.
· Green mode to Normal mode:
Step 1: Set PLLEN to 1
Step 2*: Software delay 2ms at least
Step 3: Set MODE1 to 1
After Step 3, operation mode is changed to Normal
mode.
Note: * Must delay 20ms at least, if you want to use
stable clock source
V
(M H z )
3 .5 8
D D
Once Idle mode wake-up event occurs, it will take 1024
system clock period or SST delay time to resume to
Green mode. In this case, a dummy period is inserted
after a wake-up. If the wake-up results from an interrupt
acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
completed.
= 3 V
0
To minimize power consumption, all the I/O pins should
be carefully managed before entering the Sleep mode
or Idle mode.
2
4
6
The Sleep mode or Idle mode is initialized by the
²HALT² instruction and results in the following.
8 1 0 1 2 1 4 1 6 1 8 2 0 (m s )
· The system clock will be turned off
· The WDT function will be disabled if the WDT clock
· Sleep mode or Idle mode to Green mode:
source is the instruction clock
Method 1: Any reset condition occurred
Method 2: Any interrupt is active
Method 3: A falling edge on any pin of Port A
After any source of the above descriptions, operation
mode is changed to Green mode.
The reset conditions include power on reset, external
reset, WDT time-out reset. By examining the processor
status flags, PDF and TO, the program can distinguish
between different ²reset conditions². Refer to the Reset
function for detailed description.
· The WDT function will be disabled if the WDT clock
A falling edge on port A and interrupt can be considered
as a continuation of normal execution. Each bit in port A
· The PDF flag is set and the TO flag is cleared by hard-
Rev. 1.10
source is the 32768Hz in Idle mode
· The WDT will still function if the WDT clock source is
the WDT OSC
· If the WDT function is still enabled, the WDT counter
and WDT prescaler will be cleared and recounted
again
· The contents of the on chip RAM and registers remain
unchanged
· All the I/O ports maintain their original status
ware.
19
March 1, 2004
HT23B60
Reset
To guarantee that the system oscillator is started and
stabilized, the System Start-up Timer or SST provides
an extra-delay of 1024 system clock pulses when the
system is reset or awakes from the Sleep or Idle operation mode.
There are three ways in which a reset can occur.
· Power on reset
· A low pulse onto RES pin
· time-out
By examining the processor status flags PD and TO, the
software program can distinguish between the different
²chip resets².
After these reset conditions, the Program Counter and
Stack Pointer will be cleared to 0.
V
D D
1 0 0 k W
R E S
0 .1 m F
Reset Circuit
H A L T
W D T
E x te rn a l
W a rm
W D T tim e - o u t
PD
Reset Condition
0
0
Power on reset
u
u
External reset during Normal mode or
Green mode
0
1
External reset during Sleep mode or
Idle mode
1
u
WDT time-out during Normal mode or
Green mode
1
1
WDT time-out during Sleep mode or
Idle mode
Note: ²u² stands for ²unchanged²
The functional unit chip reset status are shown below:
C o ld R e s e t
R E S
S Y S C L K
R e s e t
TO
S S T
1 0 - b it R ip p le
C o u n te r
Program Counter
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared
After a master reset,
WDT begins counting
(if the WDT function is enabled by mask option)
Timer Counter 2
Off
Input/output Port
Input mode
Stack Pointer
Points to the top of the stack
LCD Display
Disable
Reset Configuration
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
Rev. 1.10
20
March 1, 2004
HT23B60
When the reset conditions occurred, some registers may be changed or unchanged.
Reset Conditions
Register
Addr.
Power On
RES Pin
(Sleep/Idle)
RES Pin
WDT
WDT
(Sleep/Idle)
IAR0
00H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP0
01H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
IAR1
02H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
03H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
04H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
05H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
06H
0000H
0000H
0000H
0000H
0000H
TBLP
07H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
08H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
09H
0000 0111
0000 0111
0000 0111
0000 0111
STATUS
0AH
--00 xxxx
--uu uuuu
--01 uuuu
--1u uuuu
--11 uuuu
INTC0
0BH
0000 0000
0000 0000
0000 0000
0000 0000
0uuu uuuu
TMR0H
0CH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
0DH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
0EH
0000 1000
0000 1000
0000 1000
0000 1000
uu0u u000
PA
12H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
13H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
14H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
15H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
INTC1
1EH
0000 -000
0000 -000
0000 -000
-000 -000
0uuu 0uuu
TBHP
1FH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RTC
24H
0000 0000
u0u0 0000
u0u0 0000
u0u0 0000
u0u0 0000
OPMODE
26H
0100 0000
01u0 0000
01u0 0000
01u0 0000
01u0 0000
TMR2H
2AH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2L
2BH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR2C
2CH
0000 1000
0000 1000
0000 1000
0000 1000
uu0u u000
LCDC
2DH
0000 0000
0000 0000
0000 0000
0000 0000
u00u 0u00
PFDC
2FH
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uu00
PWMC
30H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PWM
31H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
SRC
32H
0001 0000
0001 0000
0001 0000
0001 0000
uuuu uuuu
SRD
33H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
VLCD
34H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu 0000
PAPHC
35H
1111 1111
1111 1111
1111 1111
1111 1111
00uu uuuu
PBPHC
36H
0011 1111
0011 1111
0011 1111
0011 1111
uuuu uuuu
LCDPC
37H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
LCDPCC
38H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
LCDPD
39H
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
LCDPDC
3AH
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
x
u
u
u
u
RAM (Data & LCD)
Note:
²u² stands for ²unchanged²
²x² stands for ²unknown²
²-² stands for ²unused²
Rev. 1.10
21
March 1, 2004
HT23B60
Timer 0
If the timer counter starts counting, it will count from the
current contents in the timer counter to FFFFH. Once an
overflow occurs, the counter is reloaded from the timer
counter preload register and at the same time generates
the corresponding interrupt request flag (T0F; bit of the
INTC0).
D a ta B u s
T im e r C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
To enable the counting operation, the Timer ON bit
(TON; bit 4 of the TMR0C) should be set to 1. The overflow of the timer counter is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I can disable the corresponding interrupt service.
O v e r flo w
to In te rru p t
T im e r C o u n te r 0
S Y S C L K /4
L o w B y te B u ffe r
In the case of timer counter OFF condition, writing data
to the timer counter preload register will also reload that
data to the timer counter. But if the timer counter is
turned on, data written to the timer counter will only be
kept in the timer counter preload register. The timer
counter will still operate until overflow occurs.
The timer 0 contains 16-bit programmable count-up
counters and the clock source come from the system
clock divided by 4.
There are three registers related to the timer counter 0;
TMR0H (0CH), TMR0L (0DH), TMR0C(0EH). Writing
TMR0L only writes the data into a low byte buffer, and
writing TMR0H will simultaneously write the data and
the contents of the low byte buffer into the timer 0
preload register (16-bit). The Timer 0 preload register is
changed by writing TMR0H operations and writing
TMR0L will keep the Timer 0 preload register unchanged.
When the timer counter (reading TMR0H) is read, the
clock will be blocked to avoid errors. As this may result
in a counting error, this must be taken into consideration
by the programmer.
Timer 2
The Timer 2 contains 16-bit programmable count-up
counters whose clock may come from the 32768 Hz oscillator or the clock source come from the system clock
divided by 4.
Reading TMR0H will also latch the TMR0L into the low
byte buffer to avoid any false timing problem. Reading
TMR0L returns the contents of the low byte buffer. In this
case, the low byte of the timer counter 0 cannot be read
directly. It must read the TMR0H first to make the low
byte contents of the Timer 0 be latched into the buffer.
There are three registers related to the timer counter 2;
TMR2H (2AH), TMR2L (2BH), TMR2C(2CH). Writing
TMR2L only writes the data into a low byte buffer, and
writing TMR2H will simultaneously write the data and
the contents of the low byte buffer into the timer 2
preload register (16-bit). The timer 2 preload register is
changed by writing TMR2H operations and writing
The TMR0C is the Timer 0 control register, which defines the Timer 0 options. The timer counter control registers define the operating mode, counting enable or
disable and active edge.
Register
TMR0C
(0EH)
Register
TMR2C
(2AH)
Rev. 1.10
Label
Bits
R/W
¾
0~2
RO
Unused bit, read as ²0²
¾
3
¾
Unused bit, read as ²0²
TON
4
RW
¾
5
¾
TM0
TM1
6
7
RW
Label
Bits
R/W
¾
0~3
¾
TON
4
RW
¾
5
¾
TM0
TM1
6
7
RW
Function
Enable/disable the timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
Fixed bit 7, 6=10, internal timer mode
Function
Unused bit, read as ²0²
Enable/disable the timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
Fixed bit 7, 6=10, internal timer mode
22
March 1, 2004
HT23B60
of the timer counter is one of the wake-up sources. No
matter what the operation mode is, writing a 0 to ET0I
can disable the corresponding interrupt service.
TMR2L will keep the timer 2 preload register unchanged.
Reading TMR2H will also latch the TMR2L into the low
byte buffer to avoid any false timing problem. Reading
TMR2L returns the contents of the low byte buffer. In
other words, the low byte of the timer counter 2 cannot
be read directly. It must read the TMR2H first to make
the low byte contents of Timer 2 be latched into the
buffer.
In the case of timer counter OFF condition, writing data
to the timer counter preload register will also reload that
data to the timer counter. But if the timer counter is
turned on, data written to the timer counter will only be
kept in the timer counter preload register. The timer
counter will still operate until overflow occurs.
The TMR2C is the Timer 2 control register, which defines the Timer 2 options. The timer counter control registers define the operating mode, counting enable or
disable and active edge.
When the timer counter (reading TMR1H) is read, the
clock will be blocked to avoid errors. As this may result
in a counting error, this must be taken into consideration
by the programmer.
If the timer counter starts counting, it will count from the
current contents in the timer counter to FFFFH. Once an
overflow occurs, the counter is reloaded from the timer
counter preload register and generates the corresponding interrupt request flag (T2F; bit of INTC0) at the same
time.
The Timer 2 can also be used as PFD output by setting
PWM1 and PWM2 to be PFD and PFDB output respectively by 2FH.7 and 2FH.6. When the PFD/PFDB function is selected, setting 2FH.4/2FH.5 to ²1² will enable
the PFD/PFDB output and setting 2FH.4/2FH.5 to ²0²
will disable the PFD/PFDB output.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR2C) should be set to 1. The overflow
PFDC
Register
Label
Bits
R/W
¾
2~0
R
TIM2
3
RW
1: The timer 2 frequency source is 3.58MHz/4
0: The timer 2 frequency source is 32768Hz
PFDB
4
RW
1: Enable PFDB
0: Disable PFDB
PFD
5
RW
1: Enable PFD
0: Disable PFD
PFDB/PWM1
6
RW
1: Enable PFDB
0: Enable PWM1
PFD/PWM2
7
RW
1: Enable PFD
0: Enable PWM2
PFDC
(2FH)
Function
Unused bit, read as ²0²
D a ta B u s
T im e r 2
P r e lo a d R e g is te r
R e lo a d
T o In te rru p t
3 .5 8 M H z /4
3 2 7 6 8 H z
M U X
P F D C .3
T im e r C o u n te r 2
O v e r flo w
L o w B y te B u ffe r
¸ 2
2 F H .5
P W M 2 d a c
2 F H .7
2 F H .4
P W M 1 d a c
Rev. 1.10
P W M 2
23
P W M 1
2 F H .6
March 1, 2004
HT23B60
RTC & WDT & LCD Clock
· RTC function
Register
RTC
(24H)
Label
Bits
R/W
¾
6,4
~0
Function
RO
Unused bit, read as ²0²
RTCEN
5
RW
Enable/disable the RTC counting (0: disable; 1: enable)
RTCSET
7
RW
RTC time-out flag (1: active; 0: inactive)
dynamically under software control. To function as an
input, the corresponding latch of the control register
must be written a ²1². The pull-high resistance will exhibit automatically if the pull-high option is selected. The
input source also depends on the control register. If the
control register bit is ²1², the input will read the pad
state. If the control register bit is ²0², the contents of the
latches will move to the internal bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration. These control
registers are mapped to locations 13H, 15H. After a chip
reset, these input/output lines remain at high levels or
floating (mask option). Each bit of these input/output
latches can be set or cleared by the ²SET [m].i² or ²CLR
[m].i² (m=12H, 14H) instruction. Some instructions first
input data and then follow the output operations. For example, the ²SET [m].i², ²CLR [m].i², ²CPL [m]² and
²CPLA [m]² instructions read the entire port states into
t h e C P U , e xe cu t e t h e d e f i n e d o p e r a t i o n s
(bit-operation), and then write the results back to the
latches or the accumulator. Each line of port A has the
capability to wake-up the device. Port B are share pad,
each pin function are defined by mask option, when the
PB3 be used as a normal I/O port, INT function must be
disable. (Set [0BH].4 to ²0²). The PB2, PB1 and PB0
share with serial data input, serial data output and serial
clock. If the serial function is selected, the related I/O
register (PB) cannot be used as general purpose register. Reading the register will result to an unknown state.
The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period is 2Hz. If the RTC
time-out occurs, the interrupt request flag RTCF and the
RTCSET flag will be set to 1. The interrupt vector for the
RTC is 14H. When the interrupt subroutine is serviced,
the interrupt request flag (RTCF) will be cleared to 0, but
the flag RTCSET maintain its original value. If RTC is
time-out, the flag RTCSET and RTCF will be set to 1.
The flag RTCSET can be cleared to 0 by software.
3 2 k H z X 'T A L
F 1
1 /1 6 3 8 4
1 /1 6
IN T
T O N
L C D D r iv e r
(2 0 4 8 H z )
Input/Output Ports
There are 14 bidirectional input/output lines in the
HT23B60, labeled PA and PB, which are mapped to the
data memory of [12H], [14H], respectively. All these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
MOV A,[m] (m=12H, 14H). For output operation, all data
is latched and remains unchanged until the output latch
is rewritten. Each I/O line has its own control register
(PAC, PBC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor (software option 35H, 36H) structures can be reconfigured
D a ta B u s
V
D
W r ite C o n tr o l R e g is te r
Q
C K
Q
S
V
D D
D D
W e a k
P u ll- u p
C h ip R e s e t
R e a d C o n tr o l R e g is te r
P u ll- H i C o n tr o l R e g is te r
D
W r ite I/O
P A 0 ~ P A 7
P B 0 ~ P B 5
Q
C K
S
Q
M
R e a d I/O
S y s te m
Rev. 1.10
W a k e - U p ( P A o n ly )
U
X
M a s k O p tio n
24
March 1, 2004
HT23B60
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
PA Pull-High Resistor
Bit7~Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
1: pull-high
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
0: No pull
Unused bit
PB Pull-High Resistor
PWM Interface
On the sampling rate table, we can easily see that the
sampling rate is dependent on the system clock. If start
bit of the 30H.0 is set as ²1², the PWM2 and PWM1 will
output a GND level voltage.
The HT23B60 provides an 8 bit (bit 7 is a sign bit) PWM
D/A interface, which is good for speech synthesis. The
user can record or synthesize the sound and digitize it
into the program ROM. This sound could be played back
in sequence of the functions as designed by the internal
program ROM. There are several algorithms that can be
used in the HT23B60, namely, PCM, m_LAW, DPCM,
ADPCM...etc.
Label Bits
The PWM circuit consists of seven counters. When initialized, QB goes high and when an overflow occurs, QB
goes low. When the PWM controller bits 0 of the 30H are
set as ²0², each of the 128 clock will initialize the counter
and load the value that come from PWM data buffer to
counter. The PWM modulation can be controlled by using a different value of the PWM data buffer. A single bit
can control the signal changes from the PWM1 or
PWM2 output. The PWM clock source comes from the
system clock divided by a 3-bit prescaler. Setting data to
P0, P1 and P2 (bit3, 4, 5 of 30H) can yield various clock
sources. Setting PWM controller bits D0, D1 (bit6, 7 of
30H) can control the interrupt as to how many times the
counter overflows.
Function
PWM
Dis/En
0
Enable/disable PWM output
0: enable; 1: disable
BZ/SP
1
Output driver select
1: buzzer; 0: speaker
6/7 Bits
2
PWM counter bit select
1: 7 bits; 0: 6 bits
P0~P2 3~5
3 bits preload counter
Bit5~3: 000B~111B (0~7); Bit3: LSB
D0, D1 6, 7 PWMI
D1
D0
PWM Interrupt
0
0
1
0
1
2
1
0
4
1
1
8
BZ/SP
6/7
Bit
F1
F2
(Sampling Rate)
Device
0
0
F0
F0/64
32 speakers
7-bit
D7
D6
D5
D4
D3
D2
D1
D0
0
1
F0
F0/128
32 speakers
6-bit
D7
D6
D5
D4
D3
D2
D1
X
Note:
1
0
F0
F0/64
Buzzer/
8 speakers
1
1
F0
F0/128
Buzzer/
8 speakers
Note:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
²X² stands for don¢t care
Bit7: Sign bit
F1: for PWM modulation clock and F2 for sampling clock
F0: system/[n+1], n=0~7 (n: 3 bits preload
counter)
²X² stands for don¢t care
Rev. 1.10
25
March 1, 2004
HT23B60
F 0
S ta r t B it
1 2 8 C lo c k
L a tc h
F 1
F 2
O n e S a m p lin g T im e
PWM
D a ta B u s
S y s te m
C lo c k
F 0
S ta r t B it
3 0 H .0
P W M I
P W M D a ta
B u ffe r (3 1 H )
P r e s c a le r
D iv .
F 1
C K
D D
D
7 B its C o u n te r
O v e r flo w
P E
F 2
V
Q
C K
Q
R
P W M D A C 1 fo r 3 2 W
S P K
P W M D A C 2 fo r 3 2 W
S P K
30H.1=0 Speaker
D a ta B u s
S y s te m
C lo c k
F 0
S ta r t B it
P W M I
P W M D a ta
B u ffe r (3 1 H )
P r e s c a le r
D iv .
F 2
F 1
C K
7 B its C o u n te r
O v e r flo w
P E
V
D D
D
Q
C K
Q
R
S ig n b it
P W M D A C 1 fo r B Z
P W M D A C 2 fo r B Z
30H.1=1 Buzzer
Rev. 1.10
26
March 1, 2004
HT23B60
Serial Interface Protocol (SPI)
3 wire SPI format, support 32KBytes/64KBytes /128K.Bytes/256KBytes
Rising edge latch data, falling edge output data
Serial RAM Control Register
Register
SRC
(32H)
Label
Bits
Function
¾
0
Unused bit, read as ²0²
Busy
1
0: The data register is full (readable) or empty (writeable) (Default=0)
1: Serial RAM interface is busy, cannot write/read the data register
¾
2
Unused bit, read as ²0²
Sread
3
1: Series read; 0: step read
W/R
4
W/R=0: read mode; To read data from the external serial RAM
W/R=1: write mode; To write data to the external serial RAM
SMODE
5
SPI mode setting
0: Mode 0; 1: Mode 3
Sclk0
6
Serial RAM interface clock, Default=0
Sclk1
7
Serial RAM interface clock, Default=0
Sclk1
Sclk0
Serial RAM interface clock selector
0
0
Serial RAM interface clock=system clock/2
0
1
Serial RAM interface clock=system clock/4
1
1
Serial RAM interface clock=system clock/8
1
1
Serial RAM interface clock=system clock/16
· Data are read from or written to the Data Register which is transmitted through the Serial RAM interface
· After the next 8-bit data are written to, it is transmitted to the 8 Serial RAM interface clock
· Within the 8 serial RAM interface clock, while transmission occurs the busy flag goes 1, after which, when the trans-
mission is completed, the busy flag goes 0
Serial RAM Data Register
Address Register
33H
SRD
7
6
5
4
3
2
1
0
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
R/W
00000000 (1sb)
SPI Interface Information
· SPI interface connection
S I
D O
S O
D I
C o n tr o lle r
(M a s te r)
S C K
S C K
P X n
C S
M e m o ry
(S la v e )
S I
S O
P X m
S C K
M e m o ry
(S la v e )
C S
Note:
Controller (master): DO/DI/SCK is SPI interface pin, PXn~PXm are generic I/O port.
Memory (slave): SI/SO/SCK is SPI interface pin, CS is chip select.
Rev. 1.10
27
March 1, 2004
HT23B60
· SPI register description
The SPI is used two register, one is data register, the other one is control register. And for the data register is used for
data transfer/receiver register, the control register is used to control and display the status of the SPI.
Control
Register
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCK
Setting
SCK
Setting
SPI Mode
Setting
Read/writ
e Mode
Setting
SPI Series
Read
Reserved
SPI busy
Reserved
B5=1
®Mode3
B5=0
®Mode0
B4=1
®Write
B4=0
®Read
B7,B6=0,0®SCK=fSYS/2
B7,B6=0,1®SCK=fSYS/4
B7,B6=1,0®SCK=fSYS/8
B7,B6=1,1®SCK=fSYS/1
6
B1=1
®Busy,
data serial Out.
RO=²0²
B1=0
®Ready,
can access data.
B3=1
®Series read
RO=²0²
B3=0
®Step read
Note: The SPI mode0 & mode3 is changed by software option.
· Write data into memory (write mode) timing chart (Mode 0)
tC
C S
S S
0
S C K
tS
D I
1
2
3
tH
U
4
5
6
0
7
1
2
3
4
5
6
7
O
H i- Z
D O
B 7
Symbol
B 6
B 5
B 4
B 3
B 2
B 1
Parameter
B 0
B 7
Min.
B 6
B 5
Typ.
B 4
B 3
B 2
B 1
B 0
Max.
Unit
¾
ns
tCSS
CS Setup Time
0
tSU
Data in Setup Time
¾
1
2 SCK
¾
¾
tHO
Data in HOLD Time
¾
1
2 SCK
¾
¾
· The following will show how to write data to memory by the way of the flowchart
S e
C o
R e
(x x x
S ta rt
ttin g
n tro l
g is te r
1 x x x x )
S e ttin g
P X n
( C h ip S e le c t)
S e ttin g
D a ta
R e g is te r
( In s tr u c tio n )
S e ttin g
D a ta
R e g is te r
(A d d re s s )
C h e c k
B u s y ?
Note:
S e
D
R e
(D
C h e c k
B u s y ?
ttin g
a ta
g is te r
a ta )
R e s e ttin g
P X n
( C h ip S e le c t)
E n d
C h e c k
B u s y ?
After to write the data register, the serial out is executed automatically, and the busy bit of the SPI will be set to
²1², when the serial out is completed, the busy bit of the SPI will be set to ²0², and can be readable/writeable in
this moment.
Rev. 1.10
28
March 1, 2004
HT23B60
· Read data from memory (read mode) timing chart (Mode 0)
tC
C S
S S
0
S C K
tS
D I
1
2
3
tH
U
4
5
6
H i- Z
1
B 7
D O
B 7
Symbol
tCSS
0
7
B 6
B 5
B 4
2
3
4
5
6
7
O
B 3
B 2
B 1
Parameter
B 5
B 4
B 3
B 2
B 1
B 0
B 0
Min.
CS Setup Time
B 6
Typ.
Max.
Unit
0
tSU
Data in Setup Time
¾
1
2 SCK
tHO
Data in HOLD Time
¾
1
2 SCK
¾
ns
¾
¾
¾
¾
· The following will show how to read data from memory by the way of the flowchart
S ta rt
S e
C o
R e
(x x x
ttin g
n tro l
g is te r
1 x x x x )
S e ttin g
P X n
( C h ip S e le c t)
S e ttin g
D a ta
R e g is te r
( In s tr u c tio n )
S e ttin g
D a ta
R e g is te r
(A d d re s s )
C h e c k
B u s y ?
S e
C o
R e
(x x x
ttin g
n tro l
g is te r
0 x x x x )
C h e c k
B u s y ?
S e
S C
R e
D
n d in g
K to
c e iv e
a ta
R e s e ttin g
P X n
( C h ip S e le c t)
E n d
C h e c k
B u s y ?
Low Voltage Detected
The Controller provides a circuit that detects the VLCD pin voltage level. To enable this detection function, the LVEN
should be written as 1. Once this function is enabled, the detection circuit needs 100ms to be stable. After that, user
could read the result from the LVFG. The low voltage detect function will consume power. For power saving, write 0 to
LVEN if the low voltage detection function is unnecessary.
The tolerance value for the 3 Conditions (Min, Typ. Max) are within 5%.
Rev. 1.10
29
March 1, 2004
HT23B60
Keyscan
LCD out port structure
D a ta B u s
Q
D
C K
S e g _ o C o n tr o l R e g is te r
Q
S
C h ip R e s e t
L C D S E G 0 ~ 1 5
D a ta B u s
0
Q
D
W r ite I/O
M
1
U
S E G 0 ~ S E G 1 5
X
Q
C K
S
C h ip R e s e t
4 6 .5 4 H z
1
3
2
4
6
5
8
7
9
1 0
1 1
1
2
3
4
1 1
1 0 2 4 H z
C O M 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
S E G 0
V D D
3 /4 V D D
2 /4 V D D
1 /4 V D D
G N D
In t F re q u e n c e 9 3 H z
< 2 5 0 m s
In t,
C le a
T u rn
T u rn
In p u
T u rn
T u rn
T u rn
T u rn
In p u
T u rn
T u rn
r L C
o n
o n
t P A
o ff
o ff
o n
o n
t P A
o ff
o ff
< 2 5 0 m s
D o u tp u t P C & P D
P A P u ll- H i R e s is te r
L C D o u tp u t P C
L C
P A
P A
L C
D
o u tp
P u ll- H
P u ll- H
D o u tp
u t
i R
i R
u t
P C
e s is te r
e s is te r
P D
L C D o u tp u t P D
P A P u ll- H i R e s is te r
R e tu rn In t.
For every Frame, each have a Common signal, all of which can generate a single interrupt. The Scan Key performs the
following:
· The keyscan loop with 32kHz system frequency
· The keyscan loop executes every 2 keyscan Int,.
· After an Interrupt occurs, clear LCD segment output port
· Turn on the PA Port¢s Pull-hi resistance
· Turn on the LCD segment output port.
· Use the LCD segment Output port and input port PA to implement the Key Scan
· Take the Scan value and store into the Memory
· Turn off the LCD segment output port transition to LCD segment output.
· Turn off the PA pull-hi
· Return to the main routine and change system frequency
· The keyscan function have to be completed in the period of interrupt time.
· The keyscan function is generated by common signal. When the LCD function is enable, the keyscan function can be
used.
Rev. 1.10
30
March 1, 2004
HT23B60
Example:
;*keyscan loop executes every 2 keyscan Int.
clr
clr
set
clr
mov
set
clr
cpla
sz
jmp
lcdpc
lcdpd
paphc
lcdpcc
a,pa
lcdpcc
paphc
acc
acc
speed_up
;clear LCD output (seg0~seg7)
;clear LCD output (seg8~seg15)
;enable PA Pull-hi
;seg0~seg7 output port
;write PA to ACC
;turn on seg0~seg7
;disable PA Pull-hi
;complement ACC
;check if stroke down
;then change from Normal mode to Green mode
set
clr
mov
set
clr
cpla
sz
jmp
reti
paphc
lcdpdc
a,pa
lcdpdc
paphc
acc
acc
speed_up
;enable PA Pull-hi
;seg8~seg15 output port
;write PA to ACC
;turn on seg8~seg15
;disable PA Pull-hi
;complement ACC
;check if stroke down
;then change from Normal mode to Green mode
LCD output control (38H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1: seg7
1: seg6
1: seg5
1: seg4
1: seg3
1: seg2
1: seg1
1: seg0
0: output
0: output
0: output
0: output
0: output
0: output
0: output
0: output
LCD output (37H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (Seg0)
D7
D6
D5
D4
D3
D2
D1
D0
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LCD output control (3AH)
Bit7
Bit6
1: seg15
1: seg14
1: seg13
1: seg12
1: seg11
1: seg10
1: seg9
1: seg8
0: output
0: output
0: output
0: output
0: output
0: output
0: output
0: output
LCD output (39H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 (Seg8)
D7
D2
D5
D4
D3
D2
D1
D7
Rev. 1.10
31
March 1, 2004
HT23B60
Mask Option
The following table shows many kinds of mask option in the Databank Controller. All these options should be defined in
order to ensure prober system functions
Name
Mask Option
WDT
WDT source selection
RC®Select the WDT OSC to be the WDT source
T1®Select the instruction clock to be the WDT source
32kHz®Select the external 32768Hz to be the WDT source
Disable®Disable the WDT function
WDTinstr
This option defines how to clear the WDT by instruction
One clear instruction®The ²CLR WDT² can clear the WDT
Two clear instructions®Only when both of the ²CLR WDT1² and ²CLR WDT2² have
been executed, then the WDT can be cleared
HALT option
HALT function selection
Defines the HALT function either disabled or enabled
Wake-up PA
Port A wake-up selection.
Defines the wake-up function activity
All port A have the capability to wake-up the chip from HALT
This wake-up function is selected per bit
This option describes the LCD bias current. There are three types of selection
*_Selectable as small, middle or large current
LCD bias register selection Small current: 660K
Middle current: 330K
Large current: 66K
PB0~2 share pad option
Defines the pad ²PB0~PB2² whether normal I/O pad or serial RAM interface pad
LCD duty option
Defines the LCD duty whether 1/10 or 1/11 duty
LCD bias option
Defines the LCD bias whether 1/4 or 1/5 bias
PB3 share pad option
Defines the pad ²PB3² whether INT interrupt input pad or normal I/O pad
Rev. 1.10
32
March 1, 2004
HT23B60
Application Circuits
1 5 k W
5 0 n F
V
3 2 7 6 8 H z
3 n F
X C
X IN
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
D D
R 1
X O U T
V L C D
V D D
R 2
L B IN
S E G 0
S E G 5 9
L C D D is p la y
C O M 0
H T 2 3 B 6 0
C O M 1 0
P B 5
P B 4
6 0 S e g m e n t
´
1 1 C o m m o n
P W M 1
P B 3
D I/
P B 2
D O / S C L K /
P B 1 P B 0
P W M 2
S R A M
P A 0
S e g 0
S e g 1
S e g 2
S e g 1 3 S e g 1 4 S e g 1 5
P A 1
P A 2
P A 3
P A 4
P A 5
Rev. 1.10
33
March 1, 2004
HT23B60
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.10
34
March 1, 2004
HT23B60
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.10
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
35
March 1, 2004
HT23B60
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
36
March 1, 2004
HT23B60
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
March 1, 2004
HT23B60
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
38
March 1, 2004
HT23B60
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
39
March 1, 2004
HT23B60
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
March 1, 2004
HT23B60
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
March 1, 2004
HT23B60
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
42
March 1, 2004
HT23B60
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
43
March 1, 2004
HT23B60
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
44
March 1, 2004
HT23B60
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
45
March 1, 2004
HT23B60
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
46
March 1, 2004
HT23B60
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
47
March 1, 2004
HT23B60
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.10
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
48
March 1, 2004
HT23B60
Package Information
100-pin QFP (14´20) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
K
a
J
1
Symbol
A
Rev. 1.10
3 0
Dimensions in mm
Min.
Nom.
Max.
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.10
¾
J
1
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
49
March 1, 2004
HT23B60
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
50
March 1, 2004