HT23C128 CMOS 16K×8-Bit Mask ROM Features • • • • • Operating voltage: 2.7V~5.5V Low power consumption – Operation: 25mA Max. (V CC=5V) 10mA Max. (VCC=3V) – Standby: 30µA Max. (VCC=5V) 10µA Max. (VCC=3V) Access time:150ns Max. (VCC=5V) 250ns Max. (VCC=3V) • • • • 16384×8 bits of mask ROM Mask options: chip enable CE/CE/OE2/OE2 and output enable OE/OE/NC & OE1/ OE1/NC TTL compatible inputs and outputs Tristate outputs Fully static operation Package type: 28-pin DIP/SOP General Description essors, but also eliminates bus contention in multiple bus microprocessor systems. An additional feature of the HT23C128 is its ability to enter the standby mode whenever the chip enable (CE/CE) is inactive, thus reducing current consumption to below 30µA. The combination of these functions makes the chip suitable for high density low power memory applications. The HT23C128 is a read-only memory with high performance CMOS storage device whose 128K of memory is arranged into 16384 words by 8 bits. For application flexibility, the chip enable and output enable control pins can be selected as active high or active low. This flexibility not only allows easy interface with most microproc- Block Diagram 1 24th Aug ’98 HT23C128 Pin Assignment Pin Description Pin Name I/O NC Description — No connection A0~A13 I Address inputs D0~D7 O Data outputs VSS I Negative power supply CE/CE/OE2/OE2 I Chip enable/Output enable input OE/OE/NC I Output enable input OE1/OE1/NC I Output enable input VCC I Positive power supply Operation Truth Table Mode CE/CE OE/OE OE1/OE1 A0~A13 D0~D7 Read H/L H/L H/L Valid Data Out Deselect H/L L/H X X High Z Deselect H/L X L/H X High Z Standby L/H X X X High Z Note: H=VIH, L=VIL, X=VIH or VIL 2 24th Aug ’98 HT23C128 Absolute Maximum Ratings* Supply Voltage ................................. –0.3V to 6V Storage Temperature................. –50°C to 125°C Input Voltage........................ –0.3V to VCC+0.3V Operating Temperature............... –40°C to 85°C *Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=–40°C to 85°C Supply voltage: 2.7V~3.6V Symbol Parameter Test Conditions Min. Typ. 2.7 — 3.6 V — — 10 mA — VSS — 0.4 V — VCC Conditions — VCC Operating Voltage — ICC Operating Current 3V VIL Input Low Voltage 3V O/P Unload, f=5MHz Max. Unit VIH Input High Voltage 3V 2.0 — VCC V VOL Output Low Voltage 3V IOL=2.1mA — — 0.4 V VOH Output High Voltage 3V IOH=–0.4mA 2.4 — VCC V ILI Input Leakage Current 3V VIN=0 to VCC — — 10 µA ILO Output Leakage Current 3V VOUT=0 to VCC — — 10 µA ISTB1 Standby Current 3V CE=VIL CE=VIH — — 500 µA ISTB2 Standby Current 3V CE≤0.2V CE≥VCC-0.2V — — 10 µA CIN Input Capacitance (See note) — f=1MHz — — 10 pF COUT Output Capacitance (See note) — f=1MHz — — 10 pF Note: These parameters are periodically sampled but not 100% tested. Ta=–40°C to 85°C Supply voltage: 4.5V~5.5V Symbol Parameter Test Conditions VCC Conditions — Min. Typ. Max. Unit 4.5 — 5.5 V — — 25 mA VCC Operating Voltage — ICC Operating Current 5V VIL Input Low Voltage 5V — VSS — 0.8 V VIH Input High Voltage 5V — 2.2 — VCC V O/P Unload, f=5MHz 3 24th Aug ’98 HT23C128 Symbol Parameter Test Conditions VCC Min. Conditions Typ. Max. Unit VOL Output Low Voltage 5V IOL=3.2mA — — 0.4 V VOH Output High Voltage 5V IOH=–1mA 2.4 — VCC V ILI Input Leakage Current 5V VIN=0 to VCC — — 10 µA ILO Output Leakage Current 5V VOUT=0 to VCC — — 10 µA ISTB1 Standby Current 5V CE=VIL CE=VIH — — 1.5 mA ISTB2 Standby Current 5V CE≤0.2V CE≥VCC-0.2V — — 30 µA CIN Input Capacitance (See note) — f=1MHz — — 10 pF COUT Output Capacitance (See note) — f=1MHz — — 10 pF Note: These parameters are periodically sampled but not 100% tested. Ta=–40°C to 85°C A.C. Characteristics Symbol VCC=2.7V~3.6V Parameter VCC=4.5V~5.5V Unit Min. Max. Min. Max. 250 — 150 — ns tCYC Cycle Time tAA Address Access Time — 250 — 150 ns tACE Chip Enable Access Time — 250 — 150 ns tAOE Output Enable Access Time — 150 — 80 ns tOH Output Hold Time — — 10 — ns tOD Output Disable Time (See Note) — — — 70 ns tOE Output Enable Time (See Note) — — 10 — ns Note: These parameters are periodically sampled but not 100% tested. A.C. test conditions Output load: see figure right Input rise and fall time: 10ns Input pulse levels: 0.4V to 2.4V Input and output timing reference levels: 0.8V and 2.0V (VCC=5V) 1.5V (VCC=3V) Output load circuit 4 24th Aug ’98 HT23C128 Functional Description • Data read mode The HT23C128 has two modes, namely data read mode and standby mode, controlled by CE/CE/OE2/OE2, OE/OE/NC and OE1/OE1/NC inputs. When both the chip enable (CE/CE/OE2/OE2) and the output enable (OE/OE/NC and OE1/OE1/NC) are active, the chip is in data read mode. Otherwise, active CE/CE and inactive OE/OE/NC or OE1/OE1/NC result in deselect mode. The output will remain in Hi-Z state. • Standby mode The HT23C128 has lower current consumption, controlled by the chip enable input (CE/CE). When a low/high level is applied to the CE/CEB input regardless of the output enable (OE/OE/NC and OE1/OE1/NC) states, the chip will enter the standby mode. Timing Diagrams • Propagation delay due to address (CE/CE/OE2/OE2, OE/OE and OE1/OE1 are active) • Propagation delay due to chip enable and output enable (address valid) 5 24th Aug ’98 HT23C128 Characteristic Curves 6 24th Aug ’98 HT23C128 7 24th Aug ’98 HT23C128 HT23C128 MASK ROM ORDERING SHEET Custom: Input Medium: EPROM DISK File (Mail Address: [email protected]) User No. Type/Ref. Name Q’ty Check Sum OTHER Memory Address Start End Control Pin and Package Form Option: (1) CE (2) CE (3) OE2 (4) OE2 (a) 28 Pin Type Pin 20: (1) OE (2) OE (3) NC Pin 22: (1) OE1 (2) OE1 (3) NC Pin 27: (1) Chip Form (2) 28 DIP (3) 28 SOP (b) Package Form: Companion User No. Package Marking Delivery Date : : Q’ty: CUSTOM CONFIRMED BY: (NAME, DATE, POSITION & CO. CHOP) HOLTEK CONFIRMED BY: (SALES) (SALES MANAGER) 8 24th Aug ’98