HOLTEK HT46R62

HT46R62/HT46C62
A/D with LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0047E An PWM application example using the HT46 series of MCUs
Features
· Operating voltage:
· Watchdog Timer
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· 20 bidirectional I/O lines
· HALT function and wake-up feature reduce power
(PA, PB0~PB5, PD0~PD2, PD4~PD6)
consumption
· Two external interrupt input
· 6-level subroutine nesting
· One 8-bit programmable timer/event counter with
· 6 channels 9-bit resolution A/D converter
PFD (programmable frequency divider) function
· 3-channel 8-bit PWM output shared with 3 I/O lines
· LCD driver with 20´3 or 19´4 segments
· Bit manipulation instruction
(logical output option for SEG0~SEG15)
· 16-bit table read instruction
· 2K´14 program memory
· Up to 0.5ms instruction cycle with 8MHz system clock
· 88´8 data memory RAM
· 63 powerful instructions
· Supports PFD for sound generation
· All instructions in 1 or 2 machine cycles
· Real Time Clock (RTC)
· Low voltage reset/detector function
· 8-bit prescaler for RTC
· 52-pin QFP, 56-pin SSOP packages
General Description
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications requiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
The HT46R62/HT46C62 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface directly to analog signals and which require LCD Interface. The mask version HT46C62 is fully pin and
functionally compatible with the OTP version HT46R62
device.
The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D
Rev. 1.60
1
July 14, 2005
HT46R62/HT46C62
Block Diagram
In te rru p t
C ir c u it
P ro g ra m
E P R O M
S T A C K
P ro g ra m
C o u n te r
M
T M R C
T M R
IN T C
P F D
In s tr u c tio n
R e g is te r
M
M P
U
X
D A T A
M e m o ry
P W
S T A T U S
A L U
S
U
Y S
/4
R T C
X
O S C 3
O S C
O S C 4
W D T O S C
P o rt D
P D
P D
P D
P D
P D
0 /P
4 /IN
5 /IN
6 /T
W M 0 ~ P D 2 /P W M 2
T 0
T 1
M R 0
6 -C h a n n e l
A /D C o n v e rte r
D
S
P B C
A C C
C 1
P o rt B
P B
L C D
M e m o ry
C 3
P A C
P o rt A
P A
L C D D R IV E R
H A L T
C O M 0 ~
C O M 2
Rev. 1.60
Y S
P D 6 /T M R
M
S h ifte r
B P
O S
R E
V D
V S
O S
fS
M
P D C
O S C 2
O S C 4
X
fS
W D T
M U X
T im in g
G e n e r a tio n
P r e s c a le r
R T C
T im e B a s e
In s tr u c tio n
D e c o d e r
U
C O M 3 /
S E G 1 9
E N /D IS
P B 0 /A N 0 ~ P B 5 /A N 5
P A 0
P A 1
P A 2
P A 3
P A 4
/B Z
/B Z
/P F D
~ P A 7
L V D /L V R
S E G 0 ~
S E G 1 8
2
July 14, 2005
HT46R62/HT46C62
Pin Assignment
1
5 6
R E S
P A 1 /B Z
2
5 5
O S C 1
P A 2
3
5 4
O S C 2
P A 3 /P F D
4
5 3
V D D
P A 4
5
5 2
O S C 3
P A 5
6
5 1
O S C 4
P A 6
7
5 0
S E G 0
P A 7
8
4 9
S E G 1
P B 0 /A N 0
9
4 8
S E G 2
P B 1 /A N 1
1 0
4 7
S E G 3
P B 2 /A N 2
1 1
4 6
S E G 4
6
P B 3 /A N 3
1 2
4 5
S E G 5
8
P B 4 /A N 4
1 3
4 4
S E G 6
P B 5 /A N 5
1 4
4 3
S E G 7
V S S
1 5
4 2
S E G 8
P D 0 /P W M 0
1 6
4 1
S E G 9
P D 1 /P W M 1
1 7
4 0
S E G 1 0
P D 2 /P W M 2
1 8
3 9
S E G 1 1
P D 4 /IN T 0
1 9
3 8
S E G 1 2
P D 5 /IN T 1
2 0
3 7
S E G 1 3
P D 6 /T M R
2 1
3 6
S E G 1 4
V L C D
2 2
3 5
S E G 1 5
V M A X
2 3
3 4
S E G 1 6
V 1
2 4
3 3
S E G 1 7
V 2
2 5
3 2
S E G 1 8
C 1
2 6
3 1
C O M 3 /S E G 1 9
C 2
2 7
3 0
C O M 2
C O M 0
2 8
2 9
C O M 1
S E G
S E G
O S C
O S C
V D
O S C
O S C
R E
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A
P A 0 /B Z
D
D
S
Z
Z
4
3
2
1
2
4
2
1
P B
P B
P B
P B
P B
P B
5
P D 0 /P
P D 1 /P
P D 2 /P
4
3
2
1
0
P A
P A
P A
/A N
/A N
/A N
/A N
/A N
/A N
V S
W M
W M
W M
5
S
2
1
0
4
3
2
1
0
7
6
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
5
1
3 9
2
3 8
3
3 7
4
3 6
5
3 5
6
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
H T 4 6 R 6 2 /H T 4 6 C 6 2
5 2 Q F P -A
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
3
4
5
7
9
1 0
1 1
1 2
1 3
1 4
1 5
S E
S E
S E
C O
C O
C O
C O
V 1
V M
V L
P D
P D
P D
G 1
G 1
G 1
M 3
M 2
M 1
M 0
6
7
8
/S E G 1 9
A X
C D
6 /T M R
5 /IN T 1
4 /IN T 0
H T 4 6 R 6 2 /H T 4 6 C 6 2
5 6 S S O P -A
Note:
The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must
select the R type by option.
Rev. 1.60
3
July 14, 2005
HT46R62/HT46C62
Pin Description
Pin Name
PA0/BZ
PA1/BZ
PA2
PA3/PFD
PA4~PA7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PD0/PWM0
PD1/PWM1
PD2/PWM2
I/O
Options
Description
Wake-up
Pull-high
Buzzer
PFD
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by option. Software instructions determine the CMOS output or
Schmitt Trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The BZ, BZ and PFD are pin-shared with
PA0, PA1 and PA3, respectively.
I/O
Pull-high
Bidirectional 6-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: bit option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and
pull-high resistor are disabled automatically.
I/O
Pull-high
PWM
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The PWM0/PWM1/PWM2 output
function are pin-shared with PD0/PD1/PD2 (dependent on PWM options).
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: bit option). The INT0, INT1 and TMR are
pin-shared with PD4/PD5/PD6.
I/O
PD4/INT0
PD5/INT1
PD6/TMR
I/O
Pull-high
VSS
¾
¾
Negative power supply, ground
I
¾
LCD power supply
VMAX
I
¾
IC maximum voltage connect to VDD, VLCD or V1
V1, V2, C1, C2
I
¾
Voltage pump
COM0~COM2
COM3/SEG19
O
1/2, 1/3 or 1/4
Duty
SEG19 can be set as a segment or as a common output driver for LCD
panel by options. COM0~COM2 are outputs for LCD panel plate.
SEG0~SEG18
O
Logical Output
LCD driver outputs for LCD panel segments. SEG0~SEG15 can be
optioned as logical outputs.
VLCD
OSC1
OSC2
I
O
Crystal or RC
OSC1 and OSC2 are connected to an RC network or a crystal (by options)
for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. The system clock may come from the
RTC oscillator. If the system clock comes from RTCOSC, these two pins
can be floating.
OSC3
OSC4
I
O
RTC or
System Clock
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
crystal oscillator for timing purposes or to a system clock source (depending on the options). No built-in capacitor
VDD
¾
¾
Positive power supply
RES
I
¾
Schmitt trigger reset input, active low
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.60
4
July 14, 2005
HT46R62/HT46C62
D.C. Characteristics
Symbol
VDD
IDD1
Parameter
Operating Voltage
Operating Current
(Crystal OSC, RC OSC)
Ta=25°C
Test Conditions
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
3V
No load, ADC Off,
fSYS=4MHz
¾
1
2
mA
¾
3
5
mA
No load, ADC Off,
fSYS=8MHz
¾
4
8
mA
¾
0.3
0.6
mA
¾
0.6
1
mA
¾
¾
1
mA
¾
¾
2
mA
¾
2.5
5
mA
¾
10
20
mA
¾
2
5
mA
¾
6
10
mA
¾
17
30
mA
¾
34
60
mA
¾
13
25
mA
¾
28
50
mA
¾
14
25
mA
¾
26
50
mA
5V
3V
Standby Current
(*fS=T1)
3V
Standby Current
(*fS=RTC OSC)
3V
ISTB4
ISTB5
ISTB6
ISTB7
Standby Current
(*fS=RTC OSC)
Standby Current
(*fS=RTC OSC)
Standby Current
(*fS=WDT OSC)
Standby Current
(*fS=WDT OSC)
Unit
¾
Operating Current
(fSYS=32768Hz)
Standby Current
(*fS=WDT OSC)
Max.
2.2
IDD3
ISTB3
Typ.
fSYS=4MHz
Operating Current
(Crystal OSC, RC OSC)
ISTB2
Min.
¾
IDD2
ISTB1
Conditions
VDD
5V
No load, ADC Off
5V
5V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
No load, system HALT,
LCD Off at HALT
No load, system HALT,
LCD On at HALT, C type
No load, system HALT,
LCD On at HALT, C type
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
(Low bias current option)
¾
10
20
mA
¾
19
40
mA
VIL1
Input Low Voltage for I/O Ports,
TMR, INT0, INT1
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR, INT0, INT1
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset Voltage
¾
¾
2.7
3.0
3.3
V
VLVD
Low Voltage Detector Voltage
¾
¾
3.0
3.3
3.6
V
IOL1
I/O Port Segment Logic Output
Sink Current
3V
6
12
¾
mA
10
25
¾
mA
-2
-4
¾
mA
-5
-8
¾
mA
IOH1
Rev. 1.60
I/O Port Segment Logic Output
Source Current
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
5
July 14, 2005
HT46R62/HT46C62
Symbol
Parameter
LCD Common and Segment
Current
IOL2
LCD Common and Segment
Current
IOH2
Test Conditions
Conditions
VDD
3V
VOL=0.1VDD
5V
3V
VOH=0.9VDD
5V
Min.
Typ.
Max.
Unit
210
420
¾
mA
350
700
¾
mA
-80
-160
¾
mA
-180
-360
¾
mA
Pull-high Resistance of I/O Ports
and INT0, INT1
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Integral
Nonlinearity Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
RPH
Note:
¾
5V
²*fS² please refer to clock option of Watchdog Timer
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
¾
32768
¾
Hz
¾
32768
¾
Hz
fSYS1
System Clock
fSYS2
System Clock
(32768Hz Crystal OSC)
fRTCOSC
RTC Frequency
¾
fTIMER
Timer I/P Frequency
tWDTOSC Watchdog Oscillator Period
Conditions
VDD
¾
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up from
HALT
¾
1024
¾
tSYS
tLVR
Low Voltage Width to Reset
¾
¾
1
¾
¾
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Note:
tSYS= 1/fSYS
Rev. 1.60
6
July 14, 2005
HT46R62/HT46C62
Functional Description
Execution Flow
specify a maximum of 2048 addresses.
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
After accessing a program memory word to fetch an instruction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each instruction to be effectively executed in a cycle. If an instruction changes the value of the program counter, two
cycles are required to complete the instruction.
When executing a jump instruction, conditional skip execution, loading a PCL register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; otherwise proceed to the next instruction.
Program Counter - PC
The program counter (PC) is 11 bits wide and it controls
the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
Mode
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
External Interrupt 0
0
0
0
0
0
0
0
0
1
0
0
External Interrupt 1
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
1
1
0
0
Time Base Interrupt
0
0
0
0
0
0
1
0
1
0
0
RTC Interrupt
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*10~*0: Program counter bits
#10~#0: Instruction code bits
Rev. 1.60
S10~S0: Stack register bits
@7~@0: PCL bits
7
July 14, 2005
HT46R62/HT46C62
· Location 008H
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations.
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
When a control transfer takes place, an additional
dummy cycle is required.
· Location 00CH
Location 00CH is reserved for the Timer/Event Counter interrupt service program. If a timer interrupt results from a Timer/Event Counter overflow, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
Program Memory - EPROM
The program memory (EPROM) is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized
into 2048´14 bits which are addressed by the program
counter and table pointer.
· Location 014H
Location 014H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 014H.
Certain locations in the ROM are reserved for special
usage:
· Location 018H
· Location 000H
Location 018H is reserved for the real time clock interrupt service program. If a real time clock interrupt occurs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 018H.
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
· Location 004H
· Table location
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
0 0 0 H
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
E x te r n a l in te r r u p t 0 s u b r o u tin e
0 0 8 H
0 0 C H
Any location in the ROM can be used as a look-up table. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of
TBLH and the remaining 1 bit is read as ²0². The
TBLH is read only, and the table pointer (TBLP) is a
read/write register (07H), indicating the table location.
Before accessing the table, the location should be
placed in TBLP. All the table related instructions require 2 cycles to complete the operation. These areas
may function as a normal ROM depending upon the
user¢s requirements.
E x te r n a l in te r r u p t 1 s u b r o u tin e
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
0 1 4 H
T im e B a s e In te r r u p t
0 1 8 H
P ro g ra m
M e m o ry
R T C In te rru p t
n 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
7 0 0 H
L o o k - u p ta b le ( 2 5 6 w o r d s )
7 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 7
Program Memory
Instruction(s)
Table Location
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.60
P10~P8: Current program counter bits
8
July 14, 2005
HT46R62/HT46C62
Stack Register - STACK
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). The space before 28H is
overlapping in each bank.
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 6 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledgment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
0 0 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
R T C C
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
1 0 H
1 1 H
Data Memory - RAM
1 2 H
P A
The data memory (RAM) is designed with 116´8 bits,
and is divided into two functional groups, namely; special function registers 28´8 bit and general purpose data
memory, 88´8 bit most of which are readable/writable,
although some are read only. The special function register are overlapped in any banks.
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
1 7 H
Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), a Bank pointer (BP;04H), an
A c c u m ul a t o r ( A C C ; 05H ) , a P r o g r am co u n t e r
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Interrupt control register 0 (INTC0;0BH), Interrupt control
register 1 (INTC1;1EH) , PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH), the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The space before 28H is overlapping in each
bank. The general purpose data memory, addressed
from 28H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment,
Rev. 1.60
S p e c ia l P u r p o s e
D a ta M e m o ry
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
1 C H
P W M 2
1 D H
1 E H
IN T C 1
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
7 F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(8 8 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
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HT46R62/HT46C62
Indirect Addressing Register
Status Register - STATUS
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading location 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. The bit 7 of MP0 and MP1 are always ²1². MP0 can only be applied to data memory,
while MP1 can be applied to data memory and LCD display memory.
Accumulator - ACC
The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
The device provides two external interrupts, one internal
timer/event counter interrupts, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.60
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July 14, 2005
HT46R62/HT46C62
tion 04H or 08H occurs. The interrupt request flag (EIF0
or EIF1) and EMI bits are all cleared to disable other
maskable interrupts.
Once an interrupt subroutine is serviced, other interrupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becoming full.
The internal Timer/Event Counter interrupt is initialized
by setting the Timer/Event Counter interrupt request flag
(TF; bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
not full, and the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further interrupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the specified location in the ROM. Only the contents of the program counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the desired control sequence, the contents should be saved in
advance.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC1), that is caused by a regular real time clock signal. After the interrupt is enabled, and the stack is not
full, and the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag (RTF) is
reset and the EMI bit is cleared to disable further interrupts.
External interrupts are triggered by a an edge transition
of INT0 or INT1 (option: high to low, low to high, low to
high or high to low), and the related interrupt request flag
(EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to locaBit No.
During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the ²RETI²
instruction is executed or the EMI bit and the related in-
Label
Function
0
EMI
Control the master (global) interrupt (1=enabled; 0=disabled)
1
EEI0
Control the external interrupt 0 (1=enabled; 0=disabled)
2
EEI1
Control the external interrupt 1 (1=enabled; 0=disabled)
3
ETI
Control the Timer/Event Counter interrupt (1=enabled; 0=disabled)
4
EIF0
External interrupt 0 request flag (1=active; 0=inactive)
5
EIF1
External interrupt 1 request flag (1=active; 0=inactive)
6
TF
Internal Timer/Event Counter request flag (1=enable; 0=disable)
7
¾
For test mode used only.
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
Function
0
¾
1
ETBI
Unused bit, read as ²0²
Control the time base interrupt (1=enabled; 0:disabled)
2
ERTI
Control the real time clock interrupt (1=enabled; 0:disabled)
3, 4
¾
5
TBF
Unused bit, read as ²0²
Time base request flag (1=active; 0=inactive)
6
RTF
Real time clock request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC1 (1EH) Register
Rev. 1.60
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July 14, 2005
HT46R62/HT46C62
oscillator is selected as the system oscillator, the system
oscillator is not stopped; but the instruction execution is
stopped. Since the 32768Hz oscillator is also designed
for timing purposes, the internal timing (RTC, time base,
WDT) operation still runs even if the system enters the
HALT mode.
terrupt control bit are set both to 1 (if the stack is not full).
To return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI sets the EMI bit and enables an
interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
External interrupt 0
Priority
Vector
1
04H
External interrupt 1
2
08H
Timer/Event Counter overflow
3
0CH
Time base interrupt
4
14H
Real time clock interrupt
5
18H
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and VSS is required,
and the range of the resistance should be from 30kW to
750kW. The system clock, divided by 4, is available on
OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature, and the
chip itself due to process variations. It is therefore, not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.
The Timer/Event Counter interrupt request flag (TF), external interrupt 1 request flag (EIF1), external interrupt 0
request flag (EIF0), enable Timer/Event Counter interrupt bit (ETI), enable external interrupt 1 bit (EEI1), enable external interrupt 0 bit (EEI0) and enable master
interrupt bit (EMI) make up of the Interrupt Control register 0 (INTC0) which is located at 0BH in the RAM. The
real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable real time clock interrupt bit (ERTI), and enable time base interrupt bit
(ETBI), on the other hand, constitute the Interrupt Control register 1 (INTC1) which is located at 1EH in the
RAM. EMI, EEI0, EEI1, ETI, ET1I, ETBI and ERTI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (RTF, TBF,
TF, EIF1, EIF0) are all set, they remain in the INTC1 or
INTC0 respectively until the interrupts are serviced or
cleared by a software instruction.
There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscillator can be applied. The crystal should be connected
between OSC3 and OSC4.
V
4 7 0 p F
O S C 1
O S C 2
fS
Y S
O S C 1
O S C 2
/4
C r y s ta l O s c illa to r
R C
O s c illa to r
O S C 3
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s because interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applications. During that period, if only one stack is left, and enabling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
O S C 4
3 2 7 6 8 H z
C r y s ta l/R T C
O s c illa to r
System Oscillator
Note:
Oscillator Configuration
32768Hz crystal enable condition: For WDT
clock source or for system clock source.
The external resistor and capacitor components
connected to the 32768Hz crystal are not necessary to provide oscillation. For applications
where precise RTC frequencies are essential,
these components may be required to provide
frequency compensation due to different crystal
manufacturing tolerances.
The device provides three oscillator circuits for system
clocks, i.e., RC oscillator, crystal oscillator and 32768Hz
crystal oscillator, determined by options. No matter what
type of oscillator is selected, the signal is used for the
system clock. The HALT mode stops the system oscillator (RC and crystal oscillator only) and ignores external
signal in order to conserve power. The 32768Hz crystal
oscillator still runs at HALT mode. If the 32768Hz crystal
Rev. 1.60
D D
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HT46R62/HT46C62
two types of software instructions; ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one type of instruction can
be active at a time depending on the options - ²CLR
WDT² times selection option. If the ²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution
of the ²CLR WDT² instruction clears the WDT. In the
case that ²CLR WDT1² and ²CLR WDT2² are chosen
(i.e., CLR WDT times equal two), these two instructions
have to be executed to clear the WDT; otherwise, the
WDT may reset the chip due to time-out.
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is
recommended to turn on the quick oscillating function
upon power on, and then turn it off after 2 seconds.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Although
the system enters the power down mode, the system
clock stops, and the WDT oscillator still works with a period of approximately 65ms@5V. The WDT oscillator can
be disabled by options to conserve power.
Watchdog Timer - WDT
Multi-function Timer
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC oscillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all executions related to the WDT lead to no operation.
The HT46R62/HT46C62 provides a multi-function timer
for the WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of an
8-stage divider and a 7-bit prescaler, with the clock
source coming from the WDT OSC or RTC OSC or the
instruction clock (i.e., system clock divided by 4). The
multi-function timer also provides a selectable frequency signal (ranges from fS/22 to fS/28) for LCD driver
circuits, and a selectable frequency signal (ranging from
fS/22 to fS/29) for the buzzer output by options. It is recommended to select a nearly 4kHz signal for the LCD
driver circuits to have proper display.
Once an internal WDT oscillator (RC oscillator with period 65ms@5V normally) is selected, it is divided by
212~215 (by option to get the WDT time-out period). The
minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the
WDT option, longer time-out periods can be realized. If
the WDT time-out is selected 215, the maximum time-out
period is divided by 215~216about 2.1s~4.3s. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the halt state the WDT may stop counting
and lose its protecting purpose. In this situation the logic
can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the
HALT will stop the system clock.
Time Base
The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period
ranges from 212/fS to 215fS selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 14H occurs.
fs
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), software instruction, and a ²HALT² instruction. There are
S y s te m
D iv id e r
P r e s c a le r
O p tio n
O p tio n
L C D D r iv e r ( fS /2 2 ~ fS /2 8 )
B u z z e r (fS /2 2~ fS /2 9)
T im e B a s e In te r r u p t
2 12/fS ~ 2 15/fS
Time Base
C lo c k /4
R T C
O S C 3 2 7 6 8 H z
O p tio n
S e le c t
fS
D iv id e r
fS /2
8
W D T
P r e s c a le r
O p tio n
W D T
1 2 k H z
O S C
C K
T
R
W D T C le a r
C K
T
R
T im e 2 15/fS ~
2 14/fS ~
2 13/fS ~
2 12/fS ~
o u
2 1
2 1
2 1
2 1
t R e s e t
6 / f
S
5 / f
S
4
/fS
3 / f
S
Watchdog Timer
Rev. 1.60
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July 14, 2005
HT46R62/HT46C62
fS
D iv id e r
P r e s c a le r
R T 2
R T 1
R T 0
8 to 1
M u x .
2 8/fS ~ 2 15/fS
R T C In te rru p t
Real Time Clock
Real Time Clock - RTC
struction, and is set by executing the ²HALT² instruction.
On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only resets the program
counter and SP, and leaves the others at their original
state.
The real time clock (RTC) is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming. Writing data to RT2,
RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a subroutine call to location 18H occurs.
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
2 8*
0
0
1
2 9*
0
1
0
210*
0
1
1
211*
1
0
0
212
1
0
1
213
1
1
0
214
1
1
1
215
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awakened using
that interrupt.
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be performed immediately after the dummy period is finished.
Note: ²*² not recommended to be used
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
· The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
Reset
· The contents of the on-chip RAM and of the registers
There are three ways in which reset may occur.
remain unchanged.
· RES is reset during normal operation
· The WDT is cleared and start recounting (if the WDT
· RES is reset during HALT
clock source is from the WDT oscillator or the real time
clock oscillator).
· WDT time-out is reset during normal operation
· All I/O ports maintain their original status.
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the reset conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
· The PDF flag is set but the TO flag is cleared.
· LCD driver is still running
(if the WDT OSC or RTC OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initialization, and the WDT overflow performs a ²warm reset².
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared by
system power-up or by executing the ²CLR WDT² in-
Rev. 1.60
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HT46R62/HT46C62
TO
PDF
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
H A L T
RESET Conditions
W D T
One timer/event counters (TMR) are implemented in the
microcontroller. The Timer/Event Counter contains a
8-bit programmable count-up counter and the clock may
come from an external source or an internal clock
source. An internal clock source comes from fSYS. The
external clock input allows the user to count external
events, measure time intervals or pulse widths, or to
generate an accurate time base.
The functional unit chip reset status is shown below.
Program Counter
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, RTC, Time Base
Cleared. After master reset,
WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
There are two registers related to the Timer/Event
Counter; TMR ([0DH]) and TMRC ([0EH]). Two physical
registers are mapped to TMR location; writing TMR puts
the starting value in the Timer/Event Counter register
and reading TMR takes the contents of the Timer/Event
Counter. The TMRC is a timer/event counter control register, which defines some options counting enable or
disable and an active edge.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
In the event count or timer mode, the timer/event counter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt request flag (TF; bit 6 of INTC0). In the pulse width measurement mode with the values of the TON and TE bits
equal to 1, after the TMR has received a transient from
low to high (or high to low if the TE bit is ²0²), it will start
counting until the TMR returns to the original level and
resets the TON. The measured result remains in the
timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement
can be made until the TON is set. The cycle measurement will re-function as long as it receives further transient pulse. In this operation mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter over-
0 .1 m F *
Reset Circuit
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
V D D
R E S
tS
S T
S S T T im e - o u t
R e s e t
Reset Timing Chart
Rev. 1.60
C o ld
R e s e t
Timer/Event Counter
An extra SST delay is added during the power-up period, and any wake-up from HALT may enable only the
SST delay.
C h ip
S S T
1 0 - b it R ip p le
C o u n te r
Reset Configuration
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
Note:
E x te rn a l
P o w e r - o n D e te c tio n
Note: ²u² stands for unchanged
V
R e s e t
T im e - o u t
R e s e t
R E S
O S C 1
W a rm
W D T
15
July 14, 2005
HT46R62/HT46C62
The register states are summarized below:
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
MP0
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
MP1
1xxx xxxx
1uuu uuuu
1uuu uuuu
1uuu uuuu
1uuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000H
0000H
0000H
0000H
0000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
RTCC
--00 0111
--00 0111
--00 0111
--00 0111
--uu uuuu
Register
Program Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PBC
--11 1111
--11 1111
--11 1111
--11 1111
--uu uuuu
PD
-111 -111
-111 -111
-111 -111
-111 -111
-uuu -uuu
PDC
-111 -111
-111 -111
-111 -111
-111 -111
-uuu -uuu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM2
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
INTC1
-00- -00-
-00- -00-
-00- -00-
-00- -00-
-uu- -uu-
ADRL
x--- ----
x--- ----
x--- ----
x--- ----
u--- ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
1--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.60
16
July 14, 2005
HT46R62/HT46C62
to ETI disables the related interrupt service. When the
PFD function is selected, executing ²SET [PA].3² instruction to enable PFD output and executing ²CLR
[PA].3² instruction to disable PFD output.
flows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the
other two modes, i.e., event and timer modes.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by instructions. The overflow of the Timer/Event Counter is
one of the wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) output at PA3
by options. Only one PFD can be applied to PA3 by options . No matter what the operation mode is, writing a 0
Bit No.
0
1
2
When the timer/event counter (reading TMR) is read,
the clock is blocked to avoid errors, as this may results
Label
Function
To define the prescaler stages.
PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
PSC0
PSC1
PSC2
3
TE
4
TON
5
¾
6
7
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs.
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable/disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
Defines the operating mode (TM1, TM0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TM0
TM1
TMRC (0EH) Register
P W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
Y S
T o P D 0 /P D 1 /P D 2 C ir c u it
8 - s ta g e P r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
8 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r
(T M R )
O v e r flo w
1 /2
to In te rru p t
P F D
P A 3 D a ta C T R L
Timer/Event Counter
Rev. 1.60
17
July 14, 2005
HT46R62/HT46C62
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
in a counting error. Blocking of the clock should be taken
into account by the programmer. It is strongly recommended to load a desired value into the TMR register
first, before turning on the related timer/event counter,
for proper operation since the initial value of TMR is unknown. Due to the timer/event scheme, the programmer
should pay special attention on the instruction to enable
then disable the timer for the first time, whenever there
is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event
function can be operated normally.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always retain
its original functions. Once the PFD option is selected,
the PFD output signal is controlled by PA3 data register
only. Writing ²1² to PA3 data register will enable the PFD
output function and writing 0 will force the PA3 to remain
at ²0². The I/O functions of PA3 are shown below.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal. The timer prescaler is also
used as the PWM counter.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
PA3
Logical
Input
Logical
Output
Input/Output Ports
There are 20 bidirectional input/output lines in the
microcontroller, labeled as PA, PB0~PB5, PD0~PD2
and PD4~PD6, which are mapped to the data memory
of [12H], [14H] and [18H] respectively. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Note:
O/P
(PFD)
Logical
PFD
Input (Timer on)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
The PA0, PA1, PA3, PD4, PD5 and PD6 are pin-shared
with BZ, BZ, PFD, INT0, INT1 and TMR pins respectively.
The PA0 and PA1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PA0/PA1 will be the buzzer signal generated by multi-function timer. The input mode
always remain in its original function. Once the BZ/BZ
option is selected, the buzzer output signal are controlled by the PA0, PA1 data register only.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt Trigger input
with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write²
instruction.
The I/O function of PA0/PA1 are shown below.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
18H) instructions.
PA0 I/O
I
I
O O O O O O O O
PA1 I/O
I
O
I
PA0 Mode
X X C B B C B B B B
PA1 Mode
X C X X X C C C B B
PA0 Data
X X D 0
PA1 Data
X D X X X D1 D D X X
PA0 Pad Status
I
I
D 0
B D0 0
0
B
PA1 Pad Status
I
D
I
I D1 D D 0
B
Note:
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Rev. 1.60
I/P
(PFD)
I
I
I
O O O O O
1 D0 0
1
B
0
1
²I² input; ²O² output
²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care
²C² CMOS output
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2. If the PWM function
is enabled, the PWM0/PWM1/PWM2 signal will appear
18
July 14, 2005
HT46R62/HT46C62
V
C o n tr o l B it
Q
D
D a ta B u s
W r ite C o n tr o l R e g is te r
C K
P u ll- h ig h
O p tio n
P A
P A
P A
P A
P A
P B
P D
P D
P D
P D
P D
P D
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
Q
C K
W r ite D a ta R e g is te r
D D
0 /B
1 /B
2
3 /P
4 ~ P
0 /A
0 /P
1 /P
2 /P
4 /IN
5 /IN
6 /T
Z
Z
F D
A 7
N 0 ~
W M
W M
W M
T 0
T 1
M R
P B 5 /A N 5
1
0
2
S
M
P A 0 /P A 1 /P A 3 /P D 0 /P D 1 /P D 2
B Z /B Z /P F D /P W M 0 /P W M 1 /P W M 2
M
R e a d D a ta R e g is te r
U
U
X
P F D E N
(P A 3 )
X
S y s te m W a k e -u p
( P A o n ly )
W a k e - u p O p tio n s
IN T 0 fo r P D 4 o n ly
IN T 1 fo r P D 5 o n ly
T M R fo r P D 6 o n ly
Input/Output Ports
PWM
on PD0/PD1/PD2 (if PD0/PD1/PD2 is operating in output mode). The I/O functions of PD0/PD1/PD2 are as
shown.
I/O
Mode
I/P
O/P
(Normal) (Normal)
PD0
PD1
PD2
Logical
Input
Logical
Output
I/P
(PWM)
O/P
(PWM)
Logical
Input
PWM0
PWM1
PWM2
The microcontroller provides 3 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1/PD2. The PWM channels have their data registers denoted as PWM0 (1AH), PWM1 (1BH) and
PWM2 (1CH). The frequency source of the PWM counter comes from fSYS. The PWM registers are three 8-bit
registers. The waveforms of PWM outputs are as
shown. Once the PD0/PD1/PD2 are selected as the
PWM outputs and the output function of PD0/PD1/PD2
are enabled (PDC.0/PDC.1/ PDC.2=²0²), writing ²1² to
PD0/PD1/PD2 data register will enable the PWM output
function and writing ²0² will force the PD0/PD1/PD2 to
stay at ²0².
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
PA3 Data PA3 Pad
Timer Preload
Register
State
Value
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
fTMR/[2´(M-N)]
Note:
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
PFD
Frequency
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
²X² stands for unused
²U² stands for unknown
²M² is ²256² for PFD
²N² is preload value for timer/event counter
²fTMR² is input clock frequency for timer/event
counter
Rev. 1.60
Parameter
AC (0~3)
Duty Cycle
i<AC
DC + 1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
19
July 14, 2005
HT46R62/HT46C62
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
PWM
Modulation Frequency
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
i<AC
DC + 1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
Rev. 1.60
20
July 14, 2005
HT46R62/HT46C62
A/D Converter
converter circuit is powered-on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure that the A/D conversion is completed,
the START should remain at ²0² until the EOCB is
cleared to ²0² (end of A/D conversion).
The 6 channels and 9 bits resolution A/D converter are
implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the converted analog channel, and give START bit a rising edge
and falling edge (0®1®0). At the end of A/D conversion, the EOCB bit is cleared. The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialization is not required.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of six
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
Bit No.
0
1
Label
Function
Selects the A/D converter clock source
00= system clock/2
ADCS0
01= system clock/8
ADCS1
10= system clock/32
11= undefined
2~6
¾
Unused bit, read as ²0²
7
TEST
For test mode used only
ACSR (27H) Register
Bit No.
Label
Function
0
1
2
ACS0
ACS1
ACS2
Defines the analog channel select.
3
4
5
PCR0
PCR1
PCR2
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
power off to reduce power consumption
6
Indicates end of A/D conversion. (0 = end of A/D conversion)
EOCB Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7
START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
Rev. 1.60
21
July 14, 2005
HT46R62/HT46C62
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
¾
¾
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
¾
¾
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
¾
¾
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
¾
¾
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
¾
¾
PB5
PB4
AN3
AN2
AN1
AN0
1
0
1
¾
¾
PB5
AN4
AN3
AN2
AN1
AN0
1
1
0
¾
¾
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
¾
¾
AN5
AN4
AN3
AN2
AN1
AN0
Port B Configuration
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN5
1
1
1
AN5
Analog Input Channel Selection
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADRL (24H)
D0
¾
¾
¾
¾
¾
¾
¾
ADRH (25H)
D8
D7
D6
D5
D4
D3
D2
D1
Note:
D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following programming example illustrates how to setup and implement an A/D conversion. The method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
mov
mov
mov
mov
EADI
a,00000001B
ACSR,a
a,00100000B
ADCR,a
:
:
:
Start_conversion:
clr
START
set
START
clr
START
Polling_EOC:
sz
EOCB
jmp
polling_EOC
mov
a,ADRH
Rev. 1.60
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result high byte value from the ADRH register
22
July 14, 2005
HT46R62/HT46C62
mov
mov
mov
adrh_buffer,a
a,ADRL
adrl_buffer,a
:
:
start_conversion
jmp
M in im u m
; save result to user defined memory
; read conversion result low byte value from the ADRL register
; save result to user defined memory
; start next A/D conversion
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
S T A R T
E O C B
A /D
tA
P C R 2 ~
P C R 0
s a m p lin g tim e
A /D
tA
D C S
0 0 0 B
s a m p lin g tim e
A /D
tA
D C S
1 0 0 B
1 0 0 B
s a m p lin g tim e
D C S
1 0 1 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
tA D C
c o n v e r s io n tim e
A /D
N o te :
A /D c lo c k m u s t b e fS
tA D C S = 3 2 tA D
tA D C = 7 6 tA D
Y S
/2 , fS
Y S
/8 o r fS
Y S
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA D C
c o n v e r s io n tim e
A /D
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
LCD Display Memory
LCD Driver Output
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 53H of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as ²1², any data
written into 40H~53H will effect the LCD display. When
the BP is cleared to ²0², any data written into 40H~53H
means to access the general purpose data memory.
The LCD display memory can be read and written to
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automatically read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
on or off, a ²1² or a ²0² is written to the corresponding bit
of the display memory, respectively. The figure illustrates the mapping between the display memory and
LCD pattern for the device.
The output number of the device LCD driver can be 20´2
or 20´3 or 19´4 by option (i.e., 1/2 duty, 1/3 duty or 1/4
duty). The bias type LCD driver can be ²R² type or ²C²
type. If the ²R² bias type is selected, no external capacitor is required. If the ²C² bias type is selected, a capacitor mounted between C1 and C2 pins is needed. The
LCD driver bias voltage can be 1/2 bias or 1/3 bias by
option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is selected, two capacitors are needed for V1 and V2 pins.
Refer to application diagram.
C O M
4 0 H
4 1 H
4 2 H
4 3 H
5 1 H
5 2 H
5 3 H
0
Option
Condition Low Bias Current High Bias Current
(Typ.)
(Typ.)
B it
1/3 Bias
(VLCD/4.5)´15mA
(VLCD/4.5)´45mA
1/2 Bias
(VLCD/3)´15mA
(VLCD/3)´45mA
²R² Type Bias Current
0
1
2
2
3
3
Note:
1
S E G M E N T
0
1
2
3
1 7
1 8
The 52-pin QFP package does not support the
charge pump (C type bias) of the LCD. The LCD
bias type must select the R type by option.
1 9
Display Memory
Rev. 1.60
23
July 14, 2005
HT46R62/HT46C62
D u r in g a R e s e t P u ls e
C O M 0 ,C O M 1 ,C O M 2
A ll L C D
d r iv e r o u tp u ts
N o r m a l O p e r a tio n M o d e
*
*
*
C O M 0
C O M 1
C O M 2 *
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e u n lig h te d
O n ly L C D s e g m e n ts O N
C O M 0 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 1 s id e a r e lig h te d
O n ly L C D s e g m e n ts O N
C O M 2 s id e a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 1 , 2 s id e s a r e lig h te d
L C D s e g m e n ts O N
C O M 0 ,1 , 2 s id e s a r e lig h te d
H A L T M o d e
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
V L
1 /2
V S
C D
V L
1 /2
V S
V L
1 /2
V S
C O M 0 , C O M 1 , C O M 2
A ll lc d d r iv e r o u tp u ts
N o te : " * " O m it th e C O M 2 s ig n a l, if th e 1 /2 d u ty L C D
V L C D
S
C D
V L C D
S
S
C D
S
V L C D
C D
S
V L C D
V L C D
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
V L
S
C D
S
C D
S
C D
C D
C D
C D
C D
C D
C D
C D
V L C D
V L C D
is u s e d .
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 1.60
24
July 14, 2005
HT46R62/HT46C62
V A
V B
V C
C O M 0
V S S
V A
V B
V C
C O M 1
V S S
V A
V B
V C
C O M 2
V S S
V A
V B
C O M 3
V C
V S S
V A
V B
V C
L C D s e g m e n ts O N
C O M 2 s id e lig h te d
V S S
N o te : 1 /4 d u ty , 1 /3 b ia s , C
ty p e : " V A " 3 /2 V L C D , " V B " V L C D , " V C " 1 /2 V L C D
1 /4 d u ty , 1 /3 b ia s , R
ty p e : "V A " V L C D , "V B " 2 /3 V L C D , "V C " 1 /3 V L C D
LCD Driver Output
LCD Segments as Logical Output
The SEG0~SEG15 also can be optioned as logical output, once an LCD segment is optioned as a logical output, the
content of bit 0 of the related segment address in LCD RAM will appear on the segment.
SEG0~SEG7 is together byte optioned as logical output, SEG8~SEG15 are bit individually optioned as logical outputs.
LCD Type
LCD Bias Type
VMAX
Rev. 1.60
R Type
1/2 bias
1/3 bias
C Type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
25
1/3 bias
3
VLCD, then VMAX connect to VDD,
2
else VMAX connect to V1
If VDD >
July 14, 2005
HT46R62/HT46C62
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
Label
Function
0~2
RT0~RT2
3
LVDC
LVD enable/disable (1/0)
4
QOSC
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
5
LVDO
LVD detection output (1/0)
1: low voltage detected, read only
6, 7
¾
8 to 1 multiplexer control inputs to select the real clock prescaler output
Unused bit, read as ²0²
RTCC (09H) Register
The LVR has the same effect or function with the external RES signal which performs chip reset. During HALT
state, LVR is disabled both LVR and LVD are disabled.
The relationship between VDD and VLVR is shown below.
V D D
5 .5 V
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
V
O P R
5 .5 V
V
L V R
3 .0 V
2 .2 V
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.60
26
July 14, 2005
HT46R62/HT46C62
Options
The following shows the options in the device. All these options should be defined in order to ensure proper functioning
system.
Options
OSC type selection.
This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.
WDT, RTC and time base clock source selection.
There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or
215/fS~216/fS.
CLR WDT times selection.
This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the
WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be
cleared.
Time Base time-out period selection.
The Time Base time-out period ranges from 212/fS to 215/fS. ²fS² means the clock source selected by options.
Buzzer output frequency selection.
There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS² means the clock source selected by options.
Wake-up selection.
This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip
from a HALT by a falling edge (bit option).
Pull-high selection.
This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB and
PD can be independently selected (bit option).
I/O pins share with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
LCD common selection.
There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4
common is selected, the segment output pin ²SEG19² will be set as a common output.
LCD bias power supply selection.
There are two types of selections: 1/2 bias or 1/3 bias
LCD bias type selection.
This option is to determine what kind of bias is selected, R type or C type.
LCD driver clock frequency selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² stands for the clock source selection by options.
LCD ON/OFF at HALT selection.
LCD Segments as logical output selection, (byte, bit, bit, bit, bit, bit, bit, bit, bit option)
[SEG0~SEG7], SEG8, SEG9, SEG10, SEG11, SEG12, SEG13, SEG14 or SEG15
LVR selection.
LVR has enable or disable options
LVD selection.
LVD has enable or disable options
PFD selection.
If PA3 is set as PFD output, PFD is the timer overflow signal of the Timer/Event Counter respectively.
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
PD2: level output or PWM2 output
INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low.
Rev. 1.60
27
July 14, 2005
HT46R62/HT46C62
Application Circuits
V
D D
0 .0 1 m F *
V D D
C O M 0 ~ C O M 2
C O M 3 /S E G 1 9
S E G 0 ~ S E G 1 8
R E S
V L C D
1 0 0 k W
0 .1 m F
1 0 k W
L C D
P A N E L
L C D
P o w e r S u p p ly
V M A X
0 .1 m F *
C 1
V S S
0 .1 m F
V
C 2
O S C
C ir c u it
R
V 2
O S C 3
P A 0 /B
P A 1 /B
P A
P A 3 /P F
P A 4 ~ P A
O S C 4
Z
2
P D 5 /IN T 1
R 1
/4
O S C 2
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
7
P B 0 /A N 0
P B 5 /A N 5
O S C 1
P D 0 /P W M 0
P D 2 /P W M 2
O S C 2
~
P D 6 /T M R
Y S
O S C 1
C 2
Z
D
fS
C 1
~
P D 4 /IN T 0
0 .1 m F
O S C
R C S y s te m O s c illa to r
3 0 k W < R O S C < 7 5 0 k W
O S C 1
0 .1 m F
O S C 2
S e e r ig h t s id e
3 2 7 6 8 H z
4 7 0 p F
V 1
O S C 1
D D
H T 4 6 R 6 2 /H T 4 6 C 6 2
3 2 7 6 8 H z C ry s ta l S y s te m
O s c illa to r
O S C 1 a n d O S C 2 le ft
u n c o n n e c te d
O S C
C ir c u it
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
C1, C2
R1
4MHz Crystal
Crystal or Resonator
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
²VMAX² connect to VDD or VLCD or V1 refer to the table.
LCD Type
LCD bias type
VMAX
Rev. 1.60
R Type
1/2 bias
1/3 bias
C Type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
28
1/3 bias
If VDD > 3/2VLCD, then VMAX connect to VDD,
else VMAX connect to V1
July 14, 2005
HT46R62/HT46C62
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.60
29
July 14, 2005
HT46R62/HT46C62
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.60
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
30
July 14, 2005
HT46R62/HT46C62
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
31
July 14, 2005
HT46R62/HT46C62
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
32
July 14, 2005
HT46R62/HT46C62
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
33
July 14, 2005
HT46R62/HT46C62
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
July 14, 2005
HT46R62/HT46C62
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
July 14, 2005
HT46R62/HT46C62
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
36
July 14, 2005
HT46R62/HT46C62
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
July 14, 2005
HT46R62/HT46C62
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
38
July 14, 2005
HT46R62/HT46C62
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
July 14, 2005
HT46R62/HT46C62
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
July 14, 2005
HT46R62/HT46C62
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
41
July 14, 2005
HT46R62/HT46C62
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
42
July 14, 2005
HT46R62/HT46C62
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
43
July 14, 2005
HT46R62/HT46C62
Package Information
52-pin QFP (14´14) Outline Dimensions
C
H
D
3 9
G
2 7
I
2 6
4 0
F
A
B
E
1 4
5 2
K
J
1
Symbol
Rev. 1.60
1 3
Dimensions in mm
Min.
Nom.
Max.
A
17.3
¾
17.5
B
13.9
¾
14.1
C
17.3
¾
17.5
D
13.9
¾
14.1
E
¾
1
¾
F
¾
0.4
¾
G
2.5
¾
3.1
H
¾
¾
3.4
I
¾
0.1
¾
J
0.73
¾
1.03
K
0.1
¾
0.2
a
0°
¾
7°
44
July 14, 2005
HT46R62/HT46C62
56-pin SSOP (300mil) Outline Dimensions
2 9
5 6
B
A
2 8
1
C
C '
G
H
D
Symbol
Rev. 1.60
a
F
E
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
720
¾
730
D
89
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
45
July 14, 2005
HT46R62/HT46C62
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Fax: 886-3-563-1189
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Fax: 886-2-2655-7373
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http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
46
July 14, 2005