HT82V14 14-Bit CCD/CIS Analog Signal Processor Features · · · · · · · Low power CMOS : 350 mW 9 ADC clock latency for digital data output 14-bit 6 MSPS A/D converter 3-channel correlated double sampler 1~6 programmable gain Input clamp circuitry for CDS-mode Internal/external circuitfor CIS · · · · · · · Internal/external voltage reference Internal MUX for channel operation 1 or 3-channel operation Pixel-rate or line-rate switch operation Programmable 3-wire serial interface +5V digital I/O compatibility 28-pin SOP/SOJ package General Description The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The HT82V14 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of the trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 14-bit A/D converter. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset, and operating mode adjustments. Block Diagram O F F S E T R E F T C M L R E F O E V o lta g e R e fe r e n c e R IN C L P C D S G IN C L P C D S B IN C L P C D S + M U X V G A + 3 ´ 8 b its D A C O ffs e t C D S C L K 1 P ix e l R a te G u a ra n te e V G A + P G A 1 4 - b it A D C C o n tro l P o rt V G A 3 ´ 2 b its C o a rs e G a in C o n fig R e g is te r C D S C L K 2 D 1 3 ~ D 0 S C L K C S S D A T A 3 ´ 5 b its F in e G a in A D C C L K 1 July 12, 2000 HT82V14 Pin Assignment C D S C L K 1 1 2 8 A V D D C D S C L K 2 2 2 7 A V S S A D C C L K 3 2 6 R IN O E 4 2 5 O F F S E T D R V D D 5 2 4 G IN D R V S S 6 2 3 C M L D 1 3 /D 5 7 2 2 B IN D 1 2 /D 4 8 2 1 R E F T D 1 1 /D 3 9 2 0 R E F D 1 0 /D 2 1 0 1 9 A V S S D 9 /D 1 1 1 1 8 A V D D D 8 /D 0 1 2 1 7 S L O A D D 7 1 3 1 6 S C L K D 6 1 4 1 5 S D A T A H T 8 2 V 1 4 2 8 S O P /S O J Pin Description Pin No. Pin Name I/O Description 1 CDSCLK1 DI CDS reset clock pulse input 2 CDSCLK2 DI CDS data clock pulse input 3 ADCCLK DI A/D sample clock input for 3-channels mode 4 OE DI Output enable 5 DRVDD ¾ Digital driver power 6 DRVSS ¾ Digital driver ground 14~7 D0~D13 DO Digital data output 15 SDATA DIO Serial data input/output 16 SCLK DI Clock input for serial interface 17 CS DI Chip select 18, 27 AVSS ¾ Analog ground 19, 28 AVDD ¾ +5V analog supply 20 REF AO Reference decoupling 21 REFT AO Reference decoupling 22 BIN AI Analog Input, blue 23 CML AO Internal reference output 24 GIN AI Analog Input, green 25 OFFSET AO CIS reference decoupling 26 RIN AI Analog input, red 2 July 12, 2000 HT82V14 Absolute Maximum Ratings Supply Voltage .............................-0.3V to 5.5V Storage Temperature ......................0°C to 70°C Input Voltage ................VSS-0.3V to VDD+0.3V Operating Temperature ...............25°C to 50°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Electrical Characteristics Symbol Parameter Test Conditions Min. Typ. Max. Unit ¾ ¾ ¾ 6 MSPS 5V±10% ¾ ¾ ¾ 5 MSPS Resolution 5V±10% ¾ ¾ 14 ¾ BIT Integral Nonlinearity (INL) 5V±10% ¾ ¾ ±4.5 ¾ LSB Differential Nonlinearity (DNL) 5V±10% ¾ -0.5 ¾ 1.2 LSB Full-scale Input Range 5V±10% ¾ ¾ 4 ¾ Vp-p Input Limits 5V±10% ¾ AVDD-0.3 ¾ AVDD+0.3 V Input Capacitance 5V±10% ¾ ¾ TBD ¾ pF Input Current 5V±10% ¾ ¾ TBD ¾ mA Coarse Gain Range 5V±10% ¾ 1 ¾ 3 V/V Coarse Gain Resolution 5V±10% ¾ ¾ 2 ¾ Bits PGA Gain Range 5V±10% ¾ 1 ¾ 2 V/V PGA Gain Resolution 5V±10% ¾ ¾ 5 ¾ Bits Offset Range 5V±10% ¾ -200 ¾ 200 mV Offset Resolution 5V±10% ¾ ¾ 8 ¾ Bits VDD Conditions 3-channel Mode with CDS 5V±10% 1-channel Mode with CDS Conversion Rate A/D Converter Analog Inputs Amplifiers 3 July 12, 2000 HT82V14 Symbol Parameter Test Conditions Min. Typ. Max. Unit ¾ 4.75 ¾ 5.25 V 5V±10% ¾ 4.75 ¾ 5.25 V 5V±10% ¾ ¾ 350 ¾ mW VDD Conditions AVDD 5V±10% DRVDD Power Supplies Power Consumption Power Consumption Digital Specifications Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit Logic Inputs VIH High Level Input Voltage 3.3V~5V ¾ 2.0 ¾ ¾ V VIL Low Level Input Voltage 3.3V~5V ¾ ¾ ¾ 0.8 V IIH High Level Input Current 3.3V~5V ¾ ¾ 10 ¾ mA IIL Low Level Input Current 3.3V~5V ¾ ¾ 10 ¾ mA CIN Input Capacitance 3.3V~5V ¾ ¾ 10 ¾ pF Logic Outputs VOH High Level Output Voltage 3.3V~5V IOH=50mA 4.5 4.9 ¾ V VOH High Level Output Voltage 3.3V~5V IOH=0.5mA 2.4 ¾ ¾ V VOL Low Level Output Voltage 3.3V~5V IOL=-50mA ¾ ¾ 0.1 V VOL Low Level Output Voltage 3.3V~5V IOL=-0.6mA ¾ ¾ 0.4 V COUT Output Capacitance 3.3V~5V ¾ 5 ¾ pF 4 ¾ July 12, 2000 HT82V14 Timing Diagrams Timing Mode Sensor Mode A CDS 3-channel internally-defined and pixel-rate mux (00) Channel Mode B CDS 1-channel internally-defined mux (01) C CIS/SHA 3-channel internally-defined and pixel-rate mux (00) D CIS/SHA 1-channel internally-defined mux (01) Mode A P ix e l n P ix e l n + 1 tA A n a lo g In p u t tA tC D D tC 1 A tC 1 C 2 A tC 2 C 1 A R A C D S C L K 1 tC 2 A C D S C L K 2 tN A D C C L K R tS tN T L 1 V P R B G tC D 1 3 ~ D 0 V P R B G G B P R (n -4 ) R (n -4 ) G (n -4 ) G (n -4 ) B (n -4 ) B (n -4 ) R (n -3 ) R (n -3 ) G (n -3 ) G (n -3 ) B (n -3 ) B (n -3 ) R (n -2 ) R (n -2 ) D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 Note: DATA timing from pixel to pixel is decided by the first rising edge of ADCCLK when CDSCLK2 is from high to low. Mode B P ix e l n P ix e l n + 1 P ix e l n + 2 A n a lo g In p u t tA tC 1 B D tA tC 1 C 2 B D tC tC 2 C 1 B R B C D S C L K 1 tC 2 B C D S C L K 2 D 1 3 ~ D 0 D (n -1 0 ) D 1 3 ~ D 6 D (n -1 0 ) D 5 ~ D 0 D (n -9 ) D 1 3 ~ D 6 5 D (n -9 ) D 5 ~ D 0 D (n -8 ) D 1 3 ~ D 6 July 12, 2000 HT82V14 Mode C P ix e l n A n a lo g In p u t tC P ix e l n + 1 tA 1 A P ix e l n + 2 D tC R A C D S C L K 2 tN V P tS A D C C L K T L R B tC D 1 3 ~ D 0 R B G B G P B (n -4 ) B (n -4 ) R (n -3 ) R (n -3 ) G (n -3 ) G (n -3 ) B (n -3 ) B (n -3 ) R (n -2 ) R (n -2 ) G (n -2 ) G (n -2 ) B (n -2 ) B (n -2 ) D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 Mode D P ix e l n P ix e l n + 1 P ix e l n + 2 P ix e l n + 3 P ix e l n + 4 P ix e l n + 5 P ix e l n + 6 A n a lo g In p u t tA D tS T L 1 tS tC T L 1 R B C D S C L K 1 D 1 3 ~ D 0 D (n -1 0 ) D (n -1 0 ) D (n -9 ) D (n -9 ) D (n -8 ) D (n -8 ) D (n -7 ) D (n -7 ) D (n -6 ) D (n -6 ) D (n -5 ) D (n -5 ) D (n -4 ) D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 D 5 ~ D 0 D 1 3 ~ D 6 6 July 12, 2000 HT82V14 Interface Timing S D A T A A 2 R /W b tD A 1 A 0 H D 7 tD D 6 D 5 D 4 D 3 D 2 D 1 D 0 S S C L K tL tL S H C S I/O write operation timing S D A T A A 2 R /W b tD A 1 A 0 H tD D 7 S tR D 6 D 5 D 4 D 3 D 2 D 1 D 0 D V S C L K tL tL S H C S I/O read operation timing *C L K tO D tO D D 1 3 ~ D 0 tH Z tE D V O E N o te : * C L K : M o d e A ,C re fe re n c e A D C C L K M o d e B r e fe r e n c e fr o m th e v is in g e d g e o f C D S C L K 1 to th e fa llin g e d g e o f C D S C L K 2 M o d e D re fe re n c e C D S C L K 1 Digital output timing 7 July 12, 2000 HT82V14 Analog Timing Specification Symbol Parameter Min. Typ. Max. Unit tCRA 3-channel Conversion Rate ¾ 500 ¾ ns tCRB 1-channel Conversion Rate ¾ 200 ¾ ns tC1A CDSCLK1 Pulse Width ¾ 50 ¾ ns tC1B CDSCLK1 Pulse Width ¾ 50 ¾ ns tC2A CDSCLK2 Pulse Width ¾ 50 ¾ ns tC2B CDSCLK2 Pulse Width ¾ 50 ¾ ns tC2C1A CDSCLK2 Falling to CDSCLK1 Rising ¾ 85 ¾ ns tC2C1B CDSCLK2 Falling to CDSCLK1 Rising ¾ 80 ¾ ns tC1C2A CDSCLK1 Falling to CDSCLK2 Rising ¾ 20 ¾ ns tC1C2B CDSCLK1 Falling to CDSCLK2 Rising ¾ 20 ¾ ns tCP ADCCLK Period ¾ 166 ¾ ns tSTL1 3-Channel Settling Time ¾ 80 ¾ ns tAD Aperture Delay ¾ 10 ¾ ns tNVP Non-overlapping Space ¾ 5 ¾ ns Min. Typ. Max. Unit Digital Timing Specification Symbol Parameter Data Output tOD Output Delay ¾ 25 ¾ ns tEDV 3-state to Data Valid 15 ¾ ¾ ns tHZ Output Enable High to 3-state 5 ¾ ¾ ns Latency ¾ 9 ¾ ADCCLK Cycles Interface Timing tDS Data Setup Time ¾ 5 ¾ ns tDH Data Hold Time ¾ 5 ¾ ns tLS Enable Setup Time ¾ 5 ¾ ns tLH Enable Hold Time ¾ 5 ¾ ns tRDV Read Data Valid Time ¾ 3 ¾ ns 8 July 12, 2000 HT82V14 Register Overview A2 A1 A0 0 0 0 Configuration Register Register 0 0 1 Red Gain Register 0 1 0 Green Gain Register 0 1 1 Blue Gain Register 1 0 0 Red Offset Register 1 0 1 Green Offset Register 1 1 0 Blue Offset Register 1 1 1 Color Index Register · Configuration register Bit Function 7 Sensor mode 6 Sensor mode 5 Clamp mode 4 Clamp mode 3 External VREF 2 Channel mode 1 Channel mode 0 External CIS reference · Description of configuration register 7 6 Mode Function 0 0 CDS For CCD 0 1 CIS For CIS dark reference: 1.4V 1 0 SHA For CIS dark reference: 0V 1 1 Reserved 5 4 Mode 0 0 Reserved 0 1 Pixel Clamp For CDS pixel-by-pixel clamp 1 0 No Clamp For CDS reset reference<5V 1 1 Reserved 2 1 Mode 0 0 0 3-channel pixel-rate mux 0 1 1 1-channel for internal define Function Function 9 July 12, 2000 HT82V14 Gain registers for R, G and B Bit Function 7 MSB of Coarse Gain (VGA) 6 LSB of Coarse Gain (VGA) 5 Reserved 4 MSB of Fine Gain (PGA) 3 2 1 0 LSB of Fine Gain (PGA) Note: VGA: Variable Gain Amplifier, formula: gain=1+ x where x=0~3 1.5 PGA: Programmable Gain Amplifier (PGA): specifies R, G, B sequence by color index register, x where x=0~31 formula: gain=1+ 31 Offset registers for R, G and B Bit 7 Function MSB of Offset word 6 5 4 3 2 1 0 LSB of Offset word Note: Offset range from -200mV to +200mV, 8-bit, 256 levels; (00.....0) equal to -200mV, (100.....0) equal to 0mV, and (11.....1) equal to +198.4mV. Color index register Bit7 Reserved Bit6 Reserved Bit5 Reserve Bit4 Index for 3 channel mode Bit3 Index for 3 channel mode Bit2 Index for 3 channel mode Bit1 Index for 1 channel mode Bit0 Index for 1 channel mode 10 July 12, 2000 HT82V14 · Truth table for 1 channel index mode Bit1 Bit0 0 0 R channel 0 1 G channel 1 0 B channel 1 1 Reserved · Truth table for 3 channel index mode Bit4 Bit3 Bit2 0 0 0 0 0 1 R®B®G 0 1 0 G®R®B G®B®R R®G®B 0 1 1 1 0 0 B®R®G 1 0 1 B®G®R 1 1 0 Reserved 1 1 1 Reserved Application Circuits 1 2 3 C D S C L K 1 A V D D C D S C L K 2 A V S S R IN A D C C L K 4 O F F S E T O E 5 0 .1 m F 6 7 8 9 1 0 1 1 1 2 1 3 1 4 D R V D D G IN D R V S S C M L D 1 3 /D 5 B IN D 1 2 /D 4 R E F T D 1 1 /D 3 R E F D 1 0 /D 2 A V S S D 9 /D 1 A V D D D 8 /D 0 S L O A D D 7 S C L K D 6 S D A T A 0 .1 m F 2 8 2 7 0 .1 m F 2 6 2 5 2 4 0 .1 m F 2 2 0 .1 m F 2 3 0 .1 m F 2 1 0 .1 m F 2 0 1 9 1 8 1 7 1 0 m F 0 .1 m F 0 .1 m F 0 .1 m F 1 6 1 5 H T 8 2 V 1 4 Note: Decoupling capacitor of RIN, GIN, BIN may change its value from 300pF to 0.1mF depending on the system environment. 11 July 12, 2000 HT82V14 Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. 12 July 12, 2000