SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • • • Latchable P-Input Ports With Power-Up Clear Choice of Logical or Arithmetic (Two’s Complement) Comparison Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects Approximately 35% Improvement in ac Performance Over Schottky TTL While Performing More Functions Cascadable to n Bits While Maintaining High Performance 10% Less Power Than STTL for an 8-Bit Comparison Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs SN54AS885 . . . JT PACKAGE SN74AS885 . . . DW OR NT PACKAGE (TOP VIEW) L/A P < QIN P > QIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 GND 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC PLE P7 P6 P5 P4 P3 P2 P1 P0 P < QOUT P > QOUT SN54AS885 . . . FK PACKAGE (TOP VIEW) P > QIN P < QIN L/A NC VCC PLE P7 description 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 4 Q7 Q6 Q5 NC Q4 Q3 Q2 19 11 12 13 14 15 16 17 18 P6 P5 P4 NC P3 P2 P1 Q1 Q0 GND NC P > QOUT P < QOUT P0 These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two’s complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information. 1 NC – No internal connection The latch is transparent when P latch-enable (PLE) input is high; the P-input port is latched when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE, P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically – 0.25 mA, which minimizes dc loading effects. The SN54AS885 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AS885 is characterized for operation from 0°C to 70°C. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 FUNCTION TABLE INPUTS OUTPUTS L/A DATA P0 – P7, Q0 – Q7 P > QIN P < QIN P > QOUT Logical H P>Q X X H L Logical Logical† H P<Q X X L H H P=Q H or L H or L H or L H or L Arithmetic L P AG Q X X H L Arithmetic Arithmetic† L Q AG P X X L H COMPARISON P < QOUT L P=Q H or L H or L H or L H or L † In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN. AG = arithmetically greater than logic symbol‡ L/A PLE P0 P1 P2 P3 P4 P5 P6 P7 P > QIN P < QIN Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 23 15 COMP M [LOGIC] M [ARITH, 2s COMP] C1 1D 1=0 0 16 17 18 19 P 20 21 P>Q 22 3 2 11 7 P<Q > < 0 10 9 8 7 Q 6 5 4 7 ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 14 P > QOUT P < QOUT SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 logic diagram (positive logic) PLE P7 P6 P5 23 P7 = Q7 C1 P7 22 1D P6 = Q6 P7 21 P6 20 P6 P5 P5 = Q5 P5 P4 P3 P2 19 P4 18 P4 P3 17 P3 P2 P3 = Q3 P2 = Q2 P1 = Q1 14 P < QOUT P2 P1 P0 16 P1 15 P1 P0 P0 = Q0 P0 Q7 Q6 4 Q7 5 Q7 Q6 Q5 6 Q4 7 Q3 8 Q2 9 Q1 10 Q0 11 P > QIN 3 P < QIN 2 1 L/A Q6 Q5 13 P > QOUT Q5 Q4 Q4 Q3 Q3 Q2 4MSB = Q2 Q1 Q1 Q0 Q0 ARITH LOGIC Pin numbers shown are for the DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS885 SN74AS885 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL tsu* Low-level output current 20 20 mA th* TA Hold time, data after PLE↓ High-level input voltage 2 Setup time, data before PLE↓ Operating free-air temperature 2 V V 2 2 ns 4.5 4 ns – 55 125 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54AS885 TYP‡ MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 20 mA VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5.5 V, VI = 0.4 V IIH L/A Others – 1.2 VCC – 2 L/A IIL P > QIN, P < QIN SN74AS885 TYP‡ MAX MIN P, Q, PLE – 1.2 VCC – 2 0.35 0.5 UNIT V V 0.5 V 0.1 0.35 0.1 mA 40 40 20 20 –4 –4 –2 –2 –1 –1 µA mA IO§ VCC = 5.5 V, VO = 2.25 V – 20 – 112 – 20 – 112 mA ICC VCC = 5.5 V, See Note 1 130 210 130 210 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with all inputs high except L/A, which is low. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 switching characteristics (see Figure 3) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX SN54AS885 SN74AS885 MIN TYP† MAX MIN TYP† MAX PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL P<Q QOUT,, P > QOUT 2 8.5 14 1 8.5 13 L/A 2 7.5 14 1 7.5 13 tPLH tPHL P < QIN,, P > QIN P<Q QOUT,, P > QOUT 2 5 10 1 5 8 2 5.5 10 1 5.5 8 tPLH tPHL Anyy P or Q data input P<Q QOUT,, P > QOUT 2 13.5 21 1 13.5 17.5 2 10 17 1 10 15 UNIT ns ns ns † All typical values are at VCC = 5 V, TA = 25°C. APPLICATION INFORMATION The ′AS885 can be cascaded to compare words longer than eight bits. Figure 1 shows the comparison of two 32-bit words; however, the design is expandable to n bits. Figure 1 shows the optimum cascading arrangement for comparing words of 32 bits or greater. Typical delay times shown are at VCC = 5 V, TA = 25°C and use the standard advanced Schottky load of RL = 500 Ω, CL = 50 pF. Figure 2 shows the fastest cascading arrangement for comparing 16-bit or 24-bit words. Typical delay times shown are at VCC = 5 V, TA = 25°C and use the standard advanced Schottky load of RL = 500 Ω, CL= 50 pF. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 APPLICATION INFORMATION PLE L/A H or L 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 20 P5 21 P6 22 P7 P > QIN 3 P < QIN 2 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 Q7 ′AS885 13 P > QOUT 14 P < QOUT L/A PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 20 P5 21 P6 22 P7 P > QIN 3 P < QIN 2 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 Q7 H or L L/A H or L 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 20 P5 21 P6 22 P7 P > QIN 3 P < QIN 2 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 Q7 1 ′AS885 ′AS885 PLE 13 P > QOUT 14 P < QOUT H or L 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 20 P5 21 P6 22 P7 P > QIN 3 P < QIN 2 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 H or L Q7 ′AS885 18 P3 19 P4 20 P5 21 P6 P7 22 P > QIN 3 P < QIN 2 Q0 11 Q1 10 Q2 9 8 Q3 7 Q4 6 Q5 5 Q6 Q7 4 13 P > QOUT 14 P < QOUT 4 13.5 ns Typical 13.5 ns Typical Figure 1. 32-Bit to 72 (n)-Bit Magnitude Comparator 6 ′AS885 PLE 23 P0 15 P1 16 P2 17 13 P > QOUT 14 P < QOUT L/A L/A 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 P > QOUT 14 P < QOUT P > QOUT P < QOUT SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 APPLICATION INFORMATION Latch Enable L/A H or L 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 P5 20 21 P6 22 P7 P > QIN 3 P < QIN 2 11 LSB Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 Q7 ′AS885 L/A 13 P > QOUT P < QOUT 14 ′AS885 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 P5 20 21 P6 22 P7 P > QIN 3 P < QIN 2 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 Q7 L/A ′AS885 1 PLE 23 15 P0 16 P1 17 P2 18 P3 19 P4 P5 20 21 P6 22 P7 13 MSB P > QIN 3 P > QOUT P < QIN 2 P < QOUT 14 11 Q0 10 Q1 9 Q2 8 Q3 7 Q4 6 Q5 5 Q6 4 MSB Q7 13 P > QOUT P < QOUT 14 LSP MSP 16 Bit 19 ns Typical 24 Bit 24.4 ns Typical Figure 2. Fastest Cascading Arrangement for Comparing 16-Bit or 24-Bit Words POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54AS885, SN74AS885 8-BIT MAGNITUDE COMPARATORS SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 3. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-89757013A ACTIVE LCCC FK 28 1 TBD 5962-8975701KA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type 5962-8975701LA ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type SN54AS885JT ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type SN74AS885DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AS885NT ACTIVE PDIP NT 24 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74AS885NT3 OBSOLETE PDIP NT 24 TBD Call TI SN74AS885NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU SNJ54AS885FK ACTIVE LCCC FK 28 1 TBD SNJ54AS885JT ACTIVE CDIP JT 24 1 TBD A42 SNPB N / A for Pkg Type SNJ54AS885W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type 15 POST-PLATE N / A for Pkg Type Call TI N / A for Pkg Type POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 10-May-2007 incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2007 TAPE AND REEL BOX INFORMATION Device SN74AS885DWR Package Pins DW 24 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) SITE 60 330 24 10.75 15.7 2.7 12 Pack Materials-Page 1 W Pin1 (mm) Quadrant 24 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74AS885DWR DW 24 SITE 60 346.0 346.0 0.0 Pack Materials-Page 2 MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI004 – OCTOBER 1994 NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN PINS ** A 24 28 A MAX 1.260 (32,04) 1.425 (36,20) A MIN 1.230 (31,24) 1.385 (35,18) B MAX 0.310 (7,87) 0.315 (8,00) B MIN 0.290 (7,37) 0.295 (7,49) DIM 24 13 0.280 (7,11) 0.250 (6,35) 1 12 0.070 (1,78) MAX B 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°– 15° 0.010 (0,25) M 0.010 (0,25) NOM 4040050 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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