www.DataSheet4U.com SN74AHC32Q-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SGDS019 – FEBRUARY 2002 D D D D D D D D OR PW PACKAGE (TOP VIEW) Qualification in Accordance With AEC-Q100† Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y † Contact factory for details. Q100 qualification data available on request. description The SN74AHC32Q is a quadruple 2-input positive-OR gate. This device performs the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION –40°C 40°C to 125°C ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING SOIC – D Tape and reel SN74AHC32QDRQ1 AHC32Q TSSOP – PW Tape and reel SN74AHC32QPWRQ1 HA32Q ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS B OUTPUT Y H X H X H H L L L A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74AHC32Q-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SGDS019 – FEBRUARY 2002 logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 ≥1 3 2 1Y 4 6 5 2Y 9 8 10 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74AHC32Q-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SGDS019 – FEBRUARY 2002 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 3 V VCC = 5.5 V MIN MAX 2 5.5 UNIT V 1.5 V 2.1 3.85 VCC = 2 V VCC = 3 V 0.5 VIL Low-level input voltage VI VO Input voltage 0 5.5 V Output voltage 0 VCC –50 V IOH High-level output current 0.9 VCC = 5.5 V IOL ∆t/∆v 1.65 VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V Low-level output current Input transition rise or fall rate V –4 –8 VCC = 2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 50 VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V 100 4 8 20 mA mA mA mA ns/V TA Operating free-air temperature –40 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 mA MIN 2V 1.9 2 1.9 2.9 3V 2.9 3 4.4 4.5 IOH = –4 mA 3V 2.58 2.48 IOH = –8 mA 4.5 V 3.94 3.8 IOL = 50 mA VOL IOL = 4 mA Ci TA = 25°C TYP MAX 4.5 V VOH II ICC MIN VCC IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VI = VCC or GND IO = 0 4.4 UNIT V 2V 0.1 0.1 3V 0.1 0.1 4.5 V 0.1 0.1 3V 0.36 0.5 4.5 V 0.36 0.5 0 V to 5.5 V ±0.1 ±1 mA 2 20 mA 5.5 V 5V POST OFFICE BOX 655303 MAX • DALLAS, TEXAS 75265 2 10 V pF 3 SN74AHC32Q-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SGDS019 – FEBRUARY 2002 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF MIN TA = 25°C TYP MAX MIN MAX 5.5 7.9 1 9.5 5.5 7.9 1 9.5 8 11.4 1 13 8 11.4 1 13 UNIT ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A or B Y CL = 15 pF tPLH tPHL A or B Y CL = 50 pF TA = 25°C MIN TYP MAX MIN MAX 3.8 5.5 1 6.5 3.8 5.5 1 6.5 5.3 7.5 1 8.5 5.3 7.5 1 8.5 MIN TYP MAX UNIT ns ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 0.8 V Quiet output, minimum dynamic VOL –0.3 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 4.7 High-level dynamic input voltage V 3.5 VIL(D) Low-level dynamic input voltage NOTE 4: Characteristics are for surface-mount packages only. V 1.5 V TYP UNIT operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz 14 pF SN74AHC32Q-Q1 QUADRUPLE 2-INPUT POSITIVE-OR GATE SGDS019 – FEBRUARY 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AHC32QDRQ1 ACTIVE SOIC D 14 2500 SN74AHC32QPWRQ1 ACTIVE TSSOP PW 14 2000 Lead/Ball Finish MSL Peak Temp (3) Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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