TI SN74VMEH22501AZQLR

SCES620 – DECEMBER 2004
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DGG OR DGV PACKAGE
(TOP VIEW)
Widebus  Family
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Modes
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
(EMI)
Compliant With VME64, 2eVME, and 2eSST
Protocols
Bus Transceiver Split LVTTL Port Provides
Feedback Path for Control and Diagnostics
Monitoring
I/O Interfaces Are 5-V Tolerant
B-Port Outputs (−48 mA/64 mA)
Y and A-Port Outputs (−12 mA/12 mA)
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
Bus Hold on 3A-Port Data Inputs
26-W Equivalent Series Resistor on
3A Ports and Y Outputs
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
1OEBY
1A
1Y
GND
2A
2Y
VCC
2OEBY
3A1
GND
LE
3A2
3A3
OE
GND
3A4
CLKBA
VCC
3A5
3A6
GND
3A7
3A8
DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OEAB
VCC
1B
GND
BIAS VCC
2B
VCC
2OEAB
3B1
GND
VCC
3B2
3B3
VCC
GND
3B4
CLKAB
VCC
3B5
3B6
GND
3B7
3B8
VCC
description/ordering information
ORDERING INFORMATION
PACKAGE†
TA
−40°C
85°C
−40
C to 85
C
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
TSSOP − DGG
Tape and reel
SN74VMEH22501ADGGR
VMEH22501A
TVSOP − DGV
Tape and reel
SN74VMEH22501ADGVR
VK501A
VFBGA − GQL
Tape and reel
SN74VMEH22501AGQLR
VK501A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Motorola is a trademark of Motorola, Inc.
OEC, UBT, and Widebus are trademarks of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
POST OFFICE BOX 655303
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1
SCES620 – DECEMBER 2004
description/ordering information (continued)
The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and
is designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched,
and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide
a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between
cards operating at LVTTL logic levels and VME64, VME64x, or VME320† backplane topologies.
The SN74VMEH22501A is pin-for-pin capatible to the VMEH22501, but operates at a wider operating
temperature (−40°C to 85°C) range.
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been
designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large
capacitive loads and include pseudo-ETL input thresholds (1/2 VCC ±50 mV) for increased noise immunity.
These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in
VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on
linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which
prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied
to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
† VME320 is a patented backplane construction by Arizona Digital, Inc.
GQL PACKAGE
(TOP VIEW)
1
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1OEBY
NC
NC
NC
NC
1OEAB
B
B
1Y
1A
GND
GND
C
2Y
2A
D
D
3A1
2OEBY
VCC
GND
VCC
GND
VCC
BIAS VCC
2OEAB
1B
C
E
E
3A2
LE
F
3A3
OE
G
3A4
CLKBA
GND
H
3A5
3A6
J
3A7
3A8
VCC
GND
DIR
NC
NC
F
G
H
J
K
2
2
K
NC − No internal connection
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• DALLAS, TEXAS 75265
2B
3B1
VCC
VCC
3B2
GND
CLKAB
3B4
VCC
GND
3B6
3B5
3B8
3B7
NC
NC
VCC
3B3
SCES620 – DECEMBER 2004
functional description
The SN74VMEH22501A is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and
D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true
logic. The device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus
transceivers.
functional description for two 1-bit bus transceivers
The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active.
When OEAB is low, the B-port outputs are disabled.
Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics
monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When
OEBY is high, the Y outputs are disabled.
The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields
A data to B bus and an input low yields B data to Y bus.
1-BIT BUS TRANSCEIVER FUNCTION TABLE
INPUTS
OUTPUT
MODE
H
Z
Isolation
H
H
A data to B bus
L
L
B data to Y bus
H
L
A data to B bus, B data to Y bus
OEAB
OEBY
L
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True driver
True driver with feedback path
• DALLAS, TEXAS 75265
3
SCES620 – DECEMBER 2004
functional description for 8-bit UBT transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE
is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS
OUTPUT
OE
DIR
H
X
L
H
3A data to 3B bus
L
L
3B data to 3A bus
Z
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data
is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
UBT TRANSCEIVER FUNCTION TABLE†
INPUTS
OE
LE
H
L
OUTPUT
3B
MODE
X
Z
Isolation
X
B0‡
B0§
Latched storage of 3A data
CLKAB
3A
X
X
L
H
L
L
L
X
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
True transparent
Clocked storage of 3A data
† 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
‡ Output level before the indicated steady-state input conditions were established,
provided that CLKAB was high before LE went low
§ Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 1.
Table 1. SN74VMEH22501A UBT Transceiver Replacement Functions
FUNCTION
8 BIT
Transceiver
’245, ’623, ’645
Buffer/driver
’241, ’244, ’541
Latched transceiver
’543
Latch
’373, ’573
Registered transceiver
’646, ’652
Flip-flop
’374, ’574
SN74VMEH22501A UBT transceiver replaces all above functions
4
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• DALLAS, TEXAS 75265
SCES620 – DECEMBER 2004
logic diagram (positive logic)
48
1OEAB
1
1OEBY
2
46
1B
1A
3
1Y
2OEAB
2OEBY
41
8
43
5
2A
2B
6
2Y
OE
DIR
14
24
32
CLKAB
LE
11
17
CLKBA
9
3A1
1D
C1
CLK
40
3B1
1D
C1
CLK
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCES620 – DECEMBER 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high or low state, VO
(see Note 1): 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output current in the low state, IO: 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Output current in the high state, IO: 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC): B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 3 and 4)
VCC,
BIAS VCC
Supply voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
Input clamp current
MIN
TYP
MAX
UNIT
3.15
3.3
3.45
V
VCC
VCC
5.5
Control inputs or A port
B port
Control inputs or A port
B port
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
V
2
V
0.5 VCC + 50 mV
Control inputs or A port
IOH
5.5
0.8
B port
0.5 VCC − 50 mV
−18
3A port and Y output
−12
B port
−48
3A port and Y output
12
B port
64
Outputs enabled
10
−40
mA
mA
mA
ns/V
µs/V
20
Operating free-air temperature
V
85
°C
NOTES: 3. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable, but generally, GND is connected first.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES620 – DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range for A and B
ports (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
UNIT
−1.2
V
3A port, any B ports,
and Y outputs
VCC = 3.15 V to 3.45 V,
IOH = −100 µA
VCC−0.2
VCC = 3.15 V
IOH = −6 mA
IOH = −12 mA
2.4
3A port and Y outputs
VCC = 3.15 V
IOH = −24 mA
IOH = −48 mA
2.4
Any B port
3A port, any B ports,
and Y outputs
VCC = 3.15 V to 3.45 V,
IOL = 100 µA
0.2
VCC = 3.15 V
IOL = 6 mA
IOL = 12 mA
0.55
3A port and Y outputs
IOL = 24 mA
IOL = 48 mA
0.4
VCC = 3.15 V
II
Control inputs,
1A and 2A
VCC = 3.45 V,
VCC = 0 or 3.45 V,
IOZH‡
3A port, any B port,
and Y outputs
IBHLO#
IBHHO||
MAX
II = −18 mA
Any B port
Ioff
IBHL§
IBHH¶
TYP†
VCC = 3.15 V,
VOL
IOZL‡
MIN
2
0.8
3A port
3A port
3A port
3A port
IOZ(PU/PD)k
V
0.55
IOL = 64 mA
VI = VCC or GND
0.6
±1
VI = 5.5 V
5
VCC = 3.45 V,
VO = VCC or 5.5 V
5
VCC = 3.45 V,
VO = GND
VCC = 0, BIAS VCC = 0,
VCC = 3.15 V,
VI or VO = 0 to 5.5 V
VI = 0.8 V
VCC = 3.15 V,
VCC = 3.45 V,
−5
3A port and Y outputs
Any B port
V
2
−20
±10
µA
A
µA
µA
A
µA
75
µA
VI = 2 V
VI = 0 to VCC
−75
µA
500
µA
VCC = 3.45 V,
VI = 0 to VCC
VCC ≤ 1.3 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE = don’t care
−500
µA
±10
µA
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ For I/O ports, the parameters IOZH and IOZL include the input leakage current.
§ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND, then
raising it to VIL max.
¶ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC, then
lowering it to VIH min.
# An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k High-impedance state during power up or power down
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• DALLAS, TEXAS 75265
7
SCES620 – DECEMBER 2004
electrical characteristics over recommended operating free-air temperature range for A and B
ports (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
VCC = 3.45 V, IO = 0,
VI = VCC or GND
ICC
VCC = 3.45 V, IO = 0,
VI = VCC or GND,
One data input switching at
one-half clock frequency,
50% duty cycle
ICCD
MIN
30
Outputs low
30
Outputs disabled
30
Outputs enabled
76
Outputs disabled
19
Cio
Control inputs
2.6
1Y or 2Y outputs
VO = 3.15 V or 0
5.6
Any B port
mA
µA
2.8
VI = 3.15 V or 0
3A port
UNIT
µA/
clock
MHz/
input
750
1A and 2A inputs
Co
MAX
Outputs high
VCC = 3.15 V to 3.45 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
∆ICCh
Ci
TYP†
VCC = 3.3 V,
pF
7.9
VO = 3.3 V or 0
† All typical values are at VCC = 3.3 V, TA = 25°C.
h This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
pF
11
12.5
pF
CC or GND.
live-insertion specifications over recommended operating free-air temperature range for B port
PARAMETER
TEST CONDITIONS
ICC (BIAS VCC)
VCC = 0 to 3.15 V,
VCC = 3.15 V to 3.45 V‡,
BIAS VCC = 3.15 V to 3.45 V,
VO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V
VCC = 0
VO = 0,
VO = 3 V,
IO
BIAS VCC = 3.15 V to 3.45 V,
MIN
IO(DC) = 0
IO(DC) = 0
1.3
POST OFFICE BOX 655303
1.5
MAX
mA
10
µA
1.7
V
−20
−100
BIAS VCC = 3.15 V
20
100
• DALLAS, TEXAS 75265
UNIT
5
BIAS VCC = 3.15 V
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ VCC − 0.5 V < BIAS VCC
8
TYP†
µA
A
SCES620 – DECEMBER 2004
timing requirements over recommended operating conditions for UBT transceiver (unless
otherwise noted) (see Figures 1 and 2)
MIN
fclock
Clock frequency
tw
Pulse duration
LE high
3A before LE↓
tsu
Setup time
3B before CLK↑
3B before LE↓
3A after CLK↑
3A after LE↓
th
Hold time
3B after CLK↑
3B after LE↓
UNIT
120
MHz
2.5
ns
3
CLK high or low
3A before CLK↑
MAX
Data high
2.1
Data low
2.2
CLK high
2
CLK low
2
Data high
2.5
Data low
2.7
CLK high
2
CLK low
2
Data high
0
Data low
0
CLK high
1
CLK low
1
Data high
0
Data low
0
CLK high
1
CLK low
1
ns
ns
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
1A or 2A
1B or 2B
tPLH
tPHL
1A or 2A
1Y or 2Y
tPZH
tPZL
OEAB
1B or 2B
OEAB
1B or 2B
tPHZ
tPLZ
MIN
TYP
MAX
4.8
8.9
4.5
7.8
6.2
14.5
6.1
13
3.9
8.1
3.7
7.4
3.3
9.7
1.8
4.8
UNIT
ns
ns
ns
ns
tr
Transition time, B port (10%−90%)
4.3
ns
tf
tPLH
Transition time, B port (90%−10%)
4.3
ns
tPHL
tPZH
tPZL
tPHZ
tPLZ
1B of 2B
1Y or 2Y
OEBY
1Y or 2Y
OEBY
1Y or 2Y
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.6
5.6
1.6
5.6
1.2
5.6
1.8
4.9
0.9
5.4
1.4
4.5
ns
ns
ns
9
SCES620 – DECEMBER 2004
switching characteristics over recommended operating conditions for UBT transceiver (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tr
tf
FROM
(INPUT)
TO
(OUTPUT)
3A
3B
LE
3B
CLKAB
3B
OE
3B
OE
3B
MAX
UNIT
MHz
5.1
9.3
4.7
8.3
5.5
10.6
4.9
8.7
5.8
10.1
4.2
8.4
4.2
9.3
3.2
8.5
4.2
9.3
2.4
5.7
ns
ns
ns
ns
ns
Transition time, B port (10%−90%)
4.3
ns
Transition time, B port (90%−10%)
4.3
ns
3B
3A
tPLH
tPHL
LE
3A
tPLH
tPHL
CLKBA
3A
tPZH
tPZL
OE
3A
OE
3A
tPLZ
TYP
120
tPLH
tPHL
tPHZ
MIN
1.5
5.9
1.7
5.9
1.7
5.9
1.7
5.9
1.1
5.5
1.4
5.5
1.5
6.2
2.1
5.5
0.8
6.2
2.3
5.6
ns
ns
ns
ns
ns
skew characteristics for bus transceiver for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
1A or 2A
1B or 2B
tsk(pp)
UNIT
ns
0.7
0.7
1B or 2B
1Y or 2Y
ns
0.7
tsk(HL)
tsk(t)†
MAX
0.8
tsk(HL)
tsk(LH)
MIN
1A or 2A
1B or 2B
3.9
1B or 2B
1Y or 2Y
1.5
1A or 2A
1B or 2B
3.6
1B or 2B
1Y or 2Y
1.4
ns
ns
† tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES620 – DECEMBER 2004
skew characteristics for UBT for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
3A
3B
3B
tsk(pp)
ns
0.8
0.7
3B
3A
ns
0.6
0.7
CLKBA
3A
ns
0.6
tsk(HL)
tsk(t)†
ns
0.8
CLKAB
tsk(HL)
tsk(LH)
UNIT
1.1
tsk(HL)
tsk(LH)
MAX
1.4
tsk(HL)
tsk(LH)
MIN
3A
3B
3.9
CLKAB
3B
3.9
3B
3A
1.6
CLKBA
3A
1.2
3A
3B
3.6
CLKAB
3B
3.5
3B
3A
1.3
CLKBA
3A
1.2
ns
ns
† tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
POST OFFICE BOX 655303
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11
SCES620 – DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
A PORT
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
B-to-A Skew
Open
6V
GND
Open
LOAD CIRCUIT
tw
3V
3V
Timing
Input
1.5 V
1.5 V
Input
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
Data
Input
VCC/2
3V
VCC/2
0V
VCC/2
tPZL
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
tPZH
tPHL
VOH
1.5 V
1.5 V
0V
3V
Input
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
12
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SCES620 – DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
B PORT
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
A-to-B Skew
Open
6V
GND
Open
LOAD CIRCUIT
tw
3V
3V
Timing
Input
Input
1.5 V
1.5 V
0V
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
3V
Data
Input
1.5 V
3V
1.5 V
0V
1.5 V
tPZL
1.5 V
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
VCC/2
tPLZ
3V
VCC/2
tPZH
tPHL
VCC/2
1.5 V
0V
3V
Input
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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13
SCES620 – DECEMBER 2004
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics tables show the switching characteristics of the device into the lumped load
shown in the parameter measurement information (PMI) (see Figures 1 and 2). All logic devices currently are tested
into this type of load. However, the designer’s backplane application probably is a distributed load. For this reason,
this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3.
5V
5V
330 Ω
0.42”
330 Ω
0.42”
0.84”
0.84”
0.42”
0.42”
ZO†
Conn.
1.5”
ZO‡
470 Ω
Conn.
Conn.
1.5”
Conn.
1.5”
1.5”
Conn.
470 Ω
Conn.
1.5”
1.5”
Rcvr
Rcvr
Rcvr
Rcvr
Rcvr
Slot 2
Slot 3
Slot 19
Slot 20
Slot 21
Drvr
Slot 1
† Unloaded backplane trace natural impedence (ZO) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal.
‡ Card stub natural impedence (ZO) is 60 Ω.
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of
the device into the backplane under full and minimum loading conditions, to help the designer better understand the
performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information.
driver in slot 11, with receiver cards in all other slots (full load)
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
1A or 2A
1B or 2B
tr¶
tf¶
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
§ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
¶ All tr and tf times are taken at the first receiver.
14
POST OFFICE BOX 655303
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MIN
TYP§
MAX
5.9
8.5
5.5
8.7
UNIT
ns
9
8.6
11.4
ns
8.9
9
10.8
ns
SCES620 – DECEMBER 2004
driver in slot 11, with receiver cards in all other slots (full load) (continued)
switching characteristics over recommended operating conditions for UBT (unless otherwise
noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
3A
3B
tPLH
tPHL
LE
3B
tPLH
tPHL
CLKAB
3B
tr‡
tf‡
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
‡ All tr and tf times are taken at the first receiver.
MIN
TYP†
MAX
6.2
8.9
5.6
9
6.1
9.1
5.6
9
6.2
9.1
5.7
9
UNIT
ns
ns
ns
9
8.6
11.4
ns
8.9
9
10.8
ns
skew characteristics for bus transceiver for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
1A or 2A
1B or 2B
MIN
TYP†
MAX
UNIT
2.5
ns
3
tsk(HL)
tsk(t)§
1A or 2A
1B or 2B
tsk(pp)
1A or 2A
1B or 2B
0.5
1
ns
3.4
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
§ tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
skew characteristics for UBT for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
3A
3B
MIN
TYP†
ns
3.4
2.7
CLKAB
3B
ns
3.4
tsk(HL)
tsk(t)§
tsk(pp)
UNIT
2.4
tsk(HL)
tsk(LH)
MAX
3A
3B
1
CLKAB
3B
1
3A
3B
0.5
3.4
CLKAB
3B
0.6
3.5
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
§ tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SCES620 – DECEMBER 2004
driver in slot 1, with one receiver in slot 21 (minimum load)
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
1A or 2A
1B or 2B
tr‡
tf‡
MIN
TYP†
MAX
5.5
7.4
5.3
7.4
UNIT
ns
Transition time, B port (10%−90%)
3.9
3.4
4.4
ns
Transition time, B port (90%−10%)
3.7
3.4
4.8
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
‡ All tr and tf times are taken at the first receiver.
switching characteristics over recommended operating conditions for UBT (unless otherwise
noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
3A
3B
tPLH
tPHL
LE
3B
tPLH
tPHL
CLKAB
3B
tr‡
tf‡
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
‡ All tr and tf times are taken at the first receiver.
MIN
TYP†
MAX
5.8
7.9
5.5
7.7
5.9
8
5.5
7.8
5.9
8.1
5.5
7.7
UNIT
ns
ns
ns
3.9
3.4
4.4
ns
3.7
3.4
4.8
ns
skew characteristics for bus transceiver for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
1A or 2A
1B or 2B
TYP†
MAX
UNIT
1.7
ns
2.1
tsk(HL)
tsk(t)§
MIN
1A or 2A
1B or 2B
1
ns
tsk(pp)
1A or 2A
1B or 2B
0.2
2.1
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
§ tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES620 – DECEMBER 2004
driver in slot 1, with one receiver in slot 21 (minimum load) (continued)
skew characteristics for UBT for specific worst-case VCC and temperature within the
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
PARAMETER
tsk(LH)
FROM
(INPUT)
TO
(OUTPUT)
3A
3B
MIN
TYP†
ns
2.3
2.1
CLKAB
3B
ns
2.4
tsk(HL)
tsk(t)‡
tsk(pp)
UNIT
2
tsk(HL)
tsk(LH)
MAX
3A
3B
1
CLKAB
3B
1
3A
3B
0.2
2.5
CLKAB
3B
0.2
2.9
ns
ns
† All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
‡ tsk(t) − Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching in opposite
directions, both low to high (LH) and high to low (HL) [tsk(t)].
By simulating the performance of the device using the VME64x backplane (see Figure 3), the maximum peak current
in or out of the B-port output, as the devices switch from one logic state to another, was found to be equivalent to
driving the lumped load shown in Figure 4.
5V
165 Ω
From Output
Under Test
235 Ω
390 pF
LOAD CIRCUIT
Figure 4. Equivalent AC Peak Output-Current Lumped Load
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17
SCES620 – DECEMBER 2004
driver in slot 1, with one receiver in slot 21 (minimum load) (continued)
In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into
distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and
high-to-low (HL) values in the lumped load shown in the PMI (see Figures 1 and 2).
6.4
6.2
Time − ns
6.0
5.8
LH
5.6
HL
5.4
5.2
5.0
Full B/P Load
Minimum B/P Load
PMI Lumped Load
Figure 5
137
162
136
160
135
158
Peak I O(HL) − mA
Peak I O(LH) − mA
Characterization-laboratory data in Figures 6 and 7 show the absolute ac peak output current, with different supply
voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices’
peak ac output drive capability.
134
133
132
131
156
154
152
150
130
148
129
146
128
3.15
3.30
3.45
144
3.15
VCC − V
VCC − V
Figure 7
Figure 6
18
3.30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3.45
SCES620 – DECEMBER 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
A TO B
35
SUPPLY CURRENT
vs
FREQUENCY
B TO A
30
VCC = 3.15 V
30
VCC = 3.45 V
25
CC(Enabled) − mA
VCC = 3.3 V
VCC = 3.45 V
20
VCC = 3.3 V
20
VCC = 3.15 V
15
I
15
I
CC(Enabled) − mA
25
10
10
5
20
5
40
60
80
100
120
20
f − Switching Frequency − MHz
40
60
80
100
120
f − Switching Frequency − MHz
Figure 9
Figure 8
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19
SCES620 – DECEMBER 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
300
VOH − High-Level Output Voltage − V
VCC = 3.15 V
250
VCC = 3.3 V
200
VCC = 3.45 V
150
100
50
0
0
10
20
30
40
50
60
70
80
90
100
IOH − High-Level Output Current − mA
Figure 10. VOL vs IOL
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
VCC = 3.45 V
VOL − Low-Level Output Voltage − V
3.5
VCC = 3.3 V
3.0
2.5
VCC = 3.15 V
2.0
1.5
1.0
0.5
0.0
0
−10
−20
−30
−40
−50
−60
−70
IOL − Low-Level Output Current − mA
Figure 11. VOH vs IOH
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−80
−90
−100
SCES620 – DECEMBER 2004
VMEbus SUMMARY
In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The
data-transfer protocols used to define the VMEbus came from the Motorola VERSA bus architecture, which owed
its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined
two basic data-transfer operations – single-cycle transfers consisting of an address and a data transfer, and a block
transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using
a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The
selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The
VMEbus system data throughput was 40 Mbyte/s. Previous to the VMEbus, it was not uncommon for the backplane
buses to require elaborate calculations to determine loading and drive current for interface design. This approach
made designs difficult and caused compatibility problems among manufacturers. To make interface design easier
and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot
terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers.
In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling
the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer
(2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA)
established a task group to specify a synchronous protocol to increase data-transfer rates to 320 Mbyte/s, or more.
The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the
asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by the receiver and requires
incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster than traditional VME64
backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The
VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x
distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 Mbyte/s.
From BLT to 2eSST − A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA,
provides additional information on VMEbus and can be obtained at www.vita.com.
maximum data transfer rates
FREQUENCY (MHz)
PROTOCOL
DATA BITS
PER CYCLE
DATA TRANSFERS
PER CLOCK CYCLE
PER SYSTEM
(Mbyte/s)
BACKPLANE
CLOCK
VMEbus IEEE-1014
BLT
32
1
40
10
10
VME64
MBLT
64
1
80
10
10
VME64x
2eVME
64
2
160
10
20
1997
VME64x
2eSST
64
2-No Ack
160−320
10−20
20−40
1999
VME320
2eSST
64
2-No Ack
320−1000
20−62.5
40−125
DATE
TOPOLOGY
1981
1989
1995
applicability
Target applications for VME backplanes include industrial controls, telecommunications, simulation,
high-energy physics, office automation, and instrumentation systems.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74VMEH22501ADGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74VMEH22501ADGVRE4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74VMEH22501ADGVRG4
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74VMEH22501ADGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74VMEH22501ADGVR
ACTIVE
TVSOP
DGV
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74VMEH22501AGQLR
NRND
BGA MI
CROSTA
R JUNI
OR
GQL
56
1000
SNPB
Level-1-240C-UNLIM
SN74VMEH22501AZQLR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
19-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74VMEH22501ADGGR
DGG
48
MLA
330
24
8.6
15.8
1.8
12
24
Q1
SN74VMEH22501ADGVR
DGV
48
MLA
330
24
6.8
10.1
1.6
12
24
Q1
SN74VMEH22501AGQLR
GQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
SN74VMEH22501AZQLR
ZQL
56
HIJ
330
16
4.8
7.3
1.45
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74VMEH22501ADGGR
DGG
48
MLA
333.2
333.2
31.75
SN74VMEH22501ADGVR
DGV
48
MLA
333.2
333.2
31.75
SN74VMEH22501AGQLR
GQL
56
HIJ
346.0
346.0
33.0
SN74VMEH22501AZQLR
ZQL
56
HIJ
346.0
346.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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