HYNIX GDC21D601

GDC21D601
32-Bit RISC MCU
Ver 1.6
HDS-GDC21D601-9908 / 10
GDC21D601
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare of
human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of
safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
3
GDC21D601
TABLE OF CONTENTS
Section 1. Overview ..................................................................................................................... 8
1. General Description .............................................................................................................. 8
2. Feature................................................................................................................................ 10
3. Package .............................................................................................................................. 12
4. Pin Assignment ................................................................................................................... 13
5. Pin Descriptions .................................................................................................................. 15
Section 2. System Architecture ................................................................................................ 20
1. Internal Bus Architecture..................................................................................................... 20
2. Arbiter ................................................................................................................................. 20
3. System Decoder ................................................................................................................. 21
4. Memory Map ....................................................................................................................... 21
5. Memory Format................................................................................................................... 22
6. Boot Mode........................................................................................................................... 22
7. Multi-Function Pin ............................................................................................................... 23
Section 3. ARM720T Core.......................................................................................................... 24
1. General Description ............................................................................................................ 24
2. Feature................................................................................................................................ 24
3. Core Block Diagram............................................................................................................ 26
Section 4. DRAM Controller ...................................................................................................... 27
1. General Description ............................................................................................................ 27
2. Hardware Interface and Signal Description ........................................................................ 28
3. Functional Description ........................................................................................................ 31
4. Register Description............................................................................................................ 34
Section 5. On-Chip SRAM ......................................................................................................... 37
1. General Description ............................................................................................................ 37
2. Signal Description ............................................................................................................... 37
3. Function Description ........................................................................................................... 37
Section 6. Static Memory Controller ........................................................................................ 38
1. General Description ............................................................................................................ 38
2. Signal Description ............................................................................................................... 39
3. Functional Description ........................................................................................................ 43
4. Programmer’ s Model.......................................................................................................... 45
4
GDC21D601
Section 7. MCU Controller......................................................................................................... 48
1. General Description ............................................................................................................ 48
2. Signal Description ............................................................................................................... 48
3. Register Description............................................................................................................ 49
Section 8. Power Management Unit ......................................................................................... 54
1. General Description ............................................................................................................ 54
2. Hardware Interface and Signal Description ........................................................................ 55
3. Operation Modes ................................................................................................................ 56
4. Register Description............................................................................................................ 58
5. Power Management Unit Register Map .............................................................................. 63
6. Test Mode Guide for MCU .................................................................................................. 64
7. Signal Timing Diagram........................................................................................................ 66
Section 9. Watchdog Timer....................................................................................................... 68
1. General Description ............................................................................................................ 68
2. Hardware Interface and Signal Description ........................................................................ 69
3. Watchdog Timer Introduction ............................................................................................. 71
4. Watchdog Timer Operation ................................................................................................ 72
5. Watchdog Timer Memory Map ........................................................................................... 74
6. Watchdog Timer Register Descriptions .............................................................................. 75
7. Examples of Register Setting.............................................................................................. 77
Section 10. Interrupt Controller ................................................................................................ 81
1. General Description ............................................................................................................ 81
2. Hardware Interface and Signal Description ........................................................................ 82
3. Interrupt Controller .............................................................................................................. 84
4. Interrupt Controller Memory Map ........................................................................................ 86
5. Interrupt Controller Register Descriptions........................................................................... 87
Section 11. Real Time Clock ..................................................................................................... 91
1. General Description ............................................................................................................ 91
2. Signal Description ............................................................................................................... 92
3. Hardware Interface ............................................................................................................. 93
4. Functional Description ........................................................................................................ 94
5. Real Time Clock Memory Map ........................................................................................... 95
6. Real Time Clock Register Descriptions .............................................................................. 95
5
GDC21D601
Section 12. General Purpose Timer Unit ................................................................................. 96
1. General Description ............................................................................................................ 96
2. Hardware Interface and Signal Description ........................................................................ 97
3. General Purpose Timer Unit Introduction ......................................................................... 100
4. General Purpose Timer Unit Operation ............................................................................ 101
5. General Purpose Timer Unit Memory Map ....................................................................... 102
6. General Purpose Timer Unit Register Descriptions.......................................................... 104
7. Examples of Register Setting............................................................................................ 108
Section 13. PIO ......................................................................................................................... 111
1. General Description .......................................................................................................... 111
2. Signal Description ............................................................................................................. 112
3. Hardware Interface ........................................................................................................... 115
4. Functional Description ...................................................................................................... 116
5. Programmer’ s Model........................................................................................................ 117
Section 14. Synchronous Serial Peripheral Interface........................................................... 118
1. General Description .......................................................................................................... 118
2. Signal Description ............................................................................................................. 119
3. Hardware Interface ........................................................................................................... 120
4. Functional Description ...................................................................................................... 121
5. Register Memory Map....................................................................................................... 123
6. SSPI Data Clock Timing Diagram..................................................................................... 124
Section 15. UART ..................................................................................................................... 125
1. General Description .......................................................................................................... 125
2. Features............................................................................................................................ 125
3. Signal Description ............................................................................................................. 126
4. Internal Block Diagram...................................................................................................... 129
5. Registers Description........................................................................................................ 130
Section 16. Smart Card Interface............................................................................................ 142
1. General Description .......................................................................................................... 142
2. Signal Description ............................................................................................................. 143
3. Hardware Interface ........................................................................................................... 144
4. Functional Description ...................................................................................................... 145
5. Programmer’ s Model........................................................................................................ 146
6
GDC21D601
2
Section 17. I C Controller ........................................................................................................ 149
1. General Description .......................................................................................................... 149
2
2. I C Controller Key Features .............................................................................................. 150
2
3. I C Controller Clocking and Pin Functions........................................................................ 150
2
4. I C Master Mode Transmit / Receive Process.................................................................. 150
2
5. I C Restart Capability (Combined Mode) .......................................................................... 151
2
6. I C Controller Programming Model ................................................................................... 152
2
7. I C Module Signal Description .......................................................................................... 154
8. Hardware Interface ........................................................................................................... 155
9. Register Memory Map....................................................................................................... 156
Section 18. Direct Memory Access Controller ...................................................................... 157
1. General Description .......................................................................................................... 157
2. Signal Description ............................................................................................................. 158
3. Programmer’ s Model........................................................................................................ 159
4. Address Modes ................................................................................................................. 163
Section 19. Debug and Test Interface .................................................................................... 167
1. General Description .......................................................................................................... 167
2. Software Development Debug and Test Interface............................................................ 167
3. Test Access Port and Boundary Scan .............................................................................. 167
Section 20. Electrical Ratings ................................................................................................. 169
1. Absolute Maximum Ratings .............................................................................................. 169
2. Thermal Characteristics.................................................................................................... 169
3. D.C Electrical Characteristics ........................................................................................... 169
APENDIX A. Register Map ....................................................................................................... 170
7
GDC21D601
GDC21D601
32-Bit RISC MCU
Section 1. Overview
1. General Description
The GDC21D601 is the HME’s 32bit high performance microcontroller unit (MCU). The GDC21D601 contains
ARM720T, which is a general-purpose 32bit microprocessor, and extensive peripherals: 6 channel 16bit Timer,
Watch Dog Timer, 2 channel UART, 2 channel SSPI, 3 channel I2C, Programmable Priority Interrupt Controller,
10 port PIO, 2 channel DMA Controller, External Memory Controller and BUS Controller including chip select
logic.
ARM720T is a 32bit Microprocessor with the CPU of the ARM7TDMI, 8KB Cache, enlarged write buffer and
Memory Management Unit (MMU). The ARM720T is fully software compatible with the ARM processor family.
GDC21D601
JTAG[0:4]
JTAG
RESET
ASB
32-bit
ARM 720T
Core
EXPRDY
EXPCLK
RTC
RTCin/Out (32.768kHz)
Timer
PORT B[0:7] / Timer TCIO / PWM
PORT C[0:3] / Timer TCIO / PWM
TCLK A,B,C / PORT C[4:6]
UART
UART channel 0 , 1
SMART Card / UART channel 2
( PORT D[0:7] ,PORT E[0:4] )
Mode[0:2]
DRAM OE, WE
WR[0:3], RD
RD&WR
AMBA Logic
BCLKOUT / PORT F[5]
BWAIT / PORT F[4]
APB Bridge
A[0:31]
D[0:31]
nCS[0:3]
nCS[4:7] / PORT H[4:7]
RAS[0:1] / PORT G[6:7]
CAS[0:3] / PORT G[0:3]
DREQ[0:1] / PORT G[2:3]
DACK[0:1] / PORT G[4:5]
Bus
controller
MCU
controller
I2C
controller
SSPI
SSPI 0, 1
( PORT E[5:7], PORT F[0:4] )
PIO
PORT I[0:7]
PORTJ[0:7]
PMU
NPDM
DRAM
controller
Internal
SRAM
(8KB)
DMA
controller
I2C channel 0
I2C channel 1
I2C channel 2
APB
IRQ[0:5] / PORT A[0:5]
INT
controller
WDT
Figure. 1 GDC21D601 Block Diagram
8
WDTOUT
GDC21D601
The general descriptions of the GDC21D601 like following :
• On-Chip Modular Architecture (using AMBA)
• Utilizes the ARM720T(“ARM7TDMI with 8Kbyte Cache and MMU”) 32bit RISC Family
• 8Kbyte internal SRAM
• support 8bit/16bit/32bit external Data bus width
• Eight Programmable Chip Select Outputs with EXPRDY
• Support Little and Big Endian memory format
• Low Power Consumption using Power Management Unit
• Fully static operation : Max. 80MHz
• Two 32bit DMA Controllers (External request only)
• Programmable Priority Interrupt Controller (6 external sources)
• Two DRAM Banks Support
• Six 16bit Multi Function Timers / Counters for General Purpose Applications
• One 8bit Watch Dog Timer (WDT)
• Real Time Clock : 32.768 KHz
• Three UARTs (Universal Asynchronous Receiver Transmitter) compatible with 16C550 UART, one
UART with Smart card interface
• Two SSPIs (Synchronous Serial Peripheral Interface) with FIFO
• Three I2C Master/Slave Controllers
• Programmable Input/Output (8bit 10 channel)
• 208 MQFP Package
9
GDC21D601
2. Feature
• ARM720T Core
- This is an ARM7TDMI CPU core with
. 8KB cache
. enlarged write buffer
. MMU(Memory Management Unit)
. On-chip ICEbreaker debug support
. 32-bit x 8 hardware multiplier
. Thumb decompressor
. High-performance 32-bit RISC architecture
. High-density 16-bit insturction set
Enhanced ARM software toolkit
THUMB code is able to provide up to 65% of
the code size of ARM, and 160% of the
performance of an equivalent ARM processor
connected to a 16-bit memory system.
The MMU supports 4G bytes Virtual address.
The allocation of virtual addresses with
different task ID improves performance in task
switching operations with the cache enabled.
• DMA Controller
- Two Channels with identical function
- Four Gigabytes of address space
- 256 Kbytes transfers to the maximum
- Data Transfer unit : Byte, Half-word, Word
- Two kinds of Bus mode
. Burst mode
. Exception mode(Cycle steal)
- Two kinds of address mode
. Single address mode
. Dual address mode
- Two types of Transfer request source
. External I/O request
. Auto-request
- Two kind of fixed priority for channels
- Interrupted when the data transfers are
complete
• DRAM Controller
- DRAM access
- Support Word, Half-word, and Byte transaction
- CBR refresh in normal operation and self-refresh
in power-down mode
- Support programmable refresh rate
- Support various DRAM access time by setting
the wait count control register
10
• Static Memory Controller
- Chip Select up to 8 (Each Bank is 256 MByte)
- Exchangeable Chip Select Active High/Low
(CS6 and CS7 only)
- Little-Endian and Big-Endian Memory Support
- Programmable wait-state (up to 16 wait-state)
- Support External BUS Ready Strobe
- Support various type Bus Control timing
- Support Word, Half-word, and Byte transaction
• On-Chip SRAM
- 8k Bytes(2048x32)
- Asynchronous SRAM
- Can write 8/16/32bits data, and read 32bits data
• MCU Controller
- The Memory Map Structure Control signals
- DRAM Power-Down Request and Powr-Down
Ack signal
- Generate the Multi Function Pin control signals
- Device Code : $GDC601
• Power Management Unit
- Power On Reset, WD_OF Reset, and S/W Reset
- Status : RESET, Power Down, RUN_FAST,
RUN_SLOW
- Provide separated clock for each modules on
chip
- Provide BCLKOUT, WD_OF, Power-Down pins
for external devices
• Watch Dog Timer
- Watchdog timer mode & interval timer mode
- Eight counter clock sources
- Generate the Power Down reset or the Watch
Dog Overflow
• Interrupt Controller
- Asynchronous interrupt controller
- Six external interrupt
- Twenty internal interrupt
- Level or edge triggered
- Mask for each interrupt source
Request of IRQ, FIQ for each interrupt source
GDC21D601
• Real Time Clock
- 32bit counter clocked by a 32.768KHz clock.
- 32bit match register
• Programmable Input Output
- up to 80 pin (8bit 10channel)
- Each pin can be configurable as either input or
output
• Timer
- 6 channel 16-bit up-count
- 4-internal pre-scaleable , 4-external input clock
. 1 interrupt per 1 channel
. 2 inout pin per 1 channel for input capture or
output compare
- Basic function :
. Compare match waveform output
. Input capture
. Match clear
. Capture clear
- Synchronous mode
. Synch. clear at two or more channel
. Synch. write at two or more channel
- PWM waveform output mode
• Synchronous Serial Interface
- Supports full duplex communication
- Sends and receives data continuously, using 16 x
8 bit FIFOs
- Built-in baud rate generator capable of
generation 4 clock rate
- Selectable clock source : either built-in buad-rate
generator or external clock
- 4 independent interrupts : transmit-end, rx-full,
tx-empty and tx-full
• UART
- 2 channel : UART only
. Compatible with 16550
. 16 byte each FIFO for TX / RX
. Start, stop and parity bit can be added or
deleted from/to serial data
. MODEM control functions (CTS, RTS, DSR,
DTR, RI and DCD )
. Fully programmable serial-interface
characteristics
: 5-, 6-, 7- or 8-bit characters
: even, odd or no-parity bit generation and
detection
: 1-, 1.5- or 2-stop bit generation and
detection
• SmartCard Interface
- 1 channel : Support SmartCard Interface
. Supports only asynchronous operation
. Supports cards that have internal reset
capability
. Supports cards that have an active low reset
input
. Supports cards that use the internal clock
. Generate the clock for a card expecting the
external clock
. Use the serial in/out ports for I/O
. Use the PIO ports for other interface signals
like RST, DETECT, etc
•I C
- 3 channels
- Master / Slave function
- Programmable clock speed
- 8bit data transfer
- Slave clock stretch support
- Maskable interrupt
- Support clock rates up to 1.84MHz Baud
2
11
GDC21D601
HME ARM
32bit MCU
GDC21D601R1
(Top View)
9921
Rev. ES
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
3. Package
Figure 2. Package Outline
12
GDC21D601
4. Pin Assignment
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NAME
A0
A1
VDD
A2
A3
A4
VSS
A5
A6
A7
VDD
A8
A9
A10
VSS
A11
A12
VDD
A13
A14
A15
VSS
A16
A17
A18
VDD
A19
A20
A21
VSS
A22
A23
WDTOUT
NPDN
VSS
RTCOSCIN
RTCOSCOUT
VDD
NTRST
TDI
TCK
VSS
TDO
TMS
PIN
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
NAME
IRQ0/PA0
VDD
IRQ1/PA1
IRQ2/PA2
IRQ3/PA3
VSS
IRQ4/PA4
IRQ5/PA5
PA6
PA7
TCIOA0/PB0
VDD
TCIOB0/PB1
TCIOA1/PB2
TCIOB1/PB3
VSS
TCIOA2/PB4
TCIOB2/PB5
TCIOA3/PB6
VDD
TCIOB3/PB7
PC0/TCIOA4
PC1/TCIOB4
VSS
PC2/TCIOA5
PC3/TCIOB5
PC4/TCLKA
VDD
PC5/TCLKB
PC6/TCLKC
PC7/TCLKD
RXD0/PD0
VSS
TXD0/PD1
RXD1/ PD2
TXD1/PD3
VDD
NCTS/ PD4
NDSR/ PD5
NDCD/ PD6
VSS
NRI/ PD7
NDTR/PE0
NRTS/PE1
PIN
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
NAME
VDD
SMDI/PE2
SMDO/PE3
SMCLK/PE4
VSS
SIN0/ PE5
PIN
133
134
135
136
137
138
SOUT0/PE6
139
SCLK0/PE7
140
VDD
141
SCS0/PF0/MemByte0 142
SIN1/PF1/MemByte1 143
SOUT1/PF2
144
VSS
145
SCLK1/PF3
146
SCS1/PF4
147
BCLKOUT/PF5
148
NFIQOUT/PF6
149
NIRQOUT/PF7
150
VDD
151
I2CSDA0
152
I2CSCL0
153
I2CSDA1
154
VSS
155
I2CSCL1
156
I2CSDA2
157
I2CSCL2
158
VDD
159
Mode0/TREQA
160
Mode1/TREQB
161
Mode2/TACK
162
VSS
163
UCLKOUT
164
UCLKIN
165
VDD
166
TEST
167
NEXTREQ/PG0
168
NRESET
169
VSS
170
NEXTACK/PG1 171
NDREQ0/PG2
172
NDACK0/PG3
173
VDD
174
NDREQ1/PG4
175
NDACK1/PG5
176
NAME
NRAS0/PG6
VSS
NRAS1/PG7
NCAS0/PH0
NCAS1/PH1
NCAS2/PH2
NCAS3/PH3
VSS
XOUT
XIN
VDD
NDRAMOE
NDRAMWE
VSS
NWR0
NWR1
NWR2
VDD
NWR3
NRD
RDNWR
VSS
NEXPRDY
EXPCLK
NCS0
NCS1
NCS2
VDD
NCS3
NCS4/PH4
NCS5/PH5
VSS
CS6/PH6
CS7/PH7
D31/PJ7
VDD
D30/PJ6
D29/PJ5
D28/PJ4
VSS
D27/PJ3
D26/PJ2
D25/PJ1
VDD
13
GDC21D601
PIN
177
178
179
180
181
182
183
184
14
NAME
D24/PJ0
D23/PI7
D22/PI6
D21/PI5
VSS
D20/PI4
D19/PI3
D18/PI2
PIN
185
186
187
188
189
190
191
192
NAME
VDD
D17/PI1
D16/PI0
D15
VSS
D14
D13
D12
PIN
193
194
195
196
197
198
199
200
NAME
VDD
D11
D10
D9
VSS
D8
D7
D6
PIN
201
202
203
204
205
206
207
208
NAME
VDD
D5
D4
D3
VSS
D2
D1
D0
GDC21D601
5. Pin Descriptions
PIN NUMBER
1~2, 4~6, 8~10,
12~14, 16~17,
19~21, 23~25,
27~29, 31~32
33
34
PIN NAME
A[31:0]
37
36
39
40
41
43
44
45
RTCOSCIN
RTCOSCOUT
NRST
TDI
TCK
TDO
TMS
IRQ0
WDTOUT
NPDN
TYPE
O
O
O
DESCRIPTION
Address Bus
Valid After RESET.
Watch Dog Timer Overflow Output
Power Down Signal from PMU block
When it is LOW, MCU entered the power down mode. When HIGH, normal
I
O
I
I
I
O
I
I/O
Real Time Clock Oscillator Input
32.768kHz
Real Time Clock Oscillator Output
JTAG Reset
JTAG Data Input
JTAG Clock Input
JTAG Data Output
JTAG Mode Signal
External Interrupt Input 0, when PINMUX_PA[0] = 0
Programmable I/O ports. Each pin can be mapped to specified
function pin name. (External IRQ0,IRQ1,…
)
53
PA0
IRQ1
PA1
IRQ2
PA2
IRQ3
PA3
IRQ4
PA4
IRQ5
PA5
PA6
54
PA7
I/O
55
TCIOA0
PB0
TCIOB0
PB1
TCIOA1
PB2
TCIOB1
PB3
TCIOA2
PB4
TCIOB2
PB5
I/O
47
48
49
51
52
57
58
59
61
62
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PIO Port A[0], when PINMUX_PA[0] = 1
External Interrupt Input 1, when PINMUX_PA[1] = 0
PIO Port A[1], when PINMUX_PA[1] = 1
External Interrupt Input 2, when PINMUX_PA[2] = 0
PIO Port A[2], when PINMUX_PA[2] = 1
External Interrupt Input 3, when PINMUX_PA[3] = 0
PIO Port A[3], when PINMUX_PA[3] = 1
External Interrupt Input 4, when PINMUX_PA[4] = 0
PIO Port A[4], when PINMUX_PA[4] =1
External Interrupt Input 5, when PINMUX_PA[5] = 0
PIO Port A[5], when PINMUX_PA[5] = 1
PIO Port A[6]
Tbclk Clock Input for TIC test
PIO Port A[7]
Tfclk Clock Input for TIC test
Timer Channel 0 Input Capture A, when PINMUX_PB[0] = 0
PIO Port B[0], when PINMUX_PB[0] = 1
Timer Channel 0 Input Capture B, when PINMUX_PB[1] = 0
PIO Port B[1], when PINMUX_PB[1] = 1
Timer Channel 1 Input Capture A, when PINMUX_PB[2] = 0
PIO Port B[2], when PINMX_PB[2] = 1
Timer Channel 1 Input Capture B, when PINMUX_PB[3] = 0
PIO Port B[3], when PINMUX_PB[3] = 1
Timer Channel 2 Input Capture A, when PINMUX_PB[4] = 0
PIO Port B[4], when PINMUX_PB[4] = 1
Timer Channel 2 Input Capture B, when PINMUX_PB[5] = 0
PIO Port B[5], when PINMUX_PB[5] = 1
15
GDC21D601
PIN NUMBER
63
65
66
67
69
70
71
73
74
75
76
78
79
80
82
83
84
86
87
88
90
91
92
16
PIN NAME
TCIOA3
PB6
TCIOB3
PB7
PC0
TCIOA4
PC1
TCIOB4
PC2
TCIOA5
PC3
TCIOB5
PC4
TCLKA
PC5
TCLKB
PC6
TCLKC
PC7
TCLKD
RXD0
PD0
TXD0
PD1
RXD1
PD2
TXD1
PD3
NCTS
PD4
NDSR
PD5
NDCD
PD6
NRI
PD7
NDTR
PE0
NRTS
PE1
SMDI
PE2
SMDO
PE3
SMCLK
PE4
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
Timer Channel 3 Input Capture A, when PINMUX_PB[6] = 0
PIO Port B[6], when PINMUX_PB[6] = 1
Timer Channel 3 Input Capture B, when PINMUX_PB[7] = 0
PIO Port B[7], when PINMUX_PB[7] = 1
PIO Port C[0], when PINMUX_PC[0] = 0
Timer Channel 4 Input Capture A, when PINMUX_PC[0] = 1
PIO Port C[1], when PINMUX_PC[1] = 0
Timer Channel 4 Input Capture B, when PINMUX_PC[1] = 1
PIO Port C[2], when PINMUX_PC[2] = 0
Timer Channel 5 Input Capture A, when PINMUX_PC[2] = 1
PIO Port C[3], when PINMUX_PC[3] = 0
Timer Channel 5 Input Capture B, when PINMUX_PC[3] = 1
PIO Port C[4], when PINMUX_PC[4] = 0
External Timer Clock Source A, when PINMUX_PC[4] = 1
PIO Port C[5], when PINMUX_PC[5] = 0
External Timer Clock Source B, when PINMUX_PC[5] = 1
PIO Port C[6], when PINMUX_PC[6] = 0
External Timer Clock Source C, when PINMUX_PC[6] = 1
PIO Port C[7], when PINMUX_PC[7] = 0
External Timer Clock Source D, when PINMUX_PC[7] = 1
UART Channel 0 Receive Data, when PINMUX_PD[0] = 0
PIO Port D[0], when PINMUX_PD[0] = 1
UART Channel 0 Transmit Data, when PINMUX_PD[1] = 0
PIO Port D[1], when PINMUX_PD[1] =1
UART Channel 1 Receive Data, when PINMUX_PD[2] = 0
PIO Port D[2], when PINMUX_PD[2] = 1
UART Ch 1 Transmit Data, when PINMUX_PD[3] = 0
PIO Port D[3], when PINMUX_PD[3] =1
UART Ch 1 Clear to Send, when PINMUX_PD[4] = 0
PIO Port D[4], when PINMUX_PD[4] = 1
UART Ch 1 Data Set Ready, when PINMUX_PD[5] = 0
PIO Port D[5], when PINMUX_PD[5] = 1
UART Ch 1 Data Carrier Detect, when PINMUX_PD[6] = 0
PIO Port D[6], when PINMUX_PD[6] = 1
UART Ch 1 Ring Indicator, when PINMUX_PD[7] = 0
PIO Port D[7], when PINMUX_PD[7] =1
UART C 1 Data Terminal Ready, when PINMUX_PE[0] = 0
PIO Port E[0], when PINMUX_PE[0] = 1
UART Ch 1 Ready to Send Data, when PINMUX_PE[1] = 0
PIO Port E[1], when PINMUX_PE[1] = 1
Smart Card Interface Data In, when PINMUX_PE[2] = 0
PIO Port E[2], when PINMUX_PE[2] = 1
Smart Card Interface Data Out, when PINMUX_PE[3] = 0
PIO Port E[3], when PINMUX_PE[3] =1
Smart Card Interface Clock Out, when PINMUX_PE[4] = 0
PIO Port E[4], when PINMUX_PE[4] = 1
GDC21D601
PIN NUMBER
94
108
PIN NAME
SIN0
PE5
BPROT0
SOUT0
PE6
BPROT1
SCLK0
PE7
BLOK
SCS0
PF0
MemByte0
SIN1
PF1
MemByte1
SOUT1
PF2
BTRANS0
SCLK1
PF3
BTRANS[1]
SCS1
PF4
BWAIT
BCLKOUT
PF5
NFIQOUT
PF6
NIRQOUT
PF7
I2CSDA0
109
110
112
113
114
116
I2CSCL0
I2CSDA1
I2CSCL1
I2CSDA2
I2CSCL2
Mode0
95
96
98
99
100
102
103
104
105
106
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DESCRIPTION
SSI Channel 0 Data In, when PINMUX_PE[5] = 0
PIO Port E[5], when PINMUX_PE[5] =1
AMNA BPROT[0] Signal, when PINMUX_PE[8] = 1
SSI Channel 0 Data Out, when PINMUX_PE[6] = 0
PIO Port E[6], when PINMUX_PE[6] = 1
AMBA BPROT[1] Signal, when PINMUX_PE[8] = 1
SSI Channel 0 Clock Out, when PINMUX_PE[7] = 0
PIO Port E[7], when PINMUX_PE[7] =1
AMBA BLOK Signal Out, when PINMUX_PE[8] = 1
SSI Channel 0 Channel Control, when PINMUX_PF[0] = 0
PIO Port F[0], when PINMUX_PF[0] = 1
MemByte[0] Signal from EBI Block, when PINMUX_PF[8] = 1
SSI Channel 1 Data In, when PINMUX_PF[1] = 0
PIO Port F[1], when PINMUX_PF[1] = 1
MemByte[1] Signal from EBI Block, when PINMUX_PF[8] = 1
SSI Channel 1 Data Out, when PINMUX_PF[2] = 0
PIO Port F[2], when PINMUX_PF[2] = 1
AMBA BTRANS[0] Signal, when PINMUX_PF[8] = 1
SSI Channel 1 Clock Out, when PINMUX_PF[3] = 0
PIO Port F[3], when PINMUX_PF[3] = 1
AMBA BTRANS[1] Signal, when PINMUX_PF[8] = 1
SSI Channel 1 Channel Control, when PINMUX_PF[4] = 0
PIO Port F[4], when PINMUX_PF[4] =1
AMBA BWAIT Signal, when PINMUX_PF[8] = 1
AMBA BCLK Signal, when PINMUX_PF[5] = 0
PIO Port F[5], when PINMUX_PF[5] = 1
AMBA NFIQ Signal, when PINMUX_PF[6] = 0
PIO Port F[6], when PINMUX_PF[6] =1
AMBA NIRQ Signal, when PINMUX_PF[7] = 0
PIO Port F[7], when PINMUX_PF[7] = 1
Data Signal for I2C Channel 0
Pins (108~110,112~114) are required to be pull-up externally.
When bus is free, this pin goes logical “HIGH”
After reset, SDA pins enter Idle state
Clock Signal for I2C Channel 0
Data Signal for I2C Channel 1
Clock Signal for I2C Channel 1
Data Signal for I2C Channel 2
Clock Signal for I2C Channel 2
Boot Mode0, when TEST pin = 0
Mode[0:1] = 00 32-bit
By default, 32-bit access
( MCU can boot from 32- bit Memory)
TREQA
117
Mode1
TREQB
I
TREQA Signal for TIC Test,
when TEST pin = 1
Boot Mode 1
TREQB Signal for TIC Test
Mode[0:1] = 01 8-bit
Mode[0:1] = 10 16-bit
Mode[0:1] = 11 Reserved
17
GDC21D601
PIN NUMBER
118
120
PIN NAME
Mode 2
TACK
UCLKIN
TYPE
I/O
I
DESCRIPTION
Boot Mode 2 (BigEndian Pin)
Big-endian Selection Pin, when this pin = 1(HIGH)
Note) When this pin is HIGH, External Data will be
transferred “Big-endian” format.
TACK Signal for TIC Test
UART Clock Oscillator Clock Input
UART block dedicated clock source supported.
(This clock source is used for UART and SMART Card Only)
121
123
124
125
UCLKOUT
TEST
NEXTREQ
PG0
NRESET
O
I
I/O
I
UART Clock Oscillator Clock Output
Test Input Pin, Select 116~118 pin as Boot Mode or TIC Signal
External Master Request Bus Mastership, when PINMUX_PG[0] = 0
PIO Port G[0], when PINMUX_PG[0] = 1
System Power On Reset Input
To ensure proper initialization after power is stable,
assert NRESET pin for at least 20µs
127
I/O
142
NEXTACK
PG1
NDREQ0
PG2
NDACK0
PG3
NDREQ1
PG4
NDACK1
PG5
NRAS0
PG6
NRAS1
PG7
NCAS0
PH0
NCAS1
PH1
NCAS2
PH2
NCAS3
PH3
XIN
141
144
145
147
148
149
151
XOUT
NDRAMOE
NDRAMWE
NWR0
NWR1
NWR2
NWR3
O
O
O
O
O
O
O
128
129
131
132
133
135
136
137
138
139
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Bus Granted Signal for External Master, when PINMUX_PG[1] = 0
PIO Port G[1] = 1, when PINMUX_PG[1] = 1
DMA Channel 0 Request, when PINMUX_PG[2] = 0
PIO Port G[2], when PINMUX_PG[2] = 1
DMA Channel 0 Acknowledge, when PINMUX_PG[3] = 0
PIO Port G[3], when PINMUX_PG[3] = 1
DMA Channel 1 Request, when PINMUX_PG[4] = 0
PIO Port G[4], when PINMUX_PG[4] = 1
DMA Channel 1 Acknowledge, when PINMUX_PG[5] = 0
PIO Port G[5], when PINMUX_PG[5] = 1
DRAM Bank #0 RAS Signal, when PINMUX_PG[6] = 0
PIO Port G[6], when PINMUX_PG[6] = 1
DRAM Bank #1 RAS Signal, when PINMUX_PG[7] = 0
PIO Port G[7], when PINMUX_PG[7] = 1
DRAM CAS0 Signal, when PINMUX_PH[0] = 0
PIO Port H[0], when PINMUX_PH[0] = 1
DRAM CAS1 Signal, when PINMUX_PH[1] = 0
PIO Port H[1], when PINMUX_PH[1] = 1
DRAM CAS2 Signal, when PINMUX_PH[2] = 0
PIO Port H[2], when PINMUX_PH[2] = 1
DRAM CAS3 Signal, when PINMUX_PH[3] = 0
PIO Port H[3], when PINMUX_PH[3] = 1
System Clock Input
(<80MHz)
External TTL oscillator input
System Clock Oscillator Output
DRAM Output Enable
DRAM Write Enable
Write Enable 0 for Static Memory(Byte)
Write Enable 1 for Static Memory(Byte)
Write Enable 2 for Static Memory(Byte)
Write Enable 3 for Static Memory(Byte)
GDC21D601
PIN NUMBER
152
153
155
PIN NAME
NRD
RDNWR
EXPRDY
TYPE
O
O
I
DESCRIPTION
Output Enable Signal for Static Memory
Read/Write Signal
Ready Signal Input
When this pin is Low, current memory transfer extended.
156
EXPCLK
O
Clock Output Signal
Active only during external cycles.
Output is same phase and speed as the bus clock
157
NCS0
O
Chip Select Signal for Bank #0
NCS pins are required to be Pull-up for proper operation.
All NCS pins are Active Low
See Fig.1 memory Map(Section 2)
158
159
161
162
165
NCS1
NCS2
NCS3
NCS4
PH4
NCS5
PH5
CS6
166
PH6
CS7
163
O
O
O
I/O
I/O
I/O
Chip Select Signal for Bank #1
Chip Select Signal for Bank #2
Chip Select Signal for Bank #3
Chip Select Signal for Bank #4, when PINMUX_PH[4] = 0
PIO Port H[4], when PINMUX_PH[4] = 1
Chip Select Signal for Bank #5, when PINMUX_PH[5] = 0
PIO Port H[5], when PINMUX_PH[5] = 1
Chip Select Signal for Bank #6, when PINMUX_PH[6] = 0
CS6 pin can be programmed active HIGH/LOW
I/O
PIO Port H[6], when PINMUX_PH[6] = 1
Chip Select Signal for Bank #7, when PINMUX_PH[7] = 0
CS7 pin can be programmed active HIGH/LOW
167, 169~171,
173~175, 177~180,
182~184, 186~188,
190~192, 194~196,
198~200, 202~204,
206~208
167, 169~171,
173~175, 177
178~180, 182~184,
186~187
3, 11, 18, 26, 38,
46, 56, 64, 72, 81,
89, 97, 107, 115,
122, 130, 143, 150,
160, 168, 176, 185,
193, 201
7, 15, 22, 30, 35,
42, 50, 60, 68, 77,
85, 93, 101, 111,
119, 126, 134, 140,
146, 154, 164, 172,
181, 189, 197, 205
PH7
D[31:0]
I/O
PIO Port H[7], when PINMUX_PH[7] = 1
Data Bus
PJ[7:0]
I/O
PIO Port J[7:0], when PINMUX_PJ[7:0] = 1
PI[7:0]
I/O
PIO Port I[7:0] , when PINMUX_PJ[7:0] = 1
VDD
I
Power
VSS
I
Ground
19
GDC21D601
Section 2. System Architecture
1. Internal Bus Architecture
The GDC21D601 take the advantage of the AMBA(Advanced Micro-controller Bus Architecture) as the internal
Bus Architecture. The AMBA specification defines an on-chip communication standard for designing highperformance embedded micocontrollers. Two distinct buses are defined within the AMBA:
- the Advanced System Bus (ASB)
- the Advanced Peripheral Bus (APB)
The AMBA ASB is for high-performance system modules. The modules connected to ASB are DRAM Controller,
Static Memory Controller, DMA Controller, On-Chip SRAM, ARM720T CPU Core, Arbiter, Decoder, APB
Bridge, and TIC.
The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and
reduced interface complexity to support peripheral functions. The modules connected to APB are PIO, Interrupt
Controller, PMU, WDT, RTC, Timer, UART, SSPI, and I2C.
See also AMBA Specification Rev. D (ARM IHI 0001D), and AMBA Specification Rev. 2.0 (ARM IHI 0011A)
for detail.
2. Arbiter
The AMBA bus specification is a multi-master bus standard. As a result, a bus arbiter is needed to ensure that only
one bus master has an access to the bus at any particular point of time. Each bus master can request the bus; the
Arbiter decides which has the highest priority and issues a grant signal accordingly. The GDC21D601 can have the
four bus master: ARM720T CPU Core, DMA Controller, TIC, and External Bus Master.
Every system must have a default bus master which grants the use of bus during reset, when no other bus master
requires the bus. During Power On Reset, the arbiter will grant the use of bus to the default bus master and hold all
other grant signals inactive. The ARM720T Core, the default bus master will grant for the use of bus under the
following conditions: Reset, standby, power-down, and no other master requesting the bus
The arbiter processes the requests of the ownership of the ASB and grants one ASB master according to the
arbitration scheme. The arbitration scheme of this implementation is a simple priority encoded scheme where the
highest priority master requesting the ASB is granted. The priority order is as follows:
Case 1) Aripri = ‘0’
1. TIC
2. DMA
3. External BUS Master
4. ARM (default bus master)
Case 2) Aripri = ‘1’
1. TIC
2. External BUS Master
3. DMA
4. ARM (default bus master)
20
GDC21D601
3. System Decoder
The decoder in an AMBA system is used to perform a centralized address decoding function, which gives two
main advantages:
- It improves the portability of peripherals, by making them independent of the system memory map.
- It simplifies the design of bus slaves, by centralizing the address decoding and bus control functions.
The decoder performs three main tasks:
- address decoder
- default transfer response
- protection unit
The decoder generates a select signal for each slave on the ASB bus and, under certain circumstances, will not
select any slaves and provide the transac-tion response itself.
The MCU System Memory Map is shown in Figure 1.
The decoder greatly simplifies the slave interface and removes the need for the slave to understand the different
types of transfer that may occur on the bus.
4. Memory Map
The system decoder controls the memory map of the system and generates a slave select signal for each memory
region.
The ReMap signal is used to provide a different memory map: ROM is required at address 0 when power on reset,
and RAM also may be used at address 0 during normal operation.
The ReMap signal is typically provided by a Power Management Unit (PMU) which drives ReMap to LOW at
reset. The signal is only driven to HIGH after a particular register in the PMU is accessed (See Section. 9 Power
Management Unot for detail). When ReMap is HIGH and isram signal is HIGH, then Memory Map Configuration
is MODE A which the internal SRAM is located at address 0x00. And When ReMap is HIGH and drambank0
signal is HIGH, then Memory Map Configuration is Mode B which the DRAM bank #0 is located at address 0x00.
The isram and drambank0 signal come from MCU Controller. See Section 8. MCU Controller for detail.
Figure 2. Memory map configuration shows both the Reset (MODE R) and the Normal (MODE B and MODE A)
memory map
Figure 1. shows the system memory map.
21
GDC21D601
5. Memory Format
The ARM720T CPU Core supports both the Big-Endian and Little-Endian format. And the GDC21D601 can also
support the Big-Endian and Little-Endian memory format. The GDC21D601 can support the Little-Endian Format
by default. When using the GDC21D601 as Big-Endian format: 1) set Boot Mode 2 pin to VDD, and 2) set the
ARM720T as Big-Endian mode with using Coprocessor instruction. 3) set the Big-Endian flag of the compile
options when compile. The example of the coprocessor instruction is in the below. It is noted that CP15 register
(CPU control register) can only be accessed with MRC and MCR instructions in a Privileged mode. See the
ARM720T Data Sheet (ARM DDI 0087D) for detail. The ARM720T Data Sheet is downloadable from ARM
home page (http://www.arm.com).
For example :
MRC
ORR
MCR
p15, 0, r3, c1, c1
r3, r3, #0x80
p15, 0, r3, c1, c1
Note : The GDC21D601 has a EBI (External Bus Interface) block which can copy the Byte or HalfWord of the lower position in data bus to higher data bus position, so you can use the GDC21D601 as
BigEnd mode by only set the Boot Mode 2 pin to VDD and in this case you may not set the ARM720T
as BigEnd Mode.
6. Boot Mode
The GDC21D601 can support 32/16/8 Bit Boot ROM. By default MCU can boot from 32 bit ROM. In this case
Boot Mode[1:0] (pin number 116 and 117) are “00”. If you want use 16 bit Boot ROM, then you must set Boot
Mode[1:0] are “10”. And in case of Booting from 8 bit ROM, you must set Boot Mode[1:0] are “01”. It is for
reserved in case that Boot Mode[1:0] are “11” . See the Table 1. The Description of the Mode Pin.
In all case of boot mode the wait cycle of Boot area is 3 cycles. If you want to know about boot mode for detail
you must see the Section 6. Static Memory Controller.
Table 1. The Description of the Mode Pin
Mode[1:0]
00
01
10
11
22
Bus width of Booting ROM
32 Bit
8 Bit
16 Bit
Reserved
GDC21D601
7. Multi-Function Pin
The GDC21D601 has 80 Bit PIO pins with multiplexed by other functional pins. So you must use properly these
multi-function pins by setting the PINMUX control registers in MCU controller. (See Section 8. MCU Controller
for detail)
0XFFFF FFFF
APB Register
0XFFFF FFFF
FD00
0XFFFF E000
0X5000 0000
FB00
I2C2
0X4000 0000
FA00
I2C1
F900
I2C0
SSI
UART1
0X1000 1000
UART0
0X1000 0000
F200
F100
F000
EE00
ED00
EC00
Chip Select Area
EB00
0X0000 0000
WINDOW AREA
TIMER
RTC
INTC
WDT
PMU
EF00
0X0800 0000
DRAM BANK #0
0X2000 0000
F600
F300
DRAMC
SMI
MCUC
ON-CHIP RAM
WINDOW AREA
0X0800 0000
0X0700 0000
0X0600 0000
0X0500 0000
0X0400 0000
DMAC
Reserved
DRAM BANK #1
UART2/Smart
F400
ARM7 TEST REG
0X3000 0000
F700
F500
Reserved
0X6000 0000
PIO
F800
MEMORY AREA
0XFFFF EAFF
FC00
0XFFFF F000
ASB Register
Reserved
0X0300 0000
0X0200 0000
0X0100 0000
0X0000 0000
nCS7
nCS6
CS6
CS7
nCS5
nCS4
nCS3
nCS2
nCS1
nCS0
Figure 1. System Memory Map
Address
0x2FFFFFF
MODE R
MODE A
MODE B
nCS2
nCS2
nCS2
nCS1
nCS1
nCS0
nCS0 or
DRAM #0
0x01FFFFFF
nCS1
0x00FFFFFF
0x00000FFF
0x00000000
DRAM #0
On-Chip RAM
1. MODE R : Reset Mode : default mode from power-on reset (ReMap is LOW)
2. MODE A : On-Chip SRAM in 0x0000 ~ 0x07FF range : ReMap is HIGH and isram is HIGH
3. MODE B : DRAM Bank #0 in 0x00000000 ~ 0x00FFFFFF range : Remap is HIGH and drambank0 is HIGH
Figure 2. Memory Map Configuration
23
GDC21D601
Section 3. ARM720T Core
1. General Description
ARM720T is 32bit microprocessor of general purpose with 8KB cache, enlarged write buffer and Memory
Management Unit (MMU), which are combined in a single chip. The CPU within ARM720T is the ARM7TDMI.
The ARM720T is software compatible with the ARM processor family. The ARM7TDMI is a member of the ARM
family of general purpose 32bit microprocessors, which offers high performance for very low power consumption
and price. This processor employs a unique architectural strategy known as THUMB, which makes it ideally suited
to high volume applications with memory restrictions or applications where code density is an issue.
The key idea behind THUMB is a super reduced instruction set. Essentially, the ARM7TDMI has two instruction
sets, the standard 32bit ARM set and 16bit THUMB set. The THUMB set’s 16bit instruction length allows it to
approach twice the density of standard ARM code while retaining most of the ARM`s performance advantage over
a traditional 16bit processor by using 16bit registers. This is possible because THUMB code operates on the same
32bit register set as ARM code.
See also ARM720T Datasheet (ARM DDI 0087D) for detail.
2. Feature
• 32bit RISC architecture
• Low power consumption
• ARM7TDMI core with;
- On-chip ICEbreaker debug support
- 32bit x 8 hardware multiplier
- Thumb decompressor
• Utilizes the ARM7TDMI embedded processor
- High performance 32 bit RISC architecture
- High density 16 bit instruction set
• Fully static operation : 0 ~ 80MHz
• 3-stage pipeline architecture (Fetch, decode, and execution stage)
• Enhanced ARM software toolkit
• MMU, Write Buffer, 8KB I/D Cache
24
GDC21D601
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an
equivalent ARM processor connected to a 16-bit memory system.
Virtual Address Bus
MMU
8KB Cache
ARM7TDMI
CPU
Coprocessor
Interface
Internal Data Bus
Data and
Address
Buffers
Control and
Clocking
Logic
JTAG
Debug
Interface
System
Control
Coprocessor
AMBA Interface
AMBA Bus
Interface
Figure 1. ARM720T Block Diagram
25
GDC21D601
3. Core Block Diagram
ScanChain2
A [ 31:0]
ALE
ABE
Address Register
P
C
b
u
s
Register Bank
(31 x 32-bit registers)
(6 status registers)
A
L
U
b
u
s
Address
Incrementer
b
u
s
32 x 8
Multiplier
B
Barrel Shifter
b
u
s
A
b
u
s
I
n
c
r
e
m
e
n
t
e
r
Scan
Control
Instruction
Decoder
&
Control
Logic
nENOUT DBE
RANGEOUT0
ICE
Breaker
D [ 31:0]
A [0:31]
Bus
Splitter
Core
Scan
Chain 1
Scan
Chain 0
TAP Controller
SCREG [3:0]
IR [3:0]
TASPM [3:0]
TDO
TDI
nTRST TMS
TCK
Figure 2. ARM7TDMI Core Block Diagram
26
ESTERN1
nRW
MAS [1:0]
nTRANS
nMREQ
nOPC
nIRQ
nFIQ
nRESET
ABORT
Instruction Pipeline
& Read Data Register
& Thumb Instruction Decoder
nENIN
RANGEOUT1
EXTERN0
SEQ
LOCK
nCPI
CPA
CPB
nM [4:0]
TBE
TBIT
HIGHZ
32-bit ALU
Write Data Register
DBGRQI
BREAKPTI
DBGACK
ECLK
nEXEC
ISYNC
BL [3:0]
APE
MCLK
nWAIT
D [0:31]
DIN [0:31]
DOUT [0:31]
GDC21D601
Section 4. DRAM Controller
1. General Description
The DRAM controller interfaces the AMBA Advanced System Bus (ASB) to external DRAM memory banks. The
DRAM controller provides the following features:
• Up to two banks of DRAM support.
• Fast page-mode sequential access support.
• EDO DRAM support
• Word, Half-word and Byte transaction support.
• Little / Big Endian Format support.
• DRAM refresh controller using CAS-before-RAS (CBR) refresh mode.
• Programmable refresh rate.
• Power-down mode where all DRAM accesses (including self-refresh) are disabled.
• Programmable DRAM timing control.
• Row/column addresses multiplexes according to DRAM capacity.
Chip PAD
DRAM Controller
Main State Machine
&
Control
nDRAMWE
nDRAMOE
nRAS[1:0]
Refresh
Timer & Controller
nCAS[3:0]
ASB Interface
&
Address Generator
nCASFB[3:0]
ASB Bus
BCLK
PDREQ
PDACK
DSELDRAM
DSELREG
BnRES
BLAST
BERROR
BWAIT
BWRITE
BSIZE[1:0]
BA[29:0]
BD[31:0]
Aout[23:0]
DataOut[31:0]
DataIn[31:0]
nOutEn[3:0]
Lat
Lat
mux
mux
mux
DRAMByte[1:0]
nDRAMALatch
nDRAMA[12:0]
nDRAMAMUX
nDRAMOutEn[3:0]
nDRAMOutLEn
nDRAMInLEn[3:0]
nDRAMInEn
EBI Signal Control
BD[31:0]
Lat
Figure 1. DRAM Controller Module Block Diagram
27
GDC21D601
2. Hardware Interface and Signal Description
The DRAM Controller module is connected to the ASB bus. Table 1. DRAM interface ASB signal descriptions
shows the internal bus interface signals to the DRAM controller.
Table 1. DRAM Interface ASB Signal Descriptions
NAME
BA [27:0]
BCLK
BD [7:0]
BERROR
BLAST
BnRES
BSIZE [1:0]
BWAIT
BWRITE
DSELDRAM
DSELREG
DESCRIPTION
System address bus (excluding high order bits).
The ASB clock timing all bus transfers.
Bidirectional system data bus.
Error slave response signal. It is driven to phase 1 if the DRAM controller is selected. This
signal will be asserted, when an access to the DRAM is attempted while the DRAM
controller is in its Power Down mode.
Last transfer of burst slave response signal. It can be driven to phase 1 if the DRAM
controller is selected. It is asserted in order to indicate a 256-word boundary to force a nonsequential access.
These signals indicate the reset status of the ASB.
These signals indicate the size of the transfer that may be byte, half-word, or word.
Wait slave response signal. It is driven to phase 1 when the DRAM controller is selected. It
is asserted while the DRAM transaction is uncompleted.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that the DRAM is selected.
When this signal is HIGH, it indicates that the DRAM configuration register is selected.
Table 2. DRAM interface External DRAM signal descriptions describes the DRAM controller connections to
external devices of the system and to EBI (External Bus Interface) block .
Table 2. External DRAM Signal Descriptions
NAME
nRAS[1:0]
NCAS[3:0]
NDRAMOE
NDRAMWE
nCASFB[3:0]
PDREQ
PDACK
DRAMAMUX
28
DESCRIPTION
Active LOW Row Address Strobes, one for each DRAM bank.
Active LOW Column Address Strobes, one for each byte.
Active LOW Output Enable.
Active LOW Write Enable.
This is the nCAS[3:0] signal fed back from the output of the nCAS[3:0] pads.
Power Down Request. This signal indicates that the DRAM controller should enter into its
low-power state, causing the DRAMs to enter into self-refresh state if refresh is enabled.
When it is deasserted, the DRAM controller will exit from low power state.
Power Down Acknowledge. This signal is asserted when the DRAM controller has
successfully entered into its low-power mode. At this point BCLK may be stopped safely. It
is deasserted when the DRAM controller has successfully exited from its low power state.
DRAM Address Multiplex Select. When this signal is HIGH, it indicates to the EBI that the
DRAMA[12:0] address should be used to generate DRAMA[12:0]. This signal provides the
support for a shared EBI, and may not be needed in a system where the DRAM controller
does not share the EBI with other memory controllers. DRAMAMUX is LOW when
DRAM accesses are not performed.
GDC21D601
NAME
NDRAMALatch
DRAMA[12:0]
NDRAMInEn
NDRAMInLEn[3:0]
NDRAMOutEn
NDRAMOutLen
DESCRIPTION
DRAM Address Latch. When this signal is LOW, it opens the EBI address latch. This
signal is HIGH when DRAM operations do not occur. This signal provides support for a
shared EBI and may not be needed in a system where the DRAM controller does not share
the EBI with other memory controllers.
These multiplexed address lines are connected to the DRAM Address.
DRAM Input Enable. When this signal is LOW, it enables the EBI drivers from latched XD
to BD. This signal is HIGH when DRAM read operations are not performed.
DRAM Input Latch Enable. When this signal is HIGH, it shuts the EBI latches on XD. This
signal is LOW when DRAM read operations are not performed.
DRAM Output Enable. When this signal is HIGH, it disables the EBI drivers from latched
BD to XD. This signal is low when DRAM write operations are not performed.
DRAM Output Latch Enable. When this signal is LOW, it opens the EBI latches on BD.
This signal is HIGH when DRAM write operations are not performed.
Accesses to the DRAM Controller module are generated as a result of the address decode put out on the ASB
address bus by the current bus master (which could be the ARM CPU or the DMA engine, for example).
The following three diagrams show the timing of the external interface for read, write and refresh cycles
(Figure 2, 3, 4).
BCLK
DRAMA[12:0]
row
col
row
col1 col2 col3
nRAS[1:0]
nCAS[1:0]
XData[31:0]
nOE
nWE
Figure 2. DRAM External Signal Timing: Read Cycles
29
GDC21D601
BCLK
DRAMA[12:0]
row
col
row
col1 col2 col3
nRAS[1:0]
nCAS[1:0]
XData[31:0]
Data
Data1 Data2 Data3
nOE
nWE
Figure 3. DRAM External Signal Timing: Write Cycles
BCLK
nRAS[1:0]
nCAS[1:0]
nOE
nWE
Figure 4. DRAM Controller Refresh Cycle
30
GDC21D601
3. Functional Description
3.1 Introduction
The DRAM controller provides connections allowing a direct interface to up to two banks of DRAM. Each bank is
32/16/8 bits wide and up to 256MB in size. Two RAS lines are provided (one per bank) and four CAS lines (one
per byte line).
3.2 Functional BreakDown
The DRAM controller consists of four main blocks: the Main State Machine & Control Block, the EBI Signal
Control Block, the ASB Interface & Address Generation Block, and the Refresh Timer & Counter Block.
3.3 Main State Machine
This block contains the main DRAM timing control state machine and the decode for the external strobe signals
for the DRAM interface. The state machine generates the timing for the nCAS and nRAS strobes, and the
multiplexing of the DRAM row and column address lines for standard DRAM cycles and refresh cycles. The
nDRAMWE and nDRAMOE signals are asserted appropriately depending on the access type. Word, Half-word,
and Byte accesses are decoded from the lower bits of the BA address bus in order to assert the appropriate nCAS
line(s). For word accesses all four nCAS lines are asserted. Figure 5. Descibes the Main State Machine Diagram.
Local arbitration for refresh cycles is also carried out here as refresh requests are received from the refresh timer
block. The block also supports the self refresh DRAM; enter to and exit from this self refresh state are initiated by
the PDRREQ signal. This is illustrated in Figure 6. DRAM signal timing: power down mode.
r_IDLE
DSEL
r_WAIT
!BWRITE
RAS
r_WnR
r_RnR
RefReq or
!DSEL
CAS
CAS
r_RnC1
CAS
BWRITE
RefReq or
!DSELD1
r_WnC1
r_CRWAIT
r_RnC2
CAS
r_WnC2
r_CWWAIT
r_RnC3
r_WnC3
r_RnC4
r_WnC4
Figure 5. Main State Machine Diagram
31
GDC21D601
3.4 EBI Control Block
This also generates the control signals required by the EBI(External Bus Interface). The EBI control signals are
divided into three main groups; those related to the control of the Address path, the DataIn path, and the DataOut
path.
Address Path Control
There are three signazls related to the address path of the EBI:
nDRAMALATCH
used to open the address latch of the EBI. This can be used to hold the external address XA
while internal accesses are performed. When this signal is asserted (active LOW) the EBI
address latch should be opened. When a DRAM access is not performed, the DRAM
controller will de-assert this signal. In a shared EBI scheme, other memory
controllers(Static Memory controller,...) must exhibit this behavior when they do not
perform memory accesses.
DRAMAMUX
used to select the DRAMA[12:0] address as the address to be used on XA. This signal will
be asserted (active HIGH) when a DRAM access occurs, and will be de-asserted when the
transfer is completed.
DRAMA[12:0]
the multiplexed row/column address used to access the DRAM.
DataIn and DataOut Path Control
There are four signals related to the data path of the EBI:
nDRAMOUTEN
used to enable the EBIs data drivers onto XData. When this signal is de-asserted (HIGH),
the EBI should disable its drive onto XData. This signal is de-asserted during read cycles
and is asserted at other times. In a shared EBI scheme, other memory controllers must
exhibit this behavior when they do not perform memory accesses.
nDRAMOUTLEN
used to latch the value of BD into the EBIs data output latches. When this signal is asserted
(active LOW), the EBI data output latch is opened. This signal will be asserted during
DRAM write transfers, and is de-asserted at other times.
nDRAMINEN
used to enable the EBI data drivers onto BD. When this signal is asserted (active LOW), the
EBI should be driven onto BD. This signal is asserted during DRAM read transfers and is
de-asserted at other times.
nDRAMINLEN[3:0] used to latch the value of XData into the EBI data input latches. When this signal is deasserted (HIGH), the EBI data input latch is shut. Four signals are provided to enable
latching of byte / half-word data. nDRAMINLEN[0] is used to latch the data on M_D[7:0].
This signal is normally asserted and will be de-asserted during DRAM read transfers to latch
the current data on XData.
32
GDC21D601
3.5 Refresh Control Block
The refresh timer is a 7-bit timer counter which counts down and generates a refresh request when it reaches zero,
at this point it is reloaded with the value in the refresh control register. This allows refresh frequencies from the
Refresh Control Register and BCLK input clock.
3.6 ASB Interface Block
The ASB interface provides the interaction with the main AMBA bus. The DRAM controller will initiate a DRAM
access when the DSELDRAM signal is asserted, or access the control registers when the DSELREG strobe is
asserted. The timing of the ASB transfers is described in detail in the AMBA Specification rev. D. At a 256-word
boundary, the BLAST signal will be asserted to indicate to the bus master that the burst sequence should be broken
within the page boundary.
This block also generates the row and column addresses. During burst mode accesses, the column address is
provided by a 10-bit column address incrementor to provide adequate column address timing.
BCLK
PDREQ
PDACK
nRAS[1:0]
nCAS[3:0]
nOE
nWE
Figure 6. DRAM Signal Timing : Power Down Mode
33
GDC21D601
4. Register Description
4.1 Memory Map
The base address (=DRAM REG Base) of the DRAM controller register bank is 0xFFFFED00.
Table 5. Memory Map of the Dram Controller Peripheral
ADDRESS
Base + 0x0
Base + 0x4
Base + 0x8
Base + 0xC
WRITE LOCATION
DRAM Refresh Control Register (RCR)
DRAM Control Register for CPU
DRAM Control Register for DMA
DRAM Test Control Register (TCR)
READ LOCATION
N/A
DRAM Control Register for CPU
DRAM Control Register for DMA
N/A
INITIAL
16’h0000
7’b0000000
6’b000000
4’b0000
4.2 DRAM Refresh Control Register(RCR)
The DRAM refresh period register is an 16-bit write register which enables the refresh and selects the refresh
period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the DRAM refresh
period register is only cleared by a Power On Reset (BnRES = 0).
15
8
REFCNT
7
6
0
RFSHEN
RFDIV
Figure 7. DRAM Controller Refresh Register
REFCNT
DRAM Refresh Clock Divisor. Refresh Clock is setting by this bit field :
RefClock = BCLK/REFCNT
The REFCNT field should not be programmed with zero since this results in no initiated refresh
cycles.
RFSHEN
DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated by the DRAM
controller at the rate set by the RFDIV field. Setting this bit also enables self-refresh mode when the
DRAM controller is in the power down state.
RFDIV
This 7-bit field sets the DRAM refresh rate. The refresh period is deriven from internally generated
clock and is given by the following formula:
Frequency (KHz) = 2*[RefClock /(RFDIV + 1)]
or
RFDIV = ( RefClock / 0.5*Refresh frequency (KHz) )
-
1
The RFDIV field should not be programmed with zero since this results in no initiated refresh cycles.
34
GDC21D601
4.3 DRAM Control Register for CPU (DRAMConCPU)
This Register controls the DRAM control signals when DRAM accessed by CPU. In normal condition, the
DRAM access time is changed by the bus master is CPU or DMA Controller. In case of bus master is DMA
Controller, the transfer timing should be properly set to the external I/O device and DRAM, so for the optimal
system performance the DRAM access by the CPU is set in this DRAM Control Register for CPU
(DRAMConCPU) and in case of the DRAM access by the DMA Controller DRAM control signals are controlled
by the DRAM Control Register for DMA (DRAMConDMA).
15
7
Reserved
6
5
4
DMAEn
TRP
TCP
3
2
WaitCnt
1
0
BankSize
Figure 8. DRAM Control Register for CPU (DRAMConCPU)
DMAEn
If DMA transfer, then the DRAM control signals are controlled by DRAM Control Register for DMA
(DRAMDonDMA) by this bit setting. When this bit is ‘0’, then the DRAM control signals are
controlled by bit fields in this Control Register (DRAMConCPU) during DRAM access.
TRP
Control the timing of difference between the RAS and CAS signal by this bit field setting. When this
bit is ‘0’, then DRAM access are absolutely no wait, so DRAM access time is very short, but should
be considered the operating frequency of the MCU and DRAM access time.
TCP
Control the timing of the Low phase of CAS signals. When this bit is ‘1’, then the Low phase of the
CAS signals are enlarged to one cycle of BCLK. When this bit is ‘0’, then the Low phase of the CAS
signals are half clock of BCLK.
WaitCnt
This bit fields control the DRAM access time. The wait state is inserted in ASB BUS by the value of
these WaitCnt fields. (00=0-wait, 01=1-wait, 10=2-wait, 11=3-wait)
BankSize
These bits indicate the data width of the DRAM Bank. The data width of the DRAM by BankSize are
shown Table 6.
Table 6. Data width of the DRAM by BankSize[1:0] fields
BankSize[1:0]
00
01
10
11
Data Width of DRAM
Byte
Half Word
Word
Reserved
35
GDC21D601
4.4 DRAM Control Register for DMA
This Register controls the DRAM control signals when DRAM accessed by DMA.
Setting the register is effective only when the DMAEn bit set by DRAMConCPU(DRAM Control register from
CPU).
15
6
Reserve
5
4
TRP
TCP
3
2
1
WaitCnt
0
BankSize
Figure 9. DRAM Control Register for DMA (DRAMConDMA)
4.5 DRAM Test Control(TCR)
The DRAM test control register is for test and should not be used during normal operation. It is a write-only
register with the following format.
15
4
Reserved
3
2
TESTINC
FORCEADV
1
0
FORCESIZE
Figure 10. DRAM Test Control Register
TESTINC
Test increment (TESTINC). This bit puts the column address increment into a test mode. In
this mode each nibble of the column address increment increments independently. Resets it to
0.
FORCEADV
Force refresh advance (FORCEREFADV). This bit forces the refresh counter to advance every
BCLK. Resets it to 0.
FORCESIZE[1:0] Force access size. These bits force the size of accesses to the DRAM bank. When this is set to
10 (default), the ASB B_SIZE is used to determine the size of the access. When this is set to
00 or 01, a byte or half-word access is forced respectively. Resets it to 10.
36
GDC21D601
Section 5. On-Chip SRAM
1. General Description
The GDC21D601 has 8-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access
controller(DMAC) with 32-bit data bus. The CPU and DMA Controller can write data into the on-chip RAM in
byte, half-word, or word units.
2. Signal Description
Table 1. Signal Descriptions
NAME
BA[31:0]
BD[31:0]
BWAIT
BLAST
BERROR
BWRITE
DSELMEM
BnRES
TYPE
I
I/O
I/O
I/O
I/O
I
I
I
DESCRIPTION
System address bus.
Bi-directional system data bus.
LOW during phase one of BCLK.
LOW during phase one of BCLK.
LOW during phase one of BCLK.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that on-chip RAM is selected.
These signals indicate the reset status of the ASB.
3. Function Description
On-Chip SRAM can read data from SRAM and can write data into SRAM in a single clock cycle through ASB bus.
And SRAM is single module which have 32 bit data bus and control lines.
The data in the On-chip RAM can always be accessed in one cycle that make the RAM ideal for use as a program
area, stack area, or data area, which requires high-speed access. The contents of the on-chip RAM are held in both
standby and power-down modes.
Memory area 0x10000000 to 0x10001FFF is allocated to the on-chip RAM as default. When isram signal from
MCU Controller is set to HIGH, memory area 0x00000000 to 0x00001FFF can be allocated to the on-chip RAM.
37
GDC21D601
Section 6. Static Memory Controller
1. General Description
The Static Memory Controller interfaces the AMBA Advanced System Bus (ASB) to the External Bus Interface
(EBI); controlling the external SRAM, ROM, Flash Memory or off-chip peripherals. Eight separate chip select
banks are provided by this block. Each bank is 256MB in size and can be programmed individually to support:
• 8-, 16- or 32-bit wide, Little-Endian and Big-Endian Memory Format
• variable wait states (up to 16 waits)
• exchangeable active low/high chip select signal (only for CS6 and CS7)
• various type control signal timing
• bus transfers can be extended using the EXPRDY input signal. EXPRDY signal can be used by
exchangeablely active HIGH or LOW in according to control register setting.
Chip PAD
Static Memory Controller
EXPRDY
EXPCLK
Main State Machine
Bank Config. Reg.
BWRITE
MODE[1:0]
RnW
ASB Bus
BCLK
BnRES
DSELSMI
DSELREG
BTRAN[1:0]
BSIZE[1:0]
nWEN[3:0]
nSRAMOE
ASB Interface
&
Chip Select encode
nCS[5:0]
CS[7:6]
nWEF[3:0]
BLAST
BERROR
BWAIT
BA[26:24, 4:0]
EBI Signal Control
Aout[23:0]
DataOut[31:0]
DataIn[31:0]
nOutEn[3:0]
Lat
Lat
mux
mux
mux
MemByte[1:0]
nSRAMALatch
nSRAMA[1:0]
nSRAMAMUX
nSRAMOutEn[3:0]
nSRAMOutLEn
nSRAMInLEn[3:0]
nSRAMInEn
BD[31:0]
BD[31:0]
Lat
Figure 1. Static Memory Controller Block Diagram
38
GDC21D601
2. Signal Description
The Static Memory Controller module is connected to the ASB bus. In Table 1. Static Memory Controller ASB
signal descriptions show the internal bus interface signals(AMBA signals) to the Static Memory Controller
Table 1. Static Memory Controller ASB Signal Descriptions
NAME
BA[26:24, 4:0]
TYPE
I
BCLK
BD[31:0]
I
I/O
BERROR
O
BLAST
O
BWAIT
O
BnRES
BSIZE[1:0]
BTRAN[1:0]
BWRITE
DSELSRAM
I
I
I
I
I
DSELREG
I
DESCRIPTION
System address bus. The SRAM controller only requires seven bits of this bus
to do the necessary encoding/decoding.
The ASB clock.
Bi-directional system data bus. The data bus is driven by this block during read
transfers from configuration registers only.
LOW during phase one of BCLK when the Static Memory Controller is
selected.
LOW during phase one of BCLK when the Static Memory Controller is
selected.
This slave response is driven during phase one of BCLK when the Static
Memory Controller is selected and is used to indicate if the memory has
completed its current transfer.
The reset status of the ASB.
The size of the transfer data which may be byte, half-word, or word.
These signals are used to determine sequential and non-sequential accesses.
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that the Static Memory Controller is
selected.
When HIGH, this signal indicates that one of the Bank Configuration registers
is selected.
39
GDC21D601
Table 2. Static Memory Controller External Signal Descriptions
NAME
EXPRDY
TYPE
I
EXPCLK
O
nWEN[3:0]
O
nWEF[3:0]
I
NSRAMOE
O
nCS[5:0]
CS[7:6]
SRAMA [1:0]
O
O
O
nSRAMALatch
O
MemByteSeq[1:0]
O
nSRAMOutLEn
nSRAMOutEn[1:0]
nSRAMInLEn[1:0]
nSRAMInEn
Mode[1:0]
O
O
O
O
I
40
DESCRIPTION
Expansion channel ready. This signal is active LOW by default, When this
signal is LOW, it will force the current memory transfer to be extended. When
the RDON bit field in Configuration Register is set, then the polarity of the
EXPRDY signal is reversed to active HIGH.
Expansion clock output. Clock output at the same phase and speed as the bus
clock. Active only during SRAM/ROM cycles.
These signals are active LOW write enables for each of the memory byte lanes
on the external bus. For example nWEN[0] controls the writes to D[7:0].
These optional connections use PADs feedback from the external side of the
nWEN[3:0] PADs. They are used to guarantee address and chip select hold
time when any write enable is LOW. If not used, they should be tied to HIGH.
This is the active LOW output enable for devices on the external bus. This is
LOW during reads from external memory and during the time that the selected
bank should drive the external data bus.
Active LOW Chip Select
Active HIGH Chip Select
These signals form the lower two bits of the external address bus. They are
used to control accesses to 16- or 8-bit memories when the AMBA bus
requests an access size larger than the memory (this is handled using multiple
external transfers).
This signal is an active LOW transparent address latch enable. It is normally
HIGH to prevent power wasting transitions on the external address bus.
These signals control the data path muxes which allow 16- or 8-bit memories to
read and write 32-bit values on the AMBA bus.
Active LOW transparent latch enable for the data out path (writes).
Active LOW byte lane data output driver enable.
Active LOW transparent latch enable for the data in path (reads).
Active LOW data input driver enable (to AMBA bus).
Booting mode configuration input. If these signals are “00” during BnRES
LOW then the SRAM Controller will select bank zero (nCS[0]) as 32-bit
memory. If these signals are “10” then select bank zero as 16-bit memory. If
these signals are “01” then bank zero as 8-bit memory.
GDC21D601
Accesses to the Static Memory Controller module can be two basic types; control register accesses and memory
area accesses. The following timing diagrams relate to the external pin timings for SRAM/ROM read and write
cycles in minimum wait states.
BCLK
BTRAN[1:0]
N_TRAN
S_TRAN
S_TRAN
S_TRAN
address n
BA[23:0]
S_TRAN
address n+4
address n+8
DSELSRAM
BWAIT
BD[31:0]
EXPCLK
nCS[5:0]
nSRAMOE
address n
A[23:0]
address n+4
address n+8
D[31:0]
EXPRDY
Deocde
Wait
read
read
read
Figure 2. ROM Read Timing
41
GDC21D601
BCLK
BTRAN[1:0]
N_TRAN
S_TRAN
S_TRAN
S_TRAN
address n
BA[23:0]
address n+4
DSELSRAM
BWAIT
BD[31:0]
EXPCLK
nWEN[3:0]
nCS[5:0]
address n+4
address n
XA[23:0]
write data
XD[31:0]
write data
EXPRDY
Deocde
Wait
write
Figure 3. SRAM Write Timing
42
write
write
GDC21D601
3. Functional Description
The Static Memory Controller has following functions:
• memory bank select
• off-chip expansion clock driver
• wait states generation
• byte lane write control
• burst read access
• various type control signal generation
These are described below.
3.1 Memory Bank Select
The chip select signal generation is controlled by BA[26:24]. From Table 3 static memory bank select coding is
shown that these signals coded to CS[7:6] and nCS[5:0].
Table 3. Static Memory Bank Select Coding (MODE R)
DSEL
1
1
1
1
1
1
1
1
BA[26:24]
000
001
010
011
100
101
110
111
CS[7:6]
00
00
00
00
00
00
01
10
nCS[5:0]
111110
111101
111011
110111
101111
011111
111111
111111
MEMORY CONFIGURATION
nCS0 configuration
nCS0 configuration
nCS2 configuration
nCS3 configuration
nCS4 configuration
nCS5 configuration
CS6 configuration
CS7 configuration
3.2 Off-Chip Expansion Clock Driver
In the Static Memory Controller, the system clock input BCLK is passed directly to EXPCLK during memory
cycles if the expansion clock enable bit of the corresponding memory bank configuration is set.
3.3 Access Sequencing
Bank configuration also determines the width of the external memory devices. When the external memory bus is
narrower than the transfer initiated from the current master, the internal transfer will take several external bus
transfers to complete. For example, in case that bank zero is configured as 8-bit wide memory and a 32-bit read is
initiated, the ASB bus will stall while the SRAM Controller reads four consecutive bytes from the memory. During
these accesses the data path is controlled (using the MemByteSeq[1:0] signals) to de-multiplex these four bytes
into one 32-bit word on the ASB bus.
43
GDC21D601
3.4 Wait State Generation
The Static Memory Controller supports wait states for read and write accesses. This is configurable between one
and 16 wait states for standard memory access and zero and 15 wait states for burst mode reads from ROMs.
Note
Wait state control refers to external transfer wait states. The number of cycles where an AMBA transfer completes
is controlled by two other factors; access width and external memory width. The Static Memory Controller also
allows transfers to be extended indefinitely, by asserting EXPRDY to LOW. To hold the current transfer EXPRDY
must be asserted on the falling edge of BCLK before the last cycle of the access. The transfer cannot be completed
until EXPRDY is HIGH for at least one cycle.
3.5 Burst Read Control
This supports sequential access burst reads of up to four consecutive locations in 8-, 16- or 32-bit memories. This
feature supports burst mode ROM devices and increases the bandwidth by using a reduced (configurable) access
time for three sequential reads following a quad-location boundary read. (Note that quad-location boundaries occur
when A[1:0]=00 for byte wide memories.)
3.6 Byte Lane Write Control
This controls nWEN[1:0] according to AMBA transfer width (indicated by BSIZE[1:0]), external memory width,
BA[1:0], and the access sequencing. The following table shows the basic coding assuming 32-bit external memory:
Table 4. nWEN Coding
BSIZE[1:0]
10 (word)
01 (half-word)
01 (half-word)
00 (byte)
00 (byte)
00 (byte)
00 (byte)
44
BA[1:0]
XX
1X
0X
11
10
01
00
nWEN[3:0]
0000
0011
1100
0111
1011
1101
1110
GDC21D601
4. Programmer’ s Model
4.1 Memory Map
The base address for the Static Memory Controller registers is 0xFFFFEC00
Table 5. Static Memory Controller Memory Map
ADDRESS
SRAMRegBase + 00000
SRAMRegBase + 00004
SRAMRegBase + 00008
SRAMRegBase + 0000C
DESCRIPTION
Memory Configuration Register 1 (MEMCFG1)
Memory Configuration Register 2 (MEMCFG2)
Memory Configuration Register 3 (MEMCFG3)
Memory Configuration Register 4 (MEMCFG4)
INITIAL VALUE
32’h00000004
32’h00000000
32’h00000000
32’h00000000
4.2 Memory Configuration Registers
31
16
15
0
NCS[n+1] Configuration Register
NCS[n] Configuration Register
Figure 4. Memory Configuration Register
Memory configuration register (MEMCFG1, 2, 3, 4) is a 32-bit read-write register which sets the configuration of
the two expansion and ROM selects. Each select is configured with a two-byte field.
31
30
29
Reserved RDON
28
CSCNTL
27
FlashON
26
CLKEN
25
24
Mem Width
23
BUREN
15
14
13
Reserved RDON
12
CSCNTL
11
FlashON
10
CLKEN
9
8
Mem Width
7
BUREN
22
20 19
16
Burst Wait Normal Wait
6
4
Burst Wait
3
0
Normal Wait
Figure 5. Two-Byte Fields in the Memory Configuration Register for CS[5:0]
(Note : Gray areas are reserved for another feature.)
15
Rsv.
14
CSON
13
RDON
12
CSCNTL
11
FlashON
10
CLKEN
9
8
7
Mem Width BUREN
6
4
Burst Wait
3
0
Normal Wait
Figure 6. Two-Byte Fields in the Memory Configuration Register for CS[6]
31
LCDON
30
CSON
29
RDON
28
CSCNTL
27
FlashON
26
CLKEN
25
24 23
22 21
16
Mem Width Reserved
LCD Wait
Figure 7. Two-Byte Fields in the Memory Configuration Register for CS[7]
45
GDC21D601
LCDON
LCD enable. When the Bank 7 is connected to LCD panel for text display, setting this bit
enables LCD wait to access directly LCD device. LCD wait bit is 6 bits therefore wait cycle
is from 1 to 64.
CSON
nCS enable. Setting this bit is enables the CS6 and CS7 to be active low signal from active
high signal that supports various devices.
RDON
select the polarity of EXPRDY. When this bit is set to 0, EXPRDY signal act as positive
active signal. When this bit is set to 1, EXPRDY signal act as negative active signal.
CSCNTL
Make the control signals (Address, Data, CS, RnW, etc.) of external device to be similar
Motorolar type CPU.
FlashON
Flash memory enable. When this bit is set to 1, memory control signals, nCS, nWEN[1:0],
and nSRAMOE, are adjusted to flash memory control signal timing.
CLKEN
Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to
the specified bank. This provides a timing reference for devices that need to extend bus
cycles using the EXPRDY input. Back to back sequential accesses result in a continuous
clock.
BUREN
Burst enable. Setting this bit enables burst reads to take advantage of faster access time from
ROM devices that support burst mode.
Note
Banks using EXPCLK and EXPRDY for off-chip peripheral control should not enable burst mode, and
should be designed and set up to use a specific number of wait states in each access. The peripheral
should time the access by counting EXPCLK cycles (there is no explicit indication of access start or
end) and determine the access direction and width by using nWEN[3:0].
Table 6. Values of the Mem Width Field Define the Bus Width Field.
Table 6. Values of the Mem Width Field
MEM WIDTH FIELD
00
01
10
11
46
EXPANSION TRANSFER MODE
32-bit wide bus access
16-bit wide bus access
8-bit wide bus access
Reserved
GDC21D601
Table 7. The values of the Normal Wait field define the values of the normal access wait state field. And the values
of the LCD Wait define likely as Table 7.
Table 7. Values of the Normal Access Wait State Field.
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NUMBER OF WAIT STATES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Table 8. Values of the Burst Wait field define the values of the burst read wait state field.
Table 8. Values of the Burst Read Wait State Field
VALUE
000
001
010
011
100
101
110
111
NUMBER OF WAIT STATES
0
1
2
3
4
5
6
7
47
GDC21D601
Section 7. MCU Controller
1. General Description
Designing the Microcontroller unit (MCU), some control signals needed by any functional block, but not drive any
other block, must be generated. So these control signals are generated in MCU Controller. The MCU Controller
(MCUC) is composed of registers which are for selecting the function of multi-function pins, for defining the
memory map structure, arbiter priority, MCU device code, and DRAM Power Down Req/Ack signals.
2. Signal Description
Table 1. Signal Descriptions
NAME
BCLK
BnRES
BA[31:0]
BD[31:0]
BWAIT
BLAST
BERROR
BWRITE
DSEL
PwrDwnAck
PwrDwnReq
Ari_pri
Isram
Drambank0
PINMUX_sigs
48
TYPE
I
I
I
I/O
O
O
O
I
I
I
O
O
O
O
O
DESCRIPTION
System bus clock.
the reset status of the ASB
System address bus
Bi-directional system data bus.
Low during phase one of BCLK
Low during phase one of BCLK
Low during phase one of BCLK
When this signal is HIGH, it indicates a write transfer and when LOW a read.
When this signal is HIGH, it indicates that MCU Controller is selected.
This signal indicates that DRAM is entered into self-refresh mode
The request of entering the self-refresh node of DRAM
Determine Arbiter Priority. See Section.2 System Architecture for detail
Allocate On-Chip SRAM address area at 0x00000000
Allocate DRAM address area at 0x00000000
These signals are for Multi-function pin
GDC21D601
3. Register Description
3.1 Register Memory Map
The base address of MCU control Register is 0xFFFFEB00.
Table 2. MCU Controller Memory Map
ADDRESS
R/W
MCURegBase + 0x0000
MCURegBase + 0x0004
R/W
R/W
INITIAL
VALUE
0x00
0x00
MCURegBase + 0x0008
R/W
0x00
MCURegBase + 0x000C
R/W
0x00
MCURegBase + 0x00010
R/W
0x00
MCURegBase + 0x00014
R/W
0x00
MCURegBase + 0x00018
R/W
0x00
MCURegBase +0x0001C
R/W
0x00
MCURegBase + 0x00020
R/W
0x00
MCURegBase + 0x00024
R/W
0x00
MCURegBase + 0x00028
R/W
0x00
MCURegBase +0x0002C
MCURegBase + 0x00030
MCURegBase + 0x00034
R
R
W
$LG601
0x0
0x0
DESCRIPTION
MCU Control Register
PINMUX_PA Register, Multi-function pin
signals for Port A[5:0]
PINMUX_PB Register, Multi-function pin
signals for Port B[7:0]
PINMUX_PC Register, Multi-function pin
signals for Port C[7:0]
PINMUX_PD Register, Multi-function pin
signals for Port D[7:0]
PINMUX_PE Register, Multi-function pin
signals for Port E[8:0]
PINMUX_PF Register, Multi-function pin
signals for Port F[8:0]
PINMUX_PG Register, Multi-function pin
signals for Port G[7:0]
PINMUX_PH Register, Multi-function pin
signals for Port H[7:0]
PINMUX_PI Register, Multi-function pin
signals for Port I[7:0]
PINMUX_PJ Register, Multi-function pin
signals for Port J[7:0]
MCU Device Code Register
DRAM Power Down Ack
DRAM Power Down Req
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
MUX Control
3.2 MCUC_CON Register
31
Reserved
drambank0
Isram
Ari_pri
2
Ari_Pri
1
Isram
0
Drambank0
When this register is HIGH, DRAM memory address bank #0 area is located at 0.
When this register is HIGH, On-Chip SRAM address area is located at 0
Arbiter Priority control signal. See also Section 2 System Architecture for details.
Figure 1. MCU Controller Register
49
GDC21D601
3.3 PINMUX Register
Table 3. PINMUX_PA Register
BIT NO.
0
1
2
3
4
5
SIGNAL NAME
PINMUX_PA[0]
PINMUX_PA[1]
PINMUX_PA[2]
PINMUX_PA[3]
PINMUX_PA[4]
PINMUX_PA[5]
When 0
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
PIN FUNCTION DESCRIPTION
When 1
PA0
PA1
PA2
PA3
PA4
PA5
PIN No.
45
47
48
49
51
52
Table 4. PINMUX_PB Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PB[0]
PINMUX_PB[1]
PINMUX_PB[2]
PINMUX_PB[3]
PINMUX_PB[4]
PINMUX_PB[5]
PINMUX_PB[6]
PINMUX_PB[7]
When 0
TCIOA0
TCIOB0
TCIOA1
TCIOB1
TCIOA2
TCIOB2
TCIOA3
TCIOB3
PIN FUNCTION DESCRIPTION
When 1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PIN No.
55
57
58
59
61
62
63
65
Table 5. PINMUX_PC Register
BIT NO.
0
1
2
3
4
5
6
7
50
SIGNAL NAME
PINMUX_PC[0]
PINMUX_PC[1]
PINMUX_PC[2]
PINMUX_PC[3]
PINMUX_PC[4]
PINMUX_PC[5]
PINMUX_PC[6]
PINMUX_PC[7]
When 0
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PIN FUNCTION DESCRIPTION
When 1
TCIOA4
TCIOB4
TCIOA5
TCIOB5
TCLKA
TCLKB
TCLKC
TCLKD
PIN No.
66
67
69
70
71
73
74
75
GDC21D601
Table 6. PINMUX_PD Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PD[0]
PINMUX_PD[1]
PINMUX_PD[2]
PINMUX_PD[3]
PINMUX_PD[4]
PINMUX_PD[5]
PINMUX_PD[6]
PINMUX_PD[7]
When 0
RXD0
TXD0
RXD1
TXD1
NCTS
NDSR
NDCD
NRI
PIN FUNCTION DESCRIPTION
When 1
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PIN No.
76
78
79
80
82
83
84
86
Table 7. PINMUX_PE Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PE[0]
PINMUX_PE[1]
PINMUX_PE[2]
PINMUX_PE[3]
PINMUX_PE[4]
PINMUX_PE[5]
PINMUX_PE[6]
PINMUX_PE[7]
When 0
NDTR
NRTS
SMDI
SMDO
SMCLK
SIN0
SOUT0
SCLK0
PIN FUNCTION DESCRIPTION
When 1
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PIN No.
87
88
90
91
92
94
95
96
Table 8. PINMUX_PF Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PF[0]
PINMUX_PF[1]
PINMUX_PF[2]
PINMUX_PF[3]
PINMUX_PF[4]
PINMUX_PF[5]
PINMUX_PF[6]
PINMUX_PF[7]
When 0
SCS0
SIN1
SOUT1
SCLK1
SCS1
BCLKOUT
NFIQOUT
NIRQOUT
PIN FUNCTION DESCRIPTION
When 1
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PIN No.
98
99
100
102
103
104
105
106
51
GDC21D601
Table 9. PINMUX_PG Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PG[0]
PINMUX_PG[1]
PINMUX_PG[2]
PINMUX_PG[3]
PINMUX_PG[4]
PINMUX_PG[5]
PINMUX_PG[6]
PINMUX_PG[7]
When 0
EXTREQ
EXTACK
DREQ0
DACK0
DREQ1
DACK1
RAS0
RAS1
PIN FUNCTION DESCRIPTION
When 1
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PIN No.
124
127
128
129
131
132
133
135
Table 10. PINMUX_PH Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PH[0]
PINMUX_PH[1]
PINMUX_PH[2]
PINMUX_PH[3]
PINMUX_PH[4]
PINMUX_PH[5]
PINMUX_PH[6]
PINMUX_PH[7]
When 0
CAS0
CAS1
CAS2
CAS3
CS4
CS5
CS6
CS7
PIN FUNCTION DESCRIPTION
When 1
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PIN No.
136
137
138
139
161
162
165
166
Table 11. PINMUX_PI Register
BIT NO.
0
1
2
3
4
5
6
7
52
SIGNAL NAME
PINMUX_PI[0]
PINMUX_PI[1]
PINMUX_PI[2]
PINMUX_PI[3]
PINMUX_PI[4]
PINMUX_PI[5]
PINMUX_PI[6]
PINMUX_PI[7]
When 0
D16
D17
D18
D19
D20
D21
D22
D23
PIN FUNCTION DESCRIPTION
When 1
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PIN No.
187
186
184
183
182
180
179
178
GDC21D601
Table 12. PINMUX_PJ Register
BIT NO.
0
1
2
3
4
5
6
7
SIGNAL NAME
PINMUX_PJ[0]
PINMUX_PJ[1]
PINMUX_PJ[2]
PINMUX_PJ[3]
PINMUX_PJ[4]
PINMUX_PJ[5]
PINMUX_PJ[6]
PINMUX_PJ[7]
When 0
D24
D25
D26
D27
D28
D29
D30
D31
PIN FUNCTION DESCRIPTION
When 1
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PIN No.
177
175
174
173
171
170
169
167
3.5 MCU Device Code Register
This Register is read only.
Device Code Value is ‘$LG601’
Binary Value : 0000 0100 1100 0100 0111 0110 0000 0001
3.6 DRAM Power Down Acknowledge Register
This Register is 1 bit read only register.
This register is set when DRAM is entered to power down mode.
3.7 DRAM Power Down Request Register
This Register is 1 bit read/write register.
When this register bit is HIGH, request to DRAM Controller to enter into power down mode of the DRAM.
53
GDC21D601
Section 8. Power Management Unit
1. General Description
The PMU block provides:
• Clock distribution of all over system
• Reset, RUN and Power down modes control
Figure 1. shows the PMU Block Diagram.
nPOR
Reset
Debounce
Digital Filter
WD_OF_IN
MAN_RESET_IN
P_A[7:0]
P_D[15:0]
P_SEL
P_STB
P_WRITE
PMU
Registers
Reset
Control
PMU
Control
B_RESETn_OUT
P_RESETn0_OUT
P_RESETn1_OUT
RESETn_EXT
WD_OF_OUT
nPDM
FASTBUS
REMAP
INT_REQ_IN
tfclk
tbclk
SCLK_IN
PCLK_IN
SPCLK
BCLK
Freq.
Control
PCLK
Freq.
Control
FCLK, BCLK
Distribution
Control
BCLK_XXX for Peripherals
PCLK_XXXX for Peripherals
PCLK
Distribution
Control
Figure 1. PMU Block Diagram
54
FCLK
BCLK_XXX for ASB block
GDC21D601
2. Hardware Interface and Signal Description
The PMU block is connected to the APB bus. Table 1. describes the APB signals and clock signals used and
produced.
Table 1. PMU Signal Descriptions
NAME
nPOR
INT_REQ_IN
WD_OF_IN
MAN_RST_IN
TYPE
I
I
I
I
P_D[15:0]
I/O
P_A[7:0]
I
P_WRITE
I
P_STB
I
P_SEL
I
SCLK_IN
PCLK_IN
I
I
Tfclk
I
Tbclk
I
BCLK_XXX
O
PCLK_XXX
FCLK
O
O
FASTBUS
O
NPDM
O
REMAP
WD_OF_OUT
B_RESETn
P_RESETn0
P_RESETn1
RESETn_OUT
O
O
O
O
O
O
DESCRIPTION
External reset input.
Interrupt request signal from the interrupt controller.
Watch dog timer overflow signal.
S/W manual reset pin from watch dog timer.
This is the bi-directional peripheral data bus. This block drives the data bus
during read cycle, when P_WRITE is LOW.
This is the peripheral address bus, which uses individual peripheral for decoding
register accesses to that peripheral. The addresses become valid before PSTB goes
to HIGH and remain valid after PSTB goes to LOW.
This signal indicates a write to a peripheral when it is HIGH and a read from a
peripheral when LOW.
It has the same timing as the peripheral address bus.
This strobe signal is used to time all accesses on the peripheral bus. The falling
edge of PSTB is coincident with the falling edge of BCLK
When HIGH, this signal indicates that module has been selected by the APB
bridge.
System clock input . This is the clock input from external clock circuit .
UART clock. This is the clock input from external UART clock module.
When it is in TIC test mode, this s the FCLK clock input signal. When TSTCR[1]
is set to 1(HIGH) for entering TIC test mode.
When it is in TIC test mode, BCLK clocks signal. First set the TSTCR[1] to 1 for
entering TIC test mode.
System Bus clock is generated from SCLK_IN. All ASB block and some APB
blocks are operated by this clock.
APB Peripheral Bus Clocks. All APB blocks are operated by the clocks.
FCLK pin for ARM720T. It is used in standard mode, when FASTBUS is LOW.
ARM720T bus mode control signal. When it is LOW, it is in standard bus mode.
When HIGH, fast bus mode.
Indicates the PDM mode of PMU. When it is LOW, MCU entered in power down
mode. When HIGH, normal operation mode.
Indicates that the reset memory map is in operation.
Watch dog overflow output signal for external devices.
Reset signal for ASB devices
Reset signal for APB devices
Same as P_RESETn0, but in manual reset mode this is not asserted.
Reset signal for external devices.
55
GDC21D601
3. Operation Modes
3.1 Introduction
The reset protocol guarantees that the multi-master
system starts up with at most one bus driver enabled
on each shared signal on the bus, and also permits a
protocol reset mechanism for time-out or
‘watchdog’ reset support.
The reset and power-down mechanism provides:
To improve power management, support for a
power-saving mode where bus clocks may be
disabled (or dropped to lower clock) is included.
Additionally a system bus, once operational,
benefits from well-defined modes of operation:
• Stable power-up sequence
• Hard Initialization (Power On Reset)
• Soft Initialization (S/W Manual Restart)
• RUN in the Standard BUS mode
• RUN in the FAST BUS mode
• Power-down mode
3.2 Reset and Operation Modes
A set of four useful states or modes is defined as
follows:
RESET
When it is power-on, watchdog timer overflow,
watchdog timer manual reset or S/W reset, the MCU
is initialized
Manual Reset / Software Reset
The manual reset, which may need to apply to allow
all soft resetting of the bus for a number of clock
cycles. In this reset states the PMU block initializes
all the ASB blocks, Bus controller, DRAM
Controller, DMA Controller, ARM CPU core, and
Arbiter, Decode. However some APB blocks are all
valid in warm reset.
Rower on Reset
Watchdog Timer Overflow and Manual Reset
The most severe form of reset which ensures that no
more than one tri-state driver is enabled on each bus
and initializes all system states to ensure that the
power supply can in fact rise to normal operating
voltage.
This state should be forced by any on-chip poweron-reset cell or external power-on signal and
maintained until bus clock is safe and stable.
The POR is forced to be in an asynchronous start-up
condition and must be recognized by all master and
slave devices to disable output drives (and wait for a
valid clock)
56
The watchdog timer can generate reset signal, when
timer overflows or sets the register value. Detailed
information are in the watchdog timer manual,
please refer to it.
RUN - ARM720T Standard Mode.
The ARM720T works using the FCLK and BCLK.
The FCLK is used for CPU operation clock, and the
B_CLK is used for internal bus access, i.e. AMBA
BUS. So CPU can operate very high frequency. This
mode can control the clock of ASB and APB
devices, so user can disable the clocks of unused
devices or peripherals. It is possible to control the
BCLK or PCLK mask register.
GDC21D601
RUN -ARM720T Fast-bus Extension Mode.
disables all of the blocks in the ASB and APB, so
the power consumption of system is dramatically low.
Although MCU is in the power down mode, user can
set some blocks are working in the power down
mode. It is possible control the BCLK or PCLK
mask register for power-down.
The ARM720T works using only the BCLK. The
CPU operation clock and AMBA bus access clock
are the same. This mode can control the clock of
ASB and APB devices, so user can disable the clock
of devices or peripherals that are not using now. It is
possible to control the BCLK mask register or
PCLK mask register.
Wake-up from the PDN Mode.
The Wake-up is a temporal state for wake-up from
power down state through the interruption. After
wake-up state, next state becomes RUN state
automatically.
PDN – Power-Down Mode
When MCU system is in the PDN State, PMU block
WD_OF
nPOR
RESET
S/W Control
Man_reset
Wake-up
by nPOR
RUN
(use FCLK)
S/W
Control
Power Down
S/W Control
S/W Man_reset
Control
RUN
(use B_CLK only)
S/W
Control
Wake-up
by Interrupt
Figure 2. Reset and Power Management State Machine.
57
GDC21D601
4. Register Description
The PMU supplies the clock to all of the blocks in the MCU.
4.1 PMU Control Register
This register controls the operation mode of PMU. When power on reset states, register value is initialized by Run
State (00). The address of register is PMU_BASE(=0xFFFF F000) + 0x00h.
Table 2. PMUCR Bit Functions
BIT
7~0
INITIAL
0x0
NAME
PMUCR
FUNCTION
0x0 - Clear PMU Status Register.
0x03 – Entering the PD(Power down) Mode
the other values - None effect.
4.2 PMU Status Register
This register holds the previous status and reset state of PMU. The address of register is PMU_BASE + 0x00h.
Table 3. PMUSR Bit Functions
BIT
5, 4
INITIAL
00
NAME
PMUST[5:4]
Previous Reset
Status bits
3, 2
00
PMUST[3:2]
Current Status bits
1, 0
00
PMUST[1:0]
Previous
Status
bits
FUNCTION
00 - The Power-On reset state (nPOR).
01 - S/W Reset state using PMU.
10 - S/W Manual reset state using WDT.
11 - WD overflow reset state using WDT.
00 - Running (FAST, SLOW) after nPOR.
01 - Running (FAST, SLOW) after WD_OF.
10 - Running (FAST, SLOW) after Man_reset
00 - Start (FAST, SLOW) after nPOR.
01 - Start (FAST, SLOW) after WD_OF.
10 - Start (FAST, SLOW) after Man_reset
11 - Start (FAST, SLOW) after PD Mode.
4.3 REMAP Register
The REMAP register controls re-mapping operation when the reset (POR or MAN_RST) signal is asserted or S/W
is reset by RSTCR. The address is PMU_BASE + 0x10h.
Table 4. REMAP Bit Functions
BIT
0
58
INITIAL
0
NAME
REMAP
FUNCTION
0 – Reset operation mode map
1 – Normal operation mode map
GDC21D601
4.4 BCLK and FCLK Control Register and BCLK Frequency Control Register
This register controls BCLK of ASB and FCLK of ARM720T. User can save the power by reduce of the clock
speed. At any moment, user can change the BCLK speed but it may push the system into unstable stage, so user
must change the clock speed only in BUS IDLE; this means there is no interaction between the devices used by
BCLK and any other devices used by PCLK. User can control the bus mode that are standard-bus mode and fastbus mode. The BCLK is only used in the fast-bus mode and ARM720T uses the both clock FCLK and BCLK in
the fast bus mode. The address is PMU_BASE + 0x04h.
Table 5. CLKCR Bit Functions
BIT
2-0
INITIAL
000
NAME
BCLKCR[2:0]
FUNCTION
Control register for BCLK selection
000 - BCLK is divided SYS_CLK by 2
001 - BCLK is divided SYS_CLK by 4
010 - BCLK is divided SYS_CLK by 8
011 - BCLK is divided SYS_CLK by 16
100 - BCLK is divided SYS_CLK by 32
101 - BCLK is divided SYS_CLK by 64
110 - BCLK is divided SYS_CLK by 128
111 - BCLK is SYS_CLK.
Table 6. CLKCR Bit Functions
BIT
3
INITIAL
1
NAME
BCLKCR[3]
FUNCTION
Control register to use in FCLK mode
1 – Fast-bus mode (not use the FCLK)
0 – Standard-bus mode
use the FCLK that same the SYS_CLK
4.5 BCLK Mask Register for the RUN & PD Mode.
This register is used for masking BCLK of ASB devices in the RUN and PD mode. When each control bits are
written to “1 or 0”, each clock of devices is controlled by enabled or disabled clock in the RUN and PD mode. The
address of the mask control register are as follows.; BCLKMSK_RUN is PMU_BASE + 0x08h, BCLKMSK_PD
is PMU_BASE + 0x0Ch. When this is 1, it is enable clock. When 0, disable clock.
Table 7. BCLKMSK Bit Functions for RUN Mode
BIT
15-13
12
11
10
9
8
7
6-1
0
INITIAL
1
1
1
1
1
1
1
111111
1
NAME
BCLKMSK_RUN
FUNCTION
Reserved bit
APB Bridge clock mask bit
BUS Controller clock mask bit
DRAM Controller clock mask bit
DMA Controller clock mask bit
TEST Controller clock mask bit
SRAM clock mask bit
Reserved bit
B_CLK Out mask bit
59
GDC21D601
Table 8. BCLKMSK Bit Functions for PD Mode
BIT
15
14
13
12
11
10
9
8
7
6-1
0
INITIAL
0
0
0
0
0
0
0
0
0
000000
0
NAME
BCLKMSK_PD
FUNCTION
ARM7TDMI core clock mask bit
AMBA Arbiter clock mask bit
AMBA Decoder clock mask bit
APB Bridge clock mask bit
BUS Controller clock mask bit
DRAM Controller clock mask bit
DMA Controller clock mask bit
TEST Controller clock mask bit
SRAM clock mask bit
Reserved bit
B_CLK Out mask bit
4.6 PCLK Mask Register
These registers are used for masking PCLK or BCLK of APB devices in the RUN or PD mode. The default values
are all the clocks of the APB devices enabled in the RUN mode, and the clocks of the APB devices disabled in the
PD mode. WDT and TIMER are APB devices but they uses the BCLK for their operation. The address of the mask
control register in RUN mode is PMU_BASE + 0x18h, and that of the power-down mask control register is
PMU_BASE + 0x1Ch. When this is 1, it enables clock. When 0, disables clock.
Table 9. PCLKMSK Bit Functions in the RUN Mode
BIT
9
8
7
6
5
4
3
2
1
0
INITIAL
1
1
1
1
1
1
1
1
1
1
BIT
9
8
7
6
5
4
3
2
1
0
INITIAL
0
0
0
0
0
0
0
0
0
0
NAME
PCLKMSK_RUN
FUNCTION
Watch dog timer clock mask bit
I2 C 2 clock mask bit
I2 C 1 clock mask bit
I2 C 0 clock mask bit
SSPI 1 clock mask bit
SSPI 0 clock mask bit
UART 2 / SMART card I/F clock mask bit
UART 1 clock mask bit
UART 0 clock mask bit
Timer clock mask bit
Table 10. PCLKMSK Bit Functions in the PD Mode
60
NAME
PCLKMSK_PD
FUNCTION
Watch dog timer clock mask bit
I2 C 2 clock mask bit
I2 C 1 clock mask bit
I2 C 0 clock mask bit
SSPI 1 clock mask bit
SSPI 0 clock mask bit
UART 2 / SMART card I/F clock mask bit
UART 1 clock mask bit
UART 0 clock mask bit
Timer clock mask bit
GDC21D601
4.7 PCLK Frequency Control Register
This register is used to selecting the frequency of PCLK in the APB at RUN mode. Default value is 0000. The
address of access the register is PMU_BASE + 0x14h
Table 11. CLKMODE Bit Functions
BIT
2-0
INITIAL
000
NAME
PCLKCR
FUNCTION
Select the PCLK source
000 – PCLK is external PCLK source
001 – PCLK is the SCLK divided by 2
010 – PCLK is the SCLK divided by 4
011 – PCLK is the SCLK divided by 8
100 – PCLK is the SCLK divided by 16
101 – PCLK is the SCLK divided by 32
110 – PCLK is the SCLK divided by 64
111 – PCLK is the SCLK divided by 128
4.8 Reset Control Register
This register is used for generating the S/W reset operation. The MCU is entered in reset state, when this register is
set to high, it is cleared automatically at the end of manual reset procedure. The address is PMU_BASE + 0x30h.
Table 12. RSTCR Bit Functions
BIT
0
INITIAL
0
NAME
RSTCR
FUNCTION
Manual reset control bits
0 - Normal , 1 - manual reset
4.9 Test Control Register
TSTCR controls the normal mode, PMU test mode or the TIC test mode. The address is PMU_BASE + 0x40h.
Table 13. TSTCR Bit Functions
BIT
1
INITIAL
0
0
0
NAME
TSTCR
FUNCTION
0 – Normal operation mode
1 – TIC Test mode
0 – Normal operation mode
1 – PMU test mode
61
GDC21D601
4.10 Test Register
This register is used to store some controls and data values for test mode. The TSTR0 is readable/writable register
and the TSTR1 is a read only register. The address of TSTR0 is PMU_BASE + 0x48h and that of TSTR1 is
PMU_BASE + 0x4Ch.
Table 14. TSTR0 Bit Functions
BIT
2
1
0
INITIAL
0
0
0
NAME
TSTR0
FUNCTION
Test bit for INT_REQ_IN input
Test bit for WD_OF_IN input
Test bit for MAN_RESET_IN input
Table 15. TSTR1 Bit Functions
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
62
INITIAL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NAME
TSTR1
FUNCTION
Test bit for BCLK_WDT
Test bit for PCLK_I2C2
Test bit for PCLK_I2C1
Test bit for PCLK_I2C0
Test bit for PCLK_SSPI 1
Test bit for PCLK_SSPI 0
Test bit for PCLK_UART 2, SMART Card
Test bit for PCLK_UART 1
Test bit for PCLK_UART 0
Test bit for BCLK_TIMER
Test bit for B_RESETn
Test bit for P_RESETn0
Test bit for P_RESETn1
Test bit for P_RESETn
Test bit for WD_OF_OUT
Test bit for REMAP
GDC21D601
5. Power Management Unit Register Map
The base address of the PMU(Power Management Unit) is 0xFFFF F000. May be different for any particular
system implementation. However, the offset address of registers is fixed.
Table 16. Register Map of the PMU
Address
PMU Base + 0x00
Name
PMUCR / PMUSR
PMU Base + 0x04
BCLKCR
PMU Base + 0x08
PMU Base + 0x0C
PMU Base + 0x10
PMU Base + 0x14
PMU Base + 0x18
PMU Base + 0x1C
PMU Base + 0x20
PMU Base + 0x30
PMU Base + 0x40
PMU Base + 0x44
PMU Base + 0x48
PMU Base + 0x4C
BCLKMSK_RUN
BCLKMSK_PD
REMAP
PCLKCR
PCLKMSK_RUN
PCLKMSK_PD
Reserved
RSTCR
TSTCR
TSTR0
TSTR1
Description
In write operation, PMU operation mode controls register. In read
operation, PMU status register shows the just previous PMU state.
BCLK frequency selection and BUS mode control(Standard / Fast
BUS mode)
BCLK Masking controls register in the RUN mode.
BCLK Masking controls register in the PD mode.
REMAP register
PCLK control register
PCLK masking controls register for the RUN mode.
PCLK masking controls register for the PD mode.
Reserved.
Reset control register
TIC test mode and PMU test control register
Reserved
Test write register for external input signals
Test read register for clocks of ASB devices and reset signals
63
GDC21D601
6. Test Mode Guide for MCU
6.1 TIC Test Mode
Step 1. Set-up TIC test environment, connect the TCLK to tbclk(=XPA[6]) pin and FCLK of fclkgen to
tfclk (=XPA[7]) pin. Until the mode of the PMU is changed to the TIC test mode, sys_clk has to
feed same TCLK to the clock.
Step 2.
Step 3.
Step 4.
Step 5.
Reset the MCU using pin nPOR low.
Then TIC becomes the bus master
Change the mode of PMU by setting the TSTCR to “10” and set TSTCR[1] to high.
Start TIC test using tbclk and tfclk pins.
Figure 3. shows TIC Test Environment of Internal Blocks.
TREQA
TREQB
TACK
TIC
APB
TIC BOX
TBUS
EBI
ASB
PCLK
BCLK
BCLK
ARM720T
FCLK
SCLK_IN
PCLK_IN
tbclk
TCLK
SYS_CLK
PMU
tfclk
FCLK
FCLKGEN
nPOR
Reset GEN
Figure 3. Internal Blocks TIC Test Environment
64
GDC21D601
6.2. TIC Test for PMU Block
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Set-up TIC test environment, connect the TCLK to tbclk and FCLK of fclkgen to tfclk pin. Until the
mode of the PMU is changed to the TIC test mode, sys_clk has to feed the clock. It is easier to test the
sys_clk and the tbclk separately.
Reset the MCU using pin nPOR low.
Then TIC becomes the bus master
Change the mode of PMU by setting the TSTCR[1:0] to “11”.
Set value to TSTR0 for test vector, and read output value in the TSTR1 of the PMU and compare it with
desired test vector.
Figure 4. shows PMU TIC Test Environment
TREQA
TREQB
TACK
TIC
APB
TIC BOX
TBUS
EBI
ASB
PCLK
BCLK
BCLK
ARM720T
FCLK
SCLK_IN
PCLK_IN
tbclk
TCLK
TESTCLK
GEN
SYS_CLK
PMU
tfclk
FCLK
FCLKGEN
nPOR
Reset GEN
Figure 4. TIC Test Environment
65
GDC21D601
7. Signal Timing Diagram
The PMU signal timing is as shown below.
7.1 Power on Reset
S_CLK
RESETn_IN
B_RESETn
P_RESETn0/1
RESETn_OUT
Figure 5. Power on Reset Timing Diagram
7.2 Watch Dog Timer Overflow
B_CLK
WD_OF_IN
WD_OF_OUT
B_RESETn
256 B_CLK
512 B_CLK
P_RESETn0/1
Figure 6. Watch Dog Timer Overflow Timing Diagram
7.3 Manual Reset
There are two manual reset cases. The first reset operation is switched by MAN_RST signal from WDT. Another
case is called S/W reset.
66
GDC21D601
B_CLK
MAN_RST
B_RESETn
512 B_CLK
P_RESETn0
P_RESETn1
High
Figure 7. Manual Reset (from WDT) Timing Diagram
B_CLK
RSTCR
B_RESETn
512 B_CLK
P_RESETn0
P_RESETn1
High
Figure 8. S/W Reset Timing Diagram
67
GDC21D601
Section 9. Watchdog Timer
1. General Description
The watchdog timer has:
• watchdog timer mode and interval timer mode
• interrupt signal INT_WDT to interrupt controller in the watchdog timer mode & interval timer mode
• output signal PORESET and MNRESET to PMU(Power Management Unit)
• eight counter clock sources
• selection whether to reset the chip internally or not
• two types of reset signal : power-on reset and manual reset
System clock
Clock
Generation
Clock
Selection
Reset
Control
Bus Interface
INT_WDT
Interrupt
Control
PORST
MNRST
Control logic
Overflow
RSTSR
TCNT
Internal
data bus
clock
TRCR
Module data bus
TCNT : Timer Counter (8bit)
TRCR : Timer/Reset Control Register (8bit)
RSTSR : Reset Status Register (2bit)
Figure 1. Watchdog Timer Module Block Diagram
68
GDC21D601
2. Hardware Interface and Signal Description
The Watchdog Timer module is connected to the APB bus.
Table 1. APB Signal Descriptions
NAME
Type
B_CLK
I
P_A[4:2]
I
P_D[7:0]
I/O
P_STB
I
P_WRITE
I
P_SEL
I
nB_RES
I
INT_WDT
O
MNRST
O
PORST
O
SOURCE/
DESTINATION
Clock controller
DESCRIPTION
System (bus) clock. This clock times all bus transfers. The clock has
two distinct phases - phase 1 when B_CLK is LOW, and phase 2
when B_CLK is HIGH.
APB Bridge
This is the peripheral address bus used by an individual peripheral for
decoding register accesses to that peripheral.
The addresses become valid before P_STB goes to HIGH and remain
valid after P_STB goes to LOW.
APB Peripherals, This is the bi-directional peripheral data bus. The data bus is driven
B_D bus
by this block during read cycles (when P_WRITE is LOW).
APB Bridge
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of P_STB is coincident with the falling edge of
B_CLK.
APB Bridge
When this signal is HIGH, it indicates a write to a peripheral. When
LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
APB Bridge
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). See AMBA Peripheral Bus Controller for more
details.
Power
Reset signal generated from the APB Bridge
Management Unit
Interrupt
When this signal is HIGH, it indicates that a system becomes
Controller
uncontrolled, and the timer counter overflows without being rewritten
correctly by the CPU or it overflows in the interval timer mode.
Power
When this signal is HIGH, this signal indicates that the manual reset
Management Unit signal has selected as the internal reset signal, and the timer counter
overflows without being rewritten correctly by the CPU or it
overflows in the interval timer mode..
Power
When this signal is HIGH, this signal indicates that the power-on
Management Unit reset signal has selected as the internal reset signal.
Writes to the Watchdog Timer module are generated from the Peripheral Bus Controller module. Figure 2.
Watchdog timer module APB write cycle summarizes this description.
69
GDC21D601
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
D a ta
P_A
Address
R e g ister
D a ta
Figure 2. Watchdog Timer Module APB Write Cycle
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D a ta
A d d ress
D a ta
Figure 3. Watchdog Timer Module APB Read Cycle
70
GDC21D601
3. Watchdog Timer Introduction
The GDC21D601 has a one-channel watchdog timer(WDT) for monitoring system operations. If a system becomes
uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an reset signal is
output to PMU.
When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer
operation, an interval timer interrupt is generated at each counter overflow.
The WDT has a clock generator which products eight counter clock sources. The clock signals are obtained by
dividing the frequency of the system clock(B_CLK). Users can select one of eight internal clock sources for input
to the TCNT by CKS2 - CKS0 in the TRCR.
Table 2. Internal Counter Clock Sources
BIT 2 - 0
(CKS2-CKS0)
000
001
010
011
100
101
110
111
CLOCK SOURCE
(SYSTEM CLOCK = 40 MHz)
The system clock is divided by 2
The system clock is divided by 8
The system clock is divided by 32
The system clock is divided by 64
The system clock is divided by 256
The system clock is divided by 512
The system clock is divided by 2048
The system clock is divided by 8192
OVERFLOW INTERVAL
12.8 us
51.2 us
204.8 us
409.6 us
1.64 ms
3.28 ms
13.11 ms
52.43 ms
71
GDC21D601
4. Watchdog Timer Operation
The Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/nIT and TMEN bits of the TRCR to 1. Software must prevent
TCNT overflow by rewriting the TCNT value(normally by writing 0x00) before overflow occurs. If the TCNT fails
to be rewritten and overflow due to a system crash or the like, INT_WDT signal and PORESET/MNRESET signal
are output. The INT_WDT signal is not output if INTEN is disabled (INTEN = 0).
TCNT
value
W T /nIT = 1
OxFF
Ox00
TMEN = 1
tim e
0 x 0 0 w r itten i n
TCNT
WTOVF = 1
F A U L T a n d internal reset generated
Figure 4. Operation in the Watchdog Timer Mode
If the RSTEN bit in the TRCR is set to 1, a signal to reset the chip will be generated internally when TCNT
overflows. Either a power-on reset or a manual reset can be selected by the RSTSEL bit.
72
GDC21D601
The Interval Timer Mode
To use the WDT as an interval timer, clear WT/nIT to 0 and set TMEN to 1. A watchdog timer interrupt
(INT_WDT) is generated each time the timer counter overflows. This function can be used to generate interval
timer interrupts at regular intervals.
TCNT
value
W T /nIT = 0
OxFF
Ox00
TMEN = 1
tim e
ITOVF = 1
W D T I N T g e n e r a ted
Figure 5. Operation in the Interval Timer Mode
4.1 Timing of Setting and Clearing the Overflow Flag
Timing of setting the overflow flag
In the interval timer mode when the TCNT overflows, the ITOVF flag is set to 1 and an watchdog timer interrupt
(INT_WDT) is requested.
In the watchdog timer mode when the TCNT overflows, the WTOVF bit of the SR is set to 1 and a WDTOUT
signal is output. When RSTEN bit is set to 1, TCNT overflow enables an internal reset signal to be generated for
the entire chip.
Timing of clearing the overflow flag
When the Reset Status Register (RSTSR) is read, the overflow flag is cleared.
73
GDC21D601
5. Watchdog Timer Memory Map
The WDT has five registers. They are used to select the internal clock source, switch to the WDT mode, control the
reset signal, and test it. The base address of the watchdog timer is fixed to 0xFFFF F100 and the offset of any
particular register from the base address is fixed.
Table 3. Memory Map of the Watchdog Timer APB Peripheral
ADDRESS
WdtBase + 0x00
WdtBase + 0x04
WdtBase + 0x08
WdtBase + 0x10
WdtBase + 0x14
74
READ LOCATION
Timer/Reset Control
Reset Status
Timer Counter
Test Output
WRITE LOCATION
Timer/Reset Control
Timer Counter
Test Input
GDC21D601
6. Watchdog Timer Register Descriptions
The following registers are provided for watchdog timer:
Timer Counter (TCNT)
8-bit readable and writable upcounter. When the timer is enabled, the timer counter starts counting pulse of the
selected clock source. When the value of the TCNT changes from 0xFF-0x00(overflows), a watchdog timer
overflow signal is generated in the both timer modes. The TCNT is initialized to 0x00 by a power-reset(nB_RES).
Timer/Reset Control Register (TRCR)
8-bit readable and writable register. The following functions are provided :
Selecting the timer mode
Selecting the internal clock source
Selecting the reset mode
Setting the timer enable bit
Being enable interrupt request
Being enable reset signal occurrence
The clock signals are obtained by dividing the frequency of the system clock.
Table 4. TRCR Bit Description
0 (clock select : CKS0)
INITIAL
VALUE
0
1 (clock select : CKS1)
2 (clock select : CKS2)
0
0
3 (reset select : RSTSEL)
0
4 (reset enable : RSTEN)
0
0 = disable
1 = enable
5 (timer enable : TMEN)
0
6 (timer mode select : WT/nIT)
0
7 (Interrupt enable : INTEN)
0
0 = disable
1 = enable
0 = interval timer mode
1 = watchdog timer mode
0 = disable
1 = enable
BIT
FUNCTION
000 =
/2
001 = /8
010 = /32
011 = /64
100 = / 256
101 = /512
110 = /2048
111 = /8192
0 = poser-on reset
1 = manual reset
select one of eight internal clock
sources for input to the TCNT.
select the type of generated internal
reset if the TCNT overflows in the
watchdog timer mode.
select whether to reset the chip
internally or not if the TCNT overflows
in the watchdog timer mode.
enable or disable the timer
select whether to use the WDT as a
watchdog timer or interval timer
enable or disable the interrupt request
75
GDC21D601
Reset Status Register (RSTSR)
Two-bit read only register. The RSTSR indicates whether TCNT is overflowed or not. The RSTSR is initialized to
0x0 by the reset signal, nB_RES.
Bit 0 (WTOVF) indicates that the TCNT has overflowed in the watchdog timer mode. Bit 1 (ITOVF) indicates that
the TCNT has overflowed in the interval timer mode.
Table 5. SR Bit Description
INITIAL
VALUE
0 (watchdog timer overflow flag : WTOVF)
0
BIT
1 (interval timer overflow flag : ITOVF)
76
0
FUNCTION
indicate that the TCNT has overflowed in the
watchdog timer mode.
indicate that the TCNT has overflowed in the
interval timer mode
GDC21D601
7. Examples of Register Setting
7.1 Interval Timer Mode
TCNT = 0x00
TRCR = 0xA0
B_CLK
MAIN_CLOCK
P_SEL
P_WRITE
P_STB
B_RES[0]
B_RES[1]
00
P_A
B8
P_D
TCNT
TCSR
FD
FE
00111000
FF
00
01
10111000
10
12
11
13
14
00111000
RSTCSR
WDTINT
FAULT
PORESET
MNRESET
OVERFLOW
Figure 6. Interrupt Clear in the Interval Timer Mode
77
GDC21D601
7.2 Watchdog Timer Mode with Internal Reset Disable
B_CLK
MAIN_CLOCK
P_SEL
P_WRITE
P_STB
B_RES[0]
B_RES[1]
P_A
P_D
TCNT
RSTCSR
TCSR
WDTINT
FAULT
PORESET
MNRESET
OVERFLOW
FD
FE
00
FF
00011111
01
¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-
TCNT = 0x00 (normally)
TRCR = 0xE0
10011111
01111000
10
00
78
11
12
13
00011111
01111000
Figure 7. Interrupt Clear in the Watchdog Timer Mode with Reset Disable
78
14
GDC21D601
7.3 Watchdog Timer Mode with Power-on Reset
B_CLK
MAIN_CLOCK
P_SEL
P_WRITE
P_STB
B_RES[0]
B_RES[1]
P_A
P_D
TCNT
RSTCSR
TCSR
WDTINT
FAULT
PORESET
MNRESET
OVERFLOW
FD
FE
00
FF
01011111
01
¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-
TCNT = 0x00
TRCR = 0xF0
11011111
01111000
10
00
78
11
12
00
11011111
00011111
01111000
00011000
Figure 8. Interrupt Clear in the Watchdog Timer Mode with Power-on Reset
79
GDC21D601
7.4 Watchdog Timer Mode with Manual Reset
B_CLK
MAIN_CLOCK
P_SEL
P_WRITE
P_STB
B_RES[0]
B_RES[1]
P_A
P_D
TCNT
RSTCSR
TCSR
WDTINT
FAULT
PORESET
MNRESET
OVERFLOW
FD
FE
00
FF
01111111
01
¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-¡-
TCNT = 0x00
TRCR = 0xF8
11111111
01111000
10
11
12
13
01111111
01111000
Figure 9. Interrupt Clear in the Watchdog Timer Mode with Manual Reset
80
14
GDC21D601
Section 10. Interrupt Controller
1. General Description
The interrupt controller has the following features :
• Asynchronous interrupt controller
• Six external interrupts
• Nineteen internal interrupts
• Low interrupt latency
• Selection of the active modes of all interrupt source inputs (Level or Edge trigger)
• Maskable for each interrupt source and output signal
• Selection of the output paths (IRQ or FIQ for each interrupt source)
nIR Q
C o n trol B lock
IRQ [25:0]
nFIQ
0
M ask R e g ister
1
T rigger M o d e R e g ister
2
T rigger Polarity R e g ister
3
D irectio n R e g ister
4
F I Q statu s R e g ister
5
IRQ status Register
6
FIQ M ask R e g ister
7
I R Q M a s k R e g ister
8
S tatu s c lear R e g ister
Bus
Interface
Internal
D a ta B u s
Figure 1. Interrupt Controller Module Block Diagram
81
GDC21D601
2. Hardware Interface and Signal Description
The Interrupt Controller module is connected to the APB bus.
Table 1. APB Signal Descriptions
NAME
TYPE
P_A[5:2]
I
P_D[26:0]
I/O
P_STB
I
P_WRITE
I
P_SEL
I
INTESource[25:0]
I
NFIQ
NIRQ
BnRES
O
O
I
82
SOURCE/
DESCRIPTION
DESTINATION
APB Bridge
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to that peripheral.
The addresses become valid before P_STB goes to HIGH and
remain valid after P_STB goes to LOW.
APB Peripherals, This is the bidirectional peripheral data bus. The data bus is driven
B_D bus
by this block during read cycles (when P_WRITE is LOW).
APB Bridge
This strobe signal is used to time all accesses on the peripheral
bus. The falling edge of P_STB is coincident with the falling edge
of B_CLK.
APB Bridge
When this signal is HIGH, it indicates a write to a peripheral.
When this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
APB Bridge
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the
system address bus (ASB). See AMBA Peripheral Bus Controller
(ARM DDI - 0044) for more details.
APB peripherals/ FIQ/IRQ interrupt signals into the Interrupt module. These active
external world
HIGH signals indicate that interrupt requests have been generated
(IRQESource[25] is internally generated in the Interrupt Controller
module and used to provide a software triggered IRQ).
ARM CORE
NFIQ interrupt input to the ARM core.
ARM CORE
NIRQ interrupt input to the ARM core.
PMU
Reset signal generated from the Power Management Unit.
GDC21D601
Writes to the Interrupt Controller module are generated from the Peripheral Bus Controller module. Figure 2.
Interrupt control module APB write cycle summarizes this.
B_CLK
P_SEL
P _ W R IT E
P_STB
P_D
D ata
P_A
A d d ress
R e g ister
D ata
Figure 2. Interrupt Control Module APB Write Cycle
83
GDC21D601
3. Interrupt Controller
3.1 Introduction
The interrupt controller provides a interface between multiple interrupt source and the processor. The interrupt
controller supports internal and external interrupt sources. Internally there are 19 peripheral interrupt sources.
Externally there are 6 interrupt sources. Therefore certain interrupt bits can be defined for the basic functionality
required in any system, while the remaining bits are available for use by other devices in any particular
implementation.
Table 2. Interrupt Controller Default Setting Value
INT #
INT 0
INT 1
INT 2
INT 3
INT 4
INT 5
INT 6
INT 7
INT 8
INT 9
INT 10
INT 11
INT 12
INT 13
INT 14
INT 15
INT 16
INT 17
INT 18
INT 19
INT 20
INT 21
INT 22
INT 23
INT 24
INT 25
INTERRUPT SOURCE
EXTERNAL INT0
EXTERNAL INT1
EXTERNAL INT2
EXTERNAL INT3
EXTERNAL INT4
EXTERNAL INT5
COM TX
COM RX
DMA
RTC
WDT
I2C0
I2C1
I2C2
UART0
UART1
Smart Card Interface
SSI CHA
SSI CHB
TIMER CHA
TIMER CHB
TIMER CHC
TIMER CHD
TIMER CHE
TIMER CHF
Software Interrupt
The Users can set the active mode of all interrupt source inputs. The default mode is the falling-edge trigger mode.
Any inversion or latching required to provide edge sensitivity must be provided at the generating source of the
interrupt.
No hardware priority scheme or any form of interrupt vectoring is provided, but the priority can be determined
using FIQ mask register and IRQ mask register under software control.
FIQ mask register and IRQ mask register are also provided to generate an interrupt under software control.
Typically these registers may be used to determine either a FIQ interrupt or an IRQ interrupt.
84
GDC21D601
3.2 Interrupt Control
The interrupt controller provides interrupt source status and interrupt request status. The interrupt mask registers
are used to determine whether an active interrupt source should generate an interrupt request to the processor or
not. A logic HIGH in the interrupt mask register indicates that the interrupt source is masked and then doesn’t
generate a request.
FIQ mask register and IRQ mask register indicate whether the interrupt source causes a processor interrupt or not.
The interrupt mode is configured by interrupt trigger mode register and interrupt trigger polarity register. And
Interrupt direction register indicates whether each interrupt source drives IRQ or FIQ.
The FIQ and IRQ status register is used to reflect the status of all channels set to produce an FIQ interrupt or IRQ
interrupt. And the status registers are cleared by writing ‘1’ to the status clear register at the edge trigger mode
only.
Source Mask
Control
Trigger Mode
Control
Polarity
Control
Direction
Control
Status
Control
Request
Control
FIQ
Mask
FIQ
IRQ source0
IRQ source1
IRQ source2
IRQ source3
IRQ source4
IRQ source5
:
:
:
:
:
:
nFIQ
Mask
Control
Edge/
Level
Control
High/
Low,
Rising/
Falling
Control
FIQ
or
IRQ
IRQ
Mask
IRQ
nIRQ
IRQ source20
IRQ source21
IRQ source22
IRQ source23
IRQ source24
IRQ source25
26
26
26
26
26
26
Clear Control
Figure 3. Interrupt Control Flow Diagram
TIC registers are used only for the production test. TIC input register is used to drive interrupt request sources by
the CPU. When this register bit 26 is set, other bits of TIC input register are regarded as interrupt sources. This bit
is cleared by system reset and should be cleared in normal operation.
Bit 25 is used as a software interrupt source. When source mask control register bit 25 is HIGH, an interrupt
request occurs. To disable the software interrupt, Source Mask Control Register bit 25 should be Low. Software
interrupt source input is fixed active HIGH and level sensitive.
85
GDC21D601
4. Interrupt Controller Memory Map
The base address of the interrupt controller is 0xFFFF F200. The offset of any particular register from the base
address is fixed.
Table 3. Memory Map of the Interrupt Controller APB Peripheral
ADDRESS
IntBase + 0x000
IntBase + 0x004
IntBase + 0x008
IntBase + 0x00C
IntBase + 0x010
IntBase + 0x014
IntBase + 0x018
IntBase + 0x01C
IntBase + 0x020
IntBase + 0x024
IntBase + 0x028
86
READ LOCATION
Mask Register
Trigger Mode Register
Trigger Polarity Register
Direction Register
FIQ Status Register (Read-only)
IRQ Status Register (Read-only)
FIQ Mask Register
IRQ Mask Register
TicOutputRegister
WRITE LOCATION
Mask Register
Trigger Mode Register
Trigger Polarity Register
Direction Register
FIQ Mask Register
IRQ Mask Register
Status Clear Register (Write-only)
TicInput Register
GDC21D601
5. Interrupt Controller Register Descriptions
The following registers are provided for both FIQ and IRQ interrupt controllers:
(1) Mask Register
Readable and Writable. The interrupt mask register is used to mask the interrupt input sources and defines which
active sources will generate an interrupt request to the processor. If certain bits within the interrupt controller are
not implemented, the corresponding bits in the interrupt mask register must be masked. A bit value 0 indicates that
the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the
interrupt is masked. Once a bit is masked, the corresponding bit in the status register is cleared. On reset, all
interrupt input sources are masked.
‘1’ : Mask
‘0’ : Unmask
Initial value : 0x3FFFFFF
25
1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
(2) Trigger Mode Register
Readable and Writable. The interrupt trigger mode register is used to configure the interrupts with the interrupt
trigger polarity register. Each interrupt can be configured to level or edge triggered. A bit value 0 indicates that the
interrupt is configured to edge triggered and a bit value 1 indicates that the interrupt is configured to level
triggered. On reset, all interrupt input sources are configured to edge triggered.
‘1’ : Level Trigger Mode
‘0’ : Edge Trigger Mode
Initial value : 0x2000000
25
1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
87
GDC21D601
(3) Trigger Polarity Register
Readable and Writable. The interrupt trigger polarity register is used to configure the interrupts with the interrupt
trigger mode register. Each interrupt can be configured to rising/high or falling/low active. A bit value 0 indicates
that the interrupt is configured to falling active for edge trigger mode and to low active for level trigger mode. A
bit value 1 indicates that the interrupt is configured to rising active for edge trigger mode and to high active for
level trigger mode. On reset, all interrupt input sources are configured to falling/low active.
‘1’ : Rising or High
‘0’ : Falling or Low
Initial value : 0x2000000
25
1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4. Interrupt Source Trigger Mode of the Interrupt Controller
TRIGGER MODE REGISTER
0
0
1
1
TRIGGER POLARITY REGISTER
0
1
0
1
DESCRIPTION
Falling-Edge (Default)
Rising-Edge
Low-Level
High-Level
(4) Direction Register
Readable and Writable. The interrupt direction register is used to determine whether each interrupt source drives
IRQ or FIQ. A bit value 0 indicates that the interrupt is driven to IRQ and a bit value 1 indicates that the interrupt
is driven to FIQ. On reset, all interrupt input sources drive IRQ.
‘1’ : Request FIQ
‘0’ : Request IRQ
Initial value : 0x0000000
25
0 0
88
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDC21D601
(5) FIQ Status Register
Read-only. The FIQ status register is used to reflect the status of all channels set to produce an FIQ interrupt
(IDR(i) = 1). When an interrupt is set for an FIQ occurring, the corresponding bit is set in FIQ status register. The
interrupt handler will examine this register to determine the channel(s) that caused the FIQ interrupt. When the
status clear register is written to ‘1’, the corresponding bit is cleared if that channel is configured to edge trigger
mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.
‘1’ : Interrupt Event Occur
‘0’ : No Interrupt Event
Initial value : 0x0000000
25
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(6) IRQ Status Register
Read-only. The IRQ status register is used to reflect the status of all channels set to produce an IRQ interrupt
(IDR(i) = 0). When an interrupt is set for an IRQ occurring, the corresponding bit is set in IRQ status register. The
interrupt handler will examine this register to determine the channel(s) that caused the IRQ interrupt. When the
status clear register is written to ‘1’, the corresponding bit is cleared if that channel is configured to edge trigger
mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.
‘1’ : Interrupt Event Occur
‘0’ : No Interrupt Event
Initial value : 0x0000000
25
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(7) FIQ Mask Register
Readable and Writable. The FIQ request mask register is used to mask the request to generate an interrupt to a
processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the FIQ
request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an
interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ
requests are unmasked.
‘1’ : Request Mask
‘0’ : Request Unmask
Initial value : 0x0000000
25
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
89
GDC21D601
(8) IRQ Mask Register
Readable and Writable. The IRQ request mask register is used to mask the request to generate an interrupt to a
processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the IRQ
request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an
interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all IRQ
requests are unmasked.
‘1’ : Request Mask
‘0’ : Request Unmask
Initial value : 0x0000000
25
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(9) Status Clear Register
Write-only. The status clear register is used to clear bits in the status register configured to the edge trigger mode.
If the channels are configured to the level trigger mode, the corresponding bits in the FIQ status register and the
IRQ status register have no effect. This register is cleared when the signal, P_STB, is LOW after this register is
written to ‘1’. When writing to this register, each data bit that is HIGH causes the corresponding bit in the status
register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the status register. Note
that the status clear register has an effect on the status register in the edge trigger mode.
‘1’ : Clear the status register
‘0’ : Not clear
Initial value : 0x0000000
25
0 0
90
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDC21D601
Section 11. Real Time Clock
1. General Description
This module is a 32-bit counter clocked by a 32.768KHz clock. This clock needs to be provided by the system,
since there is no oscillator inside the block. The clock is divided in the RTC core to provide a 1Hz clock used to
drive a 32-bit counter which forms the Real Time Clock (RTC). It also contains a 32-bit match register which can
be programmed to generate an interrupt signal when the time in the RTC matches the specific value written to this
register (alarm function - RTC event). The RTC has one event output which is synchronized with PCLK. RTCIRQ
is to be connected to the system interrupt controller.
RTCIRQ
BnRES
PCLK
PSELRTC
from/to
APB
synchronized
event output
to
interrupt
controller
PSTB
PWRITE
PA[4:2]
APB
INTERFACE
RTC
CORE
(COUNTER +
REGISTERS)
PD[31:0]
from
xtal
oscillator
CLK32K
Figure 1. Real Time Clock Connections Diagram
91
GDC21D601
2. Signal Description
The RTC module is connected to the APB bus. Table 1. APB signal descriptions describes the APB signals used
and produced.
Table 1. APB Signal Descriptions
NAME
TYPE
PCLK
I
P_A[4:2]
I
P_D[31:0]
I/O
SOURCE/
DESTINATION
Power
Management
Unit
APB Bridge
P_STB
I
APB
Peripherals,
B_D bus
APB Bridge
P_WRITE
I
APB Bridge
P_SEL
I
APB Bridge
BnRES
I
RTCIRQ
O
Power
Management
Unit
Interrupt
Controller
92
DESCRIPTION
The slow APB clock used to re-synchronize data is transferred
between the 32.768KHz clock and the APB.
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to this peripheral.
The addresses become valid before P_STB goes to HIGH and remain
valid after P_STB goes to LOW.
This is the bi-directional peripheral data bus. The data bus is driven
by this block during read cycles (when P_WRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of P_STB is coincident with the falling edge of
B_CLK.
When this signal is HIGH, it indicates a write to a peripheral. When
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). See AMBA Peripheral Bus Controller for more
details.
Reset signal generated from the PMU
Interrupt signal to the Interrupt module. When this signal is HIGH, it
indicates a valid comparison between the counter value and the match
register. It also indicates 1Hz interval with enable bit in control
register.
GDC21D601
3. Hardware Interface
The APB interface is fully APB-compliant. The APB is a non-pipelined low-power interface designed to provide a
simple interface to slave peripherals.
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
D a ta
P_A
A d d ress
R e g ister
D a ta
Figure 2. RTC Module APB Write Cycle
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D a ta
A d d ress
D a ta
Figure 3. RTC Module APB Read Cycle
93
GDC21D601
4. Functional Description
The counter is loaded by writing it to the RTC data register. The counter will count up on each rising edge of the
clock and loops back with 0 when the maximum value (0xFFFFFFFF) is reached. At any moment the counter
value can be obtained by reading the RTC data register.
The value of the match register can also be read at any time, and the read does not affect the counter value. The
status of the interrupt signal is available in the status register. The status bit is set if a comparator match event has
occurred or 1 second has elapsed. Reading from the status register will clear the status register.
Module core
A
P
B
B
u
s
Interface to APB
Data In
RTC
APB
registers
RTC
Counter
RTCIRQ
32-bit
comparator
Data Out
Match
register
PCLK
Sync
Control
1Hz
Ripple
Counter
CLK32K
Figure 4. RTC Block Diagram
94
GDC21D601
5. Real Time Clock Memory Map
The base address of the RTC is fixed as 0xFFFF F300 and the offset of any particular register from the base
address is fixed.
Table 2. RTC Memory Map
ADDRESS
RTC Base + 0x00
RTC Base + 0x04
RTC Base + 0x08
RTC Base + 0x0C
RTC Base + 0x10
RTC Base + 0x14
RTC Base + 0x18
RTC Base + 0x1C
READ LOCATION
RTC data register (RTCDR)
RTC match register (RTCMR)
RTC status (RTCS)
RTC clock divider (RTCDV)
RTC control register (RTCCR)
WRITE LOCATION
RTC data register (RTCDR)
RTC match register (RTCMR)
RTC clock divider (RTCDV)
RTC control register (RTCCR)
RTC Tic selection register (RTCTS)
TicCLK32K
TicCLKPCLK
Note The RTC clock divider register may only be written to when in test mode.
6. Real Time Clock Register Descriptions
The following user registers are provided :
RTC Data Register (RTCDR)
Read/Write. Writing to this 32-bit register will load the counter. A read will give the current value of the
counter.
RTC Match Register (RTCMR)
Read/Write. Writing to this 32-bit register will load the match register. This value can also be read back.
RTC Status Register (RTCS)
Read-only. When performing a read from this location the interrupt flag will be cleared. If a match event occurs,
bit[1] will be set. For a second event, bit[0] will be set. This register is affected by the control register.
RTC Clock Divider (RTCDV)
Read/Write. The reads to the register will return only four bits of the clock divider output. Bits [3:0] will return
bits (14, 11, 7, 3) of the divider output. Writing zero to bit[0] clears this divider.
RTC Control Register (RTCCR)
Read/Write. This register enables the interrupt. Bit[1] enables the match event interrupt (default disable = 0).
Bit[0] enables second event interrupt (default disable = 0).
RTC Tic Selection (RTCTS)
Write-only. This register is for production test purposes. Bit[0] enables TicCLK32K for 32kHz clock
replacement. Bit[1] enables TicCLKPCLK for PCLK clock replacement.
TicCLK32K
Write-only. This generates 32kHz clock for production test purposes.
TicCLKPCLK
Write-only. This generates PCLK clock for production test purposes.
95
GDC21D601
Section 12. General Purpose Timer Unit
1. General Description
The general-purpose timer unit has:
• Six channels with 16bit counter
• 12 different pulse outputs and 12 different pulse inputs
• Independent function with 12 general registers
• Compare match waveform output function
• Input capture function
• Counter-clearing function at compare match or input capture mode
• Synchronizing mode
• PWM mode
• 18 interrupt sources
• Selectable 4 internal clock sources and 4 external clock sources
EXT_CLK1- EXT_CLK4
Clock
Generation
TCIO0A - TCIO5A
TCIO0B - TCIO5B
Clock
Selection
TINT0 - TINT5
TSTARTR
TSYNR
TPWMR
Bus Interface
16-bit timer channel4
16-bit timer channel3
16-bit timer channel1
16-bit timer channel0
Control
16-bit timer channel2
pclk
Module data bus
Figure 1. General-purpose Timer Unit Module Block Diagram
96
Internal
data bus
GDC21D601
2. Hardware Interface and Signal Description
The General-purpose Timer Unit module is connected to the APB bus.
Table 1. APB Signal Descriptions
NAME
TYPE
PCLK
BnRES
PA[7:2]
I
I
I
PD[31:0]
I/O
SOURCE/
DESTINATION
PMU
PMU
APB Bridge
PSTB
I
APB Peripherals,
B_D bus
APB Bridge
PWRITE
I
APB Bridge
PSEL
I
APB Bridge
EXT_CLK1
I
External
EXT_CLK2
I
External
EXT_CLK3
I
External
EXT_CLK4
I
External
TCIO0A
I/O
External
TCIO0B
I/O
External
TCIO1A
I/O
External
TCIO1B
I/O
External
TCIO2A
I/O
External
TCIO2B
I/O
External
DESCRIPTION
Peripheral clock. This clock times all bus transfers.
Reset signal generated from the PMU
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to that peripheral.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the bi-directional peripheral data bus. This block drives the
data bus during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of
PCLK.
When this signal is HIGH, it indicates a write to a peripheral. When
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, it indicates that the APB bridge has
selected this module. This selection is a decode result of the system
address bus (ASB). See AMBA Peripheral Bus Controller for more
details.
External clock1 input. This signal is selected independently from
EXT_CLK2, EXT_CLK3, and EXT_CLK4.
External clock2 input. This signal is selected independently from
EXT_CLK1, EXT_CLK3, and EXT_CLK4.
External clock3 input. This signal is selected independently from
EXT_CLK1, EXT_CLK2, and EXT_CLK4
External clock4 input. This signal is selected independently from
EXT_CLK1, EXT_CLK2, and EXT_CLK3.
This signal is used as GRA0 input in input capture mode, GRA0
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB0 input in input capture mode, GRB0
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRA1 input in input capture mode, GRA1
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB1 input in input capture mode, GRB1
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRA2 input in input capture mode, GRA2
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB2 input in input capture mode, GRB2
output in output compare mode, and PWM output in PWM mode.
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GDC21D601
TCIO3A
I/O
SOURCE/
DESTINATION
External
TCIO3B
I/O
External
TCIO4A
I/O
External
TCIO4B
I/O
External
TCIO5A
I/O
External
TCIO5B
I/O
External
NAME
TYPE
TINT0
O
TINT1
O
TINT2
O
TINT3
O
TINT4
O
TINT5
O
98
Interrupt
Controller
Interrupt
Controller
Interrupt
Controller
Interrupt
Controller
Interrupt
Controller
Interrupt
Controller
DESCRIPTION
This signal is used as GRA3 input in input capture mode, GRA3
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB3 input in input capture mode, GRB3
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRA4 input in input capture mode, GRA4
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB4 input in input capture mode, GRB4
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRA5 input in input capture mode, GRA5
output in output compare mode, and PWM output in PWM mode.
This signal is used as GRB5 input in input capture mode, GRB5
output in output compare mode, and PWM output in PWM mode.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel0.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel1.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel2.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel3.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel4.
Interrupt signal to the Interrupt Controller module. This signal
indicates that an interrupt has been generated in channel5.
GDC21D601
The writes to the General-purpose Timer Unit module are generated from the Peripheral Bus Controller module.
Figure 2. General-purpose timer unit module APB write cycle summarizes this.
PCLK
PSEL
PWRITE
PSTB
PD
PA
Register
Data
Address
Data
Figure 2. General-Purpose Timer Unit Module APB Read Cycle
B_CLK
P_SEL
P_WRITE
P_STB
P_D
Data
P_A
Address
Register
Data
Figure 3. General-Purpose Timer Unit Module APB Write Cycle
99
GDC21D601
3. General Purpose Timer Unit Introduction
The GDC21D601 has a general-purpose timer unit (GPTU) with six channels of 16-bit timer. There are two
counter operation modes: a free running mode and a periodic mode. And each channel has independent operating
modes. There are common functions for each channel: counter operation, input capture, compare match, PWM,
and synchronized clear and write.
It is possible to select one of eight counter clock sources for all channels.
• Internal clock : counting at falling edge
BCLK / 2
BCLK / 4
BCLK / 16
BCLK / 64
• External clock: counting at rising, falling, or both edge that are user-selectable.
There are four kinds of counter clear sources which can be selected by user’s setting.
• None : never clear until overflow for free running mode
• GRA match or TPA input capture
• GRB match or TPB input capture
• Synchronous clear
100
GDC21D601
4. General Purpose Timer Unit Operation
The operation modes are described below.
Free Running Mode
Each channel can run from 0 to FFFF repeatedly. When it reaches FFFF, the interrupt signal is generated as user's
setting.
Compare Match Mode
Each channel has 2 general registers and user can read or write from/to the registers. If user wrote some values to
general register, and the counter reached that value, the channel generates interrupt and external output by user's
setting. The output value can be '1', '0', or toggle value. The counter can be cleared by user's setting when the
match with general register is detected.
Input Capture Mode
When set to input capture mode and rising any event at TPA or TPB, the counter value is transferred to GRA or
GRB respectively. The interrupt can be generated and the external event may be rising edge, falling edge or any
edge by user's setting. The counter can be cleared by user's setting when the event at TPA or TPB is detected.
Synchronized Clear & Write Mode
When some channels are set to synchronization mode, and one of them is cleared by compare match or input
capture, the other channels can be cleared simultaneously by user's setting. When some channels are set to
synchronization mode and user would write any value to one of them, the other channels can be written with same
value simultaneously by user's setting.
PWM Mode
When a channel is set to PWM mode, the channel operates like a compare match mode and the output on compare
match event is generated only at TPA. The TPA value is '1' when it is the match with GRA, and '0' when it is the
match with GRB.
101
GDC21D601
5. General Purpose Timer Unit Memory Map
The base address of the general-purpose timer unit is 0xFFFFF400 and the offset of any particular register from the
base address is fixed.
Table 2. General Purpose Timer Unit Register Memory Map
ADDRESS
Gptu Base + 0x00
Gptu Base + 0x04
Gptu Base + 0x08
Gptu Base + 0x0C
Gptu Base + 0x10
Gptu Base + 0x14
Gptu Base + 0x18
Gptu Base + 0x20
Gptu Base + 0x24
Gptu Base + 0x28
Gptu Base + 0x2C
Gptu Base + 0x30
Gptu Base + 0x34
Gptu Base + 0x38
Gptu Base + 0x40
Gptu Base + 0x44
Gptu Base + 0x48
Gptu Base + 0x4C
Gptu Base + 0x50
Gptu Base + 0x54
Gptu Base + 0x58
Gptu Base + 0x60
Gptu Base + 0x64
Gptu Base + 0x68
Gptu Base + 0x6C
Gptu Base + 0x70
Gptu Base + 0x74
Gptu Base + 0x78
Gptu Base + 0x80
Gptu Base + 0x84
Gptu Base + 0x88
Gptu Base + 0x8C
Gptu Base + 0x90
Gptu Base + 0x94
Gptu Base + 0x98
Gptu Base + 0xA0
Gptu Base + 0xA4
Gptu Base + 0xA8
Gptu Base + 0xAC
Gptu Base + 0xB0
Gptu Base + 0xB4
Gptu Base + 0xB8
102
READ LOCATION
TSTARTR
TSYNCR
TPWMR
WRITE LOCATION
TSTARTR
TSYNCR
TPWMR
TSTINR
TSTOUTR
TSTMODER
TSTINTR
TCONTR0
TIOCR0
TIER0
TSTATUSR0
TCOUNT0
GRA0
GRB0
TCONTR1
TIOCR1
TIER1
TSTATUSR1
TCOUNT1
GRA1
GRB1
TCONTR2
TIOCR2
TIER2
TSTATUSR2
TCOUNT2
GRA2
GRB2
TCONTR3
TIOCR3
TIER3
TSTATUSR3
TCOUNT3
GRA3
GRB3
TCONTR4
TIOCR4
TIER4
TSTATUSR4
TCOUNT4
GRA4
GRB4
TCONTR0
TIOCR0
TIER0
TCOUNT0
GRA0
GRB0
TCONTR1
TIOCR1
TIER1
TCOUNT1
GRA1
GRB1
TCONTR2
TIOCR2
TIER2
TCOUNT2
GRA2
GRB2
TCONTR3
TIOCR3
TIER3
TCOUNT3
GRA3
GRB3
TCONTR4
TIOCR4
TIER4
TCOUNT4
GRA4
GRB4
GDC21D601
ADDRESS
Gptu Base + 0xD0
Gptu Base + 0xD4
Gptu Base + 0xD8
Gptu Base + 0xDC
Gptu Base + 0xE0
Gptu Base + 0xE4
Gptu Base + 0xE8
READ LOCATION
TCONTR5
TIOCR5
TIER5
TSTATUSR5
TCOUNT5
GRA5
GRB5
WRITE LOCATION
TCONTR5
TIOCR5
TIER5
TCOUNT5
GRA5
GRB5
103
GDC21D601
6. General Purpose Timer Unit Register Descriptions
The following registers are provided for general purpose timer unit :
Timer Start Register (TSTARTR)
Eight-bit readable and writable register that starts and stops the counter of each channel.
Table 3. TSTARTR Bit Description
BIT
7 (reserved)
6 (reserved)
5 (STR5)
4 (STR4)
3 (STR3)
2 (STR2)
1 (STR1)
0 (STR0)
INITIAL
VALUE
1
1
0
0
0
0
0
0
FUNCTION
1 = start counting
0 = stop counting
start and stop counting
Timer Synch. Register (TSYNCR)
Eight-bit readable and writable register that selects timer synchronizing mode for each channel.
Table 4. TSYNCR Bit Description
BIT
7 (reserved)
6 (reserved)
5 (SYNC5)
4 (SYNC4)
3 (SYNC3)
2 (SYNC2)
1 (SYNC1)
0 (SYNC0)
104
INITIAL
VALUE
1
1
0
0
0
0
0
0
FUNCTION
0 = operate independently
1 = operate synchronously with
other sync. channel
select the synchronizing mode
GDC21D601
Timer PWM Mode Register (TPWMR)
Eight-bit readable and writable registers that select the PWM mode for each channel.
Table 5. TPWMR Bit Description
BIT
7 (reserved)
6 (reserved)
5 (PWM5)
4 (PWM4)
3 (PWM3)
2 (PWM2)
1 (PWM1)
0 (PWM0)
INITIAL
VALUE
1
1
0
0
0
0
0
0
FUNCTION
0 = operate normally
1 = operate in PWM mode
select the PWM mode
Timer Control Register (TCONTR)
Eight-bit readable and writable register for each channel that selects the timer counter clock source, the edges of
the external clock source, and the counter clear source.
Table 6. TCONTR Bit Description
7 (reserved)
6 (CCLR1)
5 (CCLR0)
INITIAL
VALUE
1
0
0
4 (reserved)
3 (reserved)
2 (TPSC2)
1 (TPSC1)
0 (TPSC0)
1
1
0
0
0
BIT
FUNCTION
00 = not cleared - Free running mode
01 = cleared by GRA compare match or input
capture - Periodic mode
10 = cleared by GRB compare match or input
capture - Periodic mode
11 = cleared in synchronization with other sync.
timer
Select the counter clear source
000 = internal clock 1 (BCLK/2)
001 = internal clock 2 (/4)
010 = internal clock 3 (/16)
011 = internal clock 4 (/64)
100 = external clock 1 (Ext_clk1)
101 = external clock 2 (Ext_clk2)
110 = external clock 3 (Ext_clk3)
111 = external clock 4 (Ext_clk4)
select the counter clock source
105
GDC21D601
Timer I/O Control Register (TIOCR)
Eight-bit readable and writable register that selects the output compare or input capture function for GRA and
GRB, and selects the function of the TP#A and TP#B pins. TIOCR# controls the GRs.
Table 7. TIOCR Bit Description
7 (reserved)
6 (IOB2)
5 (IOB1)
4 (IOB0)
INITIAL
VALUE
1
0
0
0
3 (reserved)
2 (IOA2)
1 (IOA1)
0 (IOA0)
1
0
0
0
BIT
FUNCTION
000 = compare match with pin output disabled
001 = 0 output at GRB compare match
010 = 1 output at GRB compare match
011 = toggle output at GRB compare match
100 = GRB captures the rising edge of input
101 = GRB captures the falling edge of input
110 = GRB captures both edge of input
select the GRB function
000 = compare match with pin output disabled
001 = 0 output at GRA compare match
010 = 1 output at GRA compare match
011 = toggle output at GRA compare match
100 = GRA captures rising edge of input
101 = GRA captures falling edge of input
110 = GRA captures both edge of input
select the GRA function
Timer Interrupt Enable Register (TIER)
Eight-bit readable and writable register that controls the enabling/disabling of overflow interrupt request and the
general register compare match/input capture interrupt requests. TIER# controls the interrupt enable/disable.
Table 8. TIER Bit Description
7 (reserved)
6 (reserved)
5 (reserved)
4 (reserved)
3 (reserved)
2 (OVFIE)
INITIAL
VALUE
1
1
1
1
1
0
1 (MCIBE)
0
0 (MCIAE)
0
BIT
106
FUNCTION
0 = disable interrupt requests by the OVFI
1 = enable interrupt requests from the OVFI
0 = disable interrupt requests by the MCIB
1 = enable interrupt requests from the MCIB
0 = disable interrupt requests by the MCIA
1 = enable interrupt requests from the MCIA
GDC21D601
Timer Status Register (TSTATUSR)
Eight-bit readable register contains the flags that indicate TCOUNT overflow/underflow and GRA/GRB compare
match or input capture. This flags are interrupt sources.
Table 9. TIER Bit Description
BIT
7 (reserved)
6 (reserved)
5 (reserved)
4 (reserved)
3 (reserved)
2 (OVFI)
INITIAL
VALUE
1
1
1
1
1
0
1 (MCIB)
0
0 (MCIA)
0
FUNCTION
0 = clear condition
1 = setting condition
indicate TCOUNT overflow/underflow
indicate a GRB compare match or
input capture
indicate a GRA compare match or
input capture
Timer Counter (TCOUNT)
16-bit readable and writable counter. The clock source is selected by TCONTR of each channel. TCOUNT is
cleared to 0x0000 by compare match with the corresponding GRA or GRB, or by input capture to GRA or GRB.
When TCOUNT is overflow or underflow, OVFI in the TSTATUSR is set to ‘1’.
TCNT0 (16 bit) : upcounter
TCNT1 (16 bit) : upcounter
TCNT2 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
TCNT0 (16 bit) : upcounter
General Register A, B (GRA, GRB)
16-bit readable and writable register. There are 2 general registers for each channel (total 12). Each general register
can function as either an output compare register or an input capture register by setting it in the TIOCR.
107
GDC21D601
7. Examples of Register Setting
7.1 Six Channels
Channel 0 : In free-running counter (Compare match - 0 output at GRB and 1 output at GRA)
Channel 1 : In a periodic counter cleared by GRB ( Compare match - Toggle output at GRA and GRB)
Channel 2 : In a periodic counter cleared by TPB ( Input capture - TPA with both edges, TPB with the falling edge)
Channel 3 : In a periodic counter cleared by GRA ( PWM mode )
Channel 4 : In a periodic counter cleared by GRA ( PWM mode : duty cycle 0% )
Channel 5 : In a periodic counter cleared by GRA ( PWM mode : duty cycle 100%)
# Setting example
RESET
.
.
TSTART = 0xC0;
TCONTR0 = 0x81;
TCONTR1 = 0xC2;
TCONTR2 = 0xC3;
TCONTR3 = 0xA5;
TCONTR4 = 0xCE;
TCONTR5 = 0xBF;
TIER0 = 0xFB;
TIER1 = 0xFA;
TIER2 = 0xFA;
TIER3 = 0xFB;
TIER4 = 0xFB;
TIER5 = 0xFB;
TIOCR0 = 0x9A;
TIOCR1 = 0xBB;
TIOCR2 = 0xDF;
TCOUNT0 = 0xFFF0;
TCOUNT1 = 0xFFF0;
TCOUNT2 = 0x0000;
TCOUNT3 = 0x0000;
TCOUNT4 = 0x0000;
TCOUNT5 = 0x0000;
GRA0 = 0xFFF4;
GRA1 = 0xFFF2;
GRA3 = 0x0A;
GRA4 = 0x04;
GRA5 = 0x0A;
GRB0 = 0xFFFA;
GRB1 = 0xFFF5;
GRB3 = 0x04;
GRB4 = 0x0A;
GRB5 = 0x04;
TPWMR = 0xF8;
TSTARTR = 0xFF;
.
{Running...}
108
//internal clock2
//internal clock3
//internal clock4
//external clock2 - rising edge
//external clock3 - falling edge
//external clock4 - both edge
//enable interrupt requests from
//enable interrupt requests from
//enable interrupt requests from
//enable interrupt requests from
//enable interrupt requests from
//enable interrupt requests from
the
the
the
the
the
the
MCIA,
MCIA
MCIA
MCIA,
MCIA,
MCIA,
MCIB
MCIB
MCIB
MCIB
GDC21D601
7.2 Free-Running Mode
# Setting example
TSTARTR
TCONTR4
TIER4 =
TCOUNT4
TSTARTR
= 0xC0;
= 0x80;
0xFC;
= 0xFFF0;
= 0xD0;
7.3 Periodic Mode
: GRA compare match
# Setting example
TSTARTR = 0xC0;
TCONTR4 = 0xA0;
TIER4 = 0xF9;
TCOUNT4 = 0x0000;
GRA4 = 0x0F;
TSTARTR = 0xD0;
7.4 Synchronizing Mode
: In a periodic mode counter cleared by GRA of channel0
In a periodic mode counter cleared by GRB of channel1
In a periodic mode counter cleared, synchronized with other sync. timer (channel2, 3, 4, 5)
Toggle output at GRA of channel0, 2, 4
Toggle output at GRB of channel1, 3, 5
# Setting example
TSTARTR = 0xC0;
TCONTR0 = 0xA0;
TCONTR1 = 0xC1;
TCONTR2 = 0xE0;
TCONTR3 = 0xE1;
TCONTR4 = 0xE0;
TCONTR5 = 0xE1;
TIOCR0 = 0x8B;
TIOCR1 = 0xB8;
TIOCR2 = 0x8B;
TIOCR3 = 0xB8;
TIOCR4 = 0x8B;
TIOCR5 = 0xB8;
TIER0 = 0xFD;
TIER1 = 0xFE;
109
GDC21D601
TIER2 = 0xFD;
TIER3 = 0xFE;
TIER4 = 0xFD;
TIER5 = 0xFE;
TCOUNT0 = 0xFF10;
TCOUNT1 = 0xFF11;
TCOUNT2 = 0xFF12;
TCOUNT3 = 0xFF13;
TCOUNT4 = 0xFF14;
TCOUNT5 = 0xFF15;
GRA0 = 0xFF1A;
GRB1 = 0xFF15;
GRA2 = 0xFF1C;
GRB3 = 0xFF1D;
GRA4 = 0xFF1E;
GRB5 = 0xFF1F;
TSYNCR = 0xFF;
TSTARTR = 0xFF;
110
GDC21D601
Section 13. PIO
1. General Description
The PIO is an APB peripheral which provides 80 bits of programmable input /output divided into ten 8-bit ports ;
port A, port B, port C, port D, port E, port F, port G, port H, port I, and port J. Each pin is configurable as either
input or output. At system reset, port A, C, E, G, I set their defaults to input and port B, D, F, H, J set their defaults
to output.
P o rt
A
D a ta
Reg.
P D [7:0]
PA [ 7 : 2 ]
A P B I/F
BnRES
PSEL
PSTB
P W R ITE
P o rt
A
D ir.
Reg.
P o rt
B
D a ta
Reg.
P o rt
B
D ir.
Reg.
E PA [ 7 : 0
PA [ 7 : 0 ]
P o rt A
PA O E [ 7 : 0 ]
E P B [7:0
P B [7:0]
P o rt B
P B O E [7:0]
Figure 1. PIO Block Diagram and PADS Connections( Port A and Port B)
Each port has a data register and a data direction register that both are 8 bits wide. The data direction register
defines whether each individual pin is an input or an output. The data register is used to read the value of the PIO
pins, both input and output, as well as to set the values of pins that are configured as outputs.
111
GDC21D601
2. Signal Description
The PIO module is connected to the APB bus. Table 1. Signal descriptions describe the APB signals used and
produced. Table 2. Specific block signal descriptions show the non-AMBA signals from the block.
Table 1. Signal Descriptions
NAME
TYPE
BnRES
PA[7:2]
I
I
PD[7:0]
I/O
SOURCE/
DESTINATION
PMU
APB Bridge
PSTB
I
APB
Peripherals, BD
bus
APB Bridge
PWRITE
I
APB Bridge
PSEL
I
APB Bridge
112
DESCRIPTION
This signal indicates a power on reset status of the bus (active LOW).
This is the part of the peripheral address bus, which is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. The data bus is
driven by this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of BCLK
(ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral and when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, it indicates the PIO module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). For more details, see AMBA Peripheral Bus
Controller
GDC21D601
Table 2. Specific Block Signal Descriptions
PA[7:0]
O
SOURCE/
DESTINATION
PADS
EPA[7:0]
I
PADS
PAOE[7:0]
O
PADS
PB[7:0]
O
PADS
EPB[7:0]
I
PADS
PBOE[7:0]
O
PADS
PC[7:0]
O
PADS
EPC[7:0]
I
PADS
PCOE[7:0]
O
PADS
PD[7:0]
O
PADS
EPD[7:0]
I
PADS
PDOE[7:0]
O
PADS
PE[7:0]
O
PADS
EPE[7:0]
I
PADS
PEOE[7:0]
O
PADS
PF[7:0]
O
PADS
EPF[7:0]
I
PADS
PFOE[7:0]
O
PADS
NAME
PG[7:0]
TYPE
Out
PADS
DESCRIPTION
Port A output driver. Values written on PADR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set to HIGH (PADDR register).
Port A input driver. It reflects the external state of the port. This
information is obtained when the PADR register is read.
Port A output enable (active LOW). Values written on PADDR
register are put onto these lines.
Port B output driver. Values written on PBDR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set to HIGH (PBDDR register).
Port B input driver. It reflects the external state of the port. This
information is obtained when the PBDR register is read.
Port B output enable (active LOW). Values written on PBDDR register
are put onto these lines.
Port C output driver. Values written on PCDR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set HIGH (PCDDR register).
Port C input driver. It reflects the external state of the port. This
information is obtained when the PCDR register is read.
Port C output enable (active LOW). Values written on PCDDR register
are put onto these lines.
Port D output driver. Values written on PDDR register are put onto
these lines and driven out to the port D pins if the corresponding data
direction bits are set to HIGH (PDDDR register).
Port D input driver. It reflects the external state of the port. This
information is obtained when the PDDR register is read.
Port D output enable (active LOW). Values written on PDDDR
register are put onto these lines.
Port E output driver. Values written on PEDR register are put onto
these lines and driven out to the port E pins if the corresponding data
direction bits are set to HIGH (PEDDR register).
Port E input driver. It reflects the external state of the port. This
information is obtained when the PEDR register is read.
Port E output enable (active LOW). Values written on PEDDR register
are put onto these lines.
Port F output driver. Values written on PFDR register are put onto
these lines and driven out to the port F pins if the corresponding data
direction bits are set to HIGH (PFDDR register).
Port F input driver. It reflects the external state of the port. This
information is obtained when the PFDR register is read.
Port F output enable (active LOW). Values written on PFDDR register
are put onto these lines.
Port G output driver. Values written on PGDR register are put onto
these lines and driven out to the port G pins if the corresponding data
direction bits are set to HIGH (PGDDR register).
113
GDC21D601
EPG[7:0]
I
SOURCE/
DESTINATION
PADS
PGOE[7:0]
O
PADS
PH[7:0]
O
PADS
EPH[7:0]
I
PADS
PHOE[7:0]
O
PADS
PI[7:0]
O
PADS
EPI[7:0]
I
PADS
PIOE[7:0]
O
PADS
PJ[7:0]
O
PADS
EPJ[7:0]
I
PADS
PJOE[7:0]
O
PADS
NAME
114
TYPE
DESCRIPTION
Port G input driver. It reflects the external state of the port. This
information is obtained when the PGDR register is read.
Port G output enable (active LOW). Values written on PGDDR
register are put onto these lines.
Port H output driver. Values written on PHDR register are put onto
these lines and driven out to the port H pins if the corresponding data
direction bits are set to HIGH (PHDDR register).
Port H input driver. It reflects the external state of the port. This
information is obtained when the PHDR register is read.
Port H output enable (active LOW). Values written on PHDDR
register are put onto these lines.
Port I output driver. Values written on PIDR register are put onto these
lines and driven out to the port I pins if the corresponding data
direction bits are set to HIGH (PIDDR register).
Port I input driver. It reflects the external state of the port. This
information is obtained when the PIDR register is read.
Port I output enable (active LOW). Values written on PIDDR register
are put onto these lines.
Port J output driver. Values written on PJDR register are put onto these
lines and driven out to the port J pins if the corresponding data
direction bits are set to HIGH (PJDDR register).
Port J input driver. It reflects the external state of the port. This
information is obtained when the PJDR register is read.
Port J output enable (active LOW). Values written on PJDDR register
are put onto these lines.
GDC21D601
3. Hardware Interface
The APB interface is fully APB-compliant. The APB is a non-pipelined low-power interface, designed to provide a
simple interface to slave peripherals.
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
P_A
R egister
D ata
A d d ress
D ata
Figure 1. APB Read
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
Data
P_A
A d d ress
R e g ister
Data
Figure 2. APB Write
115
GDC21D601
4. Functional Description
All block registers are cleared during power on reset (BnRES LOW).
This disables the output drivers for port A, C, E, G and I (input as default) and enables the drivers for port B, D, F,
H, and J (output as default).
For each port there is a Data Register and a Data Direction Register. On reads, the Data Register contains the
current status of correspondent port pins whether they are configured as input or output. Writing to a Data Register
only affects the pins that are configured as outputs.
The Data Direction Registers operates in a different manner on each port:
• For every port, a “0” in the data direction register indicates the port is defined as an output (default), a “1” in the
data direction register indicates the port is defined as an input.
116
GDC21D601
5. Programmer’ s Model
5.1 PIO Registers
The following user registers are provided:
PnDR
Port n Data Register. Values written to this 8-bit read/write register will be output on port A pins if the
corresponding data direction bits are set to HIGH (port output). Values read from this register reflect
the external states of port n, not necessarily the value should be written to it. All bits are cleared by a
system reset.
PnDDR
Port n Data Direction Register. Bits set in this 8-bit read/write register will select the corresponding
pins in port n to become an output, clearing a bit sets the pin to input. All bits are cleared by a system
reset.
n : A, B, C, D, E, F, G, H, I and J
5.2 Register Memory Map
The base address of the PIO is 0xFFFF FC00 and the offset of any particular register from the base address is
determined.
Table 3. PIO Register Memory Map
ADDRESS
PIO Base + 0x00
PIO Base + 0x04
PIO Base + 0x08
PIO Base + 0x0c
PIO Base + 0x10
PIO Base + 0x14
PIO Base + 0x18
PIO Base + 0x1c
PIO Base + 0x20
PIO Base + 0x24
PIO Base + 0x28
PIO Base + 0x2c
PIO Base + 0x30
PIO Base + 0x34
PIO Base + 0x38
PIO Base + 0x3c
PIO Base + 0x40
PIO Base + 0x44
PIO Base + 0x48
PIO Base + 0x4c
READ LOCATION
PADR register
PADDR register
PBDR register
PBDDR register
PCDR register
PCDDR register
PDDR register
PDDDR register
PEDR register
PEDDR register
PFDR register
PFDDR register
PGDR register
PGDDR register
PHDR register
PHDDR register
PIDR register
PIDDR register
PJDR register
PJDDR register
WRITE LOCATION
PADR register
PADDR register
PBDR register
PBDDR register
PCDR register
PCDDR register
PDDR register
PDDDR register
PEDR register
PEDDR register
PFDR register
PFDDR register
PGDR register
PGDDR register
PHDR register
PHDDR register
PIDR register
PIDDR register
PJDR register
PJDDR register
117
GDC21D601
Section 14. Synchronous Serial Peripheral Interface
1. General Description
The synchronous serial interface (SSPI) is a high-speed synchronous serial I/O system. The SSPI can be used for
simple I/O expansion or for allowing several MCUs to be interconnected in a multi-master configuration. Clock
polarity, clock phase, chip select polarity, and MSB /LSB first ordering are software programmable to allow direct
compatibility with a large number of peripheral devices. The SSPI system can be configured as either a master or a
slave.
SSPI IRQ
To Interrupt Controller
From
ASB
BnRES
SSICS
PSEL
PSTB
PWRITE
From/to
APB
APB
INTERFACE
Tx
16*8 FIFO
SSIOUT
SSCR1
PA[5:2]
SSSR
PD[7:0]
SSDR
PCLK
From
clock
generator
SSCR0
SSIIN
Rx
16*8 FIFO
SSTR
clock
scaler
SSICLK
Figure 1. Signal Connections of the SSPI
An 8-bit shift register feeds the output channel, SSIOUT. During transfers, the BUSY bit in the system status
register SSSR is set. Valid data can be read from a 16-bit shift register when the BUSY bit is cleared. There is also
an interrupt signal, SSIIRQ, which is asserted at the end of data transfer. Reading data clears the interrupt signal.
118
GDC21D601
2. Signal Description
The SSPI module is connected to the APB bus. Table 1. Signal descriptions describe the APB signals used and
produced. Table 2. Signal descriptions show the non-AMBA signals from the block.
Table 1. Signal Descriptions
NAME
TYPE
BnRES
PA[5:2]
I
I
PD[7:0]
I/O
SOURCE/
DESTINATION
PMU
APB Bridge
PSTB
I
APB Peripherals,
B_D
APB Bridge
PWRIT
E
I
APB Bridge
PSEL
I
APB Bridge
DESCRIPTION
ASB reset signal (active LOW).
This is the part of the peripheral address bus, and is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. This block
drives the data bus during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of
B_CLK (ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral, when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, this signal indicates that the APB bridge
has selected the SSPI module. This selection is a decode result of
the system address bus. For more details, see AMBA Peripheral Bus
Controller.
Table 2. Specific Block Signal Descriptions
NAME
TYPE
CLK
SSIIN
SSIOUT
SSICS
SCLK
SSIIRQ
I
I
O
I/O
I/O
O
SOURCE/
DESTINATION
PMU
SSIIN pad
SSIOUT pad
SSICS pad
SCLK pad
Interrupt
Controller
DESCRIPTION
SSPI clock input at a frequency of 3.68MHz., scaled /4, /8, /32, /64
Serial data input.
Serial data output.
Chip select signal.
Serial data clock to the external SSI.
Active HIGH Interrupt Request.
119
GDC21D601
3. Hardware Interface
The APB interface is fully APB-compliant. The APB is a non-pipelined low-power interface, designed to provide a
simple interface to slave peripherals.
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D a ta
A d d ress
D a ta
Figure 2. APB Read
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D ata
A d d ress
D ata
Figure 3. APB Write
120
GDC21D601
4. Functional Description
The following user registers are provided:
SSCR
SS Control Register. In the synchronous mode, data transfer is synchronized with a clock pulse. This
mode is suitable for continuous, high-speed serial communication.
• Data length: 8 bits per character.
• Uses the built-in baud rate generator as the transmit clock.
• Support both LSB first and MSB first (receive and send).
Writing to the SSCR register controls the SSPI. A write is encoded as follows.
BIT
7
6
5
4
3
2
1
0
NAME
FUNCTION
Default 1 : normal mode, 0: test mode
Default 1 : CS Polarity(low), 0: high
Default 1 : SSI enable signal
Default 1 : Master Mode , 0: slave mode
Default 1 : MSB first sin (1: MSB First, 0: LSB First)
Default 1 : MSB first sout (1: MSB First,0:LSB First)
Default 1 : Clock Polarity
Default 1 : CS enable ( use only when slave mode)
Tstmode
CS_POL
SSI_EN
MS_MODE
SIN_MSB
SOUT_MSB
CK_POL
CS_EN
SSCR0 Registers (write)
BIT
7
6
5
4
3
2
1
0
NAME
TX end interrupt enable
TX fifo empty interrupt enable
RX fifo full interrupt enable
TX fifo full interrupt enable
Rx fifo enable
Tx fifo enable
CKSEL1
CKSEL0
FUNCTION
Default 0 : disable 1: enable
Default 0 : disable 1: enable
Default 0 : disable 1: enable
Default 0 : disable 1: enable
Default 0 : disable 1: enable
Default 0 : disable 1: enable
Default 0 : Clock Rate Selects
Default 0 : Clock Rate Selects
SSCR1 Registers (write)
121
GDC21D601
SSSR
SS Status Register. This is automatically set when data transfer is complete between processor and
external device. The flag is cleared by a read of SSSR followed by a read or write of SSDR.
SSTR
SS Term Register. This is a register, which has a term between this byte and next byte by user’s setting.
The value can be 0 through 255. This is used only when master mode.
Table 4. SSSR Registers (Read)
BIT
7
6
5
4
3
2
1
0
122
NAME
RX fifo empty
TX fifo empty
RX fifo full
TX fifo full
TX end
R
R
BUSY
FUNCTION
Active high
Active high
Active high
Active high
Active high
Reserved
Reserved
when SSI transmitting and receiving
GDC21D601
5. Register Memory Map
The base address of the SSPI interface is 0xFFFF F800 and the offset of any particular register from the base
address is as followed.
ADDRESS
SSI Base
SSI Base + 0x04
SSI Base + 0x08
SSI Base + 0x0C
SSI Base + 0x10
SSI Base + 0x20
SSI Base + 0x24
SSI Base + 0x28
SSI Base + 0x2C
SSI Base + 0x30
READ LOCATION
SSCR0
SSCR1
SSDR
SSSR
WRITE LOCATION
SSCR0
SSCR1
SSDR
SSTR
SSCR0
SSCR1
SSDR
SSCR0
SSCR1
SSDR
SSSR
SSTR
SSI Register Memory Map
SSCR0 : Control Register0
SSCR1 : Control Register1
SSDR : Data Register
SSSR : Status Register
SSTR : Term Register
The output frequency is selected by programming the lower two bits of the SSCR1 register, SSCR1[1:0]. The
following table shows the possible settings:
SSCR1[1..0]
00
01
10
11
DIV
4
8
32
64
FREQUENCY (WHEN PCLK=3.6864MHZ)
921.6 KHz
460.8 KHz
115.2 KHz
57.6 KHz
SSCR1[1:0] Encoding
123
GDC21D601
6. SSPI Data Clock Timing Diagram
SICLK
C L K (C K P O L = 1 )
C L K (C K P O L = 0 )
S(SLAVES)
M SB
SIOUT(CPHA=1)
LSB
M SB
LSB
SIOUT(CPHA=0)
Figure 4. Timing Diagram
124
GDC21D601
Section 15. UART
1. General Description
This module is an Universal Asynchronous Receiver/Transmitter(UART) with FIFOs, and is functionally identical
to the 16450 on power-up (CHARACTER mode). The GM16550 can be put into an alternate mode (FIFO mode)
to relieve the CPU of excessive software overhead.
In this mode internal FIFOs are activated allowing 16 bytes plus 3 bit of error data per byte in the RCVR FIFO, to
be stored in both receive and transmit modes. All the logic is on the chip to minimize the system overhead and
maximize system efficiency.
The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a
MODEM and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the
complete status of the UART at any time during the functional operation. Status information reported includes
the type and condition of the transfer operations performed by the UART, as well as any error conditions(parity,
overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator that is capable of dividing the timing reference clock
input by divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are
also included to use this 16x clock to drive the receiver logic.
The UART has complete MODEM-control capability and a processor-interrupt system. Interrupts can be
programmed to the user’s requirements, minimizing the computing required to handle the communications link.
2. Features
• Capable of running all existing 16450 software.
• After reset, all registers are identical to the 16450 register set.
• The FIFO mode transmitter and receiver are each buffered with 16 byte FIFO’s to reduce the number of
interrupts presented to the CPU.
• Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data.
• Hold and shift registers in the 16450 mode eliminate the need for precise synchronization between the CPU and
serial data.
• Independently controlled transmit, receive, line status and data set interrupts.
• Programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock
• Independent receiver clock input.
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD).
• Fully programmable serial-interface characteristics:
5-, 6-, 7- or 8-bit characters
Even, odd, or no-parity bit generation and detection
1-, 1.5- or 2-stop bit generation and detection
Baud generation (DC to 256k baud)
• False start bit detection.
• Complete status reporting capabilities.
• Line break generation and detection.
• Internal diagnostic capabilities.
• Loopback controls for communications link fault isolation
• Full prioritized interrupt system controls.
125
GDC21D601
3. Signal Description
The GDC21D601 UART module is connected to the APB bus.
Table 1. Signal Descriptions
U_CLK
I
SOURCE/
DESTINATION
CPG
nB_RES0
I
PMU
P_A[2:0]
I
APB Bridge
P_D[7:0]
I/O
APB Bridge
P_STB
I
APB Bridge
P_WRITE
I
APB Bridge
P_SEL
I
APB Bridge
INT_UART
O
INTC
NCTS
I
External
NAME
126
Type
DESCRIPTION
UART external Clock input
This connects the main timing reference to the UART.
3.6864Mhz is recommendable input clock frequency.
Reset signal generated from the APB Bridge(Master Reset)
When this input is low, it clears all the registers (except the Receiver
Buffer, Transmitter Holding, and Divisor Latches) and the control logic
of the UART. The states of various output signals (SOUT, INT_UART,
nRTS, nDTR) are affected by an active nB_RES[0] input.
Register select. Address signals connected to these 3 inputs select a
UART register for the CPU to read from or write to during data transfer.
A table of registers and their addresses is shown below. Note that the
state of the Divisor Latches
Data Bus. This bus comprises eight TRI-STATE input/output lines.
The bus provides bi-directional communications between the UART and
the CPU. Data, control words and status information are transferred via
the P_D[7:0] data bus.
This strobe signal is used to time all accesses on the peripheral bus. The
falling edge of P_STB is coincident with the falling edge of
B_CLK.(ASB System Clock)
When this signal is HIGH, it indicates a write to a peripheral. When this
signal is LOW, it indicates a read from a peripheral. This signal has the
same timing as the peripheral address bus. It becomes valid before
P_STB goes to HIGH and remains valid after P_STB goes to LOW.
When this signal is HIGH, it indicates that this module has been selected
by the APB bridge. This selection is a decode of the system address bus
(ASB).
Interrupt. This pin goes to high whenever any one of the following
interrupt types has an active high condition and is enabled via EIR:
Receiver Error Flag; Received Data Available:timeout(FIFO Mode
only); Transmitter Holding Register Empty; and MODEM Status. The
INT_UART signal is reset to low upon the appropriate interrupt service
or a Master Reset operation.
Clear to Send. When this signal is low, it indicates that the MODEM or
data set is ready to exchange data. The NCTS signal is a MODEM status
input whose conditions can be tested by the CPU reading bit 4 (CTS) of
the MODEM Status Register indicates whether the NCTS input has
changed its state since the previous reading of the MODEM Status
Register. NCTS has no effect on the Transmitter.
** Note : Whenever the CTS bit of the MODEM Status Register
changes its state, an interrupt is generated if the MODEM Status
interrupt is enabled.
GDC21D601
SIN
I
SOURCE/
DESTINATION
External
NDSR
I
External
NDCD
I
External
NRI
I
External
NDTR
O
External
NRTS
O
External
SOUT
O
External
NAME
Type
DESCRIPTION
Serial Input. Serial data input from the communications link (peripheral
device, MODEM or data set).
Data Set Ready. When this signal is low, it indicates that the MODEM
or data set is ready to establish the communications link with the UART.
The NDSR signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 5 (DSR) of the MODEM Status Register.
Bit 5 is the complement of the nDSR signal. Bit 1(DDSR) of MODEM
status Register indicates whether the nDSR input has changed its state
since the previous reading of the MODEM status register.
** Note : Whenever the DSR bit of the MODEM Status Register
changes its state, an interrupt is generated if the MODEM Status
interrupt is enabled.
Data Carrier Detect. When this signal is low, it indicates that the data
carrier has been detected by the MODEM data set. The signal is a
MODEM status input whose condition can be tested by the CPU reading
bit 7 (DCD) of the MODEM Status Register.
Bit 7 is the complement of the signal. Bit 3 (DDCD) of the MODEM
Status Register indicates whether the input has changed its state since
the previous reading of the MODEM Status Register. NDCD has no
effect on the receiver.
** Note : Whenever the DCD bit of the MODEM Status Register
changes its state, an interrupt is generated if the MODEM Status
interrupt is enabled.
Ring Indicator. When this signal is low, it indicates that a telephone ring
signal is received by the MODEM or data set. The NRI signal is a
MODEM status input whose condition can be tested by the CPU reading
bit 6 (RI) of the MODEM Status Register. Bit 6 is the complement of
the NRI signal. Bit 2 (TERI) of the MODEM Status Register indicates
whether the NRI input signal has changed from a low to a high state
since the previous reading of the MODEM Status Register.
** Note : Whenever the RI bit of the MODEM Status Register changes
from a high to a low state, an interrupt is generated if the MODEM
Status interrupt is enabled.
Data Terminal Ready. When this is low, it informs the MODEM or data
set that the UART is ready to establish communication link.
The NDTR output signal can be set to an active low by programming bit
0 (DTR) of the MODEM Control Register to high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop mode
operation holds this signal in its inactive state.
Request To Send. When low, this informs the MODEM or data set that
the UART is ready to exchange data. The NRTS output signal can be set
to an active low by programming bit 1 (RTS) of the MODEM Control
Register. A Master Reset operation sets this signal to its inactive (high)
state. Loop mode operation holds this signal in its inactive state.
Serial Output. Composite serial data output to the communications link
(peripheral, MODEM or data set). The SOUT signal is set to the
Marking (logic 1) state upon a Master Reset operation.
127
GDC21D601
Table 2. Register Address
DLAB
0
0
x
x
x
x
x
x
x
1
1
P_A[2]
0
0
0
0
0
1
1
1
1
0
0
P_A[1]
0
0
1
1
1
0
0
1
1
0
0
P_A[0]
0
1
0
0
1
0
1
0
1
0
1
REGISTER
Receiver Buffer(read), Transmitter Holding Register(write)
Interrupt Enable
Interrupt Identification(read)
FIFO Control(write)
Line Control
Modem Control
Line Status
Modem Status
Scratch
Divisor Latch(least significant byte)
Divisor Latch(most significant byte)
Table 3. UART Reset Configuration
REGISTER / SIGNAL
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
SOUT
INT_UART (RCVR Errs)
INT_UART (RCVR Data Ready)
INT_UART (THRE)
INT_UART(Modem Status changes)
NRTS
NDTR
128
REGISTER CONTROL
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR / RESET
Read RBR / RESET
Read IIR / Write THR / RESET
Read MSR / RESET
Master Reset
Master Reset
REGISTER STATE
0000 0000
0000 0001
0000 0000
0000 0000
0000 0000
0110 0000
xxxx 0000
High
Low
Low
Low
Low
High
High
GDC21D601
4. Internal Block Diagram
P_D[7:0]
DATA
BUS
BUFFER
SELECT
RECEIVER
FIFO
RECEIVER
SHIFT
REGISTER
RECEIVER
BUFFER
REGISTER
LINE
CONTROL
REGISTER
DIVISOR
LATCH(MS)
APB I/F
&
CONTROL
LOGIC
TRANSMITTER
TIMING
&
CONTROL
LINE
STATUS
REGISTER
U_CLK
nB_RES[0]
BAUD
GENERATOR
TRANSMITTER
FIFO
TRANSMITTER
HOLDING
REGISTER
SELECT
P_SEL
P_STB
RECEIVER
TIMING
&
CONTROL
DIVISOR
LATCH(LS)
P_A[0]
P_A[1]
P_A[2]]
P_WRITE
SIN
TRANSMITTER
SHIFT
REGISTER
MODEM
CONTROL
REGISTER
SOUT
nRTS
nCTS
MODEM
CONTROL
LOGIC
MODEM
STATUS
REGISTER
nDTR
nDSR
nDCD
INTERRUPT
ENABLE
REGISTER
INTERRUPT
CONTROL
LOGIC
nRI
INT_UART
INTERRUPT
ID
REGISTER
FIFO
CONTROL
REGISTER
Figure 1. Internal Block Diagram
129
GDC21D601
5. Registers Description
There are two URATs implemented in the design, the base addresses are 0xFFFF F500 in UART0 and 0xFFFF
F600 in UART1. In Table 4. UART register address map, x can be either 0 or 1.
Table 4. UART Register Address Map
ADDRESS
UARTxBase + 0x00
UARTxBase + 0x00
UARTxBase + 0x04
UARTxBase + 0x08
UARTxBase + 0x08
UARTxBase + 0x0C
UARTxBase + 0x10
UARTxBase + 0x14
UARTxBase + 0x18
UARTxBase + 0x1C
UARTxBase + 0x00
UARTxBase + 0x04
130
NAME
Receiver Buffer (RBR)
Transmitter Holding (THR)
Interrupt Enable (IER)
Interrupt Identification (IIR)
FIFO Control (FCR)
Line Control (LCR)
MODEM Control (MCR)
Line Status (LSR)
MODEM Status (MSR)
Scratch (SCR)
Divisor Latch LS (DLL)
Divisor Latch MS (DLM)
DESCRIPTION
8-bit R/O set DLAB = 0
8-bit W/O set DLAB = 0
8-bit R/W
8-bit R/O
8-bit W/O
8-bit R/W
8-bit R/W
8-bit R/W
8-bit R/W
8-bit R/W
8-bit R/W set DLAB = 1
8-bit R/W set DLAB = 1
GDC21D601
Table 5. Summary of registers gives the details of the UART registers.
Table 5. Summary of Registers
REGISTER ADDRESS
0 DLAB =
0
Bit Receiver
No. Buffer
Register
RBR
0 Data Bit 0
(Note 1)
0 DLAB = 1 DLAB = 2
0
0
Transmitter Interrupt Interrupt
Holding
Enable
Ident
Register
Register
Register
THR
IER
IIR
Data Bit 0 Enable
0 if
received interrupt
data
pending
available
interrupt
Data Bit 1 Enable
Interrupt
transmitter ID Bit 0
holding
register
empty
interrupt
Interrupt
Data Bit 2 Enable
ID Bit 1
receiver
line status
interrupt
Data Bit 3 Enable
Interrupt
modem
ID Bit 2
status
(Note 2)
interrupt
Data Bit 4 0
0
1
Data Bit 1
2
Data Bit 2
3
Data Bit 3
4
Data Bit 4
5
Data Bit 5 Data Bit 5 0
6
Data Bit 6 Data Bit 6 0
7
Data Bit 7 Data Bit 7 0
2
3
4
5
6
7
FIFO
Control
Register
FCR
FIFO
enable
Line
Control
Register
LCR
Word
length
select
Bit 0
MODEM
Control
Register
MCR
Data
Terminal
Ready
(DTR)
Line
Status
Register
LSR
Data Ready
(DR)
MODEM
Status
Register
MSR
Data Clear
to Send
(DCTS)
Scratch
Register
RCVR
Word
FIFO reset length
select
Bit 1
Request to Overrun
Send
Error
(RTS)
(OE)
XMIT
Number of
FIFO reset stop bit
Parity
enable
Reserved
Even parity Loop
select
0
Reserved
Stick parity 0
FIFO
enabled
(Note 2)
FIFO
enabled
(Note 2)
RCVR
trigger
(LSB)
RCVR
trigger
(MSB)
Set break
0
Divisor
0
Latch
Access Bit
SCR
Bit 0
0 DLAB = 1 DLAB
1
=1
Divisor
Divisor
Latch
Latch
(LS)
(MS)
DLL
DLM
Bit 0
Bit 8
Delta Data Bit 1
Set Ready
(DDSR)
Bit 1
Bit 9
Bit 2
Bit 2
Bit 10
Bit 3
Bit 3
Bit 11
Bit 4
Bit 4
Bit 12
Bit 5
Bit 5
Bit 13
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
Parity Error Trailing
(PE)
Edge Ring
Indicator
(TERI)
Framing
Delta Data
Error
Carrier
(FE)
Detect
(DDCD)
Break
Clear to
Interrupt
Send
(BI)
(CTS)
Transmitter Data Set
Holding
Ready
Register
(DSR)
Empty
(THRE)
Transmitter Ring
Empty
Indicator
(TEMT)
(RI)
Error in
Data
RCVR
Carrier
FIFO
Detect
(Note 2)
(DCD)
Note 1 : Bit 0 is the least significant bit seriously transmitted or received.
Note 2 : These bits are always 0 in the GM16C450 mode.
The system programmer may access any of the UART registers summarized in Table 5. Summary of Registers via
the CPU. These registers control UART operation including transmission and reception of data. Each register bit in
the table has its name and reset state as shown.
131
GDC21D601
Line Control Register
The system programmer specifies the format of the asynchronous data communications exchange and set the
Divisor Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of the
Line Control Register. The read capability simplifies the system programming and eliminates the need for separate
storage in system memory of the line characteristics. Table 5. Summary of Registers shows the contents of the
LCR. Details on each bit are :
Bit 0 and 1 : These two bits specify the number of bits in each transmitted and received serial character. The
encoding of bits 0 and 1 is as follows:
Table 6. Line Control Register Encoding
BIT 1
0
0
1
1
BIT 0
0
1
0
1
CHARACTER LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2 :
This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2 is a
logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, One and a half Stop bits are generated. If bit 2 is a logic 1 when either a 6-, 7-,
or 8-bit word length is selected, two Stop bits are generated. The Receiver checks the first Stop-bit only,
regardless of the number of selected Stop bits.
Bit 3 :
This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data) or
checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity bit is
used to produce an even or odd number of 1s when the data word bits and the Parity bit are summed.)
Bit 4 :
This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number of
logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and bit 4 is
a logic 1, an even number of logic 1s is transmitted or checked.
Bit 5 :
This bit is the Stick Parity bit. When bits 3, 4, and 5 are logic 1, the Parity bit is transmitted and checked
as a logic 0. If bits 3 and 5 are 1 and bit 4 is a logic 0, then the Parity bit is transmitted and checked as a
logic 1. If bit 5 is a logic 0 Stick Parity is disabled.
Bit 6 :
This bit is the Break Control bit. It causes a break condition to be transmitted to the receiving UART.
When it is set to a logic 1, the serial output (SOUT) is forced to be the Spacing (logic 0) state. The break
is disabled by setting bit 6 to a logic 0. The Break Control bit acts only on SOUT and has no effect on
the transmitter logic.
** Note : This feature enables the CPU to alert a terminal in a computer communications system. If the
following sequence is followed, no erroneous or extraneous characters will be transmitted because of the
break.
Bit 7 :
132
This bit is the Divisor Latch Access Bit (DLAB), It must be set to high (logic 1) to access the Divisor
Latches of the Baud Generator during a Read or Write operation. It must be set to low (logic 0) to access
the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.
GDC21D601
Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to 8.0
MHz and dividing it by any divisor from 2 to 65535. 4MHz is the highest input clock frequency recommended
when the divisor=1. The output frequency of the Baud Generator is 16 x the Baud [divisor # = (frequency input) /
(baud rate x 16)]. Two 8-bit latches store the divisor in a 16-bit binary format. These Divisor Latches must be
loaded during initialization to ensure the proper operation of the Baud Generator. Upon loading either of the
Divisor Latches, a 16-bit Baud counter is immediately loaded.
Table 7. Baud rates provide decimal divisors to use with crystal frequencies of 1.8432 MHz and 3.6864 MHz. For
baud rates of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate depends on
the chosen crystal frequency. Using a divisor of zero is not recommended.
Table 7. Baud Rates
Desired Baud
Rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
1.8432 MHz
Decimal Divisor
Used to
Generate 16 x
Clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
Percent Error
Difference
Between
Desired and
Actual
0.026
0.058
0.69
2.86
Desired Baud
Rate
50
110
300
1200
2400
4800
9600
19200
38400
57600
115200
3.6864 MHz
Decimal Divisor
Used to
Generate 16 x
Clock
4608
2094
768
192
96
48
24
12
6
4
2
Percent Error
Difference
Between
Desired and
Actual
0.026
-
133
GDC21D601
Line Status Register
This register provides status information to the CPU concerning the data transfer. Table 5. Summary of Registers
shows the contents of the Line Status Register. Details on each bit are :
Bit 0 :
This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to a logic 1 whenever a complete
incoming character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit
0 is reset to a logic 0 by reading all of the data in the Receiver Buffer Register or the FIFO.
Bit 1 :
This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was
not read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby
destroying the previous character. The OE indicator is set to a logic 1 upon the detection of an overrun
condition, and reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode
data continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is
full and the next character has been completely received in the shift register. OE is indicated to the CPU
as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the
FIFO.
Bit 2 :
This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have
the correct even or odd parity, as selected by the even-parity-select bit. The PE bit is set to a logic 1 upon
the detection of a parity error and is reset to a logic 0 whenever the CPU reads the contents of the Line
Status Register. In the FIFO mode this error is associated with the particular character in the FIFO where
it applies to. This error is revealed to the CPU when its associated character is at the top of the FIFO.
Bit 3 :
This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not have a
valid stop bit. Bit 3 is set to a logic 1 whenever the Stop bit following the last data bit or parity bit is
detected as a logic 0 bit (Spacing level). The FE indicator is reset whenever the CPU reads the contents
of the Line Status Register. In the FIFO mode this error is associated with the particular character in the
FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of
the FIFO. The UART will try to resynchronize after a framing error. To do this, it assumes that the
framing error was due to the next start bit, so it samples this “start” bit twice and then takes it in the
“data”.
Bit 4 :
This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a full word transmission time (that is, the total time of
Start bit + data bits + Parity + Stop bits). The BI indicator is reset whenever the CPU reads the contents
of the Line Status Register. In the FIFO mode this error is associated with the particular character in the
FIFO where it applies to. This error is revealed to the CPU when its associated character is at the top of
the FIFO. When break occurs only one zero character is loaded into the FIFO. The next character
transfer is enabled after SIN goes to the marking state and receives the next valid start bit.
** Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt
whenever any of the corresponding conditions is detected and the interrupt is enabled.
Bit 5 :
This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the UART is
ready to accept a new character for transmission. In addition, this bit causes the UART to issue an
interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to high. The
THRE bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into
the Transmitter Shift Register. The bit is reset to logic 0 concurrently with the loading of the Transmitter
Holding Register by the CPU. In the FIFO mode this bit is set when the XMIT FIFO is empty; it is
cleared when at least 1 byte is written to the XMIT FIFO.
134
GDC21D601
Bit 6 :
This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1 whenever the Transmitter
Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. It is reset to a logic 0
whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one
whenever the transmitter FIFO and register are both empty.
Bit 7 :
In the 16450 mode, this is 0. In the FIFO mode, LSR7 is set when there is at least one parity error,
framing error or break indication in the FIFO.
LSR7 is cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO.
** Note : The Line Status Register is intended for read operations only.
FIFO Control Register
This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used to
enable the FIFOs, clear the FIFOs and set the RCVR FIFO to trigger level.
Bit 0 :
Writing a 1 to FCR0 enables both the XMIT and RCVR FIFOs. Resetting FCR0 will clear all bytes in
both FIFOs. When changing from FIFO Mode to 16C450 Mode and vice versa , data is automatically
cleared from the FIFOs. This bit must be a 1 when other FCR bits are written to or they will not be
programmed.
Bit 1 :
Writing a 1 to FCR1 resets its counter logic to 0. The shift register is not cleared. The 1 that is written to
this bit position is self-cleared.
Bit 2 :
Writing a 1 to FCR2 resets its counter logic to 0. The shift register is not cleared. The 1 that is written to
this bit position is self-cleared.
Bit 3 :
FCR3 is not used.
Bit 4,5 : FCR4 to FCR5 are reserved for future use.
Bit 6,7 : FCR6 and FCR7 are used to set the trigger level for the RCVR FIFO interrupt.
Table 8. RCVR FIFO Interrupt
FCR[7:6]
00
01
10
11
RCVR FIFO Trigger Level (Bytes)
01 (default)
04
08
14
135
GDC21D601
Interrupt Identification Register
In order to provide minimum software overhead during data character transfers, the UART prioritizes interrupts
into four levels and records them in the Interrupt Identification Register. The four levels of interrupt conditions are
as follows in order of priority :
• Receiver Line Status
• Received Data Ready
• Transmitter Holding Register Empty
• MODEM Status
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending
interrupt to the CPU. While this CPU access occurs, the UART records new interrupts, but does not change its
current indication until the access is complete. Table 5. Summary of Registers shows the contents of the IIR.
Details on each bit are :
Bit 0 :
This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is
pending or not. When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as
a pointer for the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is
pending.
Bit 1 and 2 :
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in
Table 9. Interrupt control functions.
Bit 3 :
In the 16450 mode this bit is 0. In the FIFO mode this bit is set along with bit 2 when a time-out
interrupt is pending.
Bit 4 and 5 :
These two bits of the IIR are always logic 0.
Bit 6 and 7 :
These two bits are set when FCR0 = 1.
136
GDC21D601
Table 9. Interrupt Control Functions
FIFO
MODE
ONLY
Bit 3
INTERRUPT
IDENTIFICATION
REGISTER
Bit 2
Bit 1
Bit 0
INTERRUPT SET AND RESET FUNCTIONS
Priority Level Interrupt Type
Interrupt Source
None
Receiver
Line Status
Receiver
Data Available
None
Overrun Error, Parity Error, Framing
Error or Break Interrupt
Receiver Data Available or Trigger
Level Reached
No Characters have been removed
from or input to the RCVR FIFO
during the last 4 Char. times and
there is at least 1 Char. in it during
this time
Transmitter Holding Register Empty Reading the IIR
Register (if it is the
source of interrupt) or
writing it into the
Transmitter Holding
Register
Clear to Send, Data Set Ready, Ring Reading
the
Indicator, or Data Carrier Detect
MODEM
Status
Register
0
0
0
1
0
1
1
0
Highest
0
1
0
0
Second
1
1
0
0
Second
Character
Time-out
Indication
0
0
1
0
Third
Transmitter
Holding
Register
Empty
0
0
0
0
Fourth
MODEM
Status
Interrupt
Reset Control
Reading the Line
Status Register
Reading the Receiver
Buffer Register or the
FIFO drops below the
trigger level
Reading the Receiver
Buffer Register
Interrupt Enable Register
This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt
(INT_UART) output signal. It is possible to totally disable the interrupt Enable Register (IER). Similarly, setting
bits of the IER register to a logic 1 enable the selected interrupt(s). Disabling an interrupt prevents it from being
indicated as active in the IIR and from activating the INT_UART output signal. All other system functions operate
in their normal manners, including the setting of the Line Status and MODEM Status Registers. Table 5. Summary
of Registers shows the contents of the IER. Details on each bit are :
Bit 0 :
This bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when
it is set to logic 1.
Bit 1 :
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic 1.
Bit 2 :
This bit enables the Receiver Line Status Interrupt when it is set to logic 1.
Bit 3 :
This bit enables the MODEM Status Interrupt when it is set to logic 1.
Bit 4 through 7 :These four bits are always logic 0.
137
GDC21D601
MODEM Control Register
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
The contents of the MODEM Control Register are indicated in Table 5. Summary of Registers, and are described
below.
Bit 0 :
This bit controls the Data Terminal Ready (NDTR) output. When this bit is set to a logic 1, the NDTR
output is forced to be a logic 0. When bit 0 is reset to a logic 0, the NDTR output is forced to be a logic
1.
** Note : The NDTR output of the UART may be applied to an EIA inverting line driver (such as the
DS1488) to obtain the proper polarity input at the succeeding MODEM or data set.
Bit 1 :
This bit controls the Request to Send (NRTS) output. Bit 1 affects the NRTS output in an identical
manner that described above for bit 0.
Bit 2 :
Not used
Bit 3 :
Not used
Bit 4 :
This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1,
the transmitter Serial Output (SOUT) is set to the Marking (logic 1) state. The receiver Serial Input (SIN)
is disconnected; the output of the Transmitter Shift Register is “looped back” into the Receiver Shift
Register input. The four MODEM Control inputs (NCTS, NDSR, NDCD, and NRI) are disconnected.
The two MODEM Control outputs (NDTR and NRTS) and two internal nodes (OUT1 and OUT2) are
internally connected to the four MODEM Control inputs and the MODEM Control output pins are
forced to be their inactive state (high). On the diagnostic mode, the transmitted data is immediately
received. This feature allows the processor to verify the transmit- and received-data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully operational. Their sources are
external to the part. The MODEM Control interrupts are also operational, but the interrupts sources are
now the lower four bits of the MODEM Control Register instead of the four MODEM Control inputs.
The interrupts are still controlled by the Interrupt Enable Register.
Bit 5
138
through 7 :These bits are permanently set to logic 0.
GDC21D601
MODEM Status Register
This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU. In
addition to this current-state information, four bits of the MODEM Status Register provide change information.
These bits are set to a logic 1 whenever a control input from the MODEM changes its state. They are reset to logic
0 whenever the CPU reads the MODEM Status Register.
The contents of the MODEM Status Register are indicated in Table 5. Summary of Registers, and are described
below.
Bit 0 :
This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the NCTS input to the chip
has changed its state since the last time it was read by the CPU.
Bit 1 :
This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the NDSR input to the chip
has changed its state since the last time it was read by the CPU.
Bit 2 :
This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the NRI input to the
chip has changed from a low to a high state.
Bit 3 :
This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the NDCD input to the
chip has changed its state since the last time it was read by the CPU.
** Note : Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM Status Interrupt is generated.
Bit 4 :
This bit is the complement of the Clear to Send (NCTS) input. If bit 4 (loop) of the MCR is set to a 1,
this bit is equivalent to RTS in the MCR.
Bit 5 :
This bit is the complement of the Data Set Ready (NDSR) input. If bit 4 of the MCR is set to 1, this bit
is equivalent to DTR in the MCR.
Bit 6 :
This bit is the complement of the Ring Indicator (NRI) input. If bit 4 of the MCR is set to 1, this bit is
equivalent to OUT1 in the MCR.
Bit 7 :
This bit is the complement of the Data Carrier Detect (NDCD) input. If bit 4 of the MCR is set to 1,
this bit is equivalent to OUT2 in the MCR.
Scratch Register
This 8-bit Read/Write Register does not control the UART in any way. It is intended to be used as a scratchpad
register by the programmer to hold data temporarily.
139
GDC21D601
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR 0 = 1, IER 0 = 1), RCVR interrupts occur as
follows :
1. The received data available interrupt will be issued to the CPU when the FIFO has reached its programmed
trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR-06), as before, has higher priority than the received data available(IIR-04)
interrupt.
4. The data ready bit (LSR 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO.
It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occurs as follows :
1. A FIFO timeout interrupt occurs in the following conditions :
- at least one character is in the FIFO
- the latest serial character received was longer than 4 continuous character times (if 2 stop bits are programmed,
the second one is included in this time delay).
- the latest CPU read of the FIFO was longer than 4 continuous character times.
This will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12 bit
character.
2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to
the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer is reset when the CPU reads one character
from the RCVR FIFO.
4. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the
CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR 0 = 1, IER 1 = 1), XMIT interrupts occur as
follows :
1. The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty; it is cleared as soon as the
transmitter holding register is written to (1 to 16 characters may be written to the XMIT FIFO while this
interrupt is serviced or the IIR is read.
2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever
the following occurs: THRE = 1 and there has not been at least two bytes at the same time in the transmit FIFO
since the last THRE = 1. The first transmitter interrupt affect changing FCR 0 will be immediate if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
140
GDC21D601
FIFO Polled Mode Operation
When FCR 0 = 1 resetting, IER 0, IER 1, IER 2, IER3 or all to zero puts the UART in the FIFO Polled Mode.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of
operation.
141
GDC21D601
Section 16. Smart Card Interface
1. General Description
The smart card interface block is basically a general-purpose serial interface block that has the smart card interface
features additionally. And some ports of GPIO are necessary to provide complete interfaces to the smart card. As a
general-purpose serial interface, it has the UART(16550) compatible register sets and bit definitions although it
doesn’t have the modem control pins.
As a smart card interface, it has the following general features.
• Supports only asynchronous operation.
• Supports cards that have internal reset capability.
• Supports cards that have an active low reset input.
• Supports cards that use the internal clock.
• Generate the clock for a card expecting the external clock.
• Use the serial in/out ports for I/O.
• Use the GPIO ports for other interface signals like RST, DETECT, etc.
nB-RES
U_CLK
SMCLK
INT_SCIF
P_SEL
P_WRITE
P_STB
SMDOEN
APB
Interface
Smart Card
Interface
SMDO
SMDI
P_A[3:0]
P_D[7:0]
Figure 1. Signal Connections of the SMART CARD Interface
142
SMART
CARD
GDC21D601
2. Signal Description
The SMART CARD Interface module is connected to the APB. Table 1. Signal descriptions describes the APB
signals used and produced. Table 2. Signal descriptions shows the non-AMBA signals from the block.
Table 1. Signal Descriptions
nB_RES
I
Source/
Destination
Reset Controller
P_A[3:0]
I
APB Bridge
P_D[7:0]
I/O
APB, B_D
P_STB
I
APB Bridge
P_WRITE
I
APB Bridge
P_SEL
I
APB Bridge
Name
Type
Description
This signal indicates system reset status of the bus
(active LOW)
This is part of the peripheral address bus, which is used by the
peripheral for decoding its own register accesses.
The addresses become valid before P_STB goes HIGH and
remain valid after P_STB goes LOW.
This is part of the bidirectional peripheral data bus. The data
bus is driven by this block during read cycles
(when P_WRITE is LOW).
This strobe signal is used to time all accesses on the peripheral
bus. The falling edge of P_STB is coincident with the falling
edge of B_CLK (ASB system clock).
When HIGH, this signal indicates a write to a peripheral, and
when LOW, a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes HIGH and remains valid
after P_STB goes LOW.
When HIGH, this signal indicates the SMART CARD interface
module has been selected by the APB bridge. This selection is a
decode of the system address bus (ASB). For more details see
AMBA Peripheral Bus Controller (ARM DDI 0044).
Table 2. Specific Block Signal Descriptions
Name
Type
SMDI
SMDO
SMCLK
SMDOEN
I
O
O
O
INT_SCIF
Out
Source/
Destination
SMART CARD
SMART CARD
SMART CARD
SMART CARD
Interrupt Controller
Description
Serial data input
Serial data output
Clock output for smart card that expects the external clock
Tri-State buffer enable signal for SMDO output. For normal
uart operation, it is always ‘1’. For smart card interface mode,
it’s used to prevent the serial I/O bus conflict because the serial
I/O for smart card interface is bidirectional
SMART CARD Interrupt.
143
GDC21D601
3. Hardware Interface
The APB interface is fully APB-compliant. The APB is a nonpipelined low-power interface, designed to provide a
simple interfacing to slave peripherals.
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D ata
A d d ress
D ata
Figure 2. APB Read
B_CLK
P_SEL
P_W RITE
P_STB
P_D
D ata
P_A
A d d ress
R e g ister
D ata
Figure 3. APB Write
144
GDC21D601
4. Functional Description
4.1 Reset and Detection of the Card
All the interface signals except the I/O and the CLK are connected to the GPIO ports. Usually, RST and the card
detect signal are connected to the GPIO. (The number of the interface signals needed and their functionality can
vary according to the physical application.)
The ISO/IEC 7816 standard defined the timing requirements for RST and that can be controlled by software. The
implementation of the detection of the card is not defined in the standard, but usual implementation uses the
external circuit to generate the card-detect signal that can indicates the presence of the card. The smart card
interface of the GDC27D601 also expects the “card detect signal” from the outside through the GPIO port.
Optionally, GPIO can also provide the voltage control signals that are needed to support the various kinds of smart
cards that use the different Vcc and Vpp voltages.
4.2 Transmitting the Data
Transmitting the data to the smart card is performed with the following procedure.
• Program the baud rate generator to the appropriate value.
• Software writes the data to the transmit buffer.
• After transmission, card sends an error signal if there is a parity error.
• Smart card interface detects the parity error and sets the error status for CPU to read the status.
• The CPU read s the error status and determine if re-transmission is necessary.
• If there is an error, write the same data again to the transmit buffer and re-transmit.
• Guard time is controlled by software.
4.3 Receiving the Data
Receiving the data from the smart card is done with the following procedure.
• Program the baud rate generator to the appropriate value.
• Receive the data.
• If there is an parity error, smart card interface sets the internal error status and send the error signal back to the
card through the I/O pin.
• Software checks the error status and wait for data if there is an error.
• Guard time is controlled by software.
145
GDC21D601
5. Programmer’ s Model
Smart Card Interface Mode Control Register (SMCR)
SMCR is a 3-bit readable/writable register, in which is used to control the pure smart card interface part except
uart and APB interface. All the bits in this register are initialized to 0 at reset.
Table 3. SMCR Bit Functions
BIT
0
NAME
MDSEL
1
SMCLKEN
2
SMPEDEN
FUNCTION
0 : UART (initial value)
1 : Smart card I/F
Smart card Clock Enable
0 : Disable(initial value)
1 : Enable
Parity Error Detect Enable
0 : Disable(initial value)
1 : Enable
Mode Select
Smart Card Clock Devisior Latch (SMDLL)
Smart Card Clock Devisior Latch (SMDLM)
The smart card interface has a programmable clock generator for smart card that uses the external clock. SMDLL
and SMDLM are two 8-bit latchs, in which is used to store in a 16-bit binary format. All the bits in this registers
are initialized to 0 at reset.
Table 4. SMDLL Bit Functions
BIT
7:0
NAME
devisior (LS)
FUNCTION
Divisor for SMCLK
Table 5. SMDLM Bit Functions
BIT
7:0
NAME
devisior (MS)
FUNCTION
Divisor for SMCLK
Smart Card Interface Status Register (SMSR)
SMSR is a 1-bit read-only register which is used to indicate whether partty error is detected or not. It is cleared
after reading it.
Table 6. SMSR Bit Functions
BIT
0
146
NAME
SMPEDI
FUNCTION
Parity error
0 : No interrupt occurrenrce (initial value)
1 : Interrupt occurrerce
GDC21D601
Test Register for Input (TIR)
TIR is a 3-bit write-only register defined for test purpose. This register allows simulation of input signals to the
block, as well as the generation of a special test clock signal aimed for production test vectors.
Table 7. TIR Bit Functions
BIT
2
1
0
NAME
TNMODE
TICUCLK
TICSMDI
FUNCTION
Mode select bit
0 : Normal operation mode
1 : Test mode
Programmable serial clock for test
Programmable serial data input for test
Test Register for Output (TOR)
TOR is a 3-bit read-only register defined for test purpose. This register allows simulation of output signals from
the block.
Table 8. TOR Bit Functions
BIT
2
1
0
NAME
TSMDO
TSMDOEN
TSMCLK
FUNCTION
Serial data output line
Serial outputl data enable line
Serial clock line for smart card
The following regitsers are same ones in the UART module. Details on each register see the data sheet of
GDC21D601 UART.
Receiver Buffer Register (RBR)
Transmitter Holding Register (THR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
FIFO Control Register (FCR)
Line Control Register (LCR)
Line Status Register (LSR)
Scratch Register (SCR)
Divisor Latch (DLL)
Divisor Latch (DLM)
147
GDC21D601
5.2 Register Memory Map
The base address of the SMART CARD interface is 0xFFFFF700 and the offset of any particular register from the
base address is determined.
Table 9. SMART CARD Interface Register Memory Map
ADDRESS
SMART CARD
I/F Base
SMART CARD
I/F Base + 0b0001
SMART CARD
I/F Base + 0b0010
SMART CARD
I/F Base + 0b0011
SMART CARD
I/F Base + 0b0101
SMART CARD
I/F Base + 0b0111
SMART CARD
I/F Base + 0b1000
SMART CARD
I/F Base + 0b1001
SMART CARD
I/F Base + 0b1010
SMART CARD
I/F Base + 0b1011
SMART CARD
I/F Base + 0b1100
SMART CARD
I/F Base + 0b1101
148
REGISTER
RBR/THR (DLAB = 0)
DLL (DLAB = 1)
IER (DLAB = 0)
DLM (DLAB = 1)
IIR/FCR
READ LOCATION
Receiver Buffer
Divisor Latch (LS)
Interrupt Enable
Divisor Latch (MS)
Interrupt Ident
WRITE LOCATION
Transmitter Holding
Divisor Latch (MS)
Interrupt Enable
Divisor Latch (MS)
FIF Control
LCR
Line Control
Line Control
LSR
Line Status
SCR
Scratch
Scratch
SMCR
Smart card control
Smart card control
SMDLL
Divisor Latch (LS) for SMCLK
Divisor Latch (LS) for SMCLK
SMDLM
Divisor Latch (MS) for SMCLK Divisor Latch (MS) for SMCLK
SMSR
Status for SMPED Error
TIR
TOR
Test Register for Input
Test Register for Output
GDC21D601
Section 17. I2C Controller
1. General Description
The I2C controller allows the GDC21D601 to exchange data with a number of other I2C devices such as micro
controller, EEPROMs, real-time clock devices, A/D converters, LCD displays, NTSC/PAL encoder, and etc.
The I2C is a synchronous bus that is used to connect several ICs on a board. The I2C bus uses two wires, serial data
(SDA), and serial clock (SCL) to carry information between the ICs connected to the bus.
The I2C controller consists of transmitter and receiver sections, an independent baud rate generator, and a control
unit. The transmitter and receiver sections use the same clock, which is derived from the I2C controller baud rate
generator in master mode. Refer to Figure 1. for the I2C controller block diagram.
The GDC21D601 I2C bit7(MSB) is shifted out first.
Clock divider
FSM
CLK
P_SEL
P_WRITE
P_STB
P_D
P_A
RESET
Baud register
Control register
Data register
Status register
Address register
Test register
SCL driver
SDA driver
Interrupt generate
SCL_OUT
SCL_IN
SDA_OUT
SDA_IN
Interrupt
APB(AMBA) interface
2
Figure 1. I C Block Diagram
149
GDC21D601
2. I2C Controller Key Features
The I2C controller contains the following key features:
• Two-Wire Interfaces (SDA and SCL)
• Both Master and Slave functions
• Supports Clock Rates up to 400khz in Master Mode .
• Independent Programmable Baud Rate Generator
• Local Loopback Capability for Testing
• Slave clock stretching support
3. I2C Controller Clocking and Pin Functions
The I2C controller can be configured as a master or slave for the serial channel.
When the I2C controller is a master, the I2C controller baud rate generator is used to generate the I2C controller
transmit and receive clocks. The I2C baud rate generator takes its input from the block clock input.
Both serial data (SDA) and serial clock (SCL) are bi-directional pins. These pins are connected to a positive supply
voltage via an external pull up resister. When the bus is free, both lines are high.
2
When the I C controller is working as a master, SCL is the clock output signal that shifts the received data in and
shifts the transmit data out from/to the SDA pin.
When the I2C controller functions as a slave, its internal clock is synchronized by the incoming clock from SCL
line.
4. I2C Master Mode Transmit / Receive Process
When the I2C controller functions in master mode, the I2C master initiates a transaction by transmitting a message
to the peripheral (I2C slave) as a transmitter mode. The message specifies a read or write operation. If a read
operation is specified, the direction of the transfer is changed at the moment of the first acknowledge, and the
called slave receiver becomes a slave transmitter. Otherwise, the master functions as master transmitter
continuously.
Before the data exchange, Core must check if the bus is used by other masters by reading the status register(stat_r).
If the bus is not used, the address of the slave with which you want to communicate should be written to transmit
register(tx_r), and configure the control register to start the cycle. After interrupt happens, confirming the bus is
acquired and called slave is responded. When the slave is not responded, the sequence must be ended by stop
condition by configuring control register(ctrl_r). If bus is lost and called address is not master itself, I2C block is
gone to initial state. But if bus winner calls this master, master is gone into slave mode. If all these processes are
okay, then the data transfer follows. Data transfer cycle are started by writing transmit register(tx_r) and
configuring control register. When the I2C controller functions as a receiver, tx_r is written with 0xFF. Detailed
sequence is described below.
150
GDC21D601
4.1 Master Transmitter Sequence
• Step 1 : read status register. Check if bbusy is
cleared
• Step 2 : write slave address to data register
write 5’b10111 to control register
• Step 3 : wait for interrupt
write 5’bx0011 to control register
• Step 4 : read status register. Check blost, ack_rpy
if blost is 1, go to step 1.
else if ack_rpy is 1 go to step 6.
• Step 5 : write data to transmit register
if this data is the last, go to step 6.
wait for interrupt. Go to step 4.
• Step 6 : write 5’b11011 to control register
4.2 Master Receiver Sequence
• Step 1 : read status register.
Check if bbusy is cleared
• Step 2 : write slave address to data register
write 5’b10111 to control register
• Step 3 : wait for interrupt
read status register. Check blost, ack_rpy
if blost is 1, go to step 1.
else if ack_rpy is 1, go to step 5.
write 5’b10001 to control register
write 0xff to transmit register
• Step 4 : if this data is the last, go to step 5.
wait for interrupt
read data from data register
read status register. Check ack_rpy
if ack_rpy is 0 go to step 4.
• Step 5 : write 5’b11011 to control register
5. I2C Restart Capability (Combined Mode)
The I2C controller can restart without going to STOP condition. If a I2C master wants to restart after
sending/receiving 1 byte data , just keep the start_ctrl and ack_ctrl bit in ctrl_r, and if a master wants to restart after
sending/receiving several bytes data, set start_ctrl and ack_ctrl bit in ctrl_r just before sending/receiving last data.
The followings shows the restart operation after transfer 1 byte. It sets start_ctrl and ack_ctrl to 1 at first interrupt.
1. read status register. Check if bbusy is cleared
2. write slave address to data register
write 5’b10111 to control register
3. wait for interrupt
read status register. Check ack_rpy
if ack_rpy is 1, go to step 5.
else write 5’b10111 to control register
to restart
4. wait for interrupt.
Write slave address to data register.
Write 5’b10001 to control register.
5. wait for interrupt
if this data is the last, go to step 6.
read status register. Check ack_rpy
if ack_rpy is 0 go to step 5.
6. write 5’b11011 to control register
If above data transfer is transmitter, write data to transmit register else if recevier write 8’hff to transmit register.
151
GDC21D601
6. I2C Controller Programming Model
The following paragraphs describe the registers in the I2C controller.
2
6.1 I C Control Register (ctrl_r).
ctrl_r is a write-only register that controls the I2C operation mode. Ctrl_r is cleared by reset excluding ack_ctrl bit.
7
Reserved
6
Reserved
BIT
7:5
NAME
Reserved
4
include0
3
stop_ctrl
2
start_ctrl
1
ack_ctrl
0
int_en
5
Reserved
4
include0
3
stop_ctrl
2
start_ctrl
1
ack_ctrl
0
int_en
FUNCTION
Indicates whether addr_r[0] bit should be used or not in comparing addresses in slave mode
Cleared by reset
Indicates the transfer cycle should be ended by generating stop condition in master mode
Cleared by reset
Indicates the transfer cycle should be started by generating start condition in master mode
Cleared by reset
This bit value directly goes to the SDA pin in acknowledge phase in both master and slave mode
Set by reset
Interrupt enable bit
Cleared by reset
2
6.2 I C Status Register (stat_r).
The stat_r Register is an 8-bit memory mapped and read-only register. The stat_r register shows the state of I2C
block.
7
Reserved
BIT
7:5
6
Reserved
5
Reserved
4
Intr
NAME
Reserved
3
bbusy
2
blost
FUNCTION
4
intr
3
bbusy
Indicates that interrupt is generated.
Used when interrupt polling is used
Indicates that I2C bus is used
2
blost
Indicates that bus is lost during bus arbitration
1
ack_rpy
Indicates the real state of SDA line in acknowledge phase
0
slave
Indicates that I2C block was called.
This bit is set when I2C block was called by other master
152
1
ack_rpy
0
slave
GDC21D601
2
6.3 I C Address Register (addr_r).
The addr_r is an 8-bit write-only register that is used to be accessed by other master.
7
6
5
4
3
2
1
0
addr_r
BIT
7:0
NAME
addr_r
FUNCTION
Indicates the slave address of the I2C controller.
This address is used in comparing the incoming addresses in slave mode
2
6.4 I C Baud-Rate Register (baud_r).
I2C block uses the clock generated by dividing system clock which is set in baud_r. Additionally this clock is used
to generate the SCL clock which is eight-divided by internal clock. The default value is 4. Assuming system clock
is 29Mhz, SCL clock is 300kHz and maximum SCL frequency is 1.8Mhz
7
6
5
4
3
2
1
0
baud_r
BIT
7:0
NAME
baud_r
FUNCTION
indicates the clock dividing value whose clock signal is used in internal operation internal
clock frequency is (baud_r + 2) *2 and when it is set as 255, the internal clock is halfdivided .
2
6.5 I C Data Register (data_r).
Data register is the 8bit read/write register which is used to send or receive data. Internally this register consists of
two registers, transmit register and receive register respectively. Written data is transferred to transmit register, and
read data from receive register. In every phase, SDA line is driven by transmit register and SDA line is read by
receive register.
7
6
5
4
3
2
1
0
data_r
BIT
7:0
NAME
data_r
FUNCTION
Written data is serially transmitted through the SDA line, and SDA line data is written In
receive register
153
GDC21D601
7. I2C Module Signal Description
The I2C module is connected to the APB bus. Table 1. Signal descriptions describes the APB signals used and
produced, Table 1. Signal descriptions shows the non-AMBA signals from the block.
Table 1. Signal Descriptions
BnRES
PA[3:2]
I
I
SOURCE/
DESTINATION
Reset Controller
APB Bridge
PD[7:0]
I/O
APB Peripherals
NAME
TYPE
PSTB
I
APB Bridge
PWRITE
I
APB Bridge
PSEL
I
APB Bridge
DESCRIPTION
ASB soft reset signal (active LOW).
This is part of the peripheral address bus, and is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. The data bus
is driven by this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of BCLK
(ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral, when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, it indicates the SSPI module has been
selected by the APB bridge. This selection is a decode of the system
address bus.
Table 2. Specific Block Signal Descriptions
Name
SDAin
SDAout
SCLin
SCLout
I2CIRQ
154
Type
I
O
I
O
O
Source /
Destination
PAD
PAD
PAD
PAD
Interrupt
Controller
Description
Serial data input.
Serial data output.
Serial clock in
Serial clock output
Active HIGH Interrupt Request
GDC21D601
8. Hardware Interface
The APB interface is fully APB-compliant. The APB is a non pipelined low-power interface, designed to provide a
simple interfacing to slave peripherals.
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
P_A
R e g ister
D a ta
A d d ress
D a ta
Figure 2. APB Read
B_CLK
P_SEL
P_W R ITE
P_STB
P_D
Data
P_A
Address
Register
Data
Figure 3. APB Write
155
GDC21D601
9. Register Memory Map
The base address of the I2C interface is 0xFFFF F900(channel0), 0xFFFF FA000(channel1), and 0xFFFF
FB00(channel2), the offset of any particular register from the base address is determined.
ADDRESS
I2C Base
I2C Base + 0x04
I2C Base + 0x08
I2C Base + 0x0C
I2C Base + 0x10
I2C Base + 0x14
READ LOCATION
Data_r
Stat_r
Test_r
2
I C Register Memory Map
156
WRITE LOCATION
Baud_r
Ctrl_r
Data_r
Addr_r
Test_r
GDC21D601
Section 18. Direct Memory Access Controller
1. General Description
This chip includes a 2-channel direct memory access controller (DMAC). The DMAC can be used in place of the
CPU to perform high speed data transfers among external devices equipped;, external memories, memory-mapped
external devices. Using the DMAC reduces the burden on the CPU and increases operating efficiency of the MCU.
The features of the DMA Controller are listed below :
• Two Channels with identical function
• Four Gigabytes of address space
• Max. 256 Kbytes transfer
• Data Transfer unit : Byte, Half-word, Word
• Bus mode : Burst mode, Exception mode (Cycle steal mode)
• Two kinds of address modes
- Single address mode
- Dual address mode
• Two types of Transfer request sources
- External I/O request
- Auto request
• Two kinds of fixed priorities for channels
- Channel 1’s priority > Channel 0’s priority
- Channel 0’s priority > Channel 1’s priority
• CPU can be interrupted when the specified number of data transfers are completed.
DMA Controller
BnRES
BPROT[1:0]
BCLK
AREQ
ASB Interface
AGNT
BTRAN[1:0]
BSIZE[1:0]
TRendINT
BLOK
nDMAReq[1:0]
Registers
nDMAck[1:0]
BWAIT
BA[31:0]
BD[31:]
BEROR
BWRITE
Control Block
BLAST
DSEL
DMAtrans
Figure 1. DMAC Top Block Diagram
157
GDC21D601
2. Signal Description
Table 1. DMA Controller Signal Descriptions
NAME
BCLK
TYPE
I
BnRES
BA[31:0]
BD[31:0]
AREQ
AGNT
BERROR
BLAST
BLOCK
BPROT[1:0]
BSIZE[1:0]
BTRAN[1:0]
BWAIT
I
I/O
I/O
O
I
I/O
I/O
O
O
O
O
I/O
BWRITE
DSEL
nDMAReq[1:0]
I/O
I
I
nDMAck[1:0]
I
DMAtrans
O
TRendINT
O
158
DESCRIPTION
AMBA System bus clock. This clock times all bus transfers.
The clock has two distinct phases - phase 1 where BCLK is LOW, and phase 2
where BCLK is HIGH.
This signal indicates the reset status of the bus.
ASB address. Output for DMAC operation. Input for Register access.
This is the part of Bi-directional system data bus.
Request signal for ASB Bus mastership.
Bus Grant signal from ASB arbiter.
ASB error signal.
ASB break burst signal from DRAM Controller.
ASB locked transfer signal
ASB master protection information.
ASB transaction size signal.
ASB transaction type signal.
ASB wait transfer signal. Input for DMA cycle stretch.
Out for Register access.
ASB transfer direction signal
Register select signal
DMA transfer request signal from the external I/O device. These are connected to
nDMAReq[1:0] pins
DMA transfer acknowledge signal to the external I/O device. These are connected
to nDMAAck[1:0] pins.
Indicate the DRAM access during DMA transfer. This signal connected to DRAM
Controller.
DMA transfer end interrupt signal to CPU
GDC21D601
3. Programmer’ s Model
3.1 Memory Map
The base addresses for the DMAC’s registers are not fixed and may be different for any particular system
implementation. The base address of the DMAC’s register is 0xFFFFEE00. However, the offset of any particular
DMAC’s register from the base address is fixed.
Table 2. External Signal Descriptions
ABBREVIATION
SAR0
DAR0
TNR0
CCR0
SAR1
DAR
TNR1
CCR1
TSTR0
TSTR1
TSTR2
DMAOR
ADDR.
OFFSET
H’00
H’04
H’08
H’0C
H’10
H’14
H’18
H’1C
H’20
H’24
H’28
H’2C
NAME
INITIAL
VALUE
H’00000000
H’00000000
H’00001111
H’00000000
H’00000000
H’00000000
H’00001111
H’00000000
H’00000000
H’00000000
H’00000000
H’00000000
R/W
Source Address Register for Channel 0
Destination Address Register for Channel 0
Transfer Number Register for Channel 0
Channel Control Register for Channel 0
Source Address Register for Channel 1
Destination Address Register for Channel 1
Transfer Number Register for Channel 1
Channel Control Register for channel 1
Test Register 0
Test Register 1
Test Register 2
DMA Operation Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
3.2 Source Address Register 0,1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SAB31 SAB30 SAB29 SAB28 SAB27 SAB26 SAB25 SAB24 SAB23 SAB22 SAB21 SAB20 SAB19 SAB18 SAB17 SAB16
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SAB15 SAB14 SAB13 SAB12 SAB11 SAB10 SAB9 SAB8 SAB7 SAB6 SAB5 SAB4 SAB3 SAB2 SAB1 SAB0
Figure 2. Source Address Register
3.3 Destination Address Register 0, 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DAB31DAB30DAB29 DAB28DAB27DAB26 DAB25DAB24DAB23DAB22DAB21DAB20DAB19DAB18DAB17DAB16
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAB15DAB14DAB13 DAB12DAB11DAB10 DAB9 DAB8 DAB7 DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0
Figure 3. Destination Address Register
159
GDC21D601
3.4 Transfer Number Register 0, 1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TNB15 TNB14 TNB13 TNB12 TNB11 TNB10 TNB9 TNB8 TNB7 TNB6 TNB5 TNB4 TNB3 TNB2 TNB1 TNB0
Figure 4. Transfer Number Register
3.5 Channel Control Register 0, 1
Bit
31
--
Bit
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
15
14~12
11
10
9
8
7
DRAMAcc
ACKLEN
DADRM
SADRM
TSIZE1
TSIZE0
REV.
22
--
21
--
6-5
20
--
4
19
--
3
18
--
2
17
--
16
--
1
0
RTYPE[1:0] AREQ TBUSM TENDFL INTREN CHEN
Figure 5. Channel Control Register
Table 3. Channel Control Register
15
INIT.
VALUE
0
DRAMAcc
14 ~ 12
000
ACKLEN
11
0
DADRM
10
0
SADRM
9~8
00
TSIZE[1:0]
6~5
00
RTYPE[1:0]
4
3
0
0
ATREQ
TBUSM
2
0
TENDFL
1
0
INTREN
0
0
CHEN
BIT
Others
160
0
NAME
DESCRIPTION
Indicate to the DRAM Controller during DMA transfer
0 : not DRAM access 1 : DRAM access
Enlarge the LOW phase of the DMAck signal for single address
transfer
Destination addressing mode
0 : fixed addressing
1 : incremental addressing
Source addressing mode
0 : fixed addressing
1 : incremental addressing
Transfer size
00 : Byte 01 : Half-word 10 : Word 11 : Reserved
DMA request resource selecting
00 : Memory space to Memory space
01 : Memory space to External IO Device
10 : External IO Device to Memory space
Others : Reserved
Auto request enable
Transfer bus mode
0 : Burst
1 : cycle-steal mode
Transfer end flag
0 : incomplete transfer
1 : complete transfer
Write 1 to clear this flag bit
DMA transfer complete interrupt enable
0 : interrupt disable
1 : interrupt enable
Channel mode
0 : channel disable
1 : channel enable
Reserved
GDC21D601
3.6 Test Register 0
Bit
31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
22
--
21
--
Bit
15
--
14
--
13
--
12
--
11
--
10
--
9
--
8
--
7
--
6
--
5
--
20
--
19
--
18
--
17
--
16
--
4
3
2
1
0
TCIN1 TCIN0 TREQ1TREQ0 TMEN
Figure 6. Test Register 0
Table 4. Test Register 0
BIT
4
INIT. VALUE
0
NAME
TCIN1
3
0
TCIN0
2
0
TREQ1
1
0
TREQ0
0
0
TMEN
Others
0
DESCRIPTION
Carry-in bit of channel 1 counter
0 : carry-in is not occurred
1 : carry-in is occurred
Carry-in bit of channel 0 counter
0 : carry-in is not occurred
1 : carry-in is occurred
DMAC request bit of channel 1
0 : request is not occurred
1 : request is occurred
DMAC request bit of channel 0
0 : request is not occurred
1 : request is occurred
Test mode enable bit
0 : test mode is not enable
1 : test-mode is enable
Reserved
3.7 Test Register 1
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 TA23 TA22 TA21 TA20 TA19 TA18 TA17 TA16
Bit
15
14
13
12
11
10
TA15 TA14 TA13 TA12 TA11 TA10
9
8
7
6
5
4
3
2
1
0
TA9
TA8
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Figure 7. Test Register 1
Table 5. Test Register 1
BIT
31 ~ 0
INIT. VALUE
0
NAME
TA[31:0]
DESCRIPTION
Latches BA[31:0] signal when TMEN bit of Test Register 0 is high
161
GDC21D601
3.8 Test Register 2
Bit 15
--
14
--
13
--
12
--
11
--
10
--
9
--
8
--
7
--
6
--
5
4
3
BTRAN1 BTRAN0 BSIZE1
2
1
0
BSIZE0
AREQ
BWRITE
Figure 8. Test Register 2
Table 6. Test Register 2
BIT
5~4
INIT. VALUE
00
NAME
BTRAN[1:0]
3~2
1
0
Others
00
0
0
0
BSIZE[1:0]
AREQ
BWRITE
DESCRIPTION
Latches BTRAN signal
Latches BSIZE signal
Latches AREQ signal
Latches BWRITE signal
Reserved
3.9 DMA Operation Register
Bit
31
--
30
--
29
--
28
--
27
--
26
--
25
--
24
--
23
--
22
--
21
--
20
--
19
--
18
--
Bit
15
--
14
--
13
--
12
--
11
--
10
--
9
--
8
--
7
--
6
--
5
--
4
--
3
--
2
--
Figure 9. DMA Operation Register
Table 7. DMA Operation Register
BIT
1
INIT. VALUE
0
0
0
Others
0
162
NAME
PRIOM
DMAEN
DESCRIPTION
Channel priority level selection bit
0 : Ch0 > Ch1
1 : Ch1 > Ch0
DMAC operation enable bit
0 : DMAC is not enabled
1 : DMAC is enabled
Reserved
17
--
16
--
1
0
PRIOM DMAEN
GDC21D601
4. Address Modes
4.1 Dual Address Mode
The dual address mode of DMAC are described in the Figure. 10. The source and destination area can be external
memory, internal SRAM, and external memory mapped I/O device. In dual address mode, both the transfer source
and the destination are accessed by an address. DMA Controller read the data source device and store temporarily
in temp register in DMAC. And then transfer this data destination device. So read and write transactions are
performed in one data transfer. Figure 12. shows the DMA transfer timing in the dual address mode.
The example of the register setting for dual address mode is following that : 1) set Source Address Register (SAR).
In this register you write the source area address. 2) set Destination Address Register (DAR). In this register you
write the destination area address. 3) set Transfer Number Register (TNR). In this register you can write the
transfer number value. 4) set Channel Control Register (CCR). In this register you should write properly the
control value. RTYPE[1:0] field value are should be “00”, and DARAM, SADRM fields should be “1”. You
should set the TSIZE[1:0] field properly by the transferred data width. And you must set the CHEN field to “1”.
INTREN field are set by your need. 5) finally set DMAEN field to “1” in DMA Operation Register (DMAOR). If
you set AutoReq field in CCR, as soon as set DMAEN field, DMA transfer the data.
Figure 11. show the timing diagram of DMA transfer when CCR value is 0x0D13.
Note) In the end of DMA transfer, DMA Controller is initialized by clearing the TENDFL field in CCR. This can
be performed by writing “1” value in this field.
(1) Read
Internal / External
Memory Space
DMAC
TEMP
(2) Write
Internal / External
Memory Space
Internal of MCU
Data/Address/Control
Figure 10. DMAC Dual Address Mode Block Diagram
163
GDC21D601
BCLK
AREQ
AGNT
B A [31:0]
Source Address
Destination Address
B D [31:0]
Data
B W R ITE
BTRAN[1:0]
XA[12:0]
A
N
N
S
Row Address C o l Address
N
S
A
Row Address
C o l Address
RAS
CAS
XD[15:0]
Data
Data
nDRAMOE
nDRAMWE
Figure 11. Transfer Timing in Dual Address Mode (Memory Space to Memory Space)
164
GDC21D601
4.2 Single Address Mode
The single address mode of DMAC are described in the Figure 12. In single address mode, there are two types of
transfer, one is memory-to-I/O device that source is memory area and destination is external I/O device, and the
other is external I/O device–to-memory that source is I/O device and destination is memory area. Single address
transfer mode is composed of only one data transaction, so it is very fast to transfer the data comparing with dual
addres mode in which composed of 2 transactions : read transaction and write transactio. The I/O device is acessed
by nDREQ and nDACK signals. nDACK signals are controlled by the ACKLEN field in CCR. And nDACK
signals are coincident with the RAS and CAS signals from DRAM Controller. When memory is DRAM, you must
set properly the control flags in the control register in DRAM Controller and DMA Controller.
The example of the register setting for memory-to-I/O device transfer in single address mode is following that : 1)
set Source Address Register (SAR). In this register you write the source area address. 2) set Destination Address
Register (DAR). In this register you write the destination area address. 3) set Transfer Number Register (TNR). In
this register you write the transfer number value. 4) set Channel Control Register (CCR). In this register you
should write properly the control value. When data transfer is the memory space to external I/O devices,
RTYPE[1:0] field value are should be “01”, and DARAM field is should be “0”, and SADRM fields should be “1”.
You should set the TSIZE[1:0] field properly by the transferred data width. And you must set the CHEN field to
“1”. INTREN field are set by your need. 5) finally set DMAEN field to “1” in DMA Operation Register
(DMAOR). If you set AutoReq field in CCR, as soon as set DMAEN field, DMA transfer the data.
Figure 13 shows the timing diagram of the memory-to-I/O device transfer when CCR value is 0x0523. Figure 14
shows the timing diagram of the timing diagram of the I/O device-to-memory transfer when CCR value is 0x0943.
In these case the contents of the control register for DRAM in DRAM Controller is 0x69. In the end of DMA
transfer, DMA Controller is initialized by clearing the TENDFL field in CCR. This can be performed by writing
“1” value in this field.
Address/Control
DMAC
Internal / External
Memory Space
TEMP
Internal / External
I/O Module
Data
nDACK
Internal of MCU
nDREQ
Figure 12. DMAC Single Address Mode Block Diagram
165
GDC21D601
BCLK
AREQ
AGNT
B A [31:0]
B T R A N [1:0]
Address n
A
Address n+1
N
Address n+2
N
S
B W R ITE
X A [12:0]
Row Address
Col Address n+1
Col Address n
Col Address n+2
RAS
CAS
nDREQ
nDACK
X D [15:0]
D a ta n
Data n+2
Data n+1
nDRAMOE
nDRAMWE
Figure 13. Transfer Timing in Single Burst Address Mode
(Memory Space to I/O Device with nDMACK)
BCLK
AREQ
AGNT
B A [31:0]
B T R A N [1:0]
Address
A
N
N
S
B W R ITE
X A [12:0]
R o w A d d ress C o l Address n
Col Address n+1
Col Address n+2
RAS
CAS
nDREQ
nDACK
X D [15:0]
D a ta n
Data n+1
Data n+2
nDRAMOE
nDRAMWE
Figure 14. Transfer Timing in Single Burst Address Mode
(I/O Device with nDMACK to Memory Space)
166
GDC21D601
Section 19. Debug and Test Interface
1. General Description
The GDC21D601 has built-in features which enable debug and test in a number of different contexts. Firstly, there
are circuit structures to help with software development.
Secondly, the device contains boundary scan cells for circuit board test. Finally, the device contains some special
test modes which enable the generation production patterns for the device itself.
2. Software Development Debug and Test Interface
The ARM720T Core and numerous peripherals implemented inside GDC21D601 contain hardware extensions for
advanced debugging features. These are intended to ease user development and debugging of application software,
operating systems, and the hardware itself. Full details of the debug interfaces and their programming can be found
in ARM720T Data Sheet (ARM DDI-0087). The MultiICE product enables the ARM720T to be debugged in one
environment. Refer to Guide to MultiICE (ARM DUI-0048).
3. Test Access Port and Boundary Scan
GDC21D601 contains full boundary scan on its inputs and outputs to help with circuit board test. This supports
both INTEST and EXTEST, allowing patterns to be applied serially to the GDC21D601 when fixed in a board and
for full circuit board connection respectively.
The boundary-scan interface conforms to the IEEE Std. 1149.1- 1990, Standard Test Access Port and
Boundary-Scan Architecture. (Please refer to this standard for an explanation of the terms used in this
section and for a description of the TAP controller states.) The boundary-scan interface provides a
means of testing the core of the device when it is fitted to a circuit board, and a means of driving and
sampling all the external pins of the device irrespective of the core state. This latter function permits
testing of both the device’ selectrical connections to the circuit board, and (in conjunction with other
devices on the circuit board having a similar interface) testing the integrity of the circuit board
connections between devices. The interface intercepts all external connections within the device, and
each such “ cell?is then connected together to form a serial register (the boundary scan register). The
whole interface is controlled via 5 dedicated pins: TDI, TMS, TCK, nTRST and TDO.
Full details of the debug interfaces and their programming can be found in ARM720T Data Sheet (ARM DDI0087E, Section 8 Debug Architecture).
167
GDC21D601
3.1 Reset
The boundary-scan interface includes a state-machine controller (the TAP controller).
A pulldown resistor is included in the nTRST pad which holds the TAP controller state machine in a safe state
after power up. In order to use the boundary scan interface, nTRST should be driven HIGH to take the TAP state
machine out of reset.
The action of reset (either a pulse or a DC level) is as follows:
* System mode is selected (i.e. the boundary scan chain does NOT intercept any of the signals passing between
the pads and the core).
* IDcode mode is selected. If TCK is pulsed, the contents of the ID register will be clocked out of TDO.
Note : The TAP controller inside ARM7201 contains a scan chip register which is reset to the value b0011 thus
selecting the boundary scan chain. If this register is programmed to any value other than b0011, then it
must be reprogrammed with b0011 or a reset applied before boundary scan operation can be attempted.
3.2 Pullup Resistors
The IEEE 1149.1 standard requires pullup resistors in the input pins. However, to ensure safe operation an internal
pulldown is present in the nTRST pin and therefore will have to be driven HIGH when using this interface.
Table 1. Internal Resistors for Input Pins
PIN
TCLK
nTRST
TMS
TDI
168
INTERNAL RESISTOR
Pullup
Pulldown
Pullup
Pullup
GDC21D601
Section 20. Electrical Ratings
1. Absolute Maximum Ratings
2. Thermal Characteristics
3. D.C Electrical Characteristics
169
GDC21D601
APENDIX A. Register Map
The following diagram shows System Memory Map of GDC21D601.
0XFFFF FFFF
APB Register
0XFFFF FFFF
FD00
0XFFFF E000
0X5000 0000
FB00
I2C2
0X4000 0000
FA00
I2C1
F900
I2C0
SSI
UART1
0X1000 1000
UART0
0X1000 0000
F200
F100
F000
EE00
ED00
Chip Select Area
0X0000 0000
EC00
EB00
RTC
INTC
WDT
PMU
DRAMC
SMI
MCUC
ON-CHIP RAM
WINDOW AREA
0X0800 0000
0X0700 0000
0X0600 0000
0X0500 0000
0X0400 0000
DMAC
Figure 1. System Memory Map
170
WINDOW AREA
TIMER
EF00
0X0800 0000
DRAM BANK #0
0X2000 0000
F600
F300
Reserved
DRAM BANK #1
UART2/Smart
F400
ARM7 TEST REG
0X3000 0000
F700
F500
Reserved
0X6000 0000
PIO
F800
MEMORY AREA
0XFFFF EAFF
FC00
0XFFFF F000
ASB Register
Reserved
0X0300 0000
0X0200 0000
0X0100 0000
0X0000 0000
nCS7
nCS6
nCS5
nCS4
nCS3
nCS2
nCS1
nCS0
GDC21D601
DMA Controller Registers(@0xFFFF EE00)
ABBREVIATION
ADDRESS
DESCRIPTIONS
R/W
INITIAL VALUE
SAR0
DAR0
TNR0
CCR0
0xFFFFEE00
0xFFFFEE04
0xFFFFEE08
0xFFFFEE0C
R/W
R/W
R/W
R/W
32h’00000000
32h’00000000
32h’00001111
32h’00000000
SAR1
DAR
TNR1
CCR1
TSTR0
TSTR1
TSTR2
DMAOR
0xFFFFEE10
0xFFFFEE14
0xFFFFEE18
0xFFFFEE1C
0xFFFFEE20
0xFFFFEE24
0xFFFFEE28
0xFFFFEE2C
Source Address Register for Channel 0
Destination Address Register for Channel 0
Transfer Number Register for Channel 0
Channel Control Register for Channel 0
Bit 15 : DRAM Access indicator
0: Not DRAM 1: DRAM transfer
Bit 14-12 : DMAck Low length
Bit 11 : Destination Addressing mode
0: Fixed 1: Incremental addressing
Bit 10 : Source Addressing mode
0: Fixed 1: Incremental addressing
Bit 9-8 : Transfer size
00:Byte
01:Half-word
10:Word
11:Reserved
Bit 7 : Reserved
Bit 6-5 : DMA Request mode
00 : Mem. space to Mem. space
01 : Mem.External IO Device
10 : Ext. IO Device to Mem.
11 : Reserved
Bit 4 : Auto Request Enable
Bit 3 : Transfer bus mode
0:Burst 1:Cycle-steal mode
Bit 2 : Transfer End flag
0:incomplete 1: complete
Bit 1 : Transfer complete interrupt Enable
0: disabled
1: enabled
Bit 0 : Channel control
0: Ch 0 disabled
1: Ch 0 enabled
Source Address Register for Channel 1
Destination Address Register for Channel 1
Transfer Number Register for Channel 1
Channel Control Register for channel 1
Test Register 0
Test Register 1
Test Register 2
DMA Operation Register
Bit 7-2 : Reserved
Bit 1: Channel priority level select
0: Ch0 > Ch1
1: Ch0 < Ch1
Bit 0 : DMAC operation control
0: enabled
1: disabled
R/W
R/W
R/W
R/W
R/W
R
R
R/W
32h’00000000
32h’00000000
32h’00001111
32h’00000000
32h’00000000
32h’00000000
32h’00000000
32h’00000000
171
GDC21D601
DRAM Controller Registers(@0xFFFFED00)
ABBREVIATION
ADDRESS
DESCRIPTIONS
R/W
INITIAL VALUE
DRAMRCR
0xFFFFED00
W
16h’0000
DRAMconCPU
0xFFFFED04
R/W
7b’0000000
DRAMCDMA
0xFFFFED08
DRAM Refresh Control Register
Bit 15-8: REFCNT
(DRAM Refresh Clock Divisor)
RefClock = BCLK / REFCNT
Bit 7 : DRAM Refresh clock control
0 / 1 = Disabled / Enabled
Bit 6-0 : REFDIV(DRAM Refresh rate)
Frequency (KHz)
= 2*[RefClock /(RFDIV + 1)]
DRAM Controller for CPU
Bit 15-7: Reserved
Bit 6: DMAEn(DMA Control signal )
0 / 1 = DMA Disabled / Enabled
Bit 5: TRP( trp = |RAS-CAS| )
Bit 4 : TCP(tcp= |Low phase of CAS|)
Bit 3-2: Wait count
00: 0-wait
01: 1-wait
10: 2-wait
11: 3-wait
Bit 1-0: Bank size
00 : byte
01 : Half-word
10 : Word
11 : Reserved
DRAM Controller for DMA
Bit 15-6: Reserved
Bit 5: TRP( trp = |RAS-CAS| )
Bit 4 : TCP(tcp= |Low phase of CAS|)
Bit 3-2: Wait count
00: 0-wait
01: 1-wait
10: 2-wait
11: 3-wait
Bit 1-0: Bank size
00 : byte
01 : Half-word
10 : Word
11 : Reserved
R/W
6b’000000
172
GDC21D601
DRAM Controller Registers(@0xFFFFED00) -- Continued
ABBREVIATION
DRAMTCR
ADDRESS
0xFFFFED0C
DESCRIPTIONS
DRAM Test Control Register
Bit 15-4: Reserved
Bit 3: TESTINC(Test Increment)
Column address auto increment
0 / 1 = Disabled / Enabled
Bit 2: FORCEADV
Forces refresh counter by BCLK
0 / 1 = Disabled / Enabled
Bit 1-0: Force size
00 : byte
01 : Half-word
10 : Word (Default)
11 : Reserved
R/W
INITIAL VALUE
W
4b’0010
173
GDC21D601
Static Memory Controller Registers(@0xFFFF F000)
ABBREVIATION
ADDRESS
DESCRIPTIONS
R/W
INITIAL VALUE
MEMCFG1
0xFFFFEC00
Memory Configuration Register 1
nCS1 area control
Bit 31-30: Reserved
Bit 29: EXPRDY polarity (0:Active High)
Bit 28: Control signal type
0/1=ARM type / Motorola type:
Bit 27: FlashON –Reserved
Bit 26: Expansion clock Enable
Bit 25-24: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 23: Burst mode Enable – Reserved
Bit 22-20: Burst wait cycle –Reserved
Bit 19-16: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
R/W
32’h0000000
4
nCS0 area control
Bit 15-14: Reserved
Bit 13: EXPRDY polarity (0:Active High)
Bit 12: Control signal type
0/1=ARM type / Motorola type:
Bit 11: FlashON –Reserved
Bit 10 : Expansion clock Enable
Bit 9-8: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 7: Burst mode Enable – Reserved
Bit 6-4: Burst wait cycle – Reserved
Bit 3-0: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
174
0 : Default
1 cycle
4 : Default
5 cycles
GDC21D601
Static Memory Controller Registers(@0xFFFF F000) -- Continued
ABBREVIATION
ADDRESS
DESCRIPTIONS
R/W
INITIAL VALUE
MEMCFG2
0xFFFFEC04
Memory Configuration Register 2
NCS3 area control
Bit 31-30: Reserved
Bit 29: EXPRDY polarity (0:Active High)
Bit 28: Control signal type
0/1=ARM type / Motorola type
Bit 27: FlashON –Reserved
Bit 26: Expansion clock Enable
Bit 25-24: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 23: Burst mode Enable – Reserved
Bit 22-20: Burst wait cycle –Reserved
Bit 19-16: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
R/W
32’h0000000
0
MEMCFG3
0xFFFFEC08
MEMCFG4
0xFFFFEC0C
NCS2 area control
Bit 15-14: Reserved
Bit 13: EXPRDY polarity (0:Active High)
Bit 12: Control signal type
0/1=ARM type / Motorola type:
Bit 11: FlashON –Reserved
Bit 10 : Expansion clock Enable
Bit 9-8: Mem width
00: 32-bit memory
01: 16-bit memory
10: 8-bit memory
11: Reserved
Bit 7: Burst mode Enable – Reserved
Bit 6-4: Burst wait cycle –Reserved
Bit 3-0: Access wait cycle(1~16cycles)
0000(1 cycle) ~ 1111(16 cycles)
Memory Configuration Register 3
NCS4,3 area controls
Memory Configuration Register 4
NCS6,5 area controls
Default
1 cycle
R/W
R/W
Default
1 cycle
32’h0000000
0
32’h0000000
0
175
GDC21D601
MCU Controller Registers(@0xFFFF EC00)
ABBREVIATION
MCUC
PINMUX_PA
PINMUX_PB
PINMUX_PC
PINMUX_PD
PINMUX_PE
PINMUX_PF
PINMUX_PG
PINMUX_PH
PINMUX_PI
PINMUX_PJ
MCUDC
DRAMPDACK
DRAMPDREQ
176
ADDRESS
0xFFFFEB00
0xFFFFEB04
0xFFFFEB08
0xFFFFEB0C
0xFFFFEB10
0xFFFFEB14
0xFFFFEB18
0xFFFFEB1C
0xFFFFEB20
0xFFFFEB24
0xFFFFEB28
0xFFFFEB2C
0xFFFFEB30
0xFFFFEB34
DESCRIPTIONS
MCU Control Register
Port A MUX Register (Port A[5:0])
Port B MUX Register (Port B[7:0])
Port C MUX Register (Port C[7:0])
Port D MUX Register (Port D[7:0])
Port E MUX Register (Port E[7:0])
Port F MUX Register (Port F[7:0])
Port G MUX Register (Port G[7:0])
Port H MUX Register (Port H[7:0])
Port I MUX Register (Port I[7:0])
Port J MUX Register (Port J[7:0])
MCU Device Code Register
DRAM Power Down Ack
DRAM Power Down Request
R/W
INITIAL VALUE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
8h’00
24h’LG601
8h’00
8h’00
GDC21D601
PMU Registers (@0xFFFF F000)
ABBREVIATION
PMUCR
BCLKCR
ADDRESS
0xFFFFF000
0xFFFFF004
DESCRIPTIONS
PMU Control Register
Only following values are effective.
0x00 := Clear PMU status register
0x03 := Enters the Power Down mode
PMU Status Register
Bit 7-6: Reserved
Bit 5-4: Previous Reset Status
00 : Power-On Reset status
01 : S/W Reset state by PMU
10 : S/W Manual Reset by WDT
11 : WD overflow Reset state by WDT
Bit 3-2: Current status flag bits
00 : Running state after nPOR
01 : Running state after WD_OF
10 : Running state after Man_Reset
11 : Reserved
Bit 1-0: Previous status flag bits
00 : Start state after nPOR
01 : Start state after WD_OF
10 : Start state after Man_Reset
11 : Start state after PD mode
BCLK frequency selection and BUS mode
control(Standard / Fast BUS mode)
Bit 7-4: Reserved
Bit 3: FCLK control bit
0 – Fast-bus mode (not use the FCLK)
1 – Standard-bus mode
Use FCLK as SYS_CLK
Bit 2-0: BCLK selection bits
000 : BCLK = SYS_CLK / 2
001 : BCLK = SYS_CLK / 4
010 : BCLK = SYS_CLK / 8
011 : BCLK = SYS_CLK / 16
100 : BCLK = SYS_CLK / 32
101 : BCLK = SYS_CLK / 64
110 : BCLK = SYS_CLK / 128
111 : BCLK = SYS_CLK.
R/W
W
INITIAL VALUE
8h’00
R
R/W
8h’00
177
GDC21D601
PMU Registers (@0xFFFF F000) -- Continued
ABBREVIATION
BCLKMSK_RUN
ADDRESS
0xFFFFF008
BCLKMSK_PD
0xFFFFF00C
REMAP
PCLKCR
0xFFFFF010
0xFFFFF014
178
DESCRIPTIONS
BCLK Masking controls register in the
RUN mode.
Enable / Disable clock : 1/0
Bit 15-13 : Reserved
Bit 12 : APB Bridge clock control
Bit 11 : BUS Controller clock control
Bit 10 : DRAM Controller clock control
Bit 9 : DMA Controller clock mask bit
Bit 8 : TEST Controller clock mask bit
Bit 7 : SRAM clock mask bit
Bit 6-1 : Reserved
Bit 0 : B_CLK Out mask bit
BCLK controls register (PD mode.)
Enable / Disable clock : 1/0
Bit 15 : ARM7TDMI Core clock control
Bit 14 : AMBA Arbiter clock control
Bit 13 : AMBA Decoder clock control
Bit 12 : APB Bridge clock control
Bit 11 : BUS Controller clock control
Bit 10 : DRAM Controller clock control
Bit 9 : DMA Controller clock control
Bit 8 : TEST Controller clock control
Bit 7 : SRAM clock control
Bit 6-1 : Reserved
Bit 0 : B_CLK Out control
REMAP register
PCLK control register
Bit 7-3 : Reserved
Bit 2-0: PCLK selection
000 : PCLK = external PCLK source
001 – PCLK = SCLK / 2
010 – PCLK = SCLK / 4
011 – PCLK = SCLK / by 8
100 – PCLK = SCLK / 16
101 – PCLK = SCLK / 32
110 – PCLK = SCLK / 64
111 – PCLK = SCLK / 128
R/W
R/W
INITIAL VALUE
16h’FFFF
R/W
16h’0000
R/W
R/W
8h’00
8h’00
GDC21D601
PMU Registers (@0xFFFF F000) -- Continued
ABBREVIATION
PCLKMSK_RUN
ADDRESS
0xFFFFF018
PCLKMSK_PD
0xFFFFF01C
Reserved
RSTCR
0xFFFFF020
0xFFFFF030
TSTCR
0xFFFFF040
Device Code
TSTR0
0xFFFFF044
0xFFFFF048
DESCRIPTIONS
PCLK control register in RUN mode.
Enable / Disable clock : 1/0
Bit 9 : Watchdog Timer clock control
Bit 8 : I2 C 2 clock control
Bit 7 : I2 C 1 clock control
Bit 6 : I2 C 0 clock control
Bit 5 : SSPI 1 clock control
Bit 4 : SSPI 0 clock control
Bit 3 : UART 2/ SMIC clock control
Bit 2 : UART 1 clock control
Bit 1 : UART 0 clock control
Bit 0 : Timer clock control
PCLK control register in PD mode.
Enable / Disable clock : 1/0
Bit 9 : Watchdog Timer clock control
Bit 8 : I2 C 2 clock control
Bit 7 : I2 C 1 clock control
Bit 6 : I2 C 0 clock control
Bit 5 : SSPI 1 clock control
Bit 4 : SSPI 0 clock control
Bit 3 : UART 2/ SMIC clock control
Bit 2 : UART 1 clock control
Bit 1 : UART 0 clock control
Bit 0 : Timer clock control
Reserved
Reset control register
Manual / Normal Reset : 1 / 0
Bit 7-1 : Reserved
Bit 0 : Manual Reset control
TIC test mode and PMU test control
register
Normal Operation / TIC-PMU test : 1 / 0
Bit 7-2 : Reserved
Bit 1 : TIC test mode when set to 1
Bit 0 : PMU test mode when set to 1
Reserved
Test write register for external input signals
Bit 7-3 : Reserved
Bit 2 : Test bit for INT_REQ_IN input
Bit 1 : Test bit for WD_OF_IN input
Bit 0 : Test bit for MAN_RESET input
R/W
R/W
INITIAL VALUE
10h’11FF
R/W
8h’00
R/W
R/W
8h’00
8h’00
R/W
8h’00
R
R
$LG601
8h’00
179
GDC21D601
PMU Registers (@0xFFFF F000) -- Continued
ABBREVIATION
TSTR1
180
ADDRESS
0xFFFFF04C
DESCRIPTIONS
Test read register for clocks of ASB devices
and reset signals
Bit 15 : Test bit for BCLK_WDT
Bit 14 : Test bit for PCLK_I2C 2
Bit 13 : Test bit for PCLK_I2C 1
Bit 12 : Test bit for PCLK_I2C 0
Bit 11 : Test bit for PCLK_SSPI 1
Bit 10 : Test bit for PCLK_SSPI 0
Bit 9 : Test bit for PCLK_UART 2
Bit 8 : Test bit for PCLK_UART 1
Bit 7 : Test bit for PCLK_UART 0
Bit 6 : Test bit for BCLK_TIMER
Bit 5 : Test bit for B_RESETn
Bit 4 : Test bit for P_RESETn0
Bit 3 : Test bit for P_RESETn1
Bit 2 : Test bit for P_RESETn
Bit 1 : Test bit for WD_OF_OUT
Bit 0 : Test bit for REMAP
R/W
R
INITIAL VALUE
16h’0000
GDC21D601
Watchdog Timer Register (@0xFFFF F100)
ABBREVIATION
WDTC
ADDRESS
0xFFFFF100
WDTS
0xFFFFF104
WDTCNT
WDTEST
WDTESTO
0xFFFFF108
0xFFFFF10C
0xFFFFF114
DESCRIPTIONS
Watchdog Timer Control Register
Bit 7: Interrupt Request
0 / 1 = Interrupt Disable / Enable
Bit 6: Timer Mode Select
0 / 1 = Interval / Watchdog
Bit 5: Timer Control
0 / 1 = Disable / Enable
Bit 4: WD Reset Control
0 / 1 = Disable / Enable
Bit 3: Reset Select (if WD overflowed)
0 / 1 = POR / Manual Reset
Bit 2-0: Clock Select
000 = CKS0 / 2
001 = CKS1 / 8
010 = CKS2 / 32
011 = CKS2 / 64
100 = CKS2 / 256
101 = CKS2 / 512
110 = CKS2 / 2048
111 = CKS2 / 8192
Watchdog Timer Reset Status Register
Bit 1: ITOVF(internal timer overflowed)
Bit 0: WTOVF(WD timer overflowed)
Watchdog Timer Counter Register
Watchdog Timer Test Input Register
Watchdog Timer Test Output Register
R/W
R/W
INITIAL VALUE
8b’00000000
R
2b’00
R/W
R/W
R/W
8h’00
8h’00
8h’00
R/W
R/W
R/W
R
R/W
R/W
W
W
W
INITIAL VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
RTC Control Register (@0xFFFF F300)
ABBREVIATION
RTCDR
RTCMR
RTCS
RTCDV
RTCCR
RTCTS
RTCTIC32K
RTCTICPCLK
ADDRESS
0xFFFFF300
0xFFFFF304
0xFFFFF308
0xFFFFF30C
0xFFFFF310
0xFFFFF314
0xFFFFF318
0xFFFFF31C
DESCRIPTIONS
RTC Data Register
RTC Match Register
RTC status
RTC clock divider
RTC control register
RTC TIC Selection Register
TicCLK32K
TicCLKPCLK
181
GDC21D601
Interrupt Controller Register (@0xFFFF F200)
ABBREVIATION
INTC
ADDRESS
0xFFFFF200
INTMD
INTPOL
0xFFFFF204
0xFFFFF208
INTDIR
0xFFFFF20C
INTFIQS
INTIRQS
INTFIQMSK
INTIRQMSK
INTSCL
0xFFFFF210
0xFFFFF214
0xFFFFF218
0xFFFFF21C
0xFFFFF220
INTTICIN
INTTICOUT
0xFFFFF240
0xFFFFF280
182
DESCRIPTIONS
Interrupt Control/Mask Register
INT25 : SWI(Software Interrupt)
INT24 : Timer 5
INT23 : Timer 4
INT22 : Timer 3
INT21 : Timer 2
INT20 : Timer 1
INT19 : Timer 0
INT18 : SSPI 1
INT17 : SSPI 0
INT16 : Smart Card Interface
INT15 : UART 1
INT14 : UART 0
INT13 : I2C 2
INT12 : I2C 1
INT11 : I2C 0
INT10: WDT(Watchdog Timer)
INT9 : RTC(Real Time Clock)
INT8 : DMA(Direct Memory Access)
INT7 : COM RX
INT6 : COM TX
INT5 : External Interrupt 5
INT4 : External Interrupt 4
INT3 : External Interrupt 3
INT2 : External Interrupt 2
INT1 : External Interrupt 1
INT0 : External Interrupt 0
Interrupt Trigger Mode control
Interrupt Trigger Polarity control Register.
Mode
Polarity
Triggered by
0
0
Falling Edge
0
1
Rising Edge
1
0
Low Level
1
1
High Level
Interrupt direction control Register
(0 / 1 = Request IRQ / FIQ)
FIQ Status Flag Register ( 0/1 = Clear/Set)
IRQ Status Flag Register( 0/1 = Clear/Set)
FIQ Mask Register( 0/1 = Clear/Masked)
IRQ Mask Register( 0/1 = Clear/Masked)
Interrupt Status Clear Register
0 / 1 = Clear / Set
TIC Input Register
TIC Output Register
R/W
R/W
INITIAL VALUE
26h’3FFFFFF
R/W
R/W
26h’2000000
26h’2000000
R/W
26h’0000000
R
R
R/W
R/W
W
26h’0000000
26h’0000000
26h’0000000
26h’0000000
26h’0000000
R/W
R/W
0x00
0x00
GDC21D601
General Purpose Timer Unit Control Register(@0xFFFFF400)
ABBREVIATION
TSTARTR
ADDRESS
0xFFFFF400
TSYNCR
0xFFFFF404
TPWMR
0xFFFFF408
TSTINR
TSTOUTR
TSTMODER
TSTINTR
0xFFFFF40C
0xFFFFF410
0xFFFFF414
0xFFFFF418
TCONTR0
0xFFFFF420
TIOCR0
0xFFFFF424
DESCRIPTIONS
Timer Start Register
Bit 7-6 : Reserved
Bit 5-0 : 1:start counting, 0:stop counting
Timer Sync. Register
Bit 7-6 : Reserved
Bit 5-0 : 1:sync. mode, 0:normal mode
Timer PWM Register(1=PWM,0=normal)
Bit 7-6 : Reserved
Bit 5-0 : 1: PWM mode, 0:normal mode
R/W
R/W
INITIAL VALUE
8b’11000000
R/W
8b’11000000
R/W
8b’11000000
W
R
W
R
Timer 0 Control Register
8b’1xx11yyy
xx : mode selection
00 : not cleared-Free running mode
01 : cleared by GRA(periodic mode)
10 : cleared by GRB(periodic mode)
11 : cleared in sync w/ other sync. timer
yyy : timer clock prescaler selection
000 : timer clock = BCLK/2
001 : timer clock = BCLK/4
010 : timer clock = BCLK/16
011 : timer clock = BCLK/64
100 : timer clock = EXT_CLK/2
101 : timer clock = EXT_CLK/4
110 : timer clock = EXT_CLK/64
111 : timer clock = EXT_CLK/2
R/W
8b’10011000
Timer 0 I/O Control Register
8b’1xxx1yyy
xxx : GRB function select
000 : compare match with no output
001 : output 0 when matched
010 : output 1 when matched
011 : output toggle when matched
100 : GRB input captured at rising edge
101 : GRB input captured at falling edge
110 : GRB input captured at both edge
yyy : GRA function select
000 : compare match with no output
001 : output 0 when matched
010 : output 1 when matched
011 : output toggle when matched
100 : GRA input captured at rising edge
101 : GRA input captured at falling edge
110 : GRA input captured at both edge
R/W
8b’10001000
183
GDC21D601
General Purpose Timer Unit Control Register(@0xFFFFF400) -- Continued
ABBREVIATION
TIER0
TSTATUSR0
TCOUNT0
GRA0
GRB0
TCONTR1
TIOCR1
TIER1
TSTATUSR1
TCOUNT1
GRA1
GRB1
TCONTR2
TIOCR2
TIER2
TSTATUSR2
TCOUNT2
GRA2
GRB2
TCONTR3
TIOCR3
TIER3
TSTATUSR3
TCOUNT3
GRA3
GRB3
TCONTR4
TIOCR4
TIER4
TSTATUSR4
TCOUNT4
GRA4
GRB4
184
ADDRESS
0xFFFFF428
0xFFFFF42C
0xFFFFF430
0xFFFFF434
0xFFFFF438
0xFFFFF440
0xFFFFF444
0xFFFFF448
0xFFFFF44C
0xFFFFF450
0xFFFFF454
0xFFFFF458
0xFFFFF460
0xFFFFF464
0xFFFFF468
0xFFFFF46C
0xFFFFF470
0xFFFFF474
0xFFFFF478
0xFFFFF480
0xFFFFF484
0xFFFFF488
0xFFFFF48C
0xFFFFF490
0xFFFFF494
0xFFFFF498
0xFFFFF4A0
0xFFFFF4A4
0xFFFFF4A8
0xFFFFF4AC
0xFFFFF4B0
0xFFFFF4B4
0xFFFFF4B8
DESCRIPTIONS
Timer 0 Interrupt Enable Register
8b’11111xyz
x,y,z = 0 : disable interrupt
x,y,z = 1 : enable interrupt
x = 1 : interrupt by Overflow
y = 1 : interrupt by MCIB
z = 1 : interrupt by MCIA
Timer 0 Status Register
8b’11111xyz
x (OVFI)=1 Timer Counter
Overflow/underflow occurred
y(MCIB) =1 GRB input capture/compare
match occurred
z(MCIA) =1 GRA input capture/compare
match occurred
Timer 0 Counter Register
Timer 0 General data A Register
Timer 0 General data B Register
Timer 1 Control Register
Timer 1 I/O Control Register
Timer 1 Interrupt Enable Register
Timer 1 Status Register
Timer 1 Counter Register
Timer 1 Data A Register
Timer 1 Data B Register
Timer 2 Control Register
Timer 2 I/O Control Register
Timer 2 Interrupt Enable Register
Timer 2 Status Register
Timer 2 Counter Register
Timer 2 Data A Register
Timer 2 Data B Register
Timer 3 Control Register
Timer 3 I/O Control Register
Timer 3 Interrupt Enable Register
Timer 3 Status Register
Timer 3 Counter Register
Timer 3 Data A Register
Timer 3 Data B Register
Timer 4 Control Register
Timer 4 I/O Control Register
Timer 4 Interrupt Enable Register
Timer 4 Status Register
Timer 4 Counter Register
Timer 4 Data A Register
Timer 4 Data B Register
R/W
R/W
INITIAL VALUE
8b’11111000
R
8b’11111000
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
16h’0000
16h’0000
16h’0000
8b’10011000
8b’10001000
8b’11111000
8b’11111000
16h’0000
16h’0000
16h’0000
8b’10011000
8b’10001000
8b’11111000
8b’11111000
16h’0000
16h’0000
16h’0000
8b’10011000
8b’10001000
8b’11111000
8b’11111000
16h’0000
16h’0000
16h’0000
8b’10011000
8b’10001000
8b’11111000
8b’11111000
16h’0000
16h’0000
16h’0000
GDC21D601
PIO Register (@0xFFFF FC00)
ABBREVIATION
ADDRESS
PADR
0xFFFFFC00
PADDR
0xFFFFFC04
PBDR
0xFFFFFC08
PBDDR
0xFFFFFC0C
PCDR
0xFFFFFC10
PCDDR
0xFFFFFC14
PDDR
PDDDR
PEDR
PEDDR
0xFFFFFC18
0xFFFFFC1C
0xFFFFFC20
0xFFFFFC24
DESCRIPTIONS
Port A Data Register
At Power-On default, set as IRQ pins.
IRQ[5:0] when PINMUX_PA[5:0 ] = 0
PIOA[5:0] when PINMUX_PA[5:0 ] = 1
PA[7:6] is always set to PIO
Port A Direction control Register
1: Input Port 0: Output Port
Port B Data Register
At Power-On default, set as TimerOut pins.
Timer Out when PINMUX_PB[7:0 ] = 0
PIOB[7:0] when PINMUX_PB[7:0 ] = 1
Port B Direction control Register
1: Input Port 0: Output Port
Port C Data Register
At Power-On default, set as TimerIn pins.
Timer In when PINMUX_PC[7:0 ] = 0
PIOC[7:0] when PINMUX_PC[7:0 ] = 1
Port C Direction control Register
1: Input Port 0: Output Port
Port D Data Register
At Power-On default, set as UART pins
NRI when PINMUX_PD[7] = 0
NDCD when PINMUX_PD[6] = 0
NDSR when PINMUX_PD[5] = 0
NCTS when PINMUX_PD[4] = 0
TXD1 when PINMUX_PD[3] = 0
RXD1 when PINMUX_PD[2] = 0
TXD0 when PINMUX_PD[1] = 0
RXD0 when PINMUX_PD[0] = 0
PIOD[7:0] when PINMUX_PD[7:0 ] = 1
Port D Direction control Register
1: Input Port 0: Output Port
Port E Data Register
At Power-On default, set as SM/UART pins
SCLK0 when PINMUX_PE[7] = 0
SOUT0 when PINMUX_PE[6] = 0
SIN0 when PINMUX_PE[5] = 0
SMCLK when PINMUX_PE[4] = 0
SMDO when PINMUX_PE[3] = 0
SMDI when PINMUX_PE[2] = 0
NRTS when PINMUX_PE[1] = 0
NDTR when PINMUX_PE[0] = 0
PIOE[7:0] when PINMUX_PE[7:0 ] = 1
PIOE[7:0] when PINMUX_PE[7:0 ] = 1
Port E Direction control Register
1: Input Port 0: Output Port
R/W
INITIAL VALUE
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
185
GDC21D601
PIO Register (@0xFFFF FC00) -- Continued
ABBREVIATION
PFDR
ADDRESS
0xFFFFFC28
PFDDR
0xFFFFFC2C
PGDR
0xFFFFFC30
PGDDR
0xFFFFFC34
PHDR
0xFFFFFC38
PHDDR
0xFFFFFC3C
PIDR
0xFFFFFC40
PIDDR
0xFFFFFC44
PJDR
0xFFFFFC48
PJDDR
0xFFFFFC4C
186
DESCRIPTIONS
Port F Data Register
At Power-On default, set as SSPI pins
NIRQOUT when PINMUX_PF[7] = 0
NFIQOUT when PINMUX_PF[6] = 0
BCLKOUT when PINMUX_PF[5] = 0
SCS1 when PINMUX_PF[4] = 0
SCLK1 when PINMUX_PF[3] = 0
SOUT1 when PINMUX_PF[2] = 0
SIN1 when PINMUX_PF[1] = 0
SCS0 when PINMUX_PF[0] = 0
PIOE[7:0] when PINMUX_PF[7:0 ] = 1
PIOE[7:0] when PINMUX_PF[7:0 ] = 1
PIOF[7:0] when PINMUX_PF[7:0 ] = 1
Port F Direction control Register
1: Input Port 0: Output Port
Port G Data Register
At Power-On default, set as DMA pins
RAS1 when PINMUX_PG[7] = 0
RAS0 when PINMUX_PG[6] = 0
DACK1 when PINMUX_PG[5] = 0
DREQ0 when PINMUX_PG[4] = 0
SMDO when PINMUX_PG[3] = 0
SMDI when PINMUX_PG[2] = 0
NRTS when PINMUX_PG[1] = 0
NDTR when PINMUX_PG[0] = 0
PIOG[7:0] when PINMUX_PG[7:0 ] = 1
Port G Direction control Register
1: Input Port 0: Output Port
Port H Data Register
At Power-On default, set as DRAM pins
CAS[3:0] when PINMUX_PH[3:0 ] = 0
PIOH[3:0] when PINMUX_PH[3:0 ] = 1
CS[7:4] when PINMUX_PH[7:4 ] = 0
PIOH[7:4] when PINMUX_PH[7:4 ] = 1
Port H Direction control Register
1: Input Port 0: Output Port
Port I Data Register
At Power-On default, set as DBUS pins
D[23:16] when PINMUX_PI[7:0 ] = 0
PIOI[7:0] when PINMUX_PI[7:0 ] = 1
Port I Direction control Register
1: Input Port 0: Output Port
Port J Data Register
At Power-On default, set as DBUS pins
D[31:24] when PINMUX_PJ[7:0 ] = 0
PIOJ[7:0] when PINMUX_PJ[7:0 ] = 1
Port J Direction control Register
1: Input Port 0: Output Port
R/W
R/W
INITIAL VALUE
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
8b’00000000
R/W
R/W
R/W
8b’00000000
8b’00000000
8b’00000000
GDC21D601
SSPI Register (@ 0xFFFF F800)
ABBREVIATION
SSCR0A
SSCR0B
SSDR0
SSSR0
SSTR0
SSCR1A
SSCR1B
ADDRESS
0xFFFFF800
0xFFFFF804
0xFFFFF808
0xFFFFF80C
0xFFFFF810
0xFFFFF820
0xFFFFF824
DESCRIPTIONS
SSPI 0 Control Register A
Bit 7 : Enters Test mode when set to 0
Bit 6 : CS is Active High when set to 0
Bit 5 : SSPI 0 Disabled when set to 0
Bit 4 : Slave mode when set to 0
Bit 3 : LSB input first when set to 0
Bit 2 : LSB out first when set to 0
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 0 Control Register B
Bit 7 : Tx interrupt enabled when set to 1
Bit 6 : Tx FIFO empty interrupt enable
Bit 5 : Rx FIFO full interrupt enable
Bit 4 : Tx FIFO full interrupt enable
Bit 3 : Rx FIFO enabled when set to 1
Bit 2 : Tx FIFO enabled when set to 1
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 0 Data Register
SSPI 0 Status Register
Bit 7 : Rx FIFO Empty
Bit 6 : Tx FIFO Empty
Bit 5 : Rx FIFO FULL
Bit 4 : Tx FIFO FULL
Bit 3 : Tx END
Bit 2 : Reserved
Bit 1 : Reserved
Bit 0 : SSPI BUSY
SSPI 0 Term Register
SSPI 1 Control Register A
Bit 7 : Enters Test mode when set to 0
Bit 6 : CS is Active High when set to 0
Bit 5 : SSPI 0 Disabled when set to 0
Bit 4 : Slave mode when set to 0
Bit 3 : LSB input first when set to 0
Bit 2 : LSB out first when set to 0
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
SSPI 1 Control Register B
Bit 7 : Tx interrupt enabled when set to 1
Bit 6 : Tx FIFO empty interrupt enable
Bit 5 : Rx FIFO full interrupt enable
Bit 4 : Tx FIFO full interrupt enable
Bit 3 : Rx FIFO enabled when set to 1
Bit 2 : Tx FIFO enabled when set to 1
Bit 1 : Rising edge clock when set to 0
Bit 0 : Slave: CS disabled when set to 0
R/W
R/W
R/W
R/W
R
W
R/W
R/W
INITIAL VALUE
8b’11111111
1: Normal
1: Active Low
1: Enabled
1: Master
1: MSB in
1: MSB out
1: Falling
1: CS enabled
8b’00000000
0: Disable
0: Disable
0: Enabled
0: Master
0: MSB in
0: MSB out
0: Falling
0: CS enabled
8b’11111111
8b’00000000
8b’11111111
8b’11111111
1: Normal
1: Active Low
1: Enabled
1: Master
1: MSB in
1: MSB out
1: Falling
1: CS enabled
8b’00000000
0: Disable
0: Disable
0: Enabled
0: Master
0: MSB in
0: MSB out
0: Falling
0: CS enabled
187
GDC21D601
SSPI Register (@ 0xFFFF F800) -- Continued
ABBREVIATION
SSDR1
SSSR1
SSTR1
ADDRESS
0xFFFFF828
0xFFFFF82C
0xFFFFF830
DESCRIPTIONS
SSPI 1 Data Register
SSPI 1 Status Register
Bit 7 : Rx FIFO Empty
Bit 6 : Tx FIFO Empty
Bit 5 : Rx FIFO FULL
Bit 4 : Tx FIFO FULL
Bit 3 : Tx END
Bit 2 : Reserved
Bit 1 : Reserved
Bit 0 : SSPI BUSY
SSPI 0 Term Register
R/W
R/W
R
INITIAL VALUE
8b’11111111
8b’00000000
W
8b’11111111
DESCRIPTIONS
Receiver Buffer Register
(DLAB=0)
Transmitter Holding Register (DLAB=0)
Divisor Latch LS
(DLAB=1)
Divisor Latch MS
(DLAB=1)
Interrupt Enable Register
Bit 7-4 : Reserved
Bit 3 : Modem status interrupt
Bit 2 : Receiver line status interrupt
Bit 1 : THR empty interrupt
Bit 0 : Rx data available interrupt
Interrupt Identification Register
FIFO Control Register
Bit 7 : RCVR Trigger to MSB
Bit 6 : RCVR Trigger to LSB
Bit 5-3 : Reserved
Bit 2 : XMIT FIFO Reset
Bit 1 : RCVR FIFO Reset
Bit 0 : FIFO Enable
Line Control Register
Bit 7 : DLAB (Divisor Latch Access Bit)
Bit 6 : Break control bit
Bit 5 : Stick parity bit
Bit 4 : Even parity control
Bit 3 : Parity Control
(0: Disabled)
Bit 2 : Stop bit(s)
(0: Disabled)
Bit 1,0 : character bits
00(5-bit),01(6-bit), 10(7-bit), 11(8-bit)
R/W
R
W
R/W
R/W
R/W
INITIAL VALUE
8b’10011000
8b’10011000
8b’10011000
8b’10011000
8b’00000000
R
W
8b’00000001
R/W
8b’00000000
UART Register (@0xFFFF F500)
ABBREVIATION
RBR0
THR
DLL
DLM
IER
IIR / FCR
LCR
188
ADDRESS
0xFFFFF500
0xFFFFF504
0xFFFFF508
0xFFFFF50C
GDC21D601
UART Register (@0xFFFF F500) -- Continued
ABBREVIATION
MCR
LSR
ADDRESS
0xFFFFF510
0xFFFFF514
MSR
0xFFFFF518
SCR
0xFFFFF51C
DESCRIPTIONS
MODEM Control Register
Bit 7-5 : Reserved
Bit 4 : Loop control
Bit 3,2 : Reserved
Bit 1 : RTS
Bit 0 : DTR
Line Status Register
Bit 7 : Rx FIFO Error
Bit 6 : Transmitter Empty
Bit 5 : THR Empty
Bit 4 : Break Interrupt
Bit 3 : Framming Error
Bit 2 : Parity Error
Bit 1 : Overrun Error
Bit 0 : Data Ready
MODEM Status Register
Bit 7 : DCD(Data Carrier Detect)
Bit 6 : RI(Ring Indicator)
Bit 5 : DSR(Data Set Ready)
Bit 4 : CTS(Clear To Send)
Bit 3 : DDCD(Delta Data Carrier Detec)
Bit 2 : TERI(Trailing Edge Ring Indi.)
Bit 1 : DDSR(Delta Data Set Ready)
Bit 0 : DCTS(Data Clear To Send)
Scratch Register
R/W
R/W
INITIAL VALUE
8b’00000000
R/W
8b’01100000
R/W
8b’xxxx0000
R/W
8b’10011000
189
GDC21D601
2
I C Registers (@ 0xFFFF F900 : channel 0)
ABBREVIATION
Baud_r0
CTRL0
ADDRESS
0xFFFFF900
0xFFFFF904
Data_r0
Stat_r0
0xFFFFF908
0xFFFFF90C
Addr_r0
Test_r0
0xFFFFF910
0xFFFFF914
DESCRIPTIONS
I2C Baud rate register for channel 0
I2C Control Register for channel 0
Bit 7-5 : Reserved
Bit 4 : Include address bit
Bit 3 : Transfer END
Bit 2 : Transfer START
Bit 1 : SDA pin set/clear
Bit 0 : Interrupt Enable
(0: Disabled)
I2C Data Register for channel 0
I2C Status Register for channel 0
Bit 7-5 : Reserved
Bit 4 : Interrupt Flag bit
Bit 3 : Bus Busy Flag bit
Bit 2 : Bus Lost Flag bit
Bit 1 : SDA pin Ack bit
Bit 0 : Slave Called Flag bit
I2C Address Register for channel 0
Test Register for channel 0
R/W
W
W
INITIAL VALUE
8b’00000100
8b’xxx00010
R/W
R
8b’xxxxxxxx
8b’xxx00000
W
R/W
8b’00000000
8b’00000000
R/W
W
W
R/W
R
W
R/W
INITIAL VALUE
8b’10011000
8b’10011000
8b’10011000
8b’10011000
8b’10011000
8b’10011000
R/W
W
W
R/W
R
W
R/W
INITIAL VALUE
8b’10011000
8b’10011000
8b’10011000
8b’10011000
8b’10011000
8b’10011000
2
I C Registers (@0xFFFF FA000 : channel 1)
ABBREVIATION
Baud_r1
CTRL1
Data_r1
Stat_r1
Addr_r1
Test_r1
ADDRESS
0xFFFFFA00
0xFFFFFA04
0xFFFFFA08
0xFFFFFA0C
0xFFFFFA10
0xFFFFFA14
DESCRIPTIONS
I2C Baud rate register for channel 1
I2C Control Register for channel 1
I2C Data Register for channel 1
I2C Status Register for channel 1
I2C Address Register for channel 1
Test Register for channel 1
2
I C Registers (@ 0xFFFF FB00 : channel 2)
ABBREVIATION
Baud_r2
CTRL2
Data_r2
Stat_r2
Addr_r2
Test_r2
190
ADDRESS
0xFFFFFB00
0xFFFFFB04
0xFFFFFB08
0xFFFFFB0C
0xFFFFFB10
0xFFFFFB14
DESCRIPTIONS
I2C Baud rate register for channel 2
I2C Control Register for channel 2
I2C Data Register for channel 2
I2C Status Register for channel 2
I2C Address Register for channel 2
Test Register for channel 2