GM0936TQ GM0936TQ Voice-Band Audio CODEC for CDMA Features • Designed for standard 2.048MHz master • Single 3-V operation clock for U.S. Analog, U.S. Digital, CT2, • Low power consumption – Operating mode .... 20mW Typ DECT, GSM, and PCS Standards for – Power-down mode ... 1mW Typ Hand-held Battery-Powered Telephones • Combined A/D, D/A, and Filters • On-chip voltage references • Electret microphone bias reference • Package Type : 48 LQFP, 20 DIP, 20 SOP voltage available • Compatible with all digital signal processors (DSPs) • Programmable volume control • 300 Hz - 3.6 kHz Passband with Specified Master clock 11 FSX CLK MICSEL NC 37 MICGS MICIN 41 40 EXTMIC MICBIAS 42 39 38 ____ EARA PDN 44 43 46 45 NC EARGS EARB 47 7 30 NC NC 8 29 NC DVcc 9 28 NC 10 11 27 DGND 26 NC 12 25 NC NC __________ MICMUTE NC 1 24 10 12 DOUT NC NC 23 9 13 NC NC 31 NC 8 14 NC 32 6 22 7 15 GND 5 NC NC FSR __________ EARMUTE 6 16 NC 21 DIN 5 NC DOUT NC Vcc __________ MICMUTE NC 33 19 20 VMID 4 18 MICIN 17 AGND AVcc 17 18 4 34 16 3 3 15 EARB EARGS NC NC 14 MICGS VMID 35 DIN FSR __________ EARMUTE NC CLK FSX 19 MICBIAS 36 2 13 2 20 1 NC NC 1 NC NC ____ PDN EARA NC 20 DIP/SOP (TOP VIEW) 48 48 LQFP (TOP VIEW) GM0936TQ Description The GM0936TQ contains A/D and D/A conversion functions integrated on a single chip, and utilizes the sigma-delta modulation technique to achieve high resolution data conversion and low power consumption. The GM0936TQ is an ideal analog front end device for high performance voice-band communication systems. Cellular telephone systems are targeted in particular; however, these integrated circuits can function in other systems including digital audio, telecommunications, and data acquisition. The transmit section is designed to interface directly with an electret microphone element. One of two microphone input signals, MICIN and EXTMIC, is selected by MICSEL. If MICSEL is floated or Low, then MICIN is selected, and if MICSEL is high, then EXTMIC is selected. The microphone input signal (MICIN and EXTMIC) is buffered, first-order low-pass filtered, and amplified with provision for setting the amplifier gain to accommodate a range of signal input levels. The amplified signal is 1bitmodulated by second-order sigma-delta modulator. The modulated signal is then applied to the input of high-performance FIR-type digital decimation filters with frequency response equalization. The resulting data is then clocked out of DOUT as a serial data stream. The receive section takes a frame of sereal data on DIN and converts it to analog through highperformance FIR-type digital interpolation filter together with frequency response equalization, second-order digital sigma-delta modulator, and analog reconstruction filters. On-chip voltage reference ensures a highly integrated solution and all internal voltage references are generated. An internal reference voltage, VMID, is used to develop the midlevel virtual ground for all the amplifier circuits and the microphone bias circuit.Another reference voltage, MICBIAS, can supply bias current for the microphone. Serial DSP interfaces for transmit and receive paths support directly industry standard DSP processors. The GM0936TQ devices are characterized for operation from -20 to 70¡ É . 2 GM0936TQ Block Diagram AVCC EXTMIC MICIN MICGS __________ EARMUTE AGND DVCC ANALOG Σ ∆-MODULATOR DGND SINC 3FILTER _ __ PDN FIRFILTER MICMUTE INTERFACE VOLTAGE REFERENCE VMID MICBIAS EARGS EARA POST FILTER EARB CLK FSR FSX DIN DOUT FIRDIGITAL Σ ∆- SINC 2MODULATOR FILTER FILTER 1-BIT DAC MICSEL Analog 2nd orderΣ -∆ Modulator Block Diagram x 1/2 Integrator1 Integrator2 1/2 Quantizer Y Quantizer Y Digital 2nd order Σ -∆ Modulator Block Diagram x 2 Delay2 Delay1 3 GM0936TQ Pin Description ANALOG SIGNALS TERMINAL NAME LQFP SOP&DIP AGND 34 16 Analog Ground AVcc 4 5 Analog Power (3V) EARA 44 2 O Earphone output EARB 45 3 O Side-tone output EARGS 46 4 I Side-tone input EARMUTE_ 17 10 I Earphone output mute control signal MICBIAS 42 20 O Microphone bias MICGS 41 19 O Output of the internal microphone amplifier MICIN 40 18 I Microphone input MICMUTE_ 11 6 I Microphone input mute I/O DESCRIPTION VMID 36 17 O Bias voltage reference. A pair of external, lowleakage, high-frequency capacitors (1 µF and 470 pF) should be connected between VMID and ground for filtering ETMIC 39 N/A I Hand-free MIC-IN MICSEL 38 N/A I MIC-IN selection input. When float or low, MICSEL selects MICIN. When high, MICSEL selects EXTMIC. 4 GM0936TQ Pin Description DIGITAL SIGNALS TERMINAL NAME LQFP SOP&DIP I/O DESCRIPTION CLK 19 11 I Clock input (2.048 MHz) DGND 27 16 DIN 15 8 I Receive data input DOUT 21 13 O Transmit data output DVcc 9 5 FSR 16 9 I Frame-synchronization clock input for receive channel FSX 20 12 I Frame-synchronization clock input for receive channel PDN_ 43 1,2,3, 5,6,7, 8,10, 12,13, 14,18, 22,23, 24,25, 26,28, 29,30, 31,32, 33,35 1 I Power-down input, Active Low NC Digital ground Digital power (3 V) 7, 14, 15 No internal connection 5 GM0936TQ Electrical Characteristics Absolute Maximum Ratings over operating free-air temperature range PARAMETER SYMBOL MIN Supply Voltage Range DVCC, AVCC Digital Input Voltage Range Analog Input Voltage Range TYP MAX UNIT - 0.3 3.6 V Vind - 0.3 3.6 V Vina - 0.3 3.6 V Recommended Operating Conditions PARAMETER SYMBOL MIN TYP MAX UNIT DVCC, AVCC 2.7 3.0 3.3 V High-level Input Voltage VIH 2.2 Low-level Input Voltage VIL Operating free-air Temperature TA Supply Voltage V -20 0.8 V 70 ¡ É Power Supply Characteristics, fCLK = 2.048 MHz, outputs not loaded, Vcc=3V, TA=25¡ É PARAMETER MIN TYP MAX UNIT Power Dissipation , Operating 18 mW Power Dissipation , Power down 1 mW Digital Characteristics (TA=25¡ É, DVCC = AVCC = 3V) PARAMETER MIN Input Capacitance Input Leakage Current - 10 Low-level output Voltage (IOL = 3.2mA) High-level output Voltage (IOH = -3.2mA) 2.4 6 TYP MAX UNIT 10 pF 10 § Ë 0.4 V V GM0936TQ Microphone interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage at MICIN IIB V I= 0 to 3 V +5 mV +200 nA Input bias current at MICIN B1 Unity-gain bandwidth, open loop at MICIN 1.5 MHz Av Large-signal voltage amplification at MICGS 10000 V/V Iomax Maximum output current VMID 3 µA MICBIAS(source only) 1 mA Speaker interface PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VO(PP) AC output voltage RL = 600 Ω IOmax Maximum output current ro Output resistance at EARA, EARB Gain change 1 EARMUTE low, max level when muted 7 -60 3 Vpp +1 mA Ω dB GM0936TQ Analog Characteristics (TA=25¡ É, DVCC = AVCC = 3V, fs = 8 KHz) A/D Converter PARAMETER MIN TYP MAX UNIT Oversampling Ratio 128 Resolution 13 bit Dynamic Range 70 dB 52 dB 8 KHz 50 S/(N+THD) Output Sample Rate Maximum output current for MICBIAS 1 mA Maximum output voltage for Microphone Amplifier 0.85 Vpp 0.95 Transmit filter transfer over recommended ranges of supply voltage and free-air temperature, CLK=2.048 MHz, FSX=8 kHz PARAMETER Gain relative to input signal at 1.02 kHz TEST CONDITIONS Input amplifier set for unity gain, the output for 400mVpp signal at MICGS is 0dB MIN TYP MAX UNIT fMICIN = 50 Hz 0.76 fMICIN = 200 Hz 0.73 fMICIN = 300 Hz 0.67 fMICIN = 1 kHz 0 fMICIN = 2 kHz -1.9 fMICIN = 3 kHz -4.5 fMICIN = 3.3 kHz -5.4 fMICIN = 3.8 kHz -8.9 8 dB GM0936TQ Transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage and free-air temperature (see Notes 1 and 2) MIN TYP MAX UNIT PARAMETER TEST CONDITIONS Transmit noise MICIN connected to MICGS through a 22 kΩ resistor Gain relative to input signal at 1.02 kHz 178 MICIN to DOUT at 0 dBm0 53 MICIN to DOUT at -3 dBm0 52.3 MICIN to DOUT at -6 dBm0 51.9 MICIN to DOUT at -9 dBm0 50.7 MICIN to DOUT at -12 dBm0 49.0 µVrms dB Notes: 1. The input amplifier is set for inverting unity gain. 2. Transmit noise, linear mode: 200 µVrms is equivalent to -75 dB (referenced to device 0 dB level). D/A Converter PARAMETER MIN Oversampling Ratio TYP MAX UNIT 128 Resolution 13 bit Dynamic Range 67 dB 54 dB S/(N+THD) 48 Maximum output current (RL =600§ Ù ) Output Voltage Range 0.81 +1 mA 0.91 Vpp Receive distortion, linear mode selected, over recommended ranges of supply voltage and free-air temperature PARAMETER Receive signal-to -distortion ratio with sine-wave input TEST CONDITIONS MIN TYP MAX UNIT DIN to EARA at 0 dBm0 60 DIN to EARA at -3 dBm0 59.7 DIN to EARA at -6 dBm0 59.6 DIN to EARA at -9 dBm0 56.1 DIN to EARA at -12 dBm0 55.3 9 dB GM0936TQ Power supply rejection over recommended ranges of supply voltage and operating free-air temperature PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply voltage rejection, transmit channel Idle channel, supply signal = 100mVrms f = 1 kHz (measured at DOUT) -50 dB Supply voltage rejection, receive channel Idle channel, supply signal = 100mVrms f = 1 kHz (measured at EARA) -50 dB 10 GM0936TQ Timing (TA=25¡ É, DVCC = AVCC = 3V) PARAMETER MIN TYP MAX UNIT CLK Frequency 2.048 MHz Sampling Rate 8 KHz DOUT Delay from CLK 35 ns DIN Delay from CLK 35 ns Clock timing requirements MIN Duty cycle, CLK 45% NOM MAX UNIT 50% 55% Transmit timing requirements MIN MAX UNIT tsu(FSX) Setup time, FSX high before CLK ¡ é 20 468 ns th(FSX) Hold time, FSX high after CLK ¡ é 20 468 ns Receive timing requirements MIN MAX UNIT tsu(FSR) Setup time, FSR high before CLK ¡ é 20 468 ns th(FSR) Hold time, FSR high after CLK ¡ é 20 468 ns tsu(DIN) Setup time, DIN high or low before CLK ¡ é 20 ns th(DIN) Hold time, DIN high or low after CLK ¡ é 20 ns 11 GM0936TQ Timing Diagram Receive Time Slot 0 3 4 16 17 80% tsu(FSR) 20% th(FSR) FSR 15 1 16 ≈≈ See Note B See Note A DIN 15 ≈ 20% 2 ≈ CLK 1 80% 3 2 4 th(DIN) 15 16 1 tsu(DIN) See Note C NOTES: A. This window is allowed for FSR high. B. This window is allowed for FSR low. C. Transitions are measured at 50%. Figure1. Receive Side Timing Diagram Transmit Time Slot 0 3 4 15 16 20% ≈ th(FSX) FSX See Note B tpd2 See Note A DOUT 1 tpd1 3 2 4 See Note C NOTES: A. This window is allowed for FSX high. B. This window is allowed for FSX low. C. Transitions are measured at 50%. Figure2. Transmit Side Timing Diagram 12 17 80% ≈ 20% tsu(FSX) 2 ≈≈ CLK 1 80% tpd3 15 16 GM0936TQ PRINCIPLES OF OPERATION power-down operation To minimize power consumption, a power-down mode is provided. For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled up to a high logic level and the device remains active. In the power-down mode, the average power consumption is reduced to 1mW. Timing FSX and FSR are inputs that set the sampling frequency. Data is transmitted on DOUT on the positive transitions of CLK following the rising edge of FSX. Data is received on DIN on the falling edges of CLK following FSR. Table 1. Power-On and Power-Down Procedures TYPICAL POWER CONSUMPTION DIGITAL OUTPUT STATUS PDN =high, FSX = pulses, FSR = pulses 20 mW Digital outputs active PDN =low, FSX,FSR =X 1 mW DEVICE STATUS PROCEDURE Power on Power down DOUT in the high-impedance state X = dont care 13 GM0936TQ PRINCIPLES OF OPERATION transmit operation microphone input The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as shown in Figure 3. The VMID buffer circuit provides a voltage (MICBIAS) as a bias voltage to the electret microphone. The microphone amplifier output (MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to set the amplifier gain. VMID appears at a terminal to provide a place to filter the VMID voltage. VMID VMID Reference For Amplifiers 36 4.4 µF 470 pF Reference Voltage Generator MICBIAS 42 2.2 nF 2 kΩ MICGS 41 100nF 22 kΩ 22 kΩ Microphone Amplifier MICIN To 2nd-order Σ−∆ Modulator 40 Electret Microphone GM0936TQ NOTE A: Terminal numbers shown are for the 48 LQFP package. Figure 3. Typical Microphone Interface microphone mute function The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT. transmit filter A low-pass antialiasing section is implemented by connecting a RC-pair externally between MICGS and MICIN. The RC-pair, together with the microphone amplifier, provides a single-pole low pass filter. The antialiased signal is 1bit-modulated by second-order sigma-delta modulator. The modulated signal is then applied to the input of high-performance FIR-type digital decimation filters with frequency response equalization. 14 GM0936TQ PRINCIPLES OF OPERATION encoding The encoder performs an A/D conversion on a 2nd-order Sigma-Delta (Σ-∆) modulator using a switched-capacitor technology and high-performance FIR-type digital decimation filters with frequency response equalization. The resulting data is then clocked out of DOUT as a serial data. data word structure The data word is 16 bits long. The first 13 bits comprises the audio data sample, and the last three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit direction (DOUT). The sign bit is transmitted first. receive operation decoding The serial data word is received at DIN on the first 13 clock cycles. The receive section converts a frame of sereal data to analog through high-performance FIR-type digital interpolation filter together with frequency response equalization, second-order digital sigma-delta modulator, and analog reconstruction filters. receive buffer The receive buffer contains the volume control. earphone amplifier The output can be used to drive a single-ended load with the output signal voltage centered around VMID. EARA in Figure 4 is the output pin for the decoded analog signal. EARB in the figure is used for sidetone signal output which is used internally. A resistor-capacitor pair attached to EARB is embedded to reduce the number of on-board components. See the next section for more information on sidetone generation. 15 GM0936TQ PRINCIPLES OF OPERATION 40 pF 30 kΩ 50 kΩ 44 EARA 40 pF 50 kΩ VMID 30 kΩ VMID 45 40 pF EARB 100 kΩ 46 EARGS GM0936TQ NOTE A: Terminal numbers shown are for the 48 LQFP package. Figure 4. Earphone Audio-Output Amplifier Configuration receive data format In the decoding operation, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits from the volume control word(see Table 2). The volume control function is actually an attenuation control in which the first bit received is the most significant. The maximum volume occurs when all three volume control bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB when all bits are 1s. The volume control bit are not latched into the GM0936TQ and must be present in each received data word. 16 GM0936TQ Table 2. Receive-Data Bit Definitions BIT NO. Data 0 D12 1 D11 2 D10 3 D9 4 D8 5 D7 6 D6 7 D5 8 D4 9 D3 A D2 B D1 C D0 D V2 E V1 F V0 MSB (sign bit) LSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 V2 V1 V0 PCM Data Volume Control Time Where: D12-D0 = PCM Data word V2, V1, V0 = Volume (attenuation control) 000 = maximum volume, 0 dB 111 = minimum volume, -21 dB 17 GM0936TQ APPLICATION INFORMATION output gain set and sidetone considerations The single-ended outputs EARA and EARB are capable of driving output power level up to 1mW into load impedance of 1kΩ separately.The sidetone signal and the received signal can be summed by configuring external components like in Figure 5. The amount of sidetone mixing is controlled by the resistor connected between EARB and EARGS. If the resistance become greater, the amount of sidetone mixing increases. EARA 44 To speaker driving amp. EARB 42 GM0936TQ 1 kΩ EARGS 46 2.2 nF 100 kΩ 41 MICGS 100nF 22 kΩ 40 MICIN 22 kΩ Electret Microphone NOTE A: Terminal numbers shown are for the 48 TQFP package. Figure 5. Configuration for Gain-Setting and Sidetone higher clock frequencies and sample rates The GM0936TQ is designed to work with sample rates up to 16kHz where the frequency of the frame sync determines the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock frequency, fCLK, to the frame sync frequency, fFSR/ fFSX. This ratio for the GM0936TQ is 2.048 MHz/8 kHz, or 256 master clocks per frame sync. For example, to operate the GM0936TQ at a sampling rate of fFSR and fFSX equal to 16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the GM0936TQ is operated above an 8-kHz sample rate, however, it is expected that the performance becomes somewhat degraded. Exact parameter specifications for rates up to 16-kHz sample rate are not specified at this time. 18 GM0936TQ 19 GM0936TQ 20 GM0936TQ 21