GM71C18163C GM71CS18163CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description Features The GM71C(S)18163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71C(S)18163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71C(S)18163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multiplexed address inputs permit the GM71C(S)18163C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. * 1,048,576 Words x 16 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (5V+/-10%) * Fast Access Time & Cycle Time Pin Configuration tRAC tCAC 44(50) TSOP II VCC 1 42 VSS I/O0 I/O1 2 41 3 40 I/O15 I/O14 I/O2 I/O3 4 39 5 38 I/O13 I/O12 VCC 6 37 VSS I/O4 I/O5 7 36 8 35 I/O11 I/O10 I/O6 I/O7 NC 9 34 10 33 I/O9 I/O8 11 32 NC NC WE 12 31 13 30 LCAS UCAS RAS 14 29 OE NC NC A0 15 28 16 27 17 26 A1 A2 A3 VCC 18 25 19 24 20 23 21 22 13 15 18 tRC tHPC 84 104 124 20 25 30 * Low Power Active : 1045/935/825mW (MAX) Standby : 11mW (CMOS level : MAX) 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version) * 2 CAS byte Control 42 SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC A9 A8 A7 A6 A5 A4 VSS (Top View) Rev 0.1 / Apr’01 50 60 70 GM71C(S)18163C/CL-5 GM71C(S)18163C/CL-6 GM71C(S)18163C/CL-7 (Unit: ns) 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC NC 15 36 NC 16 35 WE RAS A11 A10 A0 A1 A2 A3 VCC 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS GM71C18163C GM71CS18163CL Pin Description Pin Function Pin Function A0-A9 Address Inputs WE Read/Write Enable A0-A9 Refresh Address Inputs OE Output Enable I/O0-I/O15 Data Input/Data Output VCC Power (+5V) Row Address Strobe VSS Ground Column Address Strobe NC No Connection RAS UCAS, LCAS Ordering Information Type No. Access Time Package GM71C(S)18163CJ/CLJ -5 GM71C(S)18163CJ/CLJ -6 GM71C(S)18163CJ/CLJ -7 50ns 60ns 70ns 400 Mil 42 Pin Plastic SOJ GM71C(S)18163CT/CLT -5 GM71C(S)18163CT/CLT -6 GM71C(S)18163CT/CLT -7 50ns 60ns 70ns 400 Mil 44(50) Pin Plastic TSOP II Absolute Maximum Ratings* Symbol Parameter Rating Unit 0 ~ +70 C -55 ~ +125 C TA Ambient Temperature under Bias TSTG Storage Temperature VIN/OUT Voltage on any Pin Relative to VSS -1.0 ~ +7.0V V VCC Supply voltage Relative to VSS -1.0 ~ +7.0V V IOUT Short Circuit Output Current 50 mA PD Power Dissipation 1.0 W Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL Recommended DC Operating Conditions (TA = 0 ~ +70C) Symbol Parameter Min Typ Max Unit VCC Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - 6.0 V VIL Input Low Voltage -1.0 - 0.8 V Note: All voltage referred to Vss. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Truth Table RAS LCAS UCAS WE OE Output Operation H D D D D Open L L H H L Valid Lower byte L H L H L Valid Upper byte L L L H L Valid Word L L H L D Open Lower byte L H L L D Open Upper byte L L L L D Open Word L L H L H Undefined Lower byte L H L L H Undefined Upper byte L L L L H Undefined Word L L H H to L L to H Valid Lower byte L H L H to L L to H Valid Upper byte L L L H to L L to H Valid Word H to L H L D D Open Word H to L L H D D Open Word H to L L L D D Open Word L H H D D Open Word L L L H H Open Standby 1,3 Read cycle 1,3 Early write cycle 1,2,3 Delayed Write cycle 1,2,3 Read-modify -write cycle 1,3 CBR Refresh or Self Refresh (L-series) 1,3 RAS-only Refresh cycle 1,3 Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS <= 0ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS,LCAS. ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Rev 0.1 / Apr’01 Notes 1,3 GM71C18163C GM71CS18163CL DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C) Symbol Parameter Min Max Unit VOH Output Level Output "H" Level Voltage (IOUT = -2mA) 2.4 VCC V VOL Output Level Output "L" Level Voltage (IOUT = 2mA) 0 0.4 V ICC1 Operating Current Average Power Supply Operating Current (RAS, UCAS or LCAS Cycling: tRC = tRC min) 50ns - 190 60ns - 170 70ns - 150 - 2 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 Standby Current (TTL) Power Supply Standby Current (RAS, UCAS, LCAS = VIH, D OUT = High-Z) mA Note 1, 2 mA RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) 50ns - 190 60ns - 170 70ns -- 150 EDO Page Mode Current Average Power Supply Current EDO Page Mode (tHPC = tHPC min) 50ns - 185 60ns - 165 70ns - 145 - 1 mA - 150 uA 50ns - 190 60ns - 170 70ns - 150 - 500 uA 4,5 - 5 mA 1 - 300 uA 5 Standby Current (CMOS) Power Supply Standby Current (RAS, UCAS or LCAS >=VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) Battery Back Up Operating Current(Standby with CBR Ref.) (CBR refresh, tRC=125us, tRAS<=0.3us, DOUT=High-Z, CMOS interface) Standby Current RAS = VIH UCAS, LCAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, UCAS or LCAS <=0.2V, DOUT=High-Z, CMOS interface) mA 2 mA 1, 3 mA IL(I) Input Leakage Current Any Input (0V<=VIN<= 6V) -10 10 uA IL(O) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 6V) -10 10 uA Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while UCAS and LCAS = VIH. 4. CAS = L (<=0.2V) while RAS = L (<=0.2V). 5. L-version. Rev 0.1 / Apr’01 5 GM71C18163C GM71CS18163CL Capacitance (VCC = 5V+/-10%, TA = 25C) Symbol Parameter Min Max Unit Note CI1 Input Capacitance (Address) - 5 pF 1 CI2 Input Capacitance (Clocks) - 7 pF 1 CI/O Output Capacitance (Data-In/Out) - 7 pF 1, 2 Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. LCAS and UCAS = VIH to disable DOUT. AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Note 1, 2, 18, 19, 20) Test Conditions Input rise and fall times : 2 ns Input levels : VIL = 0V, VIH = 3V Input timing reference levels : 0.8V, 2.4V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-6 C/CL-7 C/CL-5 Unit Note Min Max Min Max Min Max tRC Random Read or Write Cycle Time 84 - 104 - 124 - ns tRP RAS Precharge Time 30 - 40 - 50 - ns tCP CAS Precharge Time 7 - 10 - 13 - ns tRAS RAS Pulse Width 50 10,000 60 10,000 70 10,000 ns tCAS CAS Pulse Width 7 10,000 10 10,000 13 10,000 ns tASR Row Address Set up Time 0 - 0 - 0 - ns tRAH Row Address Hold Time 7 - 10 - 10 - ns tASC Column Address Set-up Time 0 - 0 - 0 - ns 21 tCAH tRCD tRAD tRSH Column Address Hold Time 7 - 10 - 13 - ns 21 3 4 11 37 14 45 14 52 ns 9 25 12 30 12 35 ns RAS Hold Time 10 - 13 - 13 - ns tCSH tCRP tODD tDZO CAS Hold Time 35 - 40 - 45 - ns 23 5 - 5 - 5 - ns 22 13 - 15 - 18 - ns 5 OE Delay Time from DIN 0 - 0 - 0 - ns 6 tDZC tT CAS Delay Time from DIN 0 - 0 - 0 - ns 6 Transition Time (Rise and Fall) 2 50 2 50 2 50 ns 7 RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time OE to DIN Delay Time Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL Read Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Min Max Unit Note Min Max Min Max tRAC Access Time from RAS - 50 - 60 - 70 ns 8,9 tCAC Access Time from CAS - 13 - 15 - 18 ns 9,10,17 tAA Access Time from Address - 25 - 30 - 35 ns 9,11,17 tOAC Access Time from OE - 13 - 15 - 18 ns 9 tRCS Read Command Setup Time 0 - 0 - 0 - ns 21 tRCH Read Command Hold Time to CAS 0 - 0 - 0 - ns 12,22 tRRH tRAL Read Command Hold Time to RAS 5 - 5 - 5 - ns 12 Column Address to RAS Lead Time 25 - 30 - 35 - ns tCAL Column Address to CAS Lead Time 15 - 18 - 23 - ns tCLZ CAS to Output in Low-Z 0 - 0 - 0 - ns tOH Output Data Hold Time 3 - 3 - 3 - ns tOHO Output Data Hold Time from OE 3 - 3 - 3 - ns tOFF Output Buffer Turn-off Time - 13 - 15 - 15 ns 13,27 tOEZ Output Buffer Turn-off Time to OE - 13 - 15 - 15 ns 13 tCDD CAS to DIN Delay Time 13 - 15 - 18 - ns 5 tRCHR Read Command Hold Time from RAS 50 - 60 - 70 - ns tOHR Output Data hold Time from RAS 3 - 3 - 3 - ns 27 tOFR Output Buffer turn off to RAS - 13 - 15 - 15 ns 27 tWEZ Output Buffer turn off to WE - 13 - 15 - 15 ns tWDD WE to DIN Delay Time 13 - 15 - 18 - ns tRDD RAS to DIN Delay Time 13 - 15 - 18 - ns Rev 0.1 / Apr’01 27 GM71C18163C GM71CS18163CL Write Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-6 C/CL-7 C/CL-5 Unit Note Min Max Min Max Min Max tWCS Write Command Setup Time 0 - 0 - 0 - ns 14,21 tWCH Write Command Hold Time 7 - 10 - 13 - ns 21 tWP Write Command Pulse Width 7 - 10 - 10 - ns tRWL Write Command to RAS Lead Time 7 - 10 - 13 - ns tCWL Write Command to CAS Lead Time 7 - 10 - 13 - ns 23 tDS tDH Data-in Setup Time 0 - 0 - 0 - ns 15,23 Data-in Hold Time 7 - 10 - 13 - ns 15,23 Unit Note Read- Modify-Write Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Min Max Min Max Min Max tRWC Read-Modify-Write Cycle Time tRWD 111 - 136 - 161 - ns RAS to WE Delay Time 67 - 79 - 92 - ns 14 tCWD CAS to WE Delay Time 30 - 34 - 40 - ns 14 tAWD Column Address to WE Delay Time 42 - 49 - 57 - ns 14 tOEH OE Hold Time from WE 13 - 15 - 18 - ns Refresh Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tCSR CAS Setup Time (CAS-before-RAS Refresh Cycle) 5 - 5 - 5 - ns 21 tCHR CAS Hold Time (CAS-before-RAS Refresh Cycle) 7 - 10 - 10 - ns 22 tRPC RAS Precharge to CAS Hold Time 5 - 5 - 5 - ns 21 Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL EDO Page Mode Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tHPC EDO Page Mode Cycle Time tRASP 20 - 25 - 30 - ns 25 EDO Page Mode RAS Pulse Width - 100,000 - 100,000 - 100,000 ns 16 tACP Access Time from CAS Precharge - 30 - 35 - 40 ns 9,17,22 tRHCP RAS Hold Time from CAS Precharge 30 - 35 - 40 - ns tDOH Output data Hold Time from CAS low 3 - 3 - 3 ns tCOL CAS Hold Time referred OE 7 - 10 - 13 ns tCOP CAS to OE Setup Time 5 - 5 - 5 ns tRCHP Read command Hold Time from CAS Precharge 30 - 35 - 40 ns 9 EDO Page Mode Read-Modify-Write Cycle Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Unit Note Min Max Min Max Min Max tHPRWC EDO Page Mode Read-Modify-Write Cycle Time 57 - 68 - 79 - ns tCPW WE Delay Time from CAS Precharge 45 - 54 - 62 - ns 14,22 Unit Note Refresh Symbol Parameter GM71C(S)18163 GM71C(S)18163 GM71C(S)18163 C/CL-5 C/CL-6 C/CL-7 Min Max Min Max Min Max tREF Refresh period - 16 - 16 - 16 ms 1024 cycles tREF Refresh period (L -Series) - 128 - 128 - 128 ms 1024 cycles Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL Self Refresh Mode ( L-version ) Symbol Parameter tRASS RAS Pulse Width(Self-Refresh) tRPS tCHS GM71CS18163 CL-5 GM71CS18163 CL-6 GM71CS18163 CL-7 Min Max Min Max Min Max Unit Note 29 100 - 100 - 100 - us RAS Precharge Time(Self-Refresh) 90 - 110 - 130 - ns CAS Hold Time(Self-Refresh) -50 - -50 - -50 - ns Notes : 1. AC measurements assume tT = 2 ns. 2. An initial pause of 200us is required after power followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100pF. 10. Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max). 11. Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >= tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min) tAWD >= tAWD (min) and tCPW >= tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL 15. These parameters are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO mode cycles. 17. Access time is determined by the longer of tAA or tCAC or tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance): if tOEH<=tCWL, invalid data will be out at each I/O. 19. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 20. All the Vcc and Vss pins shall be supplied with the same voltages. 21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of UCAS or LCAS. 22. tCRP, tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS. 23. tCWL, tDH, tDS and tCHS should be satisfied by both UCAS and LCAS. 24. tCP is determined by the time that both UCAS and LCAS are high. 25. tHPC(min) can be achieved during a series of EDO page made write cycles or EDO mode write cycles. It both write and read operation are mixed in a EDO mode RAS cycle(EDO mode mix cycle (1),(2)) minimum Value of CAS cycle (tCAS+tCP+2tT) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO mode is shown in EDO mode mix cycle (1) and (2). 26. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time , generally it causes large Vcc/Vss line noise, which causes to degrade VIH min/VIL max level. 27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specification of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF. 28. EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high during CAS high, the data will not come out until next CAS access. When WE goes low during CAS high, the data will not come out until next CAS access. 29. Please do not use tRASS timing, 10us<=tRASS<=100us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS>=100us, then RAS 30. precharge time should use tRPS instead of tRP. H or L ( H : VIH(min) <= VIN <= VIH(max), L : VIL(min) <= VIN <= VIL(max) ) Rev 0.1 / Apr’01 GM71C18163C GM71CS18163CL Package Dimension Unit: Inches (mm) 42 SOJ 0.025(0.64) 0.380(9.65) MAX 0.360(9.15) MIN 0.445(11.30) MAX 0.435(11.06) MIN 0.405(10.29) MAX 0.395(10.03) MIN MIN 0.093(2.38) 1.058(26.89) MAX MIN 1.072(27.23) MAX 0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) 0.026(0.66) MIN 0.032(0.81) MAX TYP 0.015(0.38) MIN 0.020(0.50) MAX 44(50) TSOP-II 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX Rev 0.1 / Apr’01 0.016(0.40) MIN 0.024(0.60) MAX 0.004(0.12) MIN 0.008(0.21) MAX 0.820(20.82) MIN 0.830(21.08) MAX 0.012(0.30) MIN 0.017(0.45) MAX £ 0.471(11.96) MAX 0.455(11.56) MIN 0.394(10.03) MIN 0.405(10.29) MAX 0 ~ 5¡ 0.031(0.80) TYP 0.002(0.05) MIN 0.006(0.15) MAX