HL15703 HL15703 LCD Driver IC Preliminary 2Q. 1999 Hyundai Electronics Industries System IC Division 1 Preliminary HL15703 Contents 1. General Description 2. Features 3. Block Diagram 4. Pin Diagram 5. Pin Description 6. Serial I/O Data Format 7. Registers 8. Key Scan Function 9. LCD Function 10. Power On Reset 11. Power Down Mode 12. Oscillator Port 13. Electrical Characteristics 14. Application 2 Preliminary HL15703 1. General Description The HL15703 is 1/3 duty LCD display driver. It can drive directly maximum 171 segments. Also it has four general purpose output ports and a key scan function that accepts input from up to 30 keys. 2. Features • LCD display Package Dimensions 80QFP 23.2 0.5 0.15 1.0 0.35 41 40 80 1 25 24 14.0 15.5 64 65 2.70 20.0 0.5 1.0 1.5 • • • • 0.1 3.0 max • • 17.2 • ..................................... 57 segments x 3 commons 1/3 duty - 1/2 bias 1/3 duty - 1/3 bias Key scan ............................................ Maximum 30 keys Input 5 pins, Output 6 pins Power down mode ............................. Sleep mode and all segments off mode Port Output .................................................. 4 pins ( Including the LCD segment port ) Serial I/O .............................................. Data transfer and receive Power on reset ..................................... Supply voltage detection ( SVD ) RC oscillator Package ............................................... 80QFP 21.6 Unit : mm 3 Preliminary HL15703 80QFP 14.0 12.0 1.25 0.20 0.135 1.25 0.5 60 41 1 21 20 40 12.0 1.25 0.5 1.4 0.5 0.5 COM3 COM2 COM1 KS2 / SEG57 KS1 / SEG56 SEG55 3. Block Diagram 0.1 Unit : mm COMMOM DRIVER SEGMENT DRIVER VCL1 VCL2 LCD BIAS LCD DISPLAY & CONTROL REGISTER VDD VSS RES SVD RESET CLOCK SI SO SCK CE KEY SCAN TEST CONTROL 4 KIN6 KIN5 KIN4 KIN3 KIN2 KIN1 TEST SERIAL I/O KS5 KS4 KS3 KS2 KS1 OSC CLOCK GENERATOR SEG1 / P1 1.6max 80 SEG5 SEG4 / P4 14.0 1.25 61 Preliminary KS2 / S57 KS1 / S56 COM3 COM2 COM1 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 KI1 KI2 KI3 KI4 KI5 VDD VDD1 VDD2 VSS TEST OSC RES DD CE CL DI KS3 KS4 KS5 KS6 KI1 KI2 KI3 KI4 KI5 VDD VDD1 VDD2 VSS TEST OSC RES DD CE CL DI P1 / S1 P2 / S2 P3 / S3 P4 / S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 P1 / S1 P2 / S2 P3 / S3 P4 / S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 KS6 KS5 KS4 KS3 KS2 / S57 KS1 / S56 COM3 COM2 COM1 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 HL15703 4. Pin Diagram 65 64 60 80 1 80 1 50 10 60 61 50 70 10 5 41 40 70 30 20 25 24 41 40 30 21 20 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 Preliminary HL15703 5. Pin Description PIN Name I/O Pin Number SEG[55:1] O 55 LCD SEG Pins share P1,P2,P3 and P4 COM [3:1] O 3 LCD Common Pins VCL[2:1] I 2 LCD Bias Pins OSC I/O 1 Oscillator Input Pin KS[6:1] O 6 Key Scan Output Pins KIN[5:1] I 5 Key Scan Input Pins CE I 1 Serial I/O Control Pin SCK I 1 Serial I/O Clock Pin SO O 1 Serial I/O Data Output Pin SI I 1 Serial I/O Data Input Pin TEST I 1 Test Pin. “1” Test mode , “0” Normal Mode P[4:1] O 4 Output Port share SEG[4:1] RES I 1 Reset Pin VDD I 1 Power Supply Pin VSS I 1 Ground Pin 6 Contents Preliminary HL15703 6. Serial I/O Data Format 1) Writing Mode i )SCK is stopped at the low level CE SCK SI XX 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 D56 D57 0 0 0 0 0 Display data S0 S1 K0 K1 P0 P1 SC DR 0 Control data 0 DD SO CE SCK SI XX 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D58 D59 D60 D113 D114 0 0 0 0 0 Display data 0 0 0 0 0 0 0 0 0 Fixed data 1 DD SO CE SCK SI XX 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D115 D116 D117 D170 Display data D171 0 0 0 0 0 0 0 Fixed data 0 0 0 0 0 0 1 0 DD SO 7 Preliminary HL15703 ii )SCK is stopped at the high level CE SCK SI XX 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D3 D56 D57 0 0 0 0 Display data S0 S1 K0 K1 P0 P1 SC DR 0 Control data 0 DD SO CE SCK SI XX 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D58 D59 D60 D113 D114 0 0 0 0 0 Display data 0 0 0 0 0 0 0 Fixed data 0 1 DD SO CE SCK SI XX D115 D116 D117 D170 D171 Display data 0 0 0 0 0 0 0 Fixed data 0 0 0 0 0 1 0 DD SO CCB address : 42H D171~D1 : Display data S0, S1 : Sleep control data K0, K1 : Key scan output / Segment output selection data P0, P1 : Segment output / general-purpose output port selection data SC : Segment on / off control data DR : 1/2 bias or 1/3 bias drive selection data 8 Preliminary HL15703 2) Reading Mode i ) SCK is stopped at the low level CE SCK SI XX 1 1 0 0 0 0 1 0 XX B0 B1 B2 B3 A0 A1 A2 A3 XX SO KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD10 KD11 KD12 KD29 KD30 SA XX Output data X : don’t care ii ) SCK is stopped at the high level CE SCK SI XX 1 1 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 SO 0 XX A3 XX KD1 KD2 KD3 KD4 KD5 KD6 KD7 KD8 KD9 KD10 KD11 KD12 K29 K30 SA XX Output data X : don’t care CCB : 43H K30 ~ K1 : Key data SA : Sleep acknowledge data 9 Preliminary HL15703 7. Registers 1) Display Registers Output Pin SEG1/P1 SEG2/P2 SEG3/P3 SEG4/P4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 10 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 Preliminary HL15703 Output Pin COM1 COM2 COM3 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 KS1 / S56 KS2 / S57 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 D157 D160 D163 D166 D169 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 D158 D161 D164 D167 D170 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 D159 D162 D165 D168 D171 2) Control Registers Bias Selection Register DR 0 1 Bias Selection 1/3 Bias 1/2 Bias Key Scan / Segment output Selection Register Control Data K0 K1 0 0 0 1 1 X Output Pin Status Maximum number of Input Pins KS1/SEG56 KS2/SEG57 KS1 KS2 30 SEG56 KS2 25 SEG56 SEG57 20 Port Mode Register Control Data P0 P1 0 0 0 1 1 0 1 1 SEG1/ P1 SEG1 P1 P1 P1 Output Pin Status SEG2/ P2 SEG3/ P3 SEG2 SEG3 P2 SEG3 P2 P3 P2 P3 11 SEG4/ P4 SEG4 SEG4 SEG4 P4 Preliminary HL15703 Port Data Register Output Pin SEG1 / P1 SEG2 / P2 SEG3 / P3 SEG4 / P4 Port Data Register D1 D4 D7 D10 Sleep Mode Control Register Control Data Output Pin Status OSC SEG / COMMON Mode Output Oscillator S0 S1 KS1 KS2 KS3 KS4 KS5 0 0 Normal Operating Operating H H H H H 0 1 Sleep Stopped L L L L L L 1 0 Sleep Stopped L L L L L H 1 1 Sleep Stopped L H H H H H KS6 H H H H Display On/Off Control Register Control Data SC 0 1 Display Status SEG1 ~ SEG57 On Off Key Scan Data & Sleep Acknowledge Read ADDRESS 43H KS1 / SEG56 KS2 / SEG57 KS3 KS4 KS5 KS6 Read Data K1 ~ K30, SA KIN1 K1 K6 K11 K16 K21 K26 KIN1 K2 K7 K12 K17 K22 K27 KIN1 K3 K8 K13 K18 K23 K28 12 KIN1 K4 K9 K14 K19 K24 K29 KIN1 K5 K10 K15 K20 K25 K30 Preliminary HL15703 8. Key Scan Function 1) Key Scan Timing The key scan period is 384T. The HL15703 scans the key twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request 800T after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the key again.Thus the HL15703 cannot detect a key press shorter than 800T. KS1 *) KS2 *) KS3 *) KS4 *) KS5 *) KS6 *) 1 *) 1 2 *) 2 3 *) 3 4 *) 4 5 *) 5 6 6 *) 800T Key on *) In sleep mode the high / low state of these pins is determined by the S0,S1 bits in the control data. Key scan output signals are not output from pins that are set low. 2) In normal mode • The pins KS1 to KS6 are set high. • When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. • If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15703 outputs a key data read request (a low level on SO pin) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high. • After the controller reads the key data, the key data read requests is cleared ( SO pin is set high ) and the HL15703 performs another key scan. Also note that SO pin, being an open-drain output, requires a pull-up resistor. 13 Preliminary HL15703 Key input 1 Key input 2 Key Scan 800T 800T 800T CE Serial data transfer Serial data transfer Key address Serial Key data transfer address Key address SI SO Key data read Key data read request Key data read Key data read request Key data read Key data read request 3) In sleep mode • The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the sleep mode control register. • If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. • If a key is pressed for longer than 800T ( where T=1/fosc ) the HL15703 outputs a key data read request (a low level on SO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, SO will be set high. • After the controller reads the key data, the key data read request is cleared ( SO is set high ) and the HL15703 performs another key scan. However this does not clear sleep mode. Also note that SO, being an open-drain output, requires a pull-up resistor ( between 1 and 10 K). • Sleep mode key scan example Example : S0 = 0, S1 = 1 ( sleep with only KS6 high ) 14 Preliminary HL15703 “L” KS1 “L” KS2 “L” KS3 “L” KS4 “L” KS5 “H” KS6 When any one of these keys is pressed, the oscillator on the OSC pin is started and the keys are scanned. *) KIN1 KIN2 KIN3 KIN4 KIN5 *) These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operation due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Key input (KS6 line) Key Scan 800T 800T CE Serial data transfer Serial data transfer Key address Serial data transfer Key address SI SO Key data read Key data read request Key data read Key data read request Multiple Key Presses Although the HL15703 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KIN1 to KIN5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Application that do not recognize multiple key presses of threes or keys should check the key data for three or more 1 bits and ignore such data. 15 Preliminary HL15703 9. LCD Display Function 1) 1/3 Duty 1/2 Bias Waveforms COM1 VDD VCL1,VCL2 0 COM2 VDD VCL1,VCL2 0 COM3 VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM2 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM3 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM3 are on. VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM2 and COM3 are on. VDD VCL1,VCL2 0 VDD VCL1,VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. 16 Preliminary HL15703 2) 1/3 Duty 1/3 Bias Waveforms COM1 VDD VCL1 VCL2 0 COM2 VDD VCL1 VCL2 0 COM3 VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM2 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM2 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM3 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1 and COM3 are on. VDD VCL1 VCL2 0 VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM2 and COM3 are on. VDD VCL1 VCL2 0 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. 17 Preliminary HL15703 10. Power On Reset 1) Supply Voltage Detection ( SVD ) The SVD generates an output signal and resets the system when power is first applied and when the voltage drops,I.,e when the power supply voltage is less than or equal to the power down detection voltage, which is 2.5V, typical. To assure that this function operates reliably, a capacitor must be added to the power supply voltage Vdd rise time when power is first applied and the power supply voltage Vdd fall time when the voltage drops are both at least 1ms. 2) System Reset If at least 1ms is assured as the supply voltage Vdd rise time when power is applied, a system reset will be applied by the SVD output signal when the supply voltage is brought up. If at least 1ms is assured as the supply voltage Vdd fall time when power drops, a system reset will be applied in the same manner by the SVD output signal when the supply voltage is lowered. VDD SVD SVD t1 t2 CE Display and control data transfer Internal data Undefined Defined System reset period Power supply voltage Vdd rise time : t1 > 1ms Power supply voltage Vdd fall time : t2 > 1ms 3) Internal block states during the reset period • Clock generator Reset is applied and the base clock is stopped and OSC pin state is low. • Common , segment drive and display data Reset is applied and the display is turned off but display data is not cleared. • Key scan Reset is applied and all the key data is set to low. 18 Preliminary HL15703 4) Output pin states during the reset period • SEG1/P1 to SEG4/P4 : Low *) • SEG5 to SEG55 : Low • COM1 to COM3 : Low • KS1/SEG56, KS2/SEG57 : Low *) • KS3 to KS5 : X • KS6 : High • SO : High *) These output pins are forcibly set to the segment output function and held low. 11. Power Down Mode Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop ( it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. Note that the SEG1/P1 to SEG4/P4 outputs can be used as general purpose output ports according to the state of the P0 and P1 control data bits, even in sleep mode. 19 Preliminary HL15703 12. Oscillator Port OSC Pin Diagram R OSC Internal clock SLEEP C Oscillator circuit consists of internal R and C. Using Capacitor No Capacitor OSC OSC Open C HL15703 has internal resistor and capacitor, so it can be oscillation without external capacitor. If you want to adjust the clock period then you can adjust it using external capacitor. 20 Preliminary HL15703 13. Electrical Characteristics Absolute Maximum Rating at Ta=25¡ É , Vss = 0V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD max Vin1 Vin2 Vout1 Vout2 Iout1 Iout2 Iout3 Iout4 Pd max Topr Tstg Condition VDD CE,SCK,SI,RES OSC,KIN1 to KIN5, TEST,VCL1,2 SO OSC, SEG1 to SEG57, COM1 to COM3, KS1 to KS6, P1 to P4 SEG1 to SEG57 COM1 to COM3 KS1 to KS6 P1 to P4 Ta = 85¡ É Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to +7.0 unit V V V V -0.3 to VDD+0.3 V 300 3 1 5 200 -40 to +85 -55 to +125 uA mA mA mA mW ¡ É ¡ É Recommend operating ranges at Ta= -40¡ Éto +85¡ É , Vss = 0V Parameter Supply voltage Input voltage Input high level voltage Input low level voltage Recommended external capacitance Guaranteed oscillation range Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time Symbol VDD VCL1 VCL2 VIH1 VIH2 VIL Condition VDD VCL1 VCL2 CE,SCK,SI,RES KIN1 to KIN5 COSC OSC fOSC tds tdh tcp tcs tch t0H toL tr tf OSC SCK,SI SCK,SI CE,SCK CE,SCK CE,SCK SCK SCK CE,SCK,SI CE,SCK,SI SO,RPU = 4.7kΩ, CL = 10pF*1 SO,RPU = 4.7kΩ, CL = 10pF*1 SO output delay time tdc SO rise time tdr CE,SCK,SI,RES,KIN1 to KIN5 min 4.5 typ max 6.0 2/3VDD VDD 1/3VDD VDD 0.8VDD 6.0 0.6VDD VDD 0 0.2VDD unit V V V V V V TBD pF 19 160 160 160 160 160 160 160 38 76 KHz ns ns ns ns ns ns ns ns ns 1.5 µs 1.5 µs 160 160 Note : *1.Since SO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and load capacitance CL . 21 Preliminary HL15703 Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Supply voltage detection Input high level current Input low level current Input floating voltage Pull-down resistance Output off leakage current Output high level voltage Output low level voltage Symbol VH SVD IIH IIL VIF RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage*2 VMID3 VMID4 VMID5 Oscillator frequency Current drain fOSC IDD1 IDD2 IDD3 Condition min CE,SCK,SI,RES,KIN5 to KIN5 2.7 CE,SCK,SI,RES : V1 = 6.0V CE,SCK,SI RES: V1 = 0V KIN1 to KIN5 KIN1 to KIN5 : VDD = 5.0V SO : VO = 6.0V KS1 to KS6 : I0 = -500µA P1 to P4 : I0 = -1mA SEG1 to SEG57 : I0 = -20µA COM1 to COM3 : I0= -100µA KS1 to KS6 : I0 = 25µA P1 to P4 : I0 = 1mA SEG1 to SEG57 : I0 = 20µA COM1 to COM3 : I0 = 100µA SO : I0 = 1 mA COM to COM3 : 1/2 bias, Io = ¡ ¾100µA SEG1 to SEG57 : 1/3 bias, Io = ¡ ¾20µA SEG1 to SEG57 : 1/3 bias, Io = ¡ ¾20µA COM to COM3 : 1/3 bias, Io = ¡ ¾100µA COM to COM3 : 1/3 bias, Io = ¡ ¾100µA OSC : C = TBD Sleep mode VDD = 6.0V, output open, 1/2 bias,fOSC = 38 KHz VDD = 6.0V, output open, 1/3 bias,fOSC = 38 KHz typ O.1VDD 2.5 max 3.3 5.0 -5.0 0.05VDD 250 6.0 VDD -1.2 VDD -0.5 VDD -0.2 VDD -1.0 VDD -1.0 VDD -1.0 0.2 0.5 1.5 1.0 1.0 1.0 0.1 0.5 1/2 VDD 1/2VDD -1.0 +1.0 2/3VDD 2/3VDD -1.0 +1.0 1/3VDD 1/3VDD -1.0 +1.0 2/3VDD 2/3VDD -1.0 +1.0 1/3VDD 1/3VDD -1.0 +1.0 30.4 38 45.6 100 50 100 unit V V µA µA V kΩ µA V V V V V V V V V V V V V V KHz µA 230 460 µA 200 400 µA Note : *2. Excluding the bias voltage generation divider resistor built into VCL1 and VCL2 22 Preliminary HL15703 Timing diagram of SIO CE t0L t0H SCK tr tf SI tds tdh SO VIH1 VIL CE SCK tcp tch tcs SI SO tdc 23 tdr Preliminary HL15703 14. Application 1/2 bias ( for use with normal panels ) (p 1) (p 2) (p 3) (p 4) (general-purpose output ports) Used with the backlight controller or other circuit. VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 .. .. . SEG55 *1) VSS TEST C ≥ 0.047uF VCL1 VCL2 C S E G RES *2) 5 CE 7 SCK K K K K K / I I I I I K K K K K SI SO N N N N N S S S S S 5 4 3 2 1 6 5 4 3 2 From the controller To the controller To the controller power supply S E G 5 6 / K S 1 LCD panel (up to 171 segments OSC +5V .. .. . (SEG56) (SEG57) *3) • Key matrix (up to 30 keys) • ¡ ¡Æ Æ Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15703 is reset by the SVD. *2). If the RES pin is not used for system reset, it must be connected to VDD *3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 24 Preliminary HL15703 1/3 bias ( for use with normal panels ) (p 1) (p 2) (p 3) (p 4) (general-purpose output ports) Used with the backlight controller or other circuit. VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 .. .. . SEG55 *1) VSS TEST C ≥ 0.047uF C S E G RES *2) 5 CE 7 SCK K K K K K / I I I I I K K K K K SI SO N N N N N S S S S S 5 4 3 2 1 6 5 4 3 2 From the controller To the controller To the controller power supply C VCL1 VCL2 S E G 5 6 / K S 1 LCD panel (up to 171 segments OSC +5V .. .. . (SEG56) (SEG57) *3) • Key matrix (up to 30 keys) • ¡ ¡Æ Æ Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15703 is reset by the SVD. *2). If the RES pin is not used for system reset, it must be connected to VDD *3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 25 Preliminary HL15703 1/3 bias ( for use with large panels ) (p 1) (p 2) (p 3) (p 4) (general-purpose output ports) Used with the backlight controller or other circuit. VDD COM1 COM2 COM3 P1 / SEG1 P2 / SEG2 P3 / SEG3 P4 / SEG4 SEG5 .. .. . SEG55 *1) VSS TEST C ≥ 0.047uF C R • R •R C S E G RES *2) 5 CE 6 SCK K K K K K / I I I I I K K K K K SI SO N N N N N S S S S S 5 4 3 2 1 6 5 4 3 2 From the controller To the controller To the controller power supply VCL1 VCL2 S E G 5 6 / K S 1 LCD panel (up to 171 segments OSC +5V .. .. . (SEG56) (SEG57) *3) • Key matrix (up to 30 keys) • ¡ ¡Æ Æ Note : *1). Add a capacitor to the power supply line so that the power supply voltage VDD rise time when power is applied and the power supply voltage VDD fall time when power drops are both at least 1 ms, as the HL15703 is reset by the SVD. *2). If the RES pin is not used for system reset, it must be connected to VDD *3). The SO pin, being an open-drain output, requires a pull-up resistor, Select a resistance (between 1 to 10kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. 26 Preliminary