HY62UF08401C Series 256Kx16bit full CMOS SRAM Document Title 512K x 8bit 2.7 ~ 3.3V Super low Power FCMOS Slow SRAM Revision History Revision No History Draft Date Remark 00 Initial Draft Dec.18.2000 Final 01 Changed Logo Mar.23.2001 Final 02 Changed Isb1 values Jun.07.2001 Final This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 / Jun.01 Hynix Semiconductor HY62UF08401C Series DESCRIPTION FEATURES The HY62UF08401C is a high speed, super low power and 4Mbit full CMOS SRAM organized as 512K words by 8bits. The HY62UF08401C uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup -. 1.2V(min) data retention • Standard pin configuration -. 32 - sTSOP - 8X13.4(Standard) Product No. Voltage (V) Speed (ns) Operation Current/Icc(mA) HY62UF08401C-I 2.7~3.3 55/70 5 Standby Current(uA) LL SL 15 6 Temperature (°C) -40~85 Note 1. I : Industrial 2. Current value is max. PIN CONNECTION I/O1 DATA I/O BUFFER A18 WRITE DRIVER BLOCK DECODER MEMORY ARRAY 512K x 8 SENSE AMP ROW DECODER A0 COLUMN DECODER 32-sTSOP Forward /OE A10 /CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 PRE DECODER 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADD INPUT BUFFER A11 A9 A8 A13 /WE A18 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 BLOCK DIAGRAM I/O8 /CS /OE /WE PIN DESCRIPTION Pin Name /CS /WE /OE A0 ~ A18 Rev.02 / Jun.01 Pin Function Chip Select Write Enable Output Enable Address Input Pin Name I/O1 ~ I/O8 Vcc Vss Pin Function Data Input/Output Power (2.7V~3.3V) Ground 2 HY62UF08401C Series ORDERING INFORMATION Part No. HY62UF08401C-DS(I) HY62UF08401C-SS(I) Speed 55/70 55/70 Power LL-part SL-part Temp. I I Package sTSOP sTSOP Note 1. I : Industrial ABSOLUTE MAXIMUM RATINGS (1) Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 260 • 10 Unit V V °C °C W °C•sec Remark HY62UF08401C-I Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability. TRUTH TABLE /CS H L /WE X H L /OE X H L X MODE Deselected Output Disabled Read Write I/O OPERATION High-Z High-Z Dout Din Supply Current Standby Active Active Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH) Rev.02 / Jun.01 2 HY62UF08401C Series RECOMMENDED DC OPERATING CONDITION Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31. Typ 3.0 0 - Max. 3.3 0 Vcc+0.3 0.6 Unit V V V V Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested. DC ELECTRICAL CHARACTERISTICS TA = -40°C to 85°C Sym Parameter ILI Input Leakage Current ILO Output Leakage Current Icc Operating Power Supply Current ICC1 Average Operating Current ISB Standby Current (TTL Input) ISB1 Standby Current (CMOS Input) VOL VOH Output Low Output High Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS = VIH or /OE = VIH or /WE = VIL /CS = VIL, VIN = VIH or VIL, II/O = 0mA /CS = VIL, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA /CS < 0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS = VIH or VIN = VIH or VIL /CS > Vcc - 0.2V or SL VIN > Vcc - 0.2V or LL VIN < Vss + 0.2V IOL = 2.1mA IOH = -1.0mA Min -1 -1 2.4 Typ1. - Max 1 1 Unit uA uA 5 mA 40 mA 5 mA 0.2 0.2 0.5 6 15 mA uA uA - 0.4 - V V Note 1. Typical values are at Vcc = 3.0V TA = 25°C 2. Typical values are not 100% tested CAPACITANCE (Temp = 25°C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS, /WE, /OE) COUT Output Capacitance (I/O) Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF Note : These parameters are sampled and not 100% tested Rev.02 / Jun.01 3 HY62UF08401C Series AC CHARACTERISTICS TA = -40°C to 85°C, unless otherwise specified # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol 55ns Min. Max. Parameter READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write 70ns Min. Max. Unit 55 10 5 0 0 10 55 55 30 30 30 - 70 10 5 0 0 10 70 70 35 30 30 - ns ns ns ns ns ns ns ns ns 55 50 50 0 45 0 0 25 0 5 20 - 70 60 60 0 50 0 0 30 0 5 20 - ns ns ns ns ns ns ns ns ns ns AC TEST CONDITIONS TA = -40°C to 85°C, unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load AC TEST LOADS VTM=2.8V 1029 Ohm DOUT CL(1) 1728 Ohm Note 1. Including jig and scope capacitance Rev.02 / Jun.01 4 HY62UF08401C Series TIMING DIAGRAM READ CYCLE 1 (Note 1,4) tRC ADDR tAA tOH tACS /CS tCHZ(3) tOE /OE tOLZ(3) Data Out High-Z tOHZ(3) tCLZ(3) Data Valid READ CYCLE 2 (Note 1,2,4) tRC ADDR tAA tOH tOH Data Out Previous Data Data Valid READ CYCLE 3(Note 1,2,4) /CS tACS tCHZ(3) tCLZ(3) Data Out Data Valid Notes: 1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS in high for the standby, low for active Rev.02 / Jun.01 5 HY62UF08401C Series WRITE CYCLE 1(1,4,8) (/WE Controlled) tWC ADDR tWR(2) tCW /CS tAW tWP /WE tAS Data In tDW High-Z tDH Data Valid tWHZ(3,8) tOW (5) (6) Data Out WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled) tWC ADDR tAS tWR(2) tCW /CS tAW tWP /WE tDW Data In Data Out Rev.02 / Jun.01 High-Z tDH Data Valid High-Z 6 HY62UF08401C Series Notes: 1. A write occurs during the overlap of a low /WE and a low /CS. 2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS low transition occurs simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS in high for the standby, low for active DATA RETENTION ELECTRIC CHARACTERISTIC TA = -40°C to 85°C Symbol Parameter VDR Iccdr tCDR tR Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time Test Condition /CS > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS > Vcc - 0.2V or VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min 1.2 Typ1. - Max 3.3 Unit V SL - 0.1 3 uA LL - 0.1 10 uA 0 - - ns tRC - - ns See Data Retention Timing Diagram Notes: 1. Typical values are under the condition of TA = 25°C. 2. Typical value are sampled and not 100% tested DATA RETENTION TIMING DIAGRAM DATA RETENTION MODE VCC 2.7V tCDR tR VIH VDR /CS >VCC-0.2V /CS VSS Rev.02 / Jun.01 7 HY62UF08401C Series PACKAGE INFORMATION 32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST) #1 #32 UNIT : INCH(mm) 0.319(8.1) 0.311(7.9) #17 #16 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) 0.024(0.6) 0.016(0.4) Rev.02 / Jun.01 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.011(0.27) 0.007(0.17) 8 HY62UF08401C Series MARKING INFORMATION Package sTSOP Marking Example H Y 6 2 U F 0 8 1 C - c S s s t y y w w p K 4 0 O R Index • HY62UF08401C : Part Name •c : Power Consumption -D -S : Package Type -S : Speed - 55 - 70 : Temperature -I •S • ss •t : Low Low Power : Super Low Power : sTSOP : 55ns : 70ns : Industrial ( -40 ~ 85 °C ) • yy • ww •p : Year ( ex : 00 = year 2000, 01 = year 2001 ) : work week ( ex : 12 = ww12 ) : Process Code • KOR : Origin Country Note - Capital Letter - Small Letter : Fixed Item : Non-fixed Item Rev.02 / Jun.01 9