www.ti.com SCLS555 − JUNE 2004 DESCRIPTION The SN74LV8153 is a serial-to-parallel data converter. It accepts serial input data and outputs 8-bit parallel data. The automatic data-rate detection feature of the SN74LV8153 eliminates the need for an external oscillator and helps with cost and board real-estate savings. The OUTSEL pin is used to choose between open collector and push-pull outputs. The open-collector option is suitable when this device is used in applications such as LED interface, where high drive current is required. SOUT is the output that acknowledges reception of the serial data. To ensure the high-impedance state during power up or power down, OE should be tied to VCC1 through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FEATURES D Single-Wire Serial Data Input D Compatible With UART Serial-Data Format D Up to Eight Devices (64-Bit Parallel) Can D D D D D D N OR PW PACKAGE (TOP VIEW) VCC1 A0 A1 A2 D OUTSEL RESET OE SOUT GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Share the Same Bus by Using Different Combinations of A0, A1, A2 Up to 40 mA Current Drive in Open-Collector Mode for Driving LEDs Outputs Can be Configured as Open-Collector or Push-Pull Internal Oscillator and Counter for Automatic Data-Rate Detection Output Levels Are Referenced to VCC2 and Can Be Configured From 3 V to 12 V Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 1000-V Charged-Device Model (C101) SUMMARY OF RECOMMENDED OPERATING CONDITIONS VCC2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 GND PARAMETER VCC1 VCC2 3 V to 5.5 V 3 V to 13.2 V IOL 40 mA @ VCC2 = 4.5 V (open-collector mode) IOH −24 mA @ VCC2 = 12 V (push-pull mode) Maximum Data Rate 24 Kbps FUNCTION TABLE (each buffer) INPUTS OUTPUT Yn OUTSEL RESET OE Dn L H L H L L H L L H L X H X H L L X X H H H L H H H H L L L H X H X Z H L L X L OUTPUT STRUCTURE Open collector Push-pull In the open-collector mode (OUTSEL = L), the outputs are inverted, e.g., Y1 = l, when D1 = H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( Copyright 2004, Texas Instruments Incorporated www.ti.com SCLS555 − JUNE 2004 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE(1) TA PDIP − N −40°C −40 C to 85 85°C C TSSOP − PW Tube SN74LV8153N Tube SN74LV8153PW Tape and reel SN74LV8153PWR TOP-SIDE MARKING SN74LV8153N LV8153 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. PIN DESCRIPTION PIN # 1 I/O PIN FUNCTION Power-supply pin (all inputs and outputs except for Y0-Y7) A0, A1, A2 In The address pins are used to program the address of the device and allow up to eight devices to share the same bus. 5 D In Serial data input 6 OUTSEL In Choose between open-collector and push-pull type outputs (Y0-Y7). 7 RESET In Initialize register status 8 OE In Force Y0-Y7 to Hi-Z 9 SOUT Out Outputs a pulse when latch data is changed. Supplied by VCC1. 12-19 Y0-Y7 Out Push-pull or open collector parallel data outputs. Supplied by VCC2. 20 VCC2 2-4 2 PIN NAME VCC1 Power-supply pin for outputs (Y0-Y7). VCC2 can range from 3 V to 13.2 V. www.ti.com SCLS555 − JUNE 2004 data transmission protocol − The serial data should be sent as 2START-3ADDRESS-4DATA-1STOP. Two consecutive serial-data frames transmit 8 bits of data. The first frame includes the lower four bits of data (D0-D3), and the second frame includes the upper four bits (D4-D7). − The three address bits (in the consecutive frame) must be the same as those in the first frame; otherwise, the data will be dropped. − The order of the two start bits must be 0, then 1 in any frame; otherwise, the data rate will not be detected correctly. The period between the falling edge of the first start bit (ST0) and the rising edge of the second start bit (ST1) is measured to generate an internal-clock synchronized data stream. 1st Frame ST0 A0 A1 A2 2nd Frame D0 D1 D2 ST0 D3 ST1 SP A0 A1 A2 D4 D5 D6 D7 ST1 SP Example of Serial-Data Format ST0 DATA ST0 ST1 A0 A1 A2 D0 D1 D2 D3 SP ST1 A0 A1 A2 D4 D5 D6 D7 SP Internal Clock Y0−Y7 SOUT Timing Chart (1)Internal clock cannot be observed. (2)D0 is LSB and D7 is MSB. The data stream should be LSB first. 3 www.ti.com SCLS555 − JUNE 2004 logic diagram Power On Reset Data 8-Bit S/R CLK OC Timing Control 4 Y0 4 8-Bit Register Timing and Address Verification 4-Bit Register 4 Data OC Y7 3 OSC 3 Address Data A0 A1 A2 3-Bit Register SOUT RESET OUTSEL OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)(1) Supply voltage range, VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 14.5 V Input voltage range, VI(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high or low state, VO (SOUT) (2)(3) . . . . −0.5 V to VCC1 + 0.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (SOUT) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range, applied to any output in the high or low state, VO (Y0-Y7)(2)(3) . . . . −0.5 V to VCC2 + 0.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (Y0-Y7)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 14.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current, IO (OUTSEL = L, Y0-Y7 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Package thermal impedance, θJA(4): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (1)The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (2)The value of VCC is provided in the recommended operating operating condition table. (3)The package thermal impedance is calculated in accordance with JESD 51-7. 4 www.ti.com SCLS555 − JUNE 2004 recommended operating conditions(1) VCC1 VCC1 VCC2 UNIT 3 5.5 V 3 13.2 V VIL Low-level input voltage VI Input voltage OUTSEL = H High-level output current SOUT OUTSEL = H Yn Low-level output current OUTSEL = L SOUT VCC × 0.7 VCC × 0.7 3V 3V 4.5 V 4.5 V 3V 3V 4.5 V 4.5 V 0 5.5 4.5 V 4.5 V 0 5.5 12 V 0 13.2 Output voltage Yn IOL MAX Supply voltage High-level input voltage IOH MIN Supply voltage VIH VO VCC2 V VCC × 0.3 VCC × 0.3 3V 3V −2 4.5 V 4.5 V −8 4.5 V 12 V −24 3V 3V −4 4.5 V 4.5 V −8 3V 3V 4.5 V 4.5 V 3V 3V 20 4.5 V 4.5 V 40 3V 3V 4 4.5 V 4.5 V 8 V V V mA mA 2 8 mA TA Operating free-air temperature −40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5 www.ti.com SCLS555 − JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage All inputs VT− Negative-going input threshold voltage All inputs ∆VT Hysteresis (VT+ − VT−) All inputs VOH SOUT Yn VOL SOUT TYP MAX VCC2 3.3 V 3.3 V 2.31 5V 5V 3.5 3.3 V 3.3 V 0.99 5V 5V 1.5 3.3 V 3.3 V 0.33 1.32 5V 5V 0.5 2 UNIT V V V IOH = −2 mA IOH = −8 mA Yn MIN VCC1 3V 3V 2.38 4.5 V 4.5 V 3.8 IOH = −24 mA IOH = −4 mA 4.5 V 12 V 11 3V 3V 2.38 IOH = −8 mA IOL = 2 mA (OUTSEL = H) 4.5 V 4.5 V 3.8 3V 3V 0.44 IOL = 8 mA (OUTSEL = H) IOL = 40 mA (OUTSEL = L) 4.5 V 4.5 V 0.44 4.5 V 4.5 V 0.5 3V 3V 0.44 4.5 V 4.5 V 0.44 IOL = 4 mA IOL = 8 mA II IOZ VI = 5.5 V or GND VO = VCC or GND (OUTSEL = H) IOH VO = 12 V (OUTSEL = L) V 0 to 5.5 V ±1 µA 5.5 V 5.5 V ±5 µA 5.5 V 5.5 V 5 µA OUTSEL = H ICC VI = VCC or GND, IO = 0 Ioff (except SOUT) Ci VI or VO = 0 to 5.5 V, VCC = 0 VI = VCC or GND OUTSEL = L V 5 5.5 V 5.5 V 0 0 5V 5V 20 ±50 5 TA = 25°C MIN TYP µA pF switching characteristics over recommended operating free-air temperature VCC1 = VCC2 = 3.3 V ± 0.3 V (unless otherwise noted) (see Figures 1 and 2) range, FROM (INPUT) TO (OUTPUT) D7 Y Pw/2 MAX (1) D7 SOUT Pw/2 (1) RESET OE(2) Y ten OE(3) Y 200 ns tdis OE(3) Y 200 ns PARAMETER tpd tw Y SOUT Data rate LOAD CAPACITANCE mA MIN MAX 200 UNIT ns 200 CL = 50 pF Pw (4) ns 2 24 Kbps (1) The t pd is dependent on the data pulse width (Pw), and Y outputs are changed after one-half of Pw, because the internal clock is synchronized at the middle of the data pulse. Not tested, but specified by design. (2) When outputs are open collector (OUTSEL = L) (3) When outputs are push-pull (OUTSEL = H) (4) SOUT goes low when the data is received correctly and maintains a low level for one data-pulse period. Not tested, but specified by design. 6 www.ti.com SCLS555 − JUNE 2004 switching characteristics over recommended operating free-air temperature VCC1 = VCC2 = 5 V ± 0.5 V (unless otherwise noted) (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C TYP D7 Y Pw/2 MAX (1) D7 SOUT Pw/2 (1) RESET OE(2) Y ten OE(3) Y tdis OE(3) Y tpd tw Data rate Y SOUT MIN MIN MAX 150 range, UNIT ns 150 CL = 50 pF Pw 150 ns 150 ns (4) ns 2 24 Kbps (1) The tpd is dependent on the data pulse width (Pw), and Y outputs are changed after one-half of Pw, because the internal clock is synchronized at the middle of the data pulse. Not tested, but specified by design. (2) When outputs are open collector (OUTSEL = L) (3) When outputs are push-pull (OUTSEL = H) (4) SOUT goes low when the data is received correctly and maintains a low level for one data-pulse period. Not tested, but specified by design. 7 www.ti.com SCLS555 − JUNE 2004 PARAMETER MEASUREMENT INFORMATION (PUSH-PULL OUTPUT) From Output Under Test CL = 50 pF (see Note A) RL = 1 kΩ VCC1 Open S1 TEST GND S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VCC1 GND LOAD CIRCUIT VCC1 50% VCC1 Input 50% VCC1 tPLH In-Phase Output 50% VCC1 VOH 50% VCC1 VOL VOH 50% VCC1 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC1 0V Output Waveform 1 S1 at VCC (see Note B) tPLH 50% VCC1 50% VCC1 tPZL tPHL tPHL Out-of-Phase Output 0V VCC1 Output Control tPLZ ≈VCC1 50% VCC1 tPZH Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC1 VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 www.ti.com SCLS555 − JUNE 2004 PARAMETER MEASUREMENT INFORMATION (OPEN-COLLECTOR OUTPUT) VCC1 VCC1 RL = 500 Ω From Output Under Test Test Point CL (see Note A) NOTES: A. B. C. D. 50% VCC1 tPHL 0V tPLH ≈VCC1 Output LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 50% VCC1 Input 50% VCC1 VOL + 0.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ The outputs are measured one at a time, with one input transition per measurement. tPHL and tPLH are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LV8153N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LV8153NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74LV8153PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV8153PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV8153PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LV8153PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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