54HC4050 CMOS Logic Hex Non-Inverting Buffers FEATURES: DESCRIPTION: • High speed CMOS logic hex non-inverting buffers • RAD-PAK® radiation hardened against natural space radiation • Single Event Effects: - SEL: > 120 MeV/mg/cm2 • Total dose hardness: • - > 100 Krad (Si), depending upon space mission • Package: -16 Pin RAD-PAK® Flat Pack • Typical propagation delay: - 6ns at VCC = 5V, CL = 15pF, TA = 25°C • High-to-Low voltage level converter for up to VI = 16V • Fanout (over temperature range) -10 LSTTL loads (Standard Outputs) -15 LSTTL loads (Bus Driver Outputs) • Balanced propagation delay and transition times • Significant power reduction compared to LSTTL logic ICs • 2V to 6V operation • High noise immunity • -NIL = 30%, NIH = 30% of VCC at VCC = 5V Maxwell Technologies' 54HC4050 high speed CMOS Logic Hex Non-Inverting Buffers features a greater than 100 krad(Si) total dose tolerance, depending upon space mission. These parts have a modified input protection structure that enables them to be used as logic level translators which will convert high-level logic to a low-level logic while operating off the lowlevel logic supply. For example, 15V input pulse levels can be down-converted to 0V to 5V logic levels. The modified input protection structure protects the input from negative electrostatic discharge. The 54HC4050 can be used as simple buffers or inverters without level translation. 1000587 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 12.19.01 Rev 1 All data sheets are subject to change without notice 1 ©2001 Maxwell Technologies. All rights reserved. Memory Logic Diagram 54HC4050 CMOS Logic Hex Non-Inverting Buffers TABLE 1. 54HC4050 PINOUT DESCRIPTIONS PIN SYMBOL DESCRIPTION 1 VCC Power supply 8 VSS Ground 13, 16 NC Not Connected 3, 5, 7, 9, 11, 14 A-F Inputs 2 G=A Buffered Output 4 H=B Buffered Output 6 I=C Buffered Output 10 J=D Buffered Output 12 K=E Buffered Output 15 L=F Buffered Output Memory TABLE 2. 54HC4050 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Storage Temperature TS -65 150 °C Operating Temperature Range TA -55 125 °C DC Supply Voltage VCC -0.5 7.0 V DC Input Diode Current For VI < -0.5V or VI > VCC +0.5V IIK -20 +20 mA DC Output Diode Current For VO < -0.5V or VO > VCC +0.5V IOK -20 +20 mA DC Output Source or Sink Current per Output Pin For VO > -0.5V or VO < VCC +0.5V IO -25 +25 mA ICC or IGND -50 +50 mA DC VCC or Ground Current TABLE 3. DELTA LIMITS 1000587 PARAMETER VARIATION ICC ±10% of specified value in Table 5 12.19.01 Rev 1 All data sheets are subject to change without notice 2 ©2001 Maxwell Technologies. All rights reserved. 54HC4050 CMOS Logic Hex Non-Inverting Buffers TABLE 4. 54HC4050 RECOMMENDED OPERATING CONDITIONS PARAMETER Supply Voltage DC Input or output Voltage SYMBOL MIN MAX UNIT VCC 2 6 V VI, VO 0 VCC V ns -- Input Rise and Fall Time 2V 4.5V 6V 1000 500 400 Temperature Range TA -55 125 °C TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) High Level Output Voltage CMOS Loads SYMBOL VOH High Level Output Voltage TTL Loads TEST CONDITIONS VI = VIH or VIL, IO = -4mA VCC = 4.5V VOL Low Level Output Voltage TTL Loads MAX 1.9 4.4 5.9 ---- +25°C 3.98 -- -55 to 125°C 3.7 +25°C 5.48 -- -55 to 125°C 5.2 -V VI = VIH or VIL, IO = -0.02mA VCC = 2V VCC = 4.5V VCC = 6V VI = VIH or VIL, IO = 4mA VCC = 4.5V VI = VIH or VIL, IO = 5.2mA VCC = 6V UNIT V VI = VIH or VIL, IO = -0.02mA VCC = 2V VCC = 4.5V VCC = 6V VI = VIH or VIL, IO = -5.2mA VCC = 6V Low Level Output Voltage CMOS Loads MIN 0.1 0.1 0.1 +25°C 0.26 -- -55 to 125°C 0.4 -- +25°C 0.36 -- -55 to 125°C 0.4 -- High Level Input Voltage VIH VCC = 2V VCC = 4.5V VCC = 6V 1.5 3.15 4.2 ---- V Low Level Input Voltage VIL VCC = 2V VCC = 4.5V VCC = 6V ---- 0.5 1.35 1.8 V Input Leakage Current II +25°C -- ±0.1 µA -55 to 125°C -- ±1 +25°C -- ±0.5 -55 to 125°C -- ±5 VCC = 6V, VI = VCC or GND VCC = 6V, VI = 15V 1000587 12.19.01 Rev 1 Memory PARAMETER All data sheets are subject to change without notice 3 ©2001 Maxwell Technologies. All rights reserved. 54HC4050 CMOS Logic Hex Non-Inverting Buffers TABLE 5. 54HC4050 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL Quiescent Device Current TEST CONDITIONS ICC VI = VCC or GND, IO = 0mA VCC = 6V MIN MAX UNIT +25°C -- 2 µA -55 to 125°C -- 40 TABLE 6. 54HC4050 AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL Propogation Delay nA to nY tPLH, tPHL TEST CONDITION CL = 50pF VCC = 2V -- 85 -55 to 125°C -- 130 +25°C -- 17 -55 to 125°C -- 26 +25°C -- 14 -55 to 125°C -- 22 CL = 50pF VCC = 2V -- 75 -55 to 125°C -- 110 +25°C -- 15 -55 to 125°C -- 22 +25°C -- 13 -55 to 125°C -- 19 ns +25°C VCC = 4.5V VCC = 6V UNIT Memory VCC = 6V tTLH, tTHL MAX +25°C VCC = 4.5V Transition Times (Figure 1) MIN ns TABLE 7. 54HC4050 CAPACITANCE1 PARAMETER Input Capacitance Power Dissipation SYMBOL TEST CONDITIONS CI Capacitance2, 3 CPD VCC = 5V MAX UNIT 10 pF 35 pF 1. Guaranteed by design. 2. CPD is used to determine the dynamic power consumption, per gate. 3. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 4 ©2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers 54HC4050 FIGURE 1. TRANSITION TIMES AND PROPOGATION DELAY TIMES, COMBINATION LOGIC Memory 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 5 ©2001 Maxwell Technologies. All rights reserved. 54HC4050 CMOS Logic Hex Non-Inverting Buffers Memory 16-PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.115 0.135 0.150 b 0.015 0.017 0.019 c 0.004 0.005 0.007 D 0.407 0.415 0.423 E 0.275 0.280 0.285 E1 -- -- 0.500 E2 0.150 0.156 0.162 E3 0.030 0.062 -- e 0.050 BSC L 0.325 0.335 0.345 Q 0.020 0.033 0.045 S1 0.005 0.024 0.045 N 16 F16-01 Note: All dimensions in inches 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 6 ©2001 Maxwell Technologies. All rights reserved. CMOS Logic Hex Non-Inverting Buffers 54HC4050 Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 1000587 12.19.01 Rev 1 All data sheets are subject to change without notice 7 ©2001 Maxwell Technologies. All rights reserved. 54HC4050 CMOS Logic Hex Non-Inverting Buffers Product Ordering Options Model Number 54HC4050 RP X Option Details Feature Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25°C) I = Industrial (testing @ -55°C, +25°C, +125°C) Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature CMOS Logic Hex Non-Inverting Buffers 12.19.01 Rev 1 All data sheets are subject to change without notice Memory 1000587 F 8 ©2001 Maxwell Technologies. All rights reserved.