TI TXS0206

TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
MMC, SD CARD, Memory Stick™ VOLTAGE-TRANSLATION TRANSCEIVER AND LDO
VOLTAGE REGULATOR WITH ESD PROTECTION AND EMI FILTERING
FEATURES
1
•
Level Translator
– VCCA Range of 1.1 V to 3.6 V
– Fast Propagation Delay (4 ns Max When
Translating Between 1.8 V and 2.9 V)
Low-Dropout (LDO) Regulator
– 200-mA LDO Regulator With Enable
– 2.9-V Output Voltage
– 3.05-V to 5.5-V Input Voltage Range
– Very Low Dropout: 200 mV at 200 mA
•
•
•
ESD Protection Exceeds JESD 22 (A Port)
– 2000-V Human-Body Model (A114-B)
– 1000-V Charged-Device Model (C101)
±8-kV Contact Discharge IEC 61000-4-2 ESD
(B Port)
YFP PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
1
1 2 3 4
A
B
C
D
E
2
3
4
A
DAT2A
VCCA
WP/CD
DAT2B
B
DAT3A
VBATT
VCCB O/P
DAT3B
C
CMDA
GND
GND
CMDB
D
DAT0A
CLKA
CLKB
DAT0B
E
DAT1A
CLK-f
EN
DAT1B
DESCRIPTION/ORDERING INFORMATION
The TXS0206-29 is a complete solution for interfacing microprocessors with MultiMediaCards (MMCs), secure
digital (SD) cards, and Memory Stick™ cards. It is comprised of a high-speed level translator, a low-dropout
(LDO) voltage regulator, IEC level ESD protection, and EMI filtering circuitry.
The voltage-level translator has two supply voltage pins. VCCA can be operated over the full range of 1.1 V to
3.6 V. VCCB is set at 2.9 V and is supplied by an internal LDO. The integrated LDO accepts input voltages from
3.05V to as high as 5.5 V and outputs 2.9 V, 200 mA to the B-side circuitry and to the external memory card. The
TXS0206-29 enables system designers to easily interface low-voltage microprocessors to memory cards
operating at 2.9 V.
Memory card standards recommend high-ESD protection for devices that connect directly to the external memory
card. To meet this need, the TXS0206-29 incorporates ±8-kV Contact Discharge protection on the card side.
Since memory cards are widely used in mobile phones, PDAs, digital cameras, personal media players,
camcorders, set-top boxes, etc. Low static power consumption and small package size make the TXS0206-29 an
ideal choice for these applications. The TXS0206-29 is offered in a 20-bump wafer chip scale package (WCSP).
This package has dimensions of 1.96 mm × 1.56 mm, with a 0.4-mm ball pitch for effective board-space savings
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE
WCSP – YFP (Pb-free)
(2)
Tape and reel
ORDERABLE PART NUMBER
TXS0206-29YFPR
TOP-SIDE MARKING (3)
___3V2
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
The actual top-side marking has three preceding characters to denote year, month, and sequence code.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
REFERENCE DESIGN
VCCA
VCCB
VCCB
C3
0.1 μF
U1A
C4
0.1 μF
C1
0.1 μF
J1
U2
VDDA
A2
VCCA
DAT0
D1
DAT0A
DAT1
E1
DAT1A
DAT2
DAT3
CMD
CLK
CLKin
GND
WP/CD
A1
VCCB O/P
D4 DAT0B
DAT0B
DAT1B E4 DAT1B
DAT2B A4 DAT2B
DAT3B B4 DAT3B
DAT2A
B1
DAT3A
C1
CMDA
D2
CLKA
E2
CLK-f
C2
DAT2B
DAT3B
CMDB
B3
CLKB
DAT0B
DAT1B
C4 CMDB
CMDB
D3 CLKB
CLKB
CD
GND
C3
GND
Processor
SD/SDIO MMC
WP/CD
A3
WP
0
1
2
3
4
5
6
7
8
9
10
11
12
13
DAT2
DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1
WP/CD (Physical)
CD (Physical)
GND
GND
WP (Physical)
54794-0978
SD/SDIO
CardConnector
TXS0206-29
WP/CD
Figure 1. Interfacing With SD/SDIO Card
ESD – ±8-kV Contact Discharge
ESD – 2 kV
1.8 V
CPU
A Side
B Side
2.9 V
CLK
CLK
Feedback CLK
CMD
CMD
Data 0–3
Data 0–3
EN
WP, CD
Level-Shifter
Integrated
ASIP
EMI Filter
Antenna
Pins 10, 11
MMC,
SD Card, or
MS Card
WP, CD 1.8-V Pullup
Integrated PSU
2.9 V, 200 mA
WP, CD
Integrated Pullup/Pulldown Resistors
Figure 2. Typical Application Circuit
2
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TXS0206-29
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SCES690 – DECEMBER 2009
Table 1. LOGIC TABLE
EN
LDO
TRANSLATOR I/Os
L
Disabled
Disabled, pulled to VCCA, VCCB O/P through R1 and R2
at 70kΩ pullup resistors respectively
H
Active
Active
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NO.
NAME
A1
DAT2A
I/O
A2
VCCA
Power
A-port supply voltage. VCCA powers all A-port I/Os and control inputs.
A3
WP/CD
Output
Connected to write protect on the mechanical connector. The WP pin has an internal 100-kΩ pullup
resistor to VCCA.
A4
DAT2B
I/O
Data bit 2 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
B1
DAT3A
I/O
Data bit 3 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
B2
VBATT
Input
B3
VCCB O/P
Output
B4
DAT3B
I/O
Data bit 3 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
C1
CMDA
I/O
Command bit connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note
A).
C2,
C3
GND
C4
CMDB
D1
D2
Data bit 2 connected to host. Referenced to VCCA. Includes R1 pullup resistor to VCCA (see Note A).
LDO input voltage from Battery-Supply
LDO output voltage and B-port supply voltage. VCCBO/P powers all B-port I/Os.
Ground
I/O
Command bit connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
DAT0A
I/O
Data bit 0 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
CLKA
Input
D3
CLKB
Output
D4
DAT0B
I/O
Data bit 0 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
E1
DAT1A
I/O
Data bit 1 connected to host. Referenced to VCCA . Includes R1 pullup resistor to VCCA (see Note A).
E2
CLK-f
Output
E3
EN
Input
Enable/disable control. Pull EN low to place all outputs in Hi-Z state and to disable the LDO.
Referenced to VCCA.
E4
DAT1B
I/O
Data bit 1 connected to memory card. Referenced to VCCBO/P. Includes R2 pullup resistor to
VCCBO/P (see Note A).
Clock signal connected to host. Referenced to VCCA.
Clock signal connected to memory card. Referenced to VCCBO/P.
Clock feedback to host for resynchronizing data to a processor. Leave unconnected if not used.
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SCES690 – DECEMBER 2009
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VCCA
VCCB
EN
(see Note B)
CLKA
CLKB
CLK-f
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
CMDA
CMDB
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT0A
DAT0B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT1A
DAT1B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
R2
(see Note A)
One-Shot
R1
(see Note A)
Translator
One-Shot
DAT2A
DAT2B
Gate Control
One-Shot
Translator
One-Shot
VCCA
VCCB
One-Shot
R1
(see Note A)
R2
(see Note A)
Translator
One-Shot
DAT3A
DAT3B
Gate Control
One-Shot
Translator
One-Shot
VCCA
100 kW
WP/CD
A.
R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows:
R1 and R2 = 40 kΩ when a logic level low is applied to the A port or B port.
R1 and R2 = 4 kΩ when a logic level high is applied to the A port or B port.
R1 and R2 = 70 kΩ when the port is deselected (or in High-Z or 3-state).
B.
EN controls all output buffers. When EN = low, all outputs are Hi-Z.
Figure 3. Logic Diagram
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TXS0206-29
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SCES690 – DECEMBER 2009
VCCB
R7
R8
R9
R10 R11
HOST
CARD
R1
CLKB
CLK
R2
CMD
CMDB
R3
Data0
DAT0B
R4
DAT1B
Data1
R5
DAT2B
Data2
R6
Data3
DAT3B
GND
GND
RESISTORS
BIDIRECTIONAL ZENER DIODES
R1, R2, R3, R4, R5, R6
40 Ω
Vbr min
14 V at 1 mA
Tolerance
±20%
Line capacitance
<20 pF
R7, R8, R9, R10, R11
40 kΩ
Tolerance
±30%
Figure 4. ASIP Block Diagram
VCCA
RWP/CD
WP/CD
RESISTORS
RWP/CD
100 kΩ
Tolerance
±30%
Figure 5. WP/CD Pullup Resistor
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SCES690 – DECEMBER 2009
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ABSOLUTE MAXIMUM RATINGS (1)
Level Translator
over operating free-air temperature range (unless otherwise noted)
VCCA
VI
Supply voltage range
Input voltage range
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or
power-off state
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through VCCA or GND
Tstg
(1)
Storage temperature range
–65
V
V
±50
mA
±100
mA
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE RATINGS
Package thermal impedance (1)
θJA
(1)
TYP
UNIT
117
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
ABSOLUTE MAXIMUM RATINGS (1)
LDO
over operating free-air temperature range (unless otherwise noted)
VIN
Input voltage range
VOUT
Output voltage range
MIN
MAX
2.3
6.5
V
–0.3
4.6
V
Peak output current
Continuous total power dissipation
UNIT
220
mA
TBD
mW
TJ
Junction temperature range
–55
150
°C
Tstg
Storage temperature range
–55
150
°C
(1)
6
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SCES690 – DECEMBER 2009
RECOMMENDED OPERATING CONDITIONS (1)
Level Translator
VCCA
VCCA
VIH
High-level input voltage
VIL
Low-level input voltage
VO
VCCB
Supply voltage
Output voltage
A-Port CMD and
DATA I/Os
1.1 V to 1.95 V
B-Port and DATA
I/Os
1.1 V to 1.95 V
OE and CLKA
1.1 V to 3.6 V
A-Port CMD and
DATA I/Os
1.1 V to 1.95 V
B-Port CMD and
DATA I/Os
1.1 V to 1.95 V
OE and CLKA
1.1 V to 3.6 V
1.95 V to 3.6 V
1.95 V to 3.6 V
1.95 V to 3.6 V
1.95 V to 3.6 V
2.9 V
2.9 V
2.9 V
2.9 V
Active state
3-state
MIN
MAX
1.1
3.6
VCCI – 0.2
VCCI
VCCI – 0.4
VCCI
VCCI – 0.2
VCCI
VCCI – 0.4
VCCI
VCCI × 0.65
VCCI
0
0.15
0
0.15
0
0.15
0
0.15
0
VCCI × 0.35
0
VCCO
1.1 V to 1.3 V
High-level output current (CLK-f output)
1.65 V to 1.95 V
–2
–8
1.1 V to 1.3 V
0.5
1.65 V to 1.95 V
V
V
mA
–4
3 V to 3.6 V
1.4 V to 1.6 V
Low-level output current (CLK-f output)
V
–1
2.9 V
2.3 V to 2.7 V
IOL
V
–0.5
1.4 V to 1.6 V
IOH
UNIT
1
2.9 V
2
2.3 V to 2.7 V
mA
4
3 V to 3.6 V
8
IOH
High-level output current (CLK output)
2.9 V
–8
IOL
Low-level output current (CLK output)
2.9 V
8
mA
Δt/Δv
Input transition rise or fall rate
5
ns/V
TA
Operating free-air temperature
85
°C
(1)
–40
mA
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
RECOMMENDED OPERATING CONDITIONS
LDO
MIN
IOUT(PK)
Peak output current
COUT
Output capacitance
TJ
Operating junction temperature
Copyright © 2009, Texas Instruments Incorporated
MAX
200
UNIT
mA
1
100
μF
–40
125
°C
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ELECTRICAL CHARACTERISTICS
Level Translator
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
A port
(CLK-f output)
VOH
A port
(DAT and CMD
outputs)
A port
(CLK-f output)
VOL
A port
(DAT and CMD
outputs)
TEST CONDITIONS
VCCA
VCCBO/P
MIN
IOH = –100 μA
1.1 V to 3.6 V
IOH = –0.5 mA
1.1 V
0.8
IOH = –1 mA
1.4 V
1.05
IOH = –2 mA
1.65 V
IOH = –4 mA
2.3 V
IOH = –8 mA
3V
IOH = –20 μA
1.1 V to 3.6 V
IOL = 100 μA
1.1 V to 3.6 V
IOL = 0.5 mA
1.1 V
TYP (1)
1.2
2.9 V
V
1.75
2.3
VCCA × 0.8
VCCA × 0.8
0.35
IOL = 1 mA
1.4 V
IOL = 2 mA
1.65 V
IOL = 4 mA
2.3 V
0.55
IOL = 8 mA
0.35
3V
0.7
2.9 V
0.45
IOL = 135 μA
0.4
IOL = 180 μA
0.4
IOL = 220 μA
1.1 V to 3.6 V
VOH
B port
(DAT output)
CLKB output
port
VOL
B port
(DAT and CMD
outputs)
II
Control inputs
UNIT
VCCA × 0.8
2.9 V
0.4
IOL = 300 μA
V
V
0.4
IOL = 400 μA
B port
(CLK output)
MAX
0.55
IOH = –100 μA
2.9 V
IOH = –8 mA
1.1 V to 3.6 V
IOH = –20 μA
2.3
2.9 V
IOL = 100 μA
1.1 V to 3.6 V
VCCBO/P ×
0.8
V
VCCBO/P ×
0.8
VCCBO/P ×
0.8
2.9 V
IOL = 8 mA
0.7
IOL = 135 μA
0.4
IOL = 180 μA
V
0.4
IOL = 220 μA
1.1 V to 3.6 V
2.9 V
0.4
IOL = 300 μA
0.4
IOL = 400 μA
0.55
VI = VCCA or GND
V
1.1 V to 3.6 V
2.9 V
±1
μA
ICCA
VI = VCCI or GND,
IO = 0
1.1 V to 3.6 V
2.9 V
6
μA
ICCB
VI = VCCI or GND,
IO = 0
1.1 V to 3.6 V
2.9 V
5
μA
Cio
Ci
(1)
8
A port
5.5
6.5
B port
15
17.5
3.5
4.5
3
4
Control inputs
Clock input
VI = VCCA or GND
pF
pF
All typical values are at TA = 25°C.
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ELECTRICAL CHARACTERISTICS
LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VBATT
TEST CONDITIONS
TYP (1)
MIN
Input voltage
MAX
VOUT + VDO
5.5
Nominal TA = 25°C
VOUT
Output voltage
ΔVOUT
Output voltage tolerance
Nominal TA = 25°C
VDO
Dropout voltage
IOUT = 200 mA
2.75
IOUT(SC)
Short-circuit current
±3
%
200
250
mV
40
IOUT < 100 mA
μA
200
100 mA ≤ IOUT ≤ 200 mA
400
RL = 0 Ω
300
f = 1 kHz
50
f = 10 kHz
40
PSRR
Power-supply rejection ratio
VIN = 3.05 V, VOUT = 2.9 V,
CNR = 0.01 μF, IOUT = 200 mA
tSTR
Start-up time
VOUT = 2.9 V, IOUT = 200 mA, COUT = 2.2 μF
(1)
V
3.05
IOUT = 0
Ground-pin current
V
2.9
All conditions
IGND
UNIT
mA
dB
μs
200
All typical values are at TA = 25°C.
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCCB = 2.9 V ± 5% (unless otherwise noted)
VCCA = 1.2 V
± 0.1 V
MIN
Command
Data rate
Clock
Data
Command
tW
Pulse
duration Clock
Data
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
Copyright © 2009, Texas Instruments Incorporated
VCCA = 1.5 V
± 0.1 V
MAX
MIN
MAX
VCCA = 1.8 V
± 0.15 V
MIN
VCCA = 2.5 V
± 0.2 V
MAX
MIN MAX
VCCA = 3.3 V
± 0.3 V
MIN
UNIT
MAX
40
60
60
60
60
1
1
1
1
1
60
60
60
60
60
MHz
40
60
60
60
60
Mbps
Mbps
25
17
17
17
17
ns
1
1
1
1
1
μs
8.3
8.3
8.3
8.3
8.3
ns
25
17
17
17
17
ns
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCB = 2.9 V ± 5% (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCCA
= 1.2 V
± 0.1 V
MIN
Push-pull driving
CMDA
CMDB
ten
tdis
CMDB
CMDA
CLKA
CLKB
DATxA
DATxB
DATxB
DATxA
CLKA
CLK-f
EN
10.8
MIN
3.7
UNIT
MAX
3.8
3.2
10.6
2.7
6.6
2.4
5.5
2.1
4.4
2
4.1
Open-drain driving
(L-to-H)
71
175
83
180
89
201
98
249
101
233
12
6.8
5.2
4.1
3.4
Open-drain driving
(H-to-L)
2.9
9.4
2.1
7.3
2
6.4
2
5.7
2.2
4.6
Open-drain driving
(L-to-H)
77
243
87
214
93
215
99
261
105
248
3.7
3.5
3.7
3.7
11.5
6.2
5
3.9
6.2
Push-pull driving
24.7
13
8.9
6.8
4.8
B-port
Push-pull driving
1
1
1
1
1
EN
A-port
Push-pull driving
1
1
1
1
1
EN
B-port
Push-pull driving
40
39
35
38
34
EN
A-port
Push-pull driving
40
38
38
38
36
CLK-f rise time
CLKB rise time
CLK-f fall time
CMDB fall time
CLKB fall time
DATxB fall time
Channel-to-channel
skew
Command
Clock
Data
10
4.6
MAX
4.7
DATxA fall time
Max data rate
MIN
4.7
CMDA fall time
tSK(O)
6.1
MAX
6.2
DATxB rise time
tfB
MIN
6.2
CMDB rise time
tfA
MAX
VCCA
= 3.3 V
± 0.3 V
11.1
DATxA rise time
trB
MIN
VCCA
= 2.5 V
± 0.2 V
11.7
CMDA rise time
trA
MAX
VCCA
= 1.8 V
± 0.15 V
Open-drain driving
(H-to-L)
Push-pull driving
tpd
VCCA
= 1.5 V
± 0.1 V
Push-pull driving
Push-pull driving
Push-pull driving
1.6
12.2
0.4
8.3
1.1
5.9
1.9
3.3
0.8
4.2
Open-drain driving
32
120
44
127
52
150
62
201
74
194
0.6
12.7
0.5
7.2
0.4
4.5
0.7
1.5
0.7
1.4
3.3
Push-pull driving
1.6
11.6
0.6
8.4
1
6.3
1.8
4.2
1.1
Push-pull driving
1.7
6.7
0.5
5.6
1
5.2
1.5
5.2
1.9
5
Open-drain driving
66
214
71
196
73
184
76
214
79
185
1.7
4.8
1.5
4.9
1.5
4.9
1.6
5
1.6
5.1
Push-pull driving
0.4
6.8
0.6
5
0.2
5.2
0.9
5.3
1
14
Push-pull driving
0.8
4
0.8
2.3
0.2
3.1
0.3
1.5
1
2.3
Open-drain driving
1.6
3.9
1.6
3.7
1.6
3.7
1.6
3.7
1.6
3.9
1
4
0.4
6.8
0.1
1.5
0.3
2.8
0.6
1.3
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
1
3.9
0.1
3.8
0.2
2.7
0.3
2.9
0.4
1.8
1.5
4.5
1.4
5.4
1.6
5
1.6
5.6
0.8
6.3
1
4.3
1
2.3
0.8
1.9
0.8
1.6
0.9
1.3
1.6
4
1.6
4.1
1.7
4.2
1.7
4.5
0.9
5.1
1
4.8
2.3
4.3
0.8
4.9
0.2
4.9
0.8
6.9
ns
μs
ns
ns
ns
ns
ns
Push-pull driving
1
1
1
1
1
Push-pull driving
40
60
60
60
60
1
1
1
1
1
60
60
60
60
60
MHz
40
60
60
60
60
Mbps
Open-drain driving
Push-pull driving
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ns
Mbps
Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
OPERATING CHARACTERISTICS
TA = 25°C, VCCB = 2.9 V
PARAMETER
TEST
CONDITIONS
1.5 V
1.8 V
2.5 V
3V
3.3 V
15
15
15
15.7
17.1
17.1
6.3
6.4
6.5
6.5
6.5
6.5
12.5
12.3
12.3
12.5
14
14
0.2
0.2
0.2
0.3
0.3
0.3
1.2
1.2
1.2
1.2
1.2
1.2
B-port input,
DATA
A-port
Disabled
output
0.2
0.2
0.2
0.3
0.3
0.3
A-port input,
DATA
B-port
Enabled
output
31.2
30.6
30.3
29.5
28.5
28.5
28.1
27.2
27
26.9
27
27
12.9
12.8
12.9
13.2
13.2
13.2
CLK
A-port input, Enabled
B-port
DATA
output
Enabled
CpdA
CpdB
(1)
B-port input,
DATA
A-port
Enabled
output
CLK
A-port input, Disabled
B-port
DATA
output
Disabled
(1)
CLK
B-port input, Enabled
A-port
DATA
output
Enabled
A-port input,
DATA
B-port
Disabled
output
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CLK
B-port input, Disabled
A-port
DATA
output
Disabled
(1)
VCCA TYP
1.2 V
UNIT
pF
pF
0.6
0.5
0.5
0.5
0.5
0.6
0.6
0.5
0.5
0.5
0.5
0.6
1.2
1.2
1.2
1
1
1
Power dissipation capacitance per transceiver
Copyright © 2009, Texas Instruments Incorporated
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TXS0206-29
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Attenuation (dB)
SCES690 – DECEMBER 2009
Frequency (Hz)
Output Current, IOUT (mA)
Figure 6. Typical ASIP EMI Filter Frequency Response
200
150
100
50
–40
–20
0
20
40
60
80
100
Junction Temperature, TJ (°C)
Figure 7. LDO Output Current Derating
12
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Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
TYPICAL CHARACTERISTICS
LOAD REGULATION, LIGHT LOADS
200
100
160
80
120
60
80
40
40
20
0
?VOUT(mV)
D
?VOUT(mV)
D
LOAD REGULATION
TA = -40°C
-40
-80
0
-20
TA = -40°C
-40
TA = 25°C
TA = 85°C
-120
-60
-160
-80
-200
-100
0
TA = 25°C
50
100
150
TA = 85°C
0
200
1
2
3
4
5
IOUT (m A)
IOUT (m A)
LINE REGULATION
(IOUT = 5 mA)
LINE REGULATION
(IOUT = 150 mA)
0
1
-0.2
-0.4
0
TA = -40°C
-0.6
TA = -40°C
-1
TA = 25°C
-1
?VOUT(%)
D
?VOUT(%)
D
-0.8
-1.2
-1.4
-2
TA = 25°C
-3
TA = 85°C
-1.6
TA = 85°C
-4
-1.8
-2
-5
-2.2
-2.4
3
3.25 3.5 3.75
4
4.25 4.5 4.75
V IN (V)
Copyright © 2009, Texas Instruments Incorporated
5
5.25 5.5
-6
3
3.25 3.5 3.75
4
4.25 4.5 4.75
V IN (V)
5
5.25 5.5
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13
TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE
vs
TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
2
250
1
200
TA = 85°C
0
TA = 25°C
150
VDO (mV)
?VOUT(%)
D
IOUT = 50 m A
IOUT = 5 m A
-1
TA = -40°C
100
-2
IOUT = 150 m A
50
-3
-4
-40
0
-15
10
35
60
0
85
50
100
150
200
150
200
IOUT (m A)
TJ (°C)
DROPOUT VOLTAGE
vs
TEMPERATURE
GROUND PIN CURRENT
vs
OUTPUT CURRENT
300
200
175
250
150
IOUT = 150 m A
200
100
IGND(µA)
VDO (mV)
125
IOUT = 100 m A
75
150
100
50
50
25
IOUT = 5 m A
0
-40
14
0
-15
10
TJ (°C)
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35
60
85
0
50
100
IOUT (m A)
Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
GROUND PIN CURRENT
vs
TEMPERATURE (ENABLE)
CURRENT LIMIT
vs
INPUT VOLTAGE
0.40
300
IGND(µA)
200
IOUT = 150 m A
0.38
IOUT = 100 m A
0.36
TA = -40°C
IOUT(A)
250
150
TA = 25°C
0.34
100
TA = 85°C
50
0.32
IOUT = 2 m A
0
-40
0.30
-15
10
35
60
3
85
3.5
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY (VIN - VOUT = 1 V)
4.5
5
5.5
OUTPUT SPECTRAL NOISE DENSITY
(COUT = 1 µF)
10
-10
9
Output Noise Density (µV/ ?Hz)
-20
-30
-40
PSRR (dB)
4
V IN (V)
TJ (°C)
-50
-60
-70
8
7
6
5
4
3
2
-80
1
10
1.E+02
10k
100k
1.E+03
1.E+04
1.E+05
1k
Frequency (Hz)
Copyright © 2009, Texas Instruments Incorporated
0
1.E+06
1M
10M
1.E+07
10
00
00
50 m A
10
00
0
0 mA
10 m A
10
00
-100
1.E+01
1
200 m A
10
0
-90
100 m A
Frequency (Hz)
Submit Documentation Feedback
15
TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
LINE TRANSIENT RESPONSE
(COUT = 1 µF)
LOAD TRANSIENT RESPONSE
(COUT = 1 µF, VIN = 3.3 V, IOUT = 0 to 100 mA)
2.94
V IN
2.92
0.18
5.25
2.95
0.16
5
2.90
0.12
4.5
2.80
0.10
2.75
0.08
4
2.70
0.06
3.75
2.65
0.04
3.5
2.60
3.25
2.55
4.25
2.89
V OUT
2.88
2.87
2.86
-0.5
-0.4
-0.3 -0.2
tim e (m s)
-0.1
0
0.00
2.50
-0.35
3
0.1
0.02
IOUT
-0.25
-0.15
-0.05
0.05
-0.02
0.15
tim e (m s)
POWER-UP/POWER-DOWN
(COUT = 1 µF, IOUT = 150 mA)
TURN-ON RESPONSE
4
3.5
3.5
3
3
2.5
2.5
2
VIN, VOUT(V)
V IN
VIN, VOUT(V)
IOUT(A)
2.85
VOUT(V)
4.75
2.9
2.85
-0.6
0.14
V OUT
2.91
VOUT(V)
3.00
VIN (V)
2.93
5.5
2
V OUT
(COUT = 1 µF)
1.5
1.5
V IN
1
1
0.5
V OUT
(COUT = 3 µF)
0.5
V OUT
0
0
-0.5
-0.1
-0.5
-0.001
-0.05
0
0.05
0.1
0.15
tim e (m s)
16
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0.2
0.25
0.3
0
0.001 0.002 0.003 0.004 0.005 0.006
tim e (s)
Copyright © 2009, Texas Instruments Incorporated
TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
PARAMETER MEASUREMENT INFORMATION
VCCI
VCCO
VCCI
VCCO
DUT
IN
DUT
IN
OUT
15 pF
OUT
1 MW
1 MW
15 pF
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
AN OPEN-DRAIN DRIVER
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
A PUSH-PULL DRIVER
2 × VCCO
50 kW
From Output
Under Test
15 pF
S1
Open
50 kW
LOAD CIRCUIT FOR ENABLE/DISABLE
TIME MEASUREMENT
TEST
S1
tPZL/tPLZ
tPHZ/tPZH
2 × VCCO
Open
tw
VCCI
VCCI/2
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VCCO/2
0.9 y VCCO
0.1 y VCCO
VOH
VCCO/2
VOL
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VCCA/2
VCCO
VCCO/2
0.1 y VCCO
VOL
tPHZ
tPZH
VOH
0.9 y VCCO
VCCO/2
0V
tf
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 8. Load Circuit and Voltage WaveformsN
Copyright © 2009, Texas Instruments Incorporated
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TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
PRINCIPLES OF OPERATION
Applications
The TXS0206-29 device is a complete application-specific voltage-translator designed to bridge the
digital-switching compatibility gap and interface logic threshold levels between a micrprocessor with MMC, SD,
and Memory Stick™ cards. It is intended to be used in a point-to-point topology when interfacing these devices
that may or may not be operating at different interface voltages.
Architecture
The CLKA, CLKB, and CLK-f subsystem interfaces consist of a fully-buffered voltage translator design that has
its output transistors to source and sink current optimized for drive strength.
The SDIO lines comprise a semi-buffered auto-direction-sensing based translator architecture (see Figure 9) that
does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B to A
ports).
VCCA
VCCB O/P
R1
One-Shot
T1
One-Shot
T2
R2
Translator
SDIO-DATAx(A)
SDIO-DATAx(B)
Bias
N1
T3
One-Shot
Translator
T4
One-Shot
Figure 9. Architecture of an SDIO Switch-Type Cell
Each of these bidirectional SDIO channels independently determines the direction of data flow without a
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is
how this auto-direction feature is realized.
The following two key circuits are employed to facilitate the "switch-type" voltage translation function:
1. Integrated pullup resistors to provide dc-bias and drive capabilities
2. An N-channel pass-gate transistor topology (with a high RON of ~300 Ω) that ties the A-port to the B-port
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
18
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TXS0206-29
www.ti.com
SCES690 – DECEMBER 2009
For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance
from a control signal.
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,
helping maintain the data rate through the device.
During a low-to-high signal rising-edge, the O.S. circuits turn on the PMOS transistors (T1, T3) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first. This edge-rate acceleration provides high ac drive by bypassing the internal pullup resistors during
the low-to-high transition to speed up the rising-edge signal.
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first.
To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to
turn-off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum
pulse-width number provided in the Timing Requirements section of this data sheet.
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (i.e. both High or
both Low) for the one-shot to trigger again. In a DC state, the output drivers maintain a Low state through the
pass transistor. The output drivers maintain a High through the "smart pullup resistors" that dynamically change
value based on whether a Low or a High is being passed through the SDIO lines, as follows:
• RPU1 and RPU2 values are a nominal 40 kΩ when the output is driving a low
• RPU1 and RPU2 values are a nominal 4 kΩ when the output is driving a high
• RPU1 and RPU2 values are a nominal 70 kΩ when the device is disabled via the EN pin or by pulling the either
VCCA or VCCBO/P to 0 V.
The reason for using these "smart" pullup resistors is to allow the TXS0206-29 to realize a lower static power
consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and
improved simultaneous switching performance.
Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level driver interfaced to the
SDIO pins. Since the high bandwidth of these bidirectional SDIO circuits necessitates the need for a port to
quickly change from an input to an output (and vice-vera), they have a modest dc-current "sourcing" capability of
hundreds of micro-Amps, as determined by the smart pullup resistor values.
The fall time (tfA, tfB) of a signal depends on the edge rate and output impedance of the external device driving
the SDIO I/Os, as well as the capacitive loading on these lines.
Similarly, the tpd and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tpd, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXS0206-29 SDIO output sees, so it is recommended that this lumped-load capacitance be
considered and kept below 50 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other
adverse system-level affects.
Copyright © 2009, Texas Instruments Incorporated
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TXS0206-29
SCES690 – DECEMBER 2009
www.ti.com
When using the TXS0206-29 device with MMCs, SD, and Memory Stick™ to ensure that a valid receiver input
voltage high (VIH) is achieved, the value of any pulldown resistors (external or internal to a memory card) must
not be >10-kΩ value. The impact of adding too heavy a pulldown resistor (i.e. <10-kΩ value) to the data and
command lines of the TXS0206-29 device and the resulting 4-kΩ pullup & 10-kΩ pulldown voltage divider
network has a direct impact on the VIH of the signal being sent into the memory card and its associated logic.
The resulting VIH voltage for the 10-kΩ pulldown resistor value would be:
VCC × 10 kΩ / (10 kΩ+ 4 kΩ) = 0.714 × VCC
This is marginally above a valid input high voltage for a 1.8-V signal (i.e., 0.65 × VCC).
The resulting VIH voltage for 20-kΩ pulldown resistor value would be:
VCC × 20 kΩ / (20 kΩ + 4 kΩ) = 0.833 × VCC
Which is above the valid input high voltage for a 1.8-V signal of 0.65 × VCC.
.
20
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Copyright © 2009, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
TXS0206-29YFPR
ACTIVE
DSBGA
YFP
Pins Package Eco Plan (2)
Qty
20
3000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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