® ADC-321 ® 8-Bit, 50MHz Video A/D Converter FEATURES • • • • • • • • • • Low power dissipation (180mW max.) Input signal bandwith (100MHz) Optional synchronized clamp function Low input capacitance (15pF typ.) +5V or +5V/+3.3V power supply operation Differential nonlinearity (±½LSB max.) Optional self-biased reference CMOS/TTL compatible inputs Outputs 3-state TTL compatible Surface mount package INPUT/OUTPUT CONNECTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GENERAL DESCRIPTION The ADC-321 is an 8-bit, high speed, monolithic CMOS, subranging A/D converter. The ADC-321 achieves a sampling rate comparable to flash converters by employing a sub-ranging technique which uses multiple comparator blocks each containing a sample-and-hold amplifier. The ADC-321 can operate with either a single +5V or dual +5V and +3.3V power source to allow easy interfacing with 3.3V logic. An optional synchronous clamp function useful for video signal processing is provided. The ADC-321 is well suited for the portable video signal processors due to its low 125mW typical power dissipation. The ADC-321 also features ±0.5 LSB max. differential non-linearity, a self bias function that can eliminate the need for external references, SNR with THD of 45dB, a small 32-pin QFP package and an operating temperature range of –40 to +85°C FUNCTION BIT 8 (LSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) TEST +DVS (Digital) TEST A/D CLOCK NO CONNECTION NO CONNECTION CLAMP IN (CLP) +AVS (Analog) PIN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 FUNCTION NO CONNECTION DIGITAL GROUND (DGND) OUTPUT ENABLE (OE) CLAMP ENABLE (CLE) DIGITAL GROUND (DGND) CLAMP CONTROL (COP) CLAMP REF. (VREF) REF. BOTTOM SENSE (VRBS) REF. BOTTOM (VRB) ANALOG GROUND (AGND) ANALOG GROUND (AGND) ANALOG IN (VIN) +AVS (Analog) +AVS (Analog) REF. TOP (VRT) REF. TOP SENSE (VRTS) 30 OUTPUT ENABLE +AVS 16 31 DGND VRTS 17 VRT 18 +AVS 19 Reference Supply +AVS 20 A A 4-Bit Lower Sampling Comparator 4-Bit Lower Encoder B B 4-Bit Upper Sampling Comparator 4-Bit Upper Encoder Lower Data Latch 1 BIT 8 (LSB) 2 BIT 7 3 BIT 6 4 BIT 5 VIN 21 AGND 22 AGND 23 Clock Generator VRB 24 Upper Data Latch 5 BIT 4 6 BIT 3 7 BIT 2 8 BIT 1 (MSB) VRBS 25 12 A/D CLOCK – VREF 26 + D-FF 15 CLAMP IN 9 DGND 28 TEST (Open) 10 +DVS CLAMP CONTROL 27 11 TEST (Open) CLAMP ENABLE 29 Figure 1. ADC-321 Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA.) • Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 • Email: [email protected] • Internet: www.datel.com ® ® ADC-321 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) PARAMETERS Power Supply Voltage (+AVS, +DVS) Analog Input Voltage, (VIN) Reference Input Voltage (VRT, VRB) Digital Input Voltage (VIH, VIL) Digital Output Voltage (VOH, VOL) DIGITAL OUTPUTS LIMITS UNITS –0.5 to 7 –0.5 to +AVS + 0.5 –0.5 to +AVS + 0.5 –0.5 to +AVS + 0.5 –0.5 to +DVS + 0.5 Volts Volts Volts Volts Volts Output Data Delay (OE = 0V, CL = 15pF) (@ +DVS = +5V) t PLH t PHL t PLH (@+DVS = +3.3V) t PHL 3-State Output Enable Time ➆ (RL = 1kΩ, CL = 15pF) t PZH (@ +DVS = +5V) t PZL t PZH (@+DVS = +3.3V) t PZL 3-State Output Disable Time ➇ (RL = 1kΩ, CL = 15pF) t PHZ, t PLZ (@+DVS = +5V) t PHZ, t PLZ (@+DVS = +3.3V) FUNCTIONAL SPECIFICATIONS Typical at TA = 25°C, VRT = +2.5V, VRB = +0.5V, +AVS = +5V, +DVS = +3V to +5.5V, FS = 50MHz unless otherwise specified. ANALOG INPUTS MIN. TYP. MAX. UNITS Input Voltage Range ➀ Input Capacitance (@ VIN = +1.5Vdc +0.07VRMS) Input Signal Bandwidth –1dB (@ RIN = 33Ω) –3dB (@ RIN = 33Ω) +0.5 — +2.5 Volts — 15 — pF — — 60 100 — — MHz MHz Clamp Offset Voltage ➈ Clamp Pulse Width ➉ DIGITAL OUTPUTS Output Current (OE = 0V) ➄ "1" (@ +DVS = +5V) "0" Output Current (OE = 0V) ➄ (@ +DVS = +3.3V) "1" "0" Output Current ➅ (@ OE = +3V) "1" "0" Capacitance — TYP. MAX. UNITS 5.5 5.5 4.3 4.3 9.5 8.5 11.8 7.6 12.0 12.0 16.3 16.3 ns ns ns ns 2.5 2.5 3.0 3.0 4.5 6.0 7.0 5.0 8.0 8.0 9.0 9.0 ns ns ns ns 3.5 2.5 5.5 5.5 7.5 8.0 ns ns 0 1.75 20 2.75 40 3.75 mV µA 8 50 — — — — — — — — — 0 ±0.7 ±0.3 3 1.5 — — 0.5 — ±1.5 ±0.5 — — Bit MHz MHz ns LSB LSB % deg — — — — — — 45 44 44 43 38 32 — — — — — — dB dB dB dB dB dB — — — — — — 51 46 49 46 45 45 — — — — — — dB dB dB dB dB dB +4.75 +3.0 0 +5.0 — — +5.25 +5.5 100 Volts Volts mW — — — — 25 23 2 125 36 33 3 180 mA mA mA mW PERFORMANCE 260 4.1 370 5.4 480 7.7 Ω mA — 0 1.7 — — — +2.7 — — Volts Volts Volts +0.52 1.80 — +0.56 1.92 — +0.60 2.04 11 Volts Volts pF –70 20 –50 40 –30 60 mV mV 2.2 — — — — +0.8 Volts Volts –240 –240 –40 — — — — — 240 40 240 11 µA µA µA pF 10 10 — — — — ns ns MIN. TYP. MAX. UNITS Resolution Sampling Rate, maximum, FS minimum, FS Aperature Delay (Tds) Integral Linearity Error Diff. Linearity Error Diff. Gain Error 11 Diff. Phase Error 11 S/N Ratio with THD (fIN = 100kHz) (fIN = 500kHz) (fIN = 1MHz) (fIN = 3MHz) (fIN = 10MHz) (fIN = 25MHz) Spurious Free Dynamic Range (fIN = 100kHz) (fIN = 500kHz) (fIN = 1MHz) (fIN = 3MHz) (fIN = 10MHz) (fIN = 25MHz) DIGITAL INPUTS Logic Levels ➂ Input Voltage "1" Input Voltage "0" Input Current ➃ A/D CLK CLP, CLE OE Input Capacitance A/D Clock Pulse Width (tpw1) (tpw0) MIN. CLAM CIRCUIT REFERENCE INPUTS Reference Resistance VRT – VRB Reference Current Reference Voltage VRT VRB VRT – VRB Self Bias Voltage ➁ VRB VRT – VRB Capacitance (VRT, VRTS, VRB, VRBS) Offset Voltage VRT VRB (continued) POWER REQUIREMENTS Power Supply +AVS +DVS |AGND – DGND| Power Supply Current 12 1. AIS, DIS (@ +DVS = +5V) 2. AIS DIS (@ +DVS = +3.3V) Power Dissipation — 4 — — –2 — mA mA — 2.4 — — –1.2 — mA mA ENVIRONMENTAL/PHYSICAL –40 –40 — — — 11 40 40 pF µA µA Operating Temp. Range, Case Storage Temperature Range Package Type Weight –40 –55 — +85 — +150 32-pin, plastic QFP 0.007 ounces (0.2 grams) °C °C Footnotes: ➀ ➁ ➂ ➃ ➄ See technical note 6 Pin 25 tied to AGND and pin 17 tied to +AVS +AVS = +4.75 to +5.25V and +DVS = 3 to +5.5V, full operating tem. range. VIL = 0V and VIH = +AVS, full operating temp. range VOH = +DVS–0.8V and VOL = +0.4V, full operating temp. range ➅ ➆ ➇ ➈ +DVS = +3 to +5.5V, full operating temp. range OE: +3 to 0V change OE: 0 to +3V change 2.75µs clamp pulse width, 14.3MHz sampling, 15.75kHz clamping rate 2 ➉ The clamp pulse width given is for NTSC. For other processing systems adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) to equal the value for NTSC. 11 NTSC 40IRE ramp, 14.3MHz sampling 12 50MHz sampling, +AVS = +5V ® ® ADC-321 TECHNICAL NOTES 1. The ADC-321 is a monolithic CMOS device. It should be handled carefully to prevent static charge pickup. 24) will then be +2.48V and +0.56V respectively. Under an application where this self bias function is used, the effects of temperature changes are minimal. Voltage changes of the +5V supply have direct influence on the performance of the device. The use of external references is recommended for applications sensitive to gain error, no ac signals can be used as references for this device. 2. It has separate power supply terminals +AVS (pins 16, 19 and 20) and +DVS (pin 10) for the internal analog and digital circuits. It is recommended that both +AVS and +DVS be powered from a single source Other external digital circuits must be powered with a separate +DVS. A time lag between the two power supplies could induce latch up when power is turned on if separate supplies are used. The operating range of +DVS is from +3.0V to +5.5V and it allows the use of a common power supply with 3.3V digital systems. The +3.3V power for +DVS in this case should be taken or derived from the +AVS supply to avoid latch up. No power supply terminal should be left open. 7. A voltage up to +AVS + 0.5V can be applied to each digital input even when +3.3V is powered to +DVS, but the digital output voltage never exceeds +DVS. 8. Layout A/D CLOCK pulse input (pin 12) as short as possible for minimum influence on other signals. Use of a 100 ohm series resistor is recommended to protect the device as there may be some voltage difference and turn-on-time lag on the power supplies. Analog inputs signals are sampled at the falling edge of an A/D CLOCK pulse and digital data become available at the rising edge of an A/D CLOCK pulse that is delayed by 2.5 clock cycles. The A/D CLOCK are positive pulse that have 50% duty cycle. The minimum clock pulse width is 10 nsec for both high and low levels. Keep it low level while A/D conversions are on hold. 3. The ADC-321 has separate grounds, the analog GND (pins 22 and 23) and digital GND (pins 28 and 31). Separate and substantial AGND and DGND ground planes are required. These grounds have to be connected to one earth point underneath the device. Digital returns should not flow through analog grounds. Connect all ground lines to the power point. 4. Bypass all power lines to GND with 0.1µF ceramic chip capacitors as close to the device as possible. This is very important. 9. Digital output is 3-state. To enable 3-state outputs connect the OUTPUT ENABLE (pin 30) to GND. To disable, connect it to +DVS. The output is recommended to be latched and buffered through output registers. The device may be damaged if a voltage higher than +DVS + 0.5V is given to digital output pins while at high impedance level. 5. Even though the analog input capacitance is a low 15pF, it is recommended that high frequency input be provided via a high-speed buffer amplifier. A parasitic oscillation may be generated when a high-speed amplifier is used. A 33 ohm resistor inserted between the output of an amplifier and the analog input of the ADC-321 will improve the situation. Kick back noise from A/D CLOCK pulses will be observed at the analog input terminal, but this has no influence on the ADC321 performance. 10. The 50MHz sampling rate is guaranteed. It is not recommended to use this device at sampling rates slower than 500kHz because the droop characteristics of the internal sample and hold exceed the limit required to maintain the specified accuracy of the device. Also, burst mode sampling is not recommended. 6. Apply +2.5V to VRT (pin 18, reference top) and 0.5V to VRB (pin 24 reference bottom) to obtain an analog input range of +0.5V to +2.5V. Conversion accuracy is dependent on stable reference voltages. Provide reference inputs via amplifiers that have enough driving power to avoid noise problems. Keep to the following equations; 0V ≤ VRB ≤ VRT ≤ +2.7V, 11. The ADC-321 has a clamp function. This clamp is enabled when CLAMP ENABLE (pin 29) is tied to GND and is disabled when tied to +DVS or left open. Clamp pulse inputs (pin 15) are effective when this clamp function is enabled and signals are clamped whole, this clamp pulse is low. The clamp reference input (pin 26) is set by an external trim. The CCP terminal (pin 27) integrates the clamp control voltage across an external capacitor. Refer to Figure 4 for examples of various ways to use this clamp function. | VRT – VRB | ≥ 1.7V The ADC-321 has a self bias function which allows the device to work without external references. Connect VRTS (pin 17, self bias top) to +AVS and VRBS (pin 25, self bias bottom) to the analog GND to obtain an analog input range of +0.56 to +2.48V. Typical voltages at VRT (pin 18) and VRB (pin 12. The TEST 1 and 2 (pins 9 and 11) are not used. Always leave them open. 3 ® ® ADC-321 THEORY OF OPERATION comparator block and the lower comparator A block. Input voltage N+1 is sampled with the falling edge of the second clock by means of the upper comparator block and lower comparator B block. The upper comparator block finalizes comparison data UD(N) with the rising edge of the second clock. The lower comparator block finalizes comparison data LD(N) with the rising edge of the third clock. UD(N) and LD(N) are combined and routed to the output as Output Data N with the rising edge of the fourth clock. Thus there is a 2.5 clock delay from the analog input sampling point to the digital data output. (See Functional Block Diagram, Figure 1, and Timing Diagrams, Figure 2) 1. The DATEL ADC-321 is a 2-step parallel A/D converter featuring a 4-bit upper comparator group and two 4-bit lower comparator groups, each with built-in sample and hold. A reference voltage equal to the voltage between (VRT – VRB)/16 is constantly applied to the 4-bit upper comparator block. A voltage corresponding to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins provde the self generation function for VRT (reference voltage top) and VRB (reference voltage bottom) voltages. Table 2: Digital Output Coding 2. This converter uses an offset cancelation type comparator and operates synchronously with the external clock. It features various operating modes which are shown in the Timing Diagram (Figure 2) by the symbols S, H and C. These characters stand for Input Sampling (Auto Zero) Mode, Input Hold Mode and Comparison Mode. 3. The operation of the respective parts is as indicated in Figure 2-3. For instance, input voltage N is sampled with the falling edge of the first clock by means of the upper tr = 4.5ns 0V +7.812mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +0.9922V +1.000V 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 +1.500V 1 1 0 0 0 0 0 0 +1.9922V 1 1 1 1 1 1 1 1 tr = 4.5ns 3V 90% OE INPUT OUTPUT CODE MSB LSB VIN 1.3V 10% tplz 0V tpzl VOH 1.3V OUTPUT 1 10% VOL /(=DGND) tpzh tphz VOH/(=DGND) 90% OUTPUT 2 1.3V VOL Figure 2-1. ADC-321 Timing Diagram tr = 4ns tf = 4ns 3V 90% CLOCK 1.3V 10% 0V DATA 0. 7 DV S OUTPUTS 0. 3 DV S tpLH tpHL Figure 2-2. ADC-321 Timing Diagram 4 ® ® ADC-321 Tds 0ns typ. N N+3 N+1 ANALOG SIGNAL N+2 TPW0 TPW1 10ns min. 10ns min. CLOCK 1.3V TPLH TPHL DATA OUTPUTS N–3 N–2 N–1 N 1 UPPER SAMPLING COMPARTOR S (N) C (N) S (N+1) S (N+2) C (N+2) C (N+1) S (N+3) C (N+3) 1 UPPER OUTPUT DATA UD (N–1) UD (N) UD (N+1) UD (N+2) 1 LOWER SAMPLING COMPARTOR 1 S (N) H (N) C (N) S (N+2) H (N+2) C (N+2) 1 LOWER OUTPUT DATA 1 LD (N–2) LD (N) 1 LOWER SAMPLING COMPARTOR 2 H (N–1) C (N–1) S (N+1) H (N+1) C (N+1) S (N+3) H (N+3) 1 LOWER OUTPUT DATA 2 LD (N–3) LD (N–1) LD (N+1) S = Sample Mode, H = Hold Mode, C = Comparate Mode 1 Internal Operation of the ADC-321 Figure 2-3. ADC-321 Timing Diagram A/D CLOCK +5V (A) 0.1µF 0.1µF 0.1µF +12V +5V (A) +5V (D) 10µH +12V 16 500 47µF 500 0.1µF 100 0.1µF 0.1µF 47µF 74HC04 15 47µF 14 13 12 11 10 9 17 8 BIT 1 (MSB) 18 7 BIT 2 19 6 BIT 3 0.1µF 0.1µF 10µF 20 5 BIT 4 21 4 BIT 5 22 3 BIT 6 23 2 BIT 7 1 BIT 8 (LSB) ADC-321 0.1µF 180 ANALOG IN 33 500 10pF 5k 470µF 1k 120 2k 0.1µF 24 –12V +12V 47µF 0.1µF 25 26 27 28 –12V 1k 1k 10µH 5V 500 Figure 3. Typical Connection Diagram 5 29 30 31 32 ® ® ADC-321 CLAMP PULSE +5V (A) +5V (A) A/D CLOCK +5V (D) A/D CLOCK +5V (D) 16 15 14 13 12 11 16 15 9 10 8 17 VRT 10 9 7 19 6 20 5 21 4 22 3 2 19 6 20 5 21 4 22 3 23 2 23 24 1 24 33 12 11 8 7 ANALOG IN 13 18 18 ANALOG IN 14 17 33 10pF 25 26 27 28 29 30 10µF 32 31 10pF 1 25 26 VRB 27 28 29 30 31 32 +5V (A) 20k Figure 4-1. Clamp Not Used in Self Bias Mode 0.01µF Figure 4-2. Clamp Used in External Reference Mode CLAMP PULSE A/D CLOCK +5V (D) 16 15 ANALOG IN 10µF 14 13 12 11 8 18 7 19 6 20 5 21 4 22 3 23 +5V (A) ANALOG IN 10µF 27 28 29 30 12 11 10 9 8 18 7 19 6 20 5 21 4 10pF 22 3 23 2 Clamp Level Data 1 25 26 32 31 13 24 1 25 26 14 17 33 2 24 +5V (D) 16 15 9 10 17 33 10pF A/D CLOCK +5V (A) Comparator +5V (A) 27 28 29 30 31 32 D/A 20k 0.01µF 0.01µF Figure 4-3. Clamp Used in Self Bias Mode Figure 4-4. Digital Clamp Used in Self Bias Mode CLAMP PULSE +5V (A) A/D CLOCK +3.3V (D) 16 15 14 13 12 11 10 9 17 8 18 7 19 6 20 5 21 4 22 3 23 2 ANALOG IN 33 10µF 10pF +5V (A) 20k 24 1 25 26 27 28 29 30 31 32 0.01µF Figure 4-5. Clamp Used in Self Bias Mode With +5V/+3.3V Dual Power Supply 6 ® ® ADC-321 Ambient Temperature vs. Sampling Delay Analog Input Bandwidth Analog Input Frequency vs. S/N + THD, Effective Bit FS = 50MHz AVS = DVS = 5V VIN = 2Vp-p TA = 25°C –1 –1 FS = 50MHz Sine wave 1Vp-p input AVS = DVS +5V TA = 25°C –2 0.1 0 +25 +50 +75 Ambient Temperature (°C) 50 FS = 50MHz AVS = DVS = 5V VIN = 2Vp-p TA = 25°C 30 12 10 tplh 8 tphl –20 tplh –20 FS = 50MHz AVS = DVS +5V C L = 15pF 8 tphl 6 0 5 24 Supply Current (mA) 25 4.75 1 Max. Sampling Rate (MHz) 10 Input Frequency (MHz) 5 Supply Voltage (V) tplh 10 8 tphl 6 3 25 20 AVS = DVS = +5V 15 10 60 0 25 50 75 Ambient Temperature (°C) Figure 5: Typical Performance Curves 7 20 30 40 50 Sampling Frequency (MHz) Supply Voltage vs. Sampling Rate 65 –20 3.5 4.5 5 5.5 Ambient Temperature (°C) 25 5.25 FS = 50MHz fin = 1kHz, triangular wave input AVS = DVS +5V 70 FS = 10MHz +AVS = +5V TA = 25°C Sampling Rate vs. Supply Current FS = 50MHz AVS = DVS TA = 25°C 23 0 +25 +50 +75 Ambient Temperature (°C) 12 Ambient Temperature vs. Max. Sampling Rate FS = 50MHz Sine wave 1.9Vp-p AVS = DVS = +5V TA = 25°C 0.1 –20 25 25 0 +25 +50 +75 Ambient Temperature (°C) 25 0.01 20 27 Input Frequency vs. Supply Current 30 15 FS = 50MHz AVS = DVS +5V CL = 15pF 6 Supply Voltage vs. Supply Current FS = 50MHz AVS = DVS = +5V 35 10 tphl Load Capacitance (pF) Ambient Temperature vs. Supply Current –20 FS = 10MHz AVS = +5V DVS = +3.3V TA = 25°C tplh 10 0 +25 +50 +75 Load Capacitance (pF) 26 8 Ambient Temperature vs. Output Data Delay 14 12 tplh 10 0 +25 +50 +75 Ambient Temperature (°C) Output Data Delay (ns) 10 Output Data Delay (ns) 12 6 12 Load Capacitance vs. Output Data Delay Load Capacitance vs. Output Data Delay tphl FS = 50MHz AVS = DVS +5V CL = 15pF 6 0.1 1 0.01 10 Analog Input Frequency (MHz) 8 Ambient Temperature vs. Output Data Delay Supply Current (mA) 30 1 0.1 0.01 10 Analog Input Frequency (MHz) 0.1 10 100 Analog Input Frequency (MHz) Sampling Rate (MHz) 40 Output Data Delay (ns) FSDR (dB) 5 40 Ambient Temperature vs. Output Data Delay 60 Output Data Delay (ns) 6 Output Data Delay (ns) Analog Input Frequency vs. FSDR Supply Current (mA) 7 –3 –20 Supply Current (mA) 50 8 SNR (dB) 0 Effective Bit (dB) 1 Output Level (dB) Sampling Delay (ns) 0 FS = 50MHz AVS = DVS = 5V 67 65 AVS = DVS 63 4.75 5 Supply Voltage (V) 5.25 ® ® ADC-321 DIGITAL OUTPUT ANALOG INPUT REFERENCE INPUT +AVS +DVS +AVS VRTS 1 to 8 V RB 21 V RT 24 25 VRBS Rref RB DGND A/D CLOCK CLAMP REFERENCE VOLTAGE INPUT (VREF) +AVS 12 CLAMP CONTROL VOLTAGE (CCP) OUTPUT ENABLE (OE) +AVS +AVS 28 AGND AGND AGND CLAMP PULSE INPUT (CLP) CLAMP ENABLE (CLE) +AVS 27 +AVS 15 29 30 AGND AGND AGND AGND Figure 6: Equivalent Circuits 0.35 ±0.008 (9.0 ±0.2) MECHANNICAL DIMENSIONS INCHES (mm) 0.280 ±0.008 (7.1 ±0.2) 24 17 25 16 32 9 8 1 0.03 (0.8) 0.012 ±0.005 (0.03 –0.1, +0.15) 0.02 (0.5) 0.039 ±0.010 (1.5 ±0.35) 0.315 (8.0) 0.006 ±0.006 (0.15 ±0.15) 0 to 10° 0.006 ±0.003 (0.152 ±0.075) ORDERING INFORMATION ADC-321 8-bit, 50MHz A/D converter ISO 9001 R E G I S T E R E D DS-0359 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com Email: [email protected] Data sheet fax back: (508) 261-2857 DATEL DATEL DATEL DATEL 6/98 (UK) LTD. Tadley, England Tel: (01256)-880444 S.A.R.L. Montigny Le Bretonneux, France Tel: 01-34-60-01-01 GmbH Munchen, Germany Tel: 89-544334-0 KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.