ETC AHA4012B

Product Specification
AHA4012B
1.5 MBytes/sec Reed-Solomon
Error Correction Device
Advanced Hardware
Architectures, Inc.
2365 NE Hopkins Court
Pullman, WA 99163-5601
509.334.1000
Fax: 509.334.9000
e-mail: sales@aha.com
http://www.aha.com
TM
Advanced Hardware
Architectures
The Data Coding Leader
PS4012B-0100
Advanced Hardware Architectures, Inc.
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Conventions, Notations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2.1 Definition of Correction Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Correcting Capability and Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.5 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5.1 Shortened Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6 Reset and Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.6.1 Initialization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.7 Encode, Decode or Pass-through Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.8 Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9 Data Rate and Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.9.1 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.9.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.10 Reed-Solomon (ECC) Module and Error Rate Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.11 Determining Decoder Performance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.12 Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.0 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.0 Signal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Input Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 AC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5.0 Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Available Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Part Numbering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PS4012B-0100
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Advanced Hardware Architectures, Inc.
Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
ii
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Applications Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Input and Output Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Burst and Continuous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes . . . . . . . . . . . . . . . . 11
CLK Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset and Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Input - Input Buffer Always Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Data Input - Buffer Not Ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CRTN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PS4012B-0100
Advanced Hardware Architectures, Inc.
Tables
Table 1:
Table 2:
Table 3:
Table 4:
Initialization Register Settings for Encode, Decode and Pass-Through Operations . . . . . . . . . . . . . . . . . 7
Burst Operation Using 6 MHz Clock and 1 Clock/Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Continuous Operation Using 6 MHz Clock and Specified Clocks/Byte. . . . . . . . . . . . . . . . . . . . . . . . . .10
Continuous Operation for IESS-308 Codes Using 6 MHz Clock and Specified Clocks/Byte . . . . . . . . . 10
PS4012B-0100
iii
Advanced Hardware Architectures, Inc.
1.0
INTRODUCTION
The AHA4012B is a single chip integrated
circuit that implements a Reed-Solomon Forward
Error Correction algorithm. The AHA4012B is the
lowest cost member of the AHA PerFEC family
of forward error correction (FEC) devices
conforming to the Intelsat IESS-308 specification.
Data flow through the device can occur in bursts at
6 MBytes per second or continuous at 1.5 MBytes
per second maximum.
The device supports several programmable
parameters, including; block size, error threshold,
number of check bytes and mode of operations.
Shortened blocks are supported without requirement of zero padding. The data input port is used to
initialize the programmable parameters and the two
on-chip buffers are used to input and output data.
Discontinuities in data flow may be controlled by
dedicated control pins.
High operating frequency, input and output data
rate flexibility, low processing latency and various
programmable parameters make this device ideal
for many applications including: DTV, DBS,
ADSL, Satellite Communications, ISDN, High
Performance Modems and networks.
This specification provides full electrical and
mechanical information to help a system engineer
develop a system using AHA4012B. This document
contains descriptions on correction terms, pinout,
functions and features, DC and AC characteristics,
package and mechanical specifications, ordering
information and Related Technical Publications.
Software simulation of the RS code as implemented
in the device is also available. Please contact AHA
or its authorized sales representatives worldwide for
copies of Related Technical Publications and
software simulation.
1.1
FEATURES
PERFORMANCE:
• Polynomial complies to Intelsat IESS-308;
RTCA DO-217 Appendix F, Revision D and
proposed ITU-TS SG-18 (Formerly CCITT SG18) Standards
• 6 MBytes/sec burst transfer rate with a 6 MHz
clock for all block lengths
• Maximum channel rate of 1.5 MBytes/sec
continuous for block lengths from 54 bytes
through 255 bytes using a 6 MHz clock
• Processing latency time less than 101 µsec in
continuous operation for block lengths of 100
bytes
PS4012B-0100
FLEXIBILITY:
• Programmable to correct from 1 to 10 error bytes
or 20 erasure bytes per block
• Block lengths programmable from 3 to 255 bytes
• Encode, decode or pass-through capability inline with data flow
• Continuous or burst mode operation
• Programmable error threshold to help determine
channel performance
SYSTEM INTERFACE:
• Byte wide synchronous I/O ports with internal
buffering on both ports
• Input data pins used for programmable
parameters
• Dedicated control pins permit discontinuities in
system data flow
OTHERS:
• 44 pin PLCC; 50 mil lead pitch
• Pin and plug compatible with the higher
performance AHA4011
• Software emulation of the algorithm available
1.2
CONVENTIONS, NOTATIONS AND
DEFINITIONS
– Certain signals are logically true at a voltage
defined as “low” in the data sheet. All such signals
have an “N” appended to the end of the signal
name. For example, RSTN and DSON.
– “Signal assertion” means the output signal is
logically true.
– Hex values are defined with a prefix of “0x”, such
as “0x10”.
– A range of signal names is denoted by a set of
colons between the numbers. Most significant bit
is always shown first, followed by least significant
bit. For example, DI[7:0] represents Data Input
Bus 7 through 0.
– A product of two variables is expressed with an
“×”, for example, N × Ci represents Codeword
Length multiplied by Input clocks/byte.
– Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
– Channel Rate is defined as transfer rate including
user data and error correction check bytes.
Page 1 of 24
Advanced Hardware Architectures, Inc.
1.2.1
DEFINITION OF CORRECTION TERMS
NAME
TERM
K
R
N
t
P
e
E
G
(other references)
RANGE
DEFINITION
(number of bytes)
Number of user data symbols in one message block.
Message Length
Size of a symbol in AHA4012B is 8-bits. Message
(user data or message
length is K = N − R. The first message byte is
bytes)
referred to as XK−1; the last message byte is X0.
Symbols appended to the user data to detect and
correct errors. The number of check symbols
Check symbols
required in a system is R ≤ E + 2e.* The first check
(parity or redundancy)
symbol is referred to as YR−1; the last check symbol
is Y0.
Codeword Length
Sum of message and check symbols. N = K + R.
(block length)
Maximum number of error corrections performed
Error Corrections
N – K- .
by the device. The value is t = Integer ------------2
The threshold limit to determine uncorrectability
of a Codeword and the number of check bytes
Error Threshold
allocated for correction-only purposes (not for
detection).
An error is defined as an erroneous byte whose
Number of Errors
correct value and position within the message
block are both unknown.
An erasure is defined as an error whose position is
Number of Erasures
known within the message block.**
A measure of the burden of correction being placed
Burden of Correction on the capabilities of the device for that message
block. The value G = 2e + E.
1 through 253
(1, 2, 3, 4 . . . 253)
2 through 20 in
increments of 1
(2, 3, 4 . . . 20)
3 through 255
(3, 4, 5, 6 . . . 255)
1 through 10
(1, 2, 3 . . . 10)
2 through 20
(2, 3, 4 . . . 20)
0 through N
0 through N
0 through R
*
**
For every 2 check bytes, the AHA4012B can correct either 2 erasures or 1 error.
An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is
indicated by asserting the ERASE signal when the erased byte is clocked into the AHA4012B.
2.0
FUNCTIONAL DESCRIPTION
This section describes an architectural
overview of the chip and its many functions,
features and operating modes. The block diagram
for the chip shows the Reed-Solomon ECC module,
the Input and Output Buffers and their associated
control. All input and output data are clocked on the
rising edge of CLK.
Page 2 of 24
2.1
FUNCTIONAL OVERVIEW
The AHA4012B Reed-Solomon codec (coder/
decoder) is the lowest cost member of the AHA
PerFECTM family of forward error correction (FEC)
devices. This single chip, three-layer metal, CMOS
device can operate in encode, decode or passthrough modes.
The ECC core implements a full error
correcting Reed-Solomon decoder. This code is
capable of correcting up to 10 (t = 10) byte-errors or
20 (t = 10) erasures in a block.
PS4012B-0100
Advanced Hardware Architectures, Inc.
The ECC core has three phases of operation:
Data In, Calculation and Data Out. Data to be
processed is first input into a single ported Input
Buffer using a control signal DSIN. ECC core
arbitrates for the input data out of the Input Buffer.
ECC core has access to the Input Buffer on clock
edges where DSIN is not asserted.
Each block is processed within the ECC core
and calculations are made. The entire block is
processed through the ECC core and transferred
into the Output Buffer. The device asserts RDYON
signal and holds active until the Output Buffer is
completely emptied.
The ECC core loads the Output Buffer in
reverse order for either mode. Data is strobed out of
the device in forward order.
The use of internal buffers is restricted per the
rules defined in Section 2.9 Data Rate and
Latencies.
Maximum delay required for each block of a
given length to pass through the device is fixed and
does not vary with the location or the number of
errors received. This delay (or latency), expressed
in the number of clocks is discussed in a later
section.
2.2
For every 2 check bytes, the decoder corrects
either 2 erasures or 1 error. An erasure can be
determined with a parity detector or a signal dropout
detector external to the chip. An erasure is indicated
by the ERASE signal when the erased byte is
clocked into the device.
Correcting “erasures” takes only half as much
of the correction capability of the RS code as it takes
to correct “errors”, since the position information is
already known for “erasures”. The correction ability
of the code is bounded as:
R ≥ # erasures + 2 ( # errors )
Valid block length (N) is defined by the
relationship:
R + 1 ≤ N ≤ 255
where R ranges from 2 to 20.
A complete codeword can therefore range from
a minimum of 3 to a maximum of 255 bytes.
For further discussion on error rate
performance, refer to Section 2.10 Reed-Solomon
(ECC) Module and Error Rate Performance.
Figure 1:
CORRECTING CAPABILITY AND
POLYNOMIALS
Compared with other codes, RS codes require
relatively few “overhead” check bytes to be added
to the data stream to achieve a high degree of error
detection and correction. Since the AHA4012B
deals with bytes (or symbols) rather than with
individual bits, when a byte is in error it does not
matter how many bits within the byte are corrupted;
it is counted as one error.
The Reed-Solomon code is defined over the
finite field GF(28). The field defining primitive
polynomial is:
8
7
Block Diagram
RDYIN
ERASE DI[7:0]
CLK
RDYIN
DI
CLK
REGISTER
INPUT BUFFER
367x9
RSTN
RSTN
DSIN
DSIN
DSON
DSON
CONTROL
GND
GND
VDD
VDD
ECC CORE
2
P( x ) = x + x + x + x + 1
OUTPUT BUFFER
and the generator polynomial, dependent on the
variable R, is given by:
256x9
119 + R
G( x ) =
∏
i
(x – α )
REGISTER
i = 120
where R {2, 3, 4, 5, . . . 20} for the AHA4012B.
This polynomial is specified in international
standards, Intelsat IESS-308; RTCA DO-217
Appendix F, Revision D and the proposed ITU-TS
SG-18 (Formerly CCITT SG-18).
PS4012B-0100
RDYON
CRTN
DO
RDYON
CRTN
DO[7:0] ERR
A typical system block diagram is shown in the
following figure.
Page 3 of 24
Advanced Hardware Architectures, Inc.
Figure 2:
Typical Applications Diagram
ENCODER
8
DATA SOURCE
A
COMMUNICATIONS
AHA4012B
ECC COPROCESSOR
8
B
CHANNEL
1 TO x BITS WIDE
DECODER
8
AHA4012B
ECC COPROCESSOR
8
DATA SINK
C
BLOCK FORMAT AT:
SYSTEM
CONTROLLER
2.3
A KDATA PLUS R “DUMMY” BYTES
B KDATA PLUS R CHECK BYTES
C KDATA BYTES
SYSTEM
CONTROLLER
SIGNAL DESCRIPTIONS
Input Pins
Output Pins
DI[7:0] Data Input Bus. The input byte and ERASE
are latched on the rising edge of the clock
when both DSIN and RDYIN are active. If
either DSIN or RDYIN are inactive, the DI
and ERASE are ignored.
DSIN Data Input Strobe. Enables data from DI to
be loaded into the chip. When RDYIN is
active, DSIN being active on the rising
edge of the clock loads the input data in the
device. DSIN must be active for one clock
edge only per each input byte. DSIN is
ignored if RDYIN is inactive. Signal is
active low.
DSON Data Output Strobe. This input strobe
acknowledges to the chip that data
available on the Output Bus, DO, has been
received by the system. The device uses
this strobe to increment its internal address
counter to the next data location. DSON
must be active for one clock edge only per
each output byte. DSON is ignored if
RDYON is inactive. Active low.
ERASE Erasure input flag for symbol currently on
DI. Signal is active high. ERASE signal is
used for marking all check Bytes as
erasures (dummy check Bytes) during
encode operation. It is also used to mark
input symbols that contain errors during
decoding. If not used, connect this signal to
ground.
RSTN Reset. Input pin. When RSTN is active and
DSIN and DSON are inactive, the device
forces all internal control circuitry into a
known state and initializes all data path
elements. RSTN is active during
Initialization Phase. In this phase, chip
parameters are programmed by using DI
and DSIN. Signal is active low.
CLK Clock. System clock input. Refer to
Section 4.4 AC Electrical Characteristics
for clock requirements.
RDYIN Ready Input. Indicates the chip's ability to
accept data input on DI. If active, DSIN is
allowed to enable the loading of input data
on DI. When inactive, DSIN is ignored.
Signal is active low.
DO[7:0] Data Output. The output byte is available
on this bus. The value of the output byte is
undefined if RDYON is inactive. Requires
an acknowledge strobe, DSON, at a rising
edge of the clock to increment internal
address counter and output the next
location in the buffer. DO bus is always
driven and is not tristated by the device.
RDYON Ready Output. This output pin indicates the
chip's ability to generate output data. If
active, DSON is allowed to increment the
internal address counter for the next data
byte. When inactive DSON is ignored and
DO is undefined. Signal is active low.
CRTN Correctable. The output pin when active
indicates the block did not exceed the error
threshold programmed by P. Error
threshold must be programmed with the
same value as the number of check symbols
R if erasures are not used. This signal is
valid when the first message byte, XK−1, of
the block is available out of the chip.
During all other times the signal is
undefined. Signal is valid for at least one
clock. Active low.
ERR Error. Output pin indicates the current
value on DO[7:0] is a corrected byte.
Active high.
Page 4 of 24
PS4012B-0100
Advanced Hardware Architectures, Inc.
2.4
PINOUT
Figure 3:
Pinout
6
5
4
3
2
1
44
43
42
41
40
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DISN
CLK
GND
INPUT
7
8
9
10
11
12
13
14
15
16
17
TM
AHA4012B-006 PJC
39
38
37
36
35
34
33
32
31
30
29
VDD
VDD
GND
VDD
RSTN
ERASE
DSON
RDYIN
RDYON
GND
GND
DO0
DO1
DO2
DO3
DO4
DO5
DO6
VDD
DO7
ERR
CRTN
18
19
20
21
22
23
24
25
26
27
28
VDD
GND
VDD
GND
GND
VDD
*NC
*NC
VDD
GND
GND
OUTPUT
*NC = No connect, reserved for future considerations.
2.5
2.5.1
DATA FLOW
The device is first initialized for various
programmable parameters including: Erasure
Multiplier, Error Threshold, Number of Check
bytes, Number of Message bytes per block, Block
Length and a Control byte. Following this six-byte
initialization, the device may be used to encode,
decode or pass-through multiple blocks of data. The
Figure 4:
device requires reinitialization only when the
parameters are changed or a reset is required.
The device processes data as “blocks”
containing Message and Check Bytes. Order of
input bytes must be first message byte XK−1 through
last message byte X0, followed by first check byte
YR−1 through last check byte Y0. The device
contains an internal counter to keep track of start
and end of block. No external signal is required to
indicate start and end of block. The device processes
the block in this manner:
- a block is clocked into the Input Buffer;
- transferred into the ECC module;
- passed to the Output Buffer in the reverse order
from what was received at the Input Port; and
- clocked out through the Output Port via the
Output Buffer. Consecutive blocks may be
input into the Input Buffer while the Output
Buffer is being emptied.
Data is available through the Output Port in
forward order. Data is clocked out in the same order
as it is input.
SHORTENED BLOCKS
This device allows for shortened RS blocks,
thus not requiring zero padding when decoding.
During encoding, converseley, zero padding is not
performed. When the device is programmed to
decode a block of less than 244 Bytes, only the
message Bytes followed by check Bytes are sent.
Prepending with zero value Bytes to fill out the
block to 255 Bytes is not required.
Data Input and Output Order
Y0 Y1 . . . YR-2 YR-1 X 0 X 1 . . . X K-2 X K-1
Last
Byte
In
First
Byte
In
INPUT
BUFFER
ECC
Core
OUTPUT
BUFFER
Data Available
Forward Order
Last Byte Out
First Byte Out
PS4012B-0100
Y0
..
.
YR-1
X0
..
.
X K-1
Page 5 of 24
Advanced Hardware Architectures, Inc.
2.6
RESET AND INITIALIZATION
SEQUENCE
Reset and initialization first requires pulling the
RSTN low signal for at least two clocks while the
DSIN and DSON signals are held inactive, i.e.,
high.
Following this sequence, the six internal
registers, referred to as “Initialization Registers” are
strobed by DSIN. These bytes are loaded in order of
1 through 6.
The RSTN must be active low for at least two
clocks before the first initialization byte is strobed
in and remain active for at least one clock after the
final byte. RSTN must be high for at least two
clocks before the first message byte can be strobed
into the device. For a detailed timing diagram, see
Figure 8: Reset and Initialization Timing.
The chip must be reset and initialized any time
a reset is necessary.
Caveat: All six registers must be initialized
correctly for proper operation of the chip. The
device has no provisions for reading back
Initialization Register settings. This sequence must
be used if the device needs to be reset or any one
register needs updating, i.e., all registers must be
reinitialized for a change to any one register.
2.6.1
INITIALIZATION REGISTERS
BYTE 1, ERASURE MULTIPLIER:
[7:0] Multiplier value that must be programmed
as shown in Appendix A. The table shows a
value to be programmed corresponding to
the block length selected.
BYTE 2, ERROR THRESHOLD:
[4:0] The threshold for determining
uncorrectability of a data block, and the
number of check bytes allocated for
correction-only purposes. When not using
erasures set to the same value as BYTE 3,
CHECK BYTES. Minimum value of 0x02
sets the Threshold to 2 and 0x14 sets to the
maximum, 20.
[6:5] Reserved. Set to 0.
[7]
Not used. Don't care.
BYTE 3, CHECK BYTES:
[4:0] Number of check bytes in RS code, R.
Minimum setting of 0x02 indicates two
check bytes for R = 2 and 0x14 indicates the
maximum of 20.
[6:5] Reserved. Set to 0.
[7]
Not used. Don't care.
Page 6 of 24
BYTE 4, MESSAGE BYTES:
[7:0] Number of message bytes in code, K.
Minimum setting of 0x01 indicates 1 byte,
setting to 0xFD indicates the maximum 253
message bytes.
BYTE 5, BLOCK LENGTH:
[7:0] Number of bytes in block, N. Setting to
0x03 indicates 3 bytes, setting to 0xFF
indicates 255 bytes.
BYTE 6, CONTROL BYTE:
[0]
RES
Reserved. Set to 0.
[1]
NOPAR
Parity Symbol Control
When set to 0, check bytes are
output following the message
bytes.
When set to 1, check bytes are
not output following the
message bytes. Correction will
be done regardless depending
upon the bit 4, RAW, setting.
[3:2] RES
Reserved. Set both bits t o1.
[4]
RAW
Raw Data
When set to 0, outputs
corrected data.
When set to 1, outputs raw
uncorrected input data.
[5]
ERC
Erasure Rejection Control.
This bit is only used by the
device when the Erasures
exceed the ERROR
THRESHOLD or R settings.
This bit is ignored when the
Erasures are less than or equal
to ERROR THRESHOLD
or R.
When set to 0, if Erasures are
greater than the ERROR
THRESHOLD or R then
erasures are discarded and full
correction is performed. The
block is flagged uncorrectable
and the output CRTN will be
high during the first message
byte of the block.
When set to 1, if Erasures are
greater than ERROR
THRESHOLD or R then
erasures are discarded and full
correction is performed. The
output CRTN will be high only
when the block is
uncorrectable.
[7:6] Reserved, Set to 0.
PS4012B-0100
Advanced Hardware Architectures, Inc.
2.7
ENCODE, DECODE OR PASS-THROUGH OPERATIONS
The device performs three functions: encoding, decoding and pass-through. As an encoder the device
outputs the message block followed by “corrected” check bytes. As a decoder, the device outputs the
corrected message bytes with or without check bytes following the message. In pass-through operation, the
device passes the input data as it is received. In all three operations, the input block flows through the Input
Buffer into the ECC module and out of the Output Buffer. Latencies for all three operations are the same.
The device is initialized for the three operations as shown in the table below.
Table 1:
Initialization Register Settings for Encode, Decode and Pass-Through Operations
INITIALIZATION REGISTER
ERASURE MULTIPLIER
ERROR THRESHOLD
CHECK BYTES
MESSAGE BYTES
BLOCK LENGTH
CONTROL BYTE
BIT(S)
[7:0]
[7:0]
[7:0]
Appendix A Value
Set to R
Set to R
Set to the Number
[7:0]
of Message Bytes
in block, K
Set to the total of
[7:0]
Message and
Check bytes, N
[7:6] Reserved 0
5(ERC)
0
4(RAW)
0
[3:2] Reserved 1
1(NOPAR) 0
0(RESV)
0
As an encoder, the device is used with the
Erasures feature enabled in the following sequence.
(Asserting the ERASE signal high enables the
Erasure feature.)
1) After initialization, the device receives the
message data followed by “dummy” check
bytes. “Dummy” check bytes are clocked
into the device with the ERASE signal
asserted. The number of “dummy” check
bytes must equal R.
2) The ECC core processes the block by
“correcting” the check bytes and feeding
the codeword into the Output Buffer in
reverse order.
3) The block is then made available on the
output bus, DO. The state of the output
RDYON determines the availability of
data. ERR signal is asserted while the
“corrected check bytes” are output on the
output bus, DO. CRTN is asserted low
during the first message byte out of the chip
indicating that the block did not exceed the
error threshold.
PS4012B-0100
ENCODE
DECODE
PASS-THROUGH
Appendix A Value Appendix A Value
R or less
R
R
R
K
K
N
N
0
0
0
1
System specific
0
0
0
1
1
0
0
As a decoder, the device works similar to the
encode operation in the following sequence.
1) Following initialization, the system clocks
the message data and the check bytes into
the Input Buffer. ERASE signal may be
asserted as desired by the system. State of
the output signal, RDYIN determines the
chip’s ability to accept data input on the DI
bus.
2) The ECC Core processes the block by
performing necessary corrections and feeds
the codeword into the Output Buffer in
reverse order.
3) The data is available on the output port. The
state of the output signal, RDYON
determines the availability of valid data. An
output byte which has been corrected is
indicated by the device asserting ERR.
CRTN may be high or low depending upon
the THRESHOLD Register and ERC bit
programmed and the errors encountered.
Page 7 of 24
Advanced Hardware Architectures, Inc.
In pass-through operation, data flows through
the device similar to the Encode and Decode
operations. During initialization the device is
programmed as shown above. Check Bytes are
programmed in the range of 0x02 to 0x14.5. The
Block length here is the sum of message Bytes and
Check Bytes like encode and decode modes of
operation even though the device passes through the
blocks of data unchanged.
1) Following initialization, the system clocks
the codeword into the Input Buffer.
2) The codeword is processed by the ECC
module and passed on to the Output Buffer
without correction.
3) The uncorrected codeword is available at
the output port. State of the RDYON
determines the availability of valid data.
The ERASE input is ignored during the
Input phase and ERR and CRTN outputs
are not valid.
Caveat: The device has no provisions for indicating
the start and/or end of message or check bytes. It is
the system designers responsibility to keep track of
message and check bytes transitions, if required.
2.8
BUFFERS
The Input Port contains a single-ported 367x9
buffer. The Output Port contains a single-ported
256x9 buffer. These buffers store input and output
data during the correction process and help maintain
the desired system data rate. The buffers support the
ECC module during its operation phases: Data in,
Calculation and Data out. A Reset operation as
described in Section 2.6 Reset and Initialization
Sequence clears the buffers.
The use of internal buffers is restricted per the
rules defined in Section 2.9 Data Rate and
Latencies. These rules define the limitations of
using the buffers to temporarily store more than one
block. It is highly recommended that the system
designer clearly understand these rules prior to
designing the system.
The Input Buffer receives input data on the DI
bus when the ECC module is in the calculation or in
data-in phases at the desired system rate. The ability
of the Input Buffer to accept data is indicated by
RDYIN.
The Output Buffer accepts corrected data from
the ECC during the data-out phase. Corrections are
placed in the buffer at 1 clock per byte by the ECC
module to be removed by the system at its desired
rate. RDYON is asserted low when the Output
Buffer is able to output data.
Page 8 of 24
2.9
DATA RATE AND LATENCIES
This section describes data rates and processing
latencies for burst and continuous operations.
Processing latencies are the same in encode, decode
or pass-through mode operations.
The input and output rates need not be the same
for burst and continuous operations. No registers are
required to program the device for either operation.
Continuous block flow is achieved by using the
appropriate number of clocks per byte and block
length. Alternatively, data flow into and out of the
device is controlled using control signals, DSIN and
DSON.
2.9.1
BURST OPERATION
Maximum processing latency, in forward order,
expressed in number of clocks, for burst operation is
determined by: N × Ci + R + 60 + N
Definitions:
Ci = input clock rate per byte. If Ci=1, use a value
for Ci of 2 in the latency equation.
N = block length
R = number of check bytes
Processing Latency = Delay from first input byte to
first output byte
For a 6 MHz system using 1 clock per byte,
latencies and data rates are shown in the table for
burst operation. Input and Output Burst Rates in all
cases will be 6 MBytes/sec. Note: Other frequency
operations may be derived similarly.
Output Buffer may be used to hold data from
one block while the Input Buffer is being filled with
the following block. Two rules listed in the caveats
are required to accomplish this. These are illustrated
in Figure 5: Burst and Continuous Operations.
Caveats:
1. Output of block i must start coincident with or
before the input of block i + 1.
2. Output of block i must be complete:
Processing Latency − N − 8 clocks after the
start of block i + l on the input.
PS4012B-0100
Advanced Hardware Architectures, Inc.
Table 2:
Burst Operation Using 6 MHz Clock and 1 Clock/Byte
CHECK BYTES ‘R’ = 20
CHECK BYTES ‘R’ = 2
MAXIMUM MAXIMUM AVERAGE
MAXIMUM
MAXIMUM
AVERAGE
BLOCK
RATE
LATENCY
LATENCY
RATE
LATENCY
LATENCY
LENGTHS ‘N’
(# of clocks)
(µsecs) (MBytes/sec) (# of clocks)
(µsecs)
(MBytes/sec)
25
50
100
150
200
255
155
230
380
530
680
845
26
38
63
89
113
141
1.0
1.3
1.6
1.7
1.8
1.8
137
212
362
512
662
827
23
35
60
85
111
138
1.1
1.4
1.7
1.8
1.8
1.8
N
Average Rate = --------------------------------------------------------------Maximum Latency (µsec)
2.9.2
CONTINUOUS OPERATION
Multiple blocks of data may be processed
through the device continuously as shown in Figure
5: Burst and Continuous Operations. Consecutive
blocks are input into the device at the rate of Ci
clocks/byte. Data may be output in bursts depending
on whether parity is being output (controlled by
NOPAR) and the choice of Co. Continuous
operation is described by several equations. The
following terms are used in these equations:
Ci - Input clock rate per byte: Ci ≥ 4 for
continuous operation
Co - Output clock rate per byte: Co ≥ 2
Cm - Minimum of Ci and Co: if Ci < Co then
Cm = Ci; else Cm = Co
N - Reed-Solomon block length
K - Reed-Solomon message length
R - Reed-Solomon parity length (R = N − K)
L - Output data length – If parity is being
output from the chip (NOPAR = 0), L = N;
if the parity is not being output
(NOPAR = 1), L = K
A. Conditions for Continuous Operation
The allowable input and output data rates are
related to the Reed-Solomon block length by the
following two inequalities. Ci, Co, N and K must be
chosen so that these equations are satisfied.
Equation 1:
N × Cm
R + 60 + ----------------Cm – 1
---------------------------------------- + N ≤ 367
Ci
Equation 2:
B. Processing Latency
Processing latency is the time from the
beginning of a block on the input to the block being
ready for output. Maximum processing latency,
expressed in number of clocks, for continuous
operation is:
Equation 3:
N × Cm
Latency = ( N – 1 ) × C i + 60 + R + ----------------Cm – 1
C. Start and End of Output
Similar to the burst operation, Output Buffer
may be used to temporarily “hold” data from one
block while the Input Buffer is being filled.
However, these conditions must be satisfied: the
output of a data block must start after the latency
equation (Equation 3) is satisfied, but before the
maximum delay is reached. The maximum delay is:
Equation 4:
N × Ci
maximum_delay = 3 × N × C i – L × Co – --------------Ci – 1
if maximum_delay
--------------------------------------------- ≥ 367, then maximum_delay = 367 × C i
Ci
if maximum_delay
--------------------------------------------- > 2 × N, then maximum_delay = 2 × N × C i
Ci
Data of one block must be fully emptied L × Co
clocks after the start of empty process.
All of the conditions on the maximum delay
given in Equation 4 must be satisfied. If any are not,
the output data stream will begin to inhibit ECC
processing. Eventually this will cause the input
buffer to over fill and RDYIN to become inactive.
N × Ci N × C m
( N – 1 ) × C i ≥ R + 48 + --------------- + ----------------Ci – 1 Cm – 1
PS4012B-0100
Page 9 of 24
Advanced Hardware Architectures, Inc.
Figure 5:
Burst and Continuous Operations
(Note: Blocks are shown from right to left as they are input into and output from the chip. Block i is the first input
block, block i + 1 is second input block. XK−1 is the first input message byte of a block. Yo is the last input check
symbol of a block. Timings 1 and 2 in burst operation are described in Section 2.9.1 Burst Operation – Caveats.
Burst Mode Operation
Block i+1
Y 0 . . . . . . . . . . X K-1
Input Data:
2
Output Data:
Block i
Y 0 . . . . . . . . . . X K-1
1
Block i+1
Block i
Y 0 . . . . . . . . . . X K-1
Y0 . . . . . . . . . . . . . . . . . . X K-1
Processing Latency
Continuous Mode Operation
Block i+3
Input Data:
Block i+2
Block i+1
Block i
Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1
Block i+3
Output Data:
Block i+2
Block i+1
Block i
Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1
For a 6 MHz system using the required clocks per byte, maximum latencies and data rates for forward
order output are shown in the table for continuous operation. Input and Output rates are assumed the same
in this table. Note: Other frequency operations are also possible.
Table 3:
Continuous Operation Using 6 MHz Clock and Specified Clocks/Byte
CHECK BYTES ‘R’ = 20
MINIMUM
MAXIMUM MAXIMUM
BLOCK
LENGTHS ‘N’ REQUIRED DATA RATE LATENCY
25
50
100
150
200
225
255
(clocks/byte) (MBytes/sec)
6
1.0
5
1.2
4
1.5
4
1.5
4
1.5
4
1.5
4
1.5
(µsecs)
39
65
101
146
191
213
239
CHECK BYTES ‘R’ = 2
MINIMUM
MAXIMUM MAXIMUM
REQUIRED DATA RATE LATENCY
(clocks/byte)
5
5
4
4
4
4
4
(MBytes/sec)
1.2
1.2
1.5
1.5
1.5
1.5
1.5
(µsecs)
36
62
99
143
187
210
237
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 below for a system with 6 MHz clock.
Note: Other frequency operations are also possible.
Table 4:
Continuous Operation for IESS-308 Codes Using 6 MHz Clock and Specified Clocks/Byte
MINIMUM
BLOCK
MESSAGE
ERROR
REQUIRED
LENGTHS ‘N’ LENGTH ‘K’ CAPABILITY ‘t’
126
194
208
219
225
112
178
192
201
205
7
8
8
9
10
(clocks/byte)
4
4
4
4
4
MAXIMUM
DATA RATE
MAXIMUM
LATENCY
(MBytes/sec)
1.5
1.5
1.5
1.5
1.5
(# of clocks)
742
1107
1181
1242
1276
MAXIMUM
LATENCY
(µsecs)
124
185
197
207
213
Appendix B shows a spreadsheet table of block lengths vs. latencies for a 6 MHz clock system.
Page 10 of 24
PS4012B-0100
Advanced Hardware Architectures, Inc.
2.10 REED-SOLOMON (ECC) MODULE AND ERROR RATE PERFORMANCE
119 + R
G( x) =
The module implements a full error correcting
Reed-Solomon (RS) decoder whose function is to
perform the necessary corrections on the input
blocks. The code used by the decoder is capable of
generating corrections for up to 10 (t = 10) byteerrors in an RS block over the block length between
R + 1 to 255 bytes. The number of message bytes in
an RS block, K, is equal to the RS block length
minus R (K = N − R). The RS code implemented
uses the primitive polynomial
8
7
i
(x – α )
i = 120
An RS block consists of message and
redundancy bytes. The number of message bytes in
the block, K, is programmable during initialization.
The number of check bytes is R and can be
programmed during initialization to be 2 through 20
in increments of 1.
The ECC Module outputs corrected data by
performing an XOR of the correction vector with
the corresponding message or check byte.
Corrected bytes are flagged with a signal ERR
asserted.
The Symbol Error Rate Performance of the
Reed Solomon code used is shown in Figure 6.
2
P(x ) = x + x + x + x + 1
to generate GF(256). The generator polynomial for
the code is:
Figure 6:
∏
Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes
-0
10
-2
10
-4
10
-6
10
P
-8
10
t=1
-10
10
-12
10
t=8 t=5
-14
10
t=10
-16
10
-0
10
-1
10
-2
10
-3
10
The most common measures of performance for
Reed-Solomon code are PSE, PUE and CBER. PSE is the
probability of symbol errors and is the ratio of the
number of received symbol errors to the total
number of received symbols. In the AHA4012B
device the symbol length, m, is equal to 8 bits. PUE
is the probability of an uncorrectable error and is the
ratio of the number of uncorrectable code blocks to
the total number of received code blocks. An
uncorrectable error occurs when more than t
received symbols are in error. CBER is the Corrected
Bit Error Rate. The CBER is the reciprocal of
expected number of correct bits between errors.
If input noise is random,
If P SE
P UE = 10
PS4012B-0100
–7
t=3
-4
10
P
-5
10
-6
10
-7
10
-8
10
The figure shows probability of symbol error
and uncorrectable error for block size (N) of 255. It
shows the ability of various levels of Reed-Solomon
error correction to restore the integrity of the
corrupted data. For example, using 255 byte blocks,
if 1 out of 1000 of the received bytes have one or
more bit errors, RS correction with t = 5 will restore
the data to 1 error in 2 million blocks (510 million
bytes).
For a detailed discussion on error rate
performance of Reed-Solomon code, refer to the
AHA Application Note, Primer: Reed-Solomon
Error Correction Codes (ECC) (ANRS01).
PUE
CBER = -------------m×N
–4
= 8 × 10 with t = 5,
–7
– 11
10
and C BER = ------------------ = 4.9 × 10
8 × 255
Page 11 of 24
Advanced Hardware Architectures, Inc.
2.11 DETERMINING DECODER
PERFORMANCE BOUNDARIES
2.12 ERASURES
The chip is capable of utilizing erasure
information. R erasures may be corrected in any
block assuming there are no unmarked errors.
The correction capability is: E + 2e ≤ R
where E = number of erasures (marked errors)
e = number of unmarked errors
R = number of check symbols
AHA4012B supports a programmable feature
that allows a system designer to determine the
channel performance. This programmable feature,
referred to as error threshold, P, sets a number of
errors to be allowed by the chip prior to flagging the
block uncorrectable. Erasure Rejection Control bit
of the Control Byte register determines the
condition of CRTN output pin.
P and R are both independently selectable by
the user during the Initialization Control Sequence.
The various configurations of P and R are described
as follows:
P > R This is not a sensible choice since this
implies that more check bytes are allocated
for (correction-only) purposes than there
are total check bytes (for both correction
and detection). The device will work as if P
was set equal to R.
P = R This configuration maximizes the ability to
correct errors, particularly if R itself has
been chosen to be its maximum value of 20.
This is the usual choice. This situation
causes the CRTN output to flag a message
block as uncorrectable at an error level
exceeding that of which the device is
capable.
P < R This increases the level of error detection
capability. This situation causes the CRTN
output to flag a message block as
uncorrectable at an error level below that of
which the device is capable. This mode
only works with erasures.
Caveat: Output block may be corrupted if a block
exceeds the correction ability of the ECC module.
Figure 7:
If there are more than P or R erasures the
erasure information is discarded, and full error
correction is attempted. The chip can be
programmed to either call such a block
uncorrectable or not. If programmed not to call the
block uncorrectable (ERC bit set to 1), the ECC will
utilize the full error correction capability to decide if
the block is correctable.
3.0
OPERATIONAL DESCRIPTION
This section describes the relationship of
associated signals for various functions of the chip.
3.1
CLOCK
The clock input to the chip must meet the timing
requirements shown in Figure 7. The chip is entirely
static thus allowing the clock to stop in either the
active or inactive state for an indefinite period
without loss of stored information.
CLK Characteristics
CLK
1
2
3
1
4
5
NUMBER
1
2
3
4
5
DESCRIPTION
CLK rise time
CLK high time
CLK fall time
CLK low time
CLK period
MINIMUM
MAXIMUM
UNITS
5
nsec
nsec
nsec
nsec
nsec
50
5
50
166.7
All timing diagrams in this specification use the clock at the CLK pin as the reference point.
Page 12 of 24
PS4012B-0100
Advanced Hardware Architectures, Inc.
3.2
INITIALIZATION
This section describes the Reset and Initialization Sequence timing. For a detailed discussion on these
sequences, refer to Section 2.6 Reset and Initialization Sequence.
Figure 8:
Reset and Initialization Timing
CLK
1 2
1 2
RSTN
DSIN
DSON
3
DI
1
4
3
5
6
at least 2
clock edges
Input 6 bytes data for initialization
RESET
INITIALIZE
NUMBER
1
2
3
2
DESCRIPTION
at least 1
clock edge
at least 2
clock edges
Data
MINIMUM
RSTN and DSIN setup time
RSTN and DSIN hold time
RSTN and DSIN assertion
MAXIMUM
10
0
2
UNITS
nsec
nsec
Clock edges
Initialization bytes are strobed into the device while RSTN and DSIN are low during rising edges of
CLK. The RSTN must be active low for at least two clocks before the first initialization byte is strobed in
and remain active for at least one clock after the final byte. If initialization bytes are not loaded while RSTN
is active, the bytes maintain their previously defined values. After power-on the initializing registers'
contents are undefined.
For a detailed description of the Initialization Registers, refer to Section 2.6 Reset and Initialization
Sequence.
3.3
DATA INPUT
The chip latches the input data on the DI pins on the rising edge of the CLK when DSIN and RDYIN are
both active. The two figures below show the timing diagrams for Buffer Ready and Buffer Not Ready conditions.
Figure 9:
Data Input - Input Buffer Always Ready
CLK
RSTN
DI
1 2
1 2
valid
1 2
1 2
valid
1 2
1 2
1 2
1 2
valid
valid
valid
1 2
1 2
valid
DSIN
high = erase
ERASE
RDYIN
PS4012B-0100
Page 13 of 24
Advanced Hardware Architectures, Inc.
NUMBER
1
2
DESCRIPTION
MINIMUM
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
MAXIMUM
UNITS
10
0
nsec
nsec
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If
RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high
in four sample clocks and Ci is 3, 2, 1, 1, 2 clocks per byte.
Figure 10: Data Input - Buffer Not Ready
CLK
RSTN
1 2
DI
1 2
1 2
valid
1 2
1 2
1 2
1 2
valid
valid
valid
valid
DSIN
3
3
3
3
RDYIN
NUMBER
1
2
3
DESCRIPTION
MINIMUM
DI, ERASE and DSIN setup time
DI, ERASE and DSIN hold time
RDYIN output delay
MAXIMUM
UNITS
15
nsec
nsec
nsec
10
0
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 10.
3.4
DATA OUTPUT
The DO pins are driven from a register clocked on the rising edge of CLK.
Valid data on the DO pins is indicated by RDYON being active. When RDYON is inactive, data on the
DO pins is undefined, and DSON is ignored. The DSON signal acknowledges receiving the data and is used
by the device to internally increment the address counter and output the next location in the buffer. This data
output timing is shown in Figure 11. Co is 4, 1, 1 and 1 clock per byte in this example.
Figure 11: Data Output
CLK
3
3
3
valid
DO, ERR
1 2
valid
1 2
1 2
3
valid
1 2
1 2
1 2
valid
valid
1 2
1 2
DSON
3
3
3
RDYON
NUMBER
1
2
3
Page 14 of 24
DESCRIPTION
DSON setup time
DSON hold time
DO and RDYON output delay
MINIMUM
MAXIMUM
UNITS
15
nsec
nsec
nsec
10
2
PS4012B-0100
Advanced Hardware Architectures, Inc.
CRTN is valid for an RS block when the first message byte, X K-1, is strobed out of the chip. Figure 12
shows the output timing. CRTN is valid on the first byte of the block from the Output Buffer. In this example
only message bytes are output, no check bytes.
Figure 12: CRTN Timing
CLK
3
3
3
Block m
Byte X 1
DO
Block m
Byte X 0
1 2
1 2
1 2
3
Block m+1
Byte X K-1
1 2
1 2
1 2
Block m+1
Byte X K-2
1 2
DSON
3
error
VALID
CRTN
See Note
correctable
3
RDYON
NUMBER
1
2
3
Note:
DESCRIPTION
DSON setup time
DSON hold time
DO and RDYON output delay
MINIMUM
MAXIMUM
UNITS
15
nsec
nsec
nsec
10
2
CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the
error threshold, P, CRTN is inactive (high).
PS4012B-0100
Page 15 of 24
Advanced Hardware Architectures, Inc.
4.0
SIGNAL SPECIFICATIONS
4.1
INPUT SPECIFICATIONS
PIN
NUMBER
SIGNAL
NAME
SELF LOAD
(maximum in pF)
TSETUP
(min in nsec)
THOLD
(min in nsec)
STROBE
43
44
1
2
3
4
5
6
42
33
35
41
34
DI[7]
DI[6]
DI[5]
DI[4]
DI[3]
DI[2]
DI[1]
DI[0]
DSIN
DSON
RSTN
CLK
ERASE
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
N/A
10
0
0
0
0
0
0
0
0
0
2
0
N/A
0
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
N/A
CLK
N/A = Not Applicable
(Refer to DC ELECTRICAL CHARACTERISTICS for pad specifications)
4.2
OUTPUT SPECIFICATIONS
PIN
NUMBER
SIGNAL
NAME
LOAD CAP
(maximum in pF)
TDEL
(min in nsec)
TDEL
(max in nsec)
STROBE
REF
26
24
23
22
21
20
19
18
31
32
28
27
DO[7]
DO[6]
DO[5]
DO[4]
DO[3]
DO[2]
DO[1]
DO[0]
RDYON
RDYIN
CRTN
ERR
60
60
60
60
60
60
60
60
60
60
60
60
0
0
0
0
0
0
0
0
0
0
0
0
15
15
15
15
15
15
15
15
15
15
15
15
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
(Refer to DC ELECTRICAL CHARACTERISTICS for pad specifications)
Page 16 of 24
PS4012B-0100
Advanced Hardware Architectures, Inc.
4.3
4.4
POWER & GROUND PINS
Symbol
8, 10, 11, 16, 17, 29, 30, 37, 40
7, 9, 12, 15, 25, 36, 38, 39
GND
VDD
Characteristic
Clock frequency
Clock low time
Clock high time
Clock rise time
Clock fall time
Symbol
Tsetup
Thold
Characteristic
Input setup time
Input hold time
CLOCK RATE
Min
0
50
50
Max
Units
Test Conditions
6
MHz
nsec
nsec
nsec
nsec
Vil to Vih
Vil to Vih
5
5
INPUTS
Min
Max
10
0
Units
Test Conditions
nsec
nsec
See Note 1
See Notes 1 and 2
Setup and hold times measured from a valid high [2.0V] on the clock input pin.
DSON has a 2 nsec hold time.
Symbol
Tout
Note:
SIGNAL NAME
AC ELECTRICAL CHARACTERISTICS
Fclock
Tlow
Thigh
Trise
Tfall
Notes:
1)
2)
PIN NUMBER
Characteristic
Output delay
OUTPUTS
Min
Max
Units
Test Conditions
0
15
nsec
See Note
Output delay measured from valid high [2.0V] on the clock input pad. The output loads for the AC test are
given in Section 4.2 Output Specifications.
PS4012B-0100
Page 17 of 24
Advanced Hardware Architectures, Inc.
4.5
DC ELECTRICAL CHARACTERISTICS
Symbol
ABSOLUTE MAXIMUM STRESS RATINGS
Characteristic
Min
Max
Units
Tstg
Storage temperature
Vdd
Supply voltage
Vin
Input voltage
Package: 44-pin PLCC (JEDEC Standard)
Symbol
Supply voltage
Idd
Idd
Ta
P
Symbol
Vih
Vil
Iil
Cin
Symbol
Voh
Vol
Ioh
Iol
Page 18 of 24
150
6.0
Vdd+0.5
OPERATING CONDITIONS
Characteristic
Min
Max
Vdd
Ta
−55
−0.5
Vss−0.5
deg C
V
V
Units
5.25
V
Supply current
1.0
mA
Supply current
Operating temperature
(commercial part marking)
Operating temperature
(industrial part marking)
Power
30
mA
0
70
deg C
-40
85
deg C
.16
W
Max
Units
Vdd
0.8
10
10
V
V
µΑ
pF
Max
Units
Vdd
0.4
V
V
mA
mA
Characteristic
Input high voltage
Input low voltage
Input leakage
Capacitance
Characteristic
Output high voltage
Output low voltage
Output high current
Output low current
4.75
INPUTS
Min
2.0
Vss
−10
OUTPUTS
Min
2.4
Vss
−8
8
Test Conditions
Test Conditions
Static; Clock
stopped externally
Vdd=5V
Test Conditions
6 MHz
0<Vin<Vdd
Not 100% tested
Test Conditions
Ioh=8mA
Iol=8mA
Voh=2.4V
Vol=0.4V
PS4012B-0100
Advanced Hardware Architectures, Inc.
5.0
PACKAGING
PLCC Dimensions
Inches
(Millimeters)
B
A
.050
(1.27)
C
D
min/max
min/max
min/max
.685/.695
.650/.656
.165/.180
(17.40/17.65) (16.51/16.66) (4.19/4.57)
E
F
G
min
.020
(0.51)
±
.002
(0.051)
±
.0035
(0.089)
Packaging
Pin 1 Identification
AHA4012B-006 PJC
TM
C B
YYWWD-(COUNTRY OF ORIGIN)
LLLLL
A
D
E
F = Lead Planarity
G = Lead Skew
Note: YYWWD = Data Code
LLLL = Lead Skew
Complete Package Drawing Available Upon Request.
6.0
ORDERING INFORMATION
6.1
AVAILABLE PARTS
PART NUMBER
AHA4012B-006 PJC
AHA4012B-006 PJI
PS4012B-0100
DESCRIPTION
Reed-Solomon ECC Integrated Circuit - Commercial Temperature
Reed-Solomon ECC Integrated Circuit - Industrial Temperature
Page 19 of 24
Advanced Hardware Architectures, Inc.
6.2
PART NUMBERING
AHA
4012
B-
006
P
J
C, I
Manufacturer
Device
Number
Revision
Level
Speed
Designation
Package
Material
Package Type
Temperature
Specification
Device Number:
4012
Revision Letter:
B
Package Material Codes:
P
Plastic
Package Type Codes:
J
J - Leaded Chip Carrier
Temperature Specifications:
C
I
7.0
Commercial 0°C to + 70°C
Industrial
-40°C to + 85°C
RELATED TECHNICAL PUBLICATIONS
PART NUMBER
PB4012B
PS4011
PS4013
ABRS03
ABRS04
ABRS08
ABSTD1
ANRS01
ANRS02
ANRS03
ANRS05
ANRS12
ANRS13
RSEVAL
IESS-308,
Appendix F
Page 20 of 24
DESCRIPTION
AHA Product Brief – AHA4012B 1.5 MBytes/sec Reed-Solomon Error Correction
Device
AHA Product Specification – AHA4011 10 MBytes/sec Reed-Solomon Error Correction
Device
AHA Product Specification – AHA4013 12.5 MBytes/sec Reed-Solomon Error
Correction Device
AHA Application Brief – AHA4011 and AHA4012 Device Differences
AHA Application Brief – Reed-Solomon Evaluation Software Version 3.0
AHA Application Brief – AHA4012A and AHA4012B Device Differences
AHA Application Brief – AHA Data Compression and Forward Error Correction
Standards
AHA Application Note – Primer: Reed-Solomon Error Correction Codes (ECC)
AHA Application Note – Interleaving for Burst Error Correction
AHA Application Note – Reed-Solomon Evaluation Software Version 3.0
AHA Application Note – Serial I/O Interface to AHA4011/AHA4012
AHA Application Note – Frequently Asked Questions and Answers About the
AHA4011/AHA4012
AHA Application Note – Converting from LSI Logic’s L647xx Device to AHA4011/12
Reed-Solomon Evaluation Software Version 3.0 (Windows)
Concatenation of Reed-Solomon (RS) Outer Coding with the Existing Inner FEC (Not
available from AHA)
PS4012B-0100
Advanced Hardware Architectures, Inc.
APPENDIX A
Table of Elements
BLOCK
SIZE ‘N’
1
5
9
13
17
21
25
29
33
37
41
45
49
53
57
61
65
69
73
77
81
85
89
93
97
101
105
109
113
117
121
125
129
133
137
141
145
149
153
157
161
165
169
173
177
181
185
PS4012B-0100
HEX
VALUE
1
10
87
dd
6f
ec
71
8b
1d
57
62
3c
ce
d8
3f
fe
d6
df
4f
65
4c
55
42
b5
f3
6
60
1c
47
e5
e1
a1
34
4e
75
cb
88
2d
59
82
8d
7d
4b
25
d9
2f
79
BLOCK
SIZE ‘N’
2
6
10
14
18
22
26
30
34
38
42
46
50
54
58
62
66
70
74
78
82
86
90
94
98
102
106
110
114
118
122
126
130
134
138
142
146
150
154
158
162
166
170
174
178
182
186
HEX
VALUE
2
20
89
3d
de
5f
e2
91
3a
ae
c4
78
1b
37
7e
7b
2b
39
9e
ca
98
aa
84
ed
61
c
c0
38
8e
4d
45
c5
68
9c
ea
11
97
5a
b2
83
9d
fa
96
4a
35
5e
f2
BLOCK
SIZE ‘N’
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
67
71
75
79
83
87
91
95
99
103
107
111
115
119
123
127
131
135
139
143
147
151
155
159
163
167
171
175
179
183
187
HEX
VALUE
4
40
95
7a
3b
be
43
a5
74
db
f
f0
36
6e
fc
f6
56
72
bb
13
b7
d3
8f
5d
c2
18
7
70
9b
9a
8a
d
d0
bf
53
22
a9
b4
e3
81
bd
73
ab
94
6a
bc
63
BLOCK
SIZE ‘N’
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
124
128
132
136
140
144
148
152
156
160
164
168
172
176
180
184
188
HEX
VALUE
8
80
ad
f4
76
fb
86
cd
e8
31
1e
67
6c
dc
7f
6b
ac
e4
f1
26
e9
21
99
ba
3
30
e
e0
b1
b3
93
1a
27
f9
a6
44
d5
ef
41
85
fd
e6
d1
af
d4
ff
c6
Page 21 of 24
Advanced Hardware Architectures, Inc.
BLOCK
SIZE ‘N’
189
193
197
201
205
209
213
217
221
225
229
233
237
241
245
249
253
HEX
VALUE
b
b0
a3
14
c7
48
15
d7
cf
c8
b8
23
b9
33
3e
ee
51
BLOCK
SIZE ‘N’
190
194
198
202
206
210
214
218
222
226
230
234
238
242
246
250
254
HEX
VALUE
16
e7
c1
28
9
90
2a
29
19
17
f7
46
f5
66
7c
5b
a2
BLOCK
SIZE ‘N’
191
195
199
203
207
211
215
219
223
227
231
235
239
243
247
251
255
HEX
VALUE
2c
49
5
50
12
a7
54
52
32
2e
69
8c
6d
cc
f8
b6
c3
BLOCK
SIZE ‘N’
192
196
200
204
208
212
216
220
224
228
232
236
240
244
248
252
HEX
VALUE
58
92
a
a0
24
c9
a8
a4
64
5c
d2
9f
da
1f
77
eb
For example, for a block size of 205, the value to be programed in Byte 1 of the Initialization Register
is 0xc7.
/*This is a C program to generate Table of Elements. Pass a value of block length, N in decimal to this,
and obtain the Element value in hex.*/
int alpha(n)
int n;
{ int i,b,c;
c=01;
for (i=1;i<n;i++) {
b=c<<1;
if (b>0377)
b=b^0607;
c=b;
}
return c;
}
main()
{
int i;
printf(“Enter N--> ”);
scanf(“%d”,&i);
if(i<1 || i>255)
printf(“1<=N<=255”);
else
printf(“\nN = %d\tALPHA = %2x\n\n”, i, alpha(i));
}
Page 22 of 24
PS4012B-0100
Advanced Hardware Architectures, Inc.
APPENDIX B
AHA4012B Data Rate Calculations in Continuous Operation
Assumptions and Equations:
1) 6 MHz Clock is used; clock period =167 ns.
2) Input Rate (Ci) = Output Rate (Co)
C
Ci – 1
i
3) Latency = C i × ( N – 1 ) + ( R + 60 ) + N × -------------
4) Data Rate = 6 MHz/Ci clocks/byte
5) GOOD or BAD based on inequality equation:
Cm
R + 60 + N × ---------------Cm – 1
------------------------------------------------- + N ≤ 367
Ci
(5)
6) GOOD or BAD based on inequality equation:
Ci
Cm
( N – 1 ) × C i ≥ R + 48 + N × -------------- + N × ---------------Ci – 1
Cm – 1
7)
Note:
(6)
Check symbols are input into and output from the chip along with message symbols.
The following tables show examples of Data Rates and Latencies for various block sizes. Other block sizes
are also possible.
CLOCKS
N
/BYTE
4
4
4
4
4
4
4
4
4
4
4
4
4
25
50
53
75
100
126
194
208
219
200
225
250
255
CLOCKS
N
/BYTE
4
4
4
4
4
4
4
4
4
4
4
PS4012B-0100
25
50
75
100
125
150
175
200
225
250
255
T
MAXIMUM LATENCY DATA RATE
EQUATION 5 EQUATION 6
10
10
10
10
10
7
8
8
9
10
10
10
10
CLOCKS µSECONDS
209
35
343
57
359
60
476
79
609
102
742
124
1107
185
1181
197
1242
207
1143
191
1276
213
1409
235
1436
240
T
MAXIMUM LATENCY DATA RATE
EQUATION 5 EQUATION 6
5
5
5
5
5
5
5
5
5
5
5
CLOCKS µSECONDS
199
33
333
56
466
78
599
100
733
122
866
145
999
167
1133
189
1266
211
1399
234
1426
238
(MB/sec)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
BAD
BAD
BAD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
(MB/sec)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
BAD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
Page 23 of 24
Advanced Hardware Architectures, Inc.
CLOCKS
N
/BYTE
4
4
4
4
4
4
4
4
4
4
4
25
50
75
100
125
150
175
200
225
250
255
CLOCKS
N
/BYTE
4
4
4
4
4
4
4
4
4
4
4
Page 24 of 24
25
50
75
100
125
150
175
200
225
250
255
T
MAXIMUM LATENCY DATA RATE
EQUATION 5 EQUATION 6
3
3
3
3
3
3
3
3
3
3
3
CLOCKS µSECONDS
195
33
329
55
462
77
595
99
729
122
862
144
995
166
1129
189
1262
211
1395
233
1422
237
T
MAXIMUM LATENCY DATA RATE
EQUATION 5 EQUATION 6
1
1
1
1
1
1
1
1
1
1
1
CLOCKS µSECONDS
191
32
325
54
458
76
591
99
725
121
858
143
991
165
1125
188
1258
210
1391
232
1418
237
(MB/sec)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
BAD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
(MB/sec)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
BAD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
GOOD
PS4012B-0100