ETC ALC202

Avance Logic, Inc.
ALC202
ALC202
AC’97 Audio CODEC
Draft Spec.
Preliminary
Version 0.62
September 26, 2001
http://www.realtek.com.tw
Preliminary
Avance Logic, Inc.
ALC202
1. Features
Single chip audio CODEC with high S/N ratio (>90 dB).
20-bit DAC, 18-bit ADC.
Stereo full-duplex CODEC with independent and variable sampling rate.
4 analog line-level stereo input with 5-bit volume control : LINE_IN,CD,VIDEO,AUX
2 analog line-level mono input : PC_BEEP,PHONE_IN.
Mono output with 5-bit volume control.
Stereo output with 6-bit volume control.
2 MIC inputs: Software selectable.
Power management and enhanced power saving.
3D Stereo Enhancement
External Amplifier power down capability.
Multiple CODEC extension.
Compliant with AC’97 2.2 specification
50mW/8W amplifier at LINE/ Headphone output
Jack-detect function to mute LINE/MONO/HP output, to control S/PDIF output.
Supports S/PDIF out is compliant with AC’97 rev2.2.
2 GPIO pins.
14.318MHzà24.576MHz digital PLL.
Supports double sampling rate (96KHz) of DVD audio playback.
+30dB boost preamplifier for MIC input.
Power support: Digital: 3.3V Analog: 3.3V/5V
Standard 48-Pin LQFP Package
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2. Pin Description
2.1
Digital I/O pins: 11 pins
Name
RESET#
XTL-IN
Type
I
I
Pin No
11
2
XTL-OUT
O
3
Crystal output pad
I
IO
I
O
I/O
10
6
5
8
43
GPIO1
I/O
44
ID0#
EAPD / JD
I
O
45
47
SPDIFO /
TEST
O
48
Sample Sync (48KHz)
Bit clock output (12.288Mhz)
Serial TDM AC97 output
Serial TDM AC97 input
I: General purpose input pin-0. (Can
be software volume up)
O: General purpose output pin-0.
I: General purpose input pin-1.
(Can be software volume down)
O: General purpose output pin-1
ID strap 0
External Amplifier power down
control / Jack –Detect sense a low to
high edge
S/PDIF output / TEST output
SYNC
BIT-CLK
SDATA-OUT
SDATA-IN
GPIO0
2.2
Description
AC'97 H/W reset
Crystal input pad
Characteristic Definition
Schmitt trigger input
Crystal: 24.576M/14.318M crystal input
External: 24.576M/14.318M external clock input
Crystal: 24.576M/14.318M crystal output
External: 24.576M/14.318M clock output
Schmitt trigger input
CMOS input/output Vt=0.35Vdd
Schmitt trigger input
CMOS output,
Internally pulled high by a 50K resistor.
Internally pulled high by a 50K resistor.
CMOS input Vt=0.35Vdd
CMOS output / input, JD should be internally pulled
high by a 50K resistor
Digital output has 12 [email protected] driving capability.
Analog I/O Pins: 18 pins
Name
PC-BEEP
PHONE
AUX-L
AUX-R
VIDEO-L
VIDEO-R
Type
I
I
I
I
I
I
Pin No
12
13
14
15
16
17
http://www.realtek.com.tw
Preliminary
Description
PC speaker input
Speakerphone input
AUX Left channel
AUX Right channel
Video audio Left channel
Video audio Right channel
-2-
Characteristic Definition
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Rev0.62
Avance Logic, Inc.
ALC202
CD-L
CD-GND
CD-R
MIC1
MIC2
LINE-L
LINE-R
LINE-OUTL
I
I
I
I
I
I
I
O
18
19
20
21
22
23
24
35
CD audio Left channel
CD audio analog GND
CD audio Right channel
First Mic input
Second Mic input
Line input Left channel
Line input Right channel
Line-Out Left channel
LINE-OUTR
O
36
Line-Out Right channel
HP-OUT-L
O
39
HP-OUT-R
O
41
MONO-OUT
O
37
Headphone Out – Left (ALC202)
True-LINE-Out-Left (ALC202A)
Headphone Out – Left (ALC202)
True-LINE-Out-Left (ALC202A)
Speaker Phone output
2.3
Filter/References: 7 pins
Name
VREF
VREFOUT
AFILT1
AFILT2
VRAD
VRDA
2.4
Type
O
Pin No
27
28
29
30
31
32
Description
Reference voltage
Ref. voltage out with 8mA drive
ADC anti-aliasing filter capacitor
ADC anti-aliasing filter capacitor
ADC reference voltage capacitor
DAC reference voltage capacitor
Characteristic Definition
1uf capacitor to analog ground
Analog output (2.25V – 2.75V)
1000pf capacitor to analog ground.
1000pf capacitor to analog ground.
1uf capacitor to analog ground
1uf capacitor to analog ground
Power/Ground: 8 pins
Name
AVDD1
AVDD2
AVSS1
AVSS2
DVDD1
DVDD2
DVSS1
DVSS2
2.5
Type
I
I
I
I
I
I
I
I
Pin No
25
38
26
42
1
9
4
7
Description
Analog VDD (5.0V or 3.3V)
Analog VDD (5.0V or 3.3V)
Analog GND
Analog GND
Digital VDD (3.3V)
Digital VDD (3.3V)
Digital GND
Digital GND
Characteristic Definition
Others: 1 pin
Name
TEST
NC
2.6
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
ALC202: Analog output without op-amp (1.0Vrms)
ALC202A: Analog output with op-amp (1.4Vrms)
ALC202: Analog output without op-amp (1.0Vrms)
ALC202A: Analog output with op-amp (1.4Vrms)
ALC202: Analog output with op-amp
ALC202A: Analog output without op-amp
ALC202: Analog output with op-amp
ALC202A: Analog output without op-amp
Analog output (1Vrms)
Type
O
Pin No
48
33,40,34
Description
Output DAC clock and ADC clock
No Connection.
Characteristic Definition
Digital pin shared with SPDIFO
Crystal (Clock) Source Selection: 1 pin
Name
Type
Pin No
Description
Characteristic Definition
XTLSEL
I
46a
Crystal Selection
Internal pull high by a 50K resistor.
¶XTLSEL:
XTLSEL=floating, the clock source is 24.576MHz crystal or external clock. (Default)
XTLSEL=pull low, select 14.318MHzà24.576MHz digital PLL
The default state of MX7A.15 if power on latched inversely from XTLSEL.
-3http://www.realtek.com.tw
Preliminary
Rev0.62
Preliminary
http://www.realtek.com.tw
-4-
DAC
0*
+20/30dB
1
MX20.8
mono analog
stereo analog
stereo digital
SRC
* : default setting
VIDEO-IN
AUX-IN
CD-IN
LINE-IN
PHONE
MIC1
MIC2
PC-BEEP
PCM out
MX16
MX12
MX14
MX10
MX0E
MX0C
MX0A
MX18
stereo mix
mono mix
phone
mic
line
CD
video
aux
MX20.13
MX22
3D
PCM out
MX1A
M
U
X
MX1C
SRC
RESET#
Yes
No
Yes
No
RESET#
HP-OUT
PCM in
MONO-OUT
LINE-OUT
AMP
SPDIF Output
ALC202
ADC
Mono
Volume
MX06
Record
Gain
0*
1
MX20.9
MX02
Master
Volume
MX04
HeadPhone
Volume
MX2A / MX3A
SPDIF Out
Control
Avance Logic, Inc.
ALC202
2.7 Mixer Block Diagram
Rev0.62
Preliminary
http://www.realtek.com.tw
-5-
DAC
0*
+20/30dB
1
MX20.8
mono analog
stereo analog
stereo digital
SRC
* : default setting
VIDEO-IN
AUX-IN
CD-IN
LINE-IN
MIC1
MIC2
PHONE
PC-BEEP
PCM out
MX16
MX14
MX12
MX10
MX0E
MX0C
MX0A
MX18
stereo mix
mono mix
phone
mic
line
CD
video
aux
MX20.13
MX22
3D
PCM out
MX1A
M
U
X
MX1C
SRC
RESET#
Yes
No
Yes
No
RESET#
LINE-OUT
PCM in
MONO-OUT
AMP
HP-OUT
SPDIF Output
ALC202A
ADC
Mono
Volume
MX06
Record
Gain
0*
1
MX20.9
MX02
Master
Volume
MX04
HeadPhone
Volume
MX2A / MX3A
SPDIF Out
Control
Avance Logic, Inc.
ALC202
Rev0.62
Avance Logic, Inc.
ALC202
3. ALC202 Pin Assignment
LINE-OUT-R
LINE-OUT-L
NC
NC
VRDA
VRAD
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
3.1 Pin-Out Diagram:
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
ALC202
LINE-IN-R
LINE-IN-L
MIC2
MIC1
CD-R
CD-GND
CD-L
VIDEO-R
VIDEO-L
AUX-R
AUX-L
PHONE
24
23
22
21
20
19
18
17
16
15
14
13
1 2 3 4 5 6 7 8 9 10 11 12
LINE-OUT-R
LINE-OUT-L
NC
NC
VRDA
VRAD
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
DVDD1
XTL-IN
XTL-OUT
DVSS1
SDATA-OUT
BIT-CLK
DVSS2
SDATA-IN
DVDD2
SYNC
RESET#
PC-BEEP
MONO-OUT
AVDD2
HP-OUT-L
NC
HP-OUT-R
AVSS2
GPIO0
GPIO1
ID0#
XTLSEL
EAPD(JD)
SPDIFO/TEST
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
ALC202A
24
23
22
21
20
19
18
17
16
15
14
13
1 2 3 4 5 6 7 8 9 10 11 12
LINE-IN-R
LINE-IN-L
MIC2
MIC1
CD-R
CD-GND
CD-L
VIDEO-R
VIDEO-L
AUX-R
AUX-L
PHONE
DVDD1
XTL-IN
XTL-OUT
DVSS1
SDATA-OUT
BIT-CLK
DVSS2
SDATA-IN
DVDD2
SYNC
RESET#
PC-BEEP
MONO-OUT
AVDD2
TRUE-LINE-OUT-L
NC
TRUE-LINE-OUT-R
AVSS2
GPIO0
GPIO1
ID0#
XTLSEL
EAPD(JD)
SPDIFO/TEST
-6http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
4. Mixer Registers
All mixer register access with odd-number will return with 0.
Reading unimplemented registers will return 0.
REG.
(HEX)
00h
02h
NAME
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 DEFAU
LT
Reset
Master
Volume
04h Headphone
volume
06h
Mono-Out
Volume
0Ah
PC_BEEP
Volume
0Ch
PHONE
Volume
0Eh MIC Volume
X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 5990h
Mute X ML5 ML4 ML3 ML2 ML1 ML0 X
X MR5 MR4 MR3 MR2 MR1 MR0 8000h/
0000h
Mute X HPL HPL HPL HPL HPL HPL X
X HPR HPR HPR HPR HPR HPR 8000h/
5
4
3
2
1
0
5
4
3
2
1
0 0000h
Mute X
X
X
X
X
X
X
X
X
X MM MM MM MM MM 8000h/
4
3
2
1
0 0000h
Mute X
X
X
X
X
X
X
X
X
X PB3 PB2 PB1 PB0 X 8000h
10h
Mute
X
X
X
X
X
Mute
X
X
X
X
X
Line-In
Volume
CD Volume
Video
Volume
Aux Volume
PCM Out
Volume
Record
Select
Record Gain
Mute
X
Mute
Mute
3Ah
General
Purpose
3D Control
Power Down
Ctrl/Status
Extended
Audio ID
Extended
Audio Status
PCM front
Out Sample
Rate
PCM Input
Sample Rate
S/PDIF Ctl
76h
78h
7Ch
7Eh
GPIO Setup
GPIO Status
Vendor ID1
Vendor ID2
12h
14h
16h
18h
1Ah
1Ch
20h
22h
26h
28h
2Ah
2Ch
32h
X: reserved bit
X
X
X
X
PH4 PH3 PH2 PH1 PH0 8008h
X
BC
X
MI4 MI3 MI2 MI1 MI0 8008h
X
BGO BGO
1
0
NL4 NL3 NL2 NL1 NL0
X
X
X
NR4 NR3 NR2 NR1 NR0 8808h
X
X
X
X
CL4 CL3 CL2 CL1 CL0
VL4 VL3 VL2 VL1 VL0
X
X
X
X
X
X
CR4 CR3 CR2 CR1 CR0 8808h
VR4 VR3 VR2 VR1 VR0 8808h
Mute
Mute
X
X
X
X
AL4 AL3 AL2 AL1 AL0
PL4 PL3 PL2 PL1 PL0
X
X
X
X
X
X
X
X
X
X
X
X
Mute
X
X
X
X
X
POP
X
3D
X
X
X
AR4 AR3 AR2 AR1 AR0 8808h
PR4 PR3 PR2 PR1 PR0 8808h/
0808h
X
X RRS RRS RRS 0000h
2
1
0
X RRG RRG RRG RRG 8000h
3
2
1
0
X
X
X
X
X 0000h
X
X
LRS LRS LRS X
2
1
0
LRG LRG LRG LRG X
3
2
1
0
X
X MIX MS LBK
X
X
X
X
X
X
X
X
X
X
X
X
X DP2 DP1
EAP PR6 PR5 PR4 PR3 PR2 PR1 PR0 X
X
X
X REF ANL DAC
D
ID1 ID0 X
X REV REV AM X
X
X
X
X
X SPDI X
1
0
AP
F
X
X
X
X
X SPC X
X
X
X SPS SPS X SPDI X
V
A1 A0
F
FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR FSR
15 14
13 12 11
10
9
8
7
6
5
4
3
2
1
DP0 0000h
ADC 000Fh
VRA 0605h
VRA 0000h
FSR BB80h
0
ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR ISR BB80h
15 14
13 12 11
10
9
8
7
6
5
4
3
2
1
0
V
0
SPS SPS L CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COP /AU PRO 2000h
R1 R0
Y DIO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0000h
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
0 414Ch
0
1
0
0
0
1
1
1
0
0
0
1
V3 V2 V1 V0 4740h
-7http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
MX00
Bit
15
14:10
9
8
7
6
5
4
3
2
1
0
Reset
Default: 5990H
Type
Function
Reserved
R
return 10110b
R
Read as 0 (Not support 20-bit ADC)
R
Read as 1 (Support 18-bit ADC)
R
Read as 1 (Support 20-bit DAC)
R
Read as 0 (Not support 18-bit DAC)
R
Read as 0 (Not support for Loudness)
R
Read as 1 (Headphone output support)
R
Read as 0 (Not simulated stereo ,for analog 3D block use)
R
Read as 0 (Not Bess & Treble Control)
R
Reserved,Read as 0
R
Read as 0 (No Dedicated Mic PCM input)
ŒWrite to this register will reset all mixer register to their default value. The written data
should be ignored.
MX02
Bit
15
14
13:8
7:6
5:0
Master Volume
Default: 8000H / 0000H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Master Left Volume (MLV[5..0]) in 1.5 dB step
Reserved
R/W Master Right Volume (MRV[5..0]) in 1.5 dB step
ΠFor MRV/MLV, 00h
0 dB attenuation
3Fh
94.5 dB attenuation
•When ID=01,10,11, the default value is 0000H.
MX04
Bit
15
14
13:8
7:6
5:0
Headphone Output Volume
Default: 8000H / 0000H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Headphone Output Left Volume (HPL[5..0]) in 1.5 dB step
Reserved
R/W Headphone Output Right Volume (HPR[5..0]) in 1.5 dB step
ŒFor HPR/HPL, 00h
0 dB attenuation
3Fh 94.5 dB attenuation
•When ID=01,10,11, the default value is 0000H.
MX06
Bit
15
14:5
4:0
MONO_OUT Volume
Default: 8000H / 0000H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Mono Master Volume (MMV[4..0]) in 1.5 dB step
ΠFor MMV,
00h
0 dB attenuation
1Fh
46.5 dB attenuation
•Implement 5-bit volume control only. Writing 1xxxxx will be interpreted as x11111 and
response when read with x11111 too.
ÌWhen ID=01,10,11, the default value is 0000H.
-8-
http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
MX0A
Bit
15
14:5
4:1
0
PC BEEP Volume
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W PC Beep Volume (PBV[3..0]) in 3 dB step
Reserved
ΠFor PBV,
00h
0 dB attenuation
0Fh
45 dB attenuation
Default: 8000H
MX0C
Bit
15
14:5
4:0
PHONE Volume
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Phone Volume (PV[4..0]) in 1.5 dB step
ΠFor PV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
Default: 8008H
MX0E
Bit
15
14:10
9:8
MIC Volume
Default: 8008H
Type
Function
R/W Mute Control 0: Normal 1 : Mute (-¥ dB)
Reserved
R/W Boost Gain Option (BGO)·
00: 20 dB 01: 6 dB 10: 12 dB 11: 29.5 dB (V=30*Vmic-in)
7
Reserved
6
R/W Boost Control (BC)
0: Disable 1: Enable Boost
5
Reserved
4:0
R/W Mic Volume (MV[4..0]) in 1.5 dB step
ΠFor MV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
· If 29.5dB boost gain is selected, input resistor can be reduced to save area of feedback
resistor.
MX10
Bit
15
14:13
12:8
7:5
4:0
MX12
Bit
15
LINE_IN Volume
Default: 8808H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Line-In Left Volume (NLV[4..0]) in 1.5 dB step
Reserved
R/W Line-In Right Volume (NRV[4..0]) in 1.5 dB step
ΠFor NLV/NRV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
CD Volume
Type
R/W Mute Control 0 : Normal
Default: 8808H
Function
1 : Mute (-¥ dB)
-9-
http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
14:13
12:8
7:5
4:0
ALC202
Reserved
CD Left Volume (CLV[4..0]) in 1.5 dB step
Reserved
R/W CD Right Volume (CRV[4..0]) in 1.5 dB step
ΠFor CLV/CRV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
R/W
MX14
Bit
15
14:13
12:8
7:5
4:0
VIDEO Volume
Default: 8808H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Video Left Volume (VLV[4..0]) in 1.5 dB step
Reserved
R/W Video Right Volume (VRV[4..0]) in 1.5 dB step
ΠFor VLV/VRV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
MX16
Bit
15
14:13
12:8
7:5
4:0
AUX Volume
Default: 8808H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W AUX Left Volume (ALV[4..0]) in 1.5 dB step
Reserved
R/W AUX Right Volume (ARV[4..0]) in 1.5 dB step
ΠFor ALV/ARV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
MX18
Bit
15
14:13
12:8
7:5
4:0
PCM_OUT Volume
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W PCM Volume (PLV[4..0]) in 1.5 dB step
Reserved
R/W PCM Right Volume (PRV[4..0]) in 1.5 dB step
ΠFor PLV/PRV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
ÌWhen ID=01,10,11, the default value is 0808H.
Default: 8808H / 0808H
MX1A
Bit
15:11
10:8
7:3
2:0
Record Select
Type
Function
Reserved
R/W Left record source select (LRS[2..0])
Reserved
R/W Right record source select (RRS[2..0])
ΠFor LRS
Default: 0000H
- 10 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
0
0
0
0
0
0
0
7
• For RRS
0
0
0
0
0
0
0
0
ALC202
MIC
CD LEFT
VIDEO LEFT
AUX LEFT
LINE LEFT
STEREO MIXER OUTPUT LEFT
MONO MIXER OUTPUT
PHONE
MIC
CD RIGHT
VIDEO RIGHT
AUX RIGHT
LINE RIGHT
STEREO MIXER OUTPUT RIGHT
MONO MIXER OUTPUT
PHONE
MX1C
Bit
15
14:12
11:8
7:4
3:0
Record Gain
Default: 8000H
Type
Function
R/W Mute Control 0 : Normal 1 : Mute (-¥ dB)
Reserved
R/W Left Record Gain Select (LRG[3..0]) in 1.5 dB step
Reserved
R/W Right Record Gain Select (RRG[3..0]) in 1.5 dB step
ŒFor LRG/RRG, 0Fh
+22.5dB
00h
0 dB (No Gain)
MX20
Bit
15:14
13
12:10
9
8
7
6:0
General Purpose Register
Default : 0000H
Type
Function
Reserved, Read as 0
R/W 3D Control 1: On 0: Off
Reserved, Read as 0
R/W Mono output select 0 : MIX 1 : MIC
R/W Mic select 0 : Mic 1 1 : Mic 2
R/W AD to DA loop-back control 0 : Disable 1 : Enable
Reserved
MX22
3D Control
Bit
Type
15:3
Reserved ,Read as 0
2:0
R/W Depth control (DP[2..0])
Œ3D effect control
DP[2:0]
Function
DP[2:0]
000
0%(off*)
100
001
12.5%
101
010
25%
110
011
37.5
111
- 11 http://www.realtek.com.tw
Preliminary
Default : 0000H
Function
Function
50%
67.5%
75%
100%
Rev0.62
Avance Logic, Inc.
ALC202
MX26
Bit
15
14
13
12
11
10
9
8
7:4
3
2
1
0
Powerdown Control/Status
Default: 000FH
Type
Function
R/W PR7 External Amplifier Power Down (EAPD) 0: normal 1: Power down
R/W PR6 0: Normal 1: Power down Headphone Out (HP-OUT)
R/W PR5 0: Normal 1: Disable internal clock
R/W PR4 0: Normal 1: Power down AC-Link
R/W PR3 0: Normal 1: Power down Mixer (Vref off)
R/W PR2 0: Normal 1: Power down Mixer (Vref still on)
R/W PR1 0: Normal 1: Power down PCM DAC
R/W PR0 0: Normal 1: Power down PCM ADC and input MUX
Reserved, Read as 0
R
Vref status 1: Vref is up to normal level 0: Not yet
R
Analog Mixer status 1: Ready 0: Not yet
R
DAC status 1: Ready 0: Not yet
R
ADC status 1: Ready 0: Not yet
MX28
Bit
15
14
13:12
11:10
9
8:6
5:4
Extended Audio ID
Default: 060Fh
Type
Function
R
ID1 Ê
R
ID0
Reserved, Read as 0
R
REV[1:0]=01 to indicates ALC202 is AC’97 rev2.2 compliant.
R
AMAP read as 1 (DAC mapping based on ID)
Reserved, Read as 0
R/W DSA[1:0], DAC Slot AssignmentË (Default value depends on ID[1:0])
DSA[1:0] control DAC slot assignment described in AC’97 rev2.2.
Reserved, Read as 0
R
SPDIF read as 1 (S/PDIF is supported)
R
DRA read as 1
R
VRA read as 1 (Variable Rate Audio is supported)
ÊID1 is latched inversely from pin 46 when system reset. ID0 is latched inversely from pin 45
when system reset.
ËALC202 maps DAC slot according to the following table: (default maps to AC’97 spec.
rev2.2)
DSA[1:0]
Left DAC slot # Right DAC slot #
Comment
0,0
3
4
Default when ID[1:0]=00
0,1
7
8
Default when ID[1:0]=01,10
1,0
6
9
Default when ID[1:0]=11
1,1
10
11
3
2
1
0
MX2A
Bit
15:11
10
9:6
5:4
Extended Audio Status and control register
Default: 0000H
Type
Function
Reserved
R
SPCV (S/PDIF Configuration Valid)
0: current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid.
1: current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid.
Reserved
R/W SPSA[1:0] (S/PDIF Slot Assignment)
00: S/PDIF source data assigned to AC-LINK slot3/4.
01: S/PDIF source data assigned to AC-LINK slot7/8.
10: S/PDIF source data assigned to AC-LINK slot6/9.
- 12 -
http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
3
2
1
0
ALC202
11: S/PDIF source data assigned to AC-LINK slot10/11.
Reserved
R/W SPDIF 1: enable 0: disable (SPDIFO is in high impedance)
R/W DRA
1: enable 0: disable
R/W VRA. 1: enable 0: disable¶
ÊIf VRA = 0, ALC202 ADC/DAC operate at fixed 48KHz sampling rate. Otherwise, it
operates with variable sampling rate defined in MX2C and MX32. VRA also control write
operation of MX2Cand MX32.
MX2C
Bit
15:0
PCM DAC Rate
Default: BB80H
Type
Function
R/W FOSR[15:0]Output sampling rate.
ÊALC202 support the following sampling rate required in PC99/PC2001 design guide.
Sampling rate
FOSR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned .
ËWhen MX2A.0=0 (VRA is disable), this register will return BB80h when read.
MX32
Bit
15:0
PCM ADC Rate
Default: BB80H
Type
Function
R/W FISR[15:0]Output sampling rate.
ÊALC202 support the following sampling rate required in PC99/PC2001 design guide.
Sampling rate
FISR[15:0]
8000
1F40h
11025
2B11h
12000
2EE0
16000
3E80h
22050
5622h
24000
5DC0
32000
7D00h
44100
AC44h
48000
BB80h
Note that If the value written is not support, the closest value is returned .
ËWhen MX2A.0=0 (VRA is disable), this register will return BB80h when read.
MX3A
Bit
15
S/PDIF Channel Status and Control
Default: 2000H
Type
Function
R/W Validity Control (control V bit in Sub-Frame)
0: the V bit (valid flag) in sub-frame depends on whether the S/PDIF data is
under-run or over-run.
1: the V bit in sub-frame is always send as 1 to indicate the invalid data is not
suitable for receiver.
- 13 -
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Preliminary
Rev0.62
Avance Logic, Inc.
14
R
13:12
R/W
11
10:4
3
R/W
R/W
R/W
2
R/W
1
R/W
0
R
ALC202
DRS (Double Rate S/PDIF)
ALC202 doesn’t support double rate S/PDIF, this bit is always 0.
SPSR[1:0] (S/PDIF Sample Rate)
00: sample rate set to 44.1KHz , Fs[0:3]=0000
01: reserved
10: sample rate set to 48.0KHz , Fs[0:3]=0100 (default)
11: sample rate set to 32.0KHz , Fs[0:3]=1100
LEVEL (Generation Level)
CC[6:0] (Category Code)
PRE (Preemphasis)
0 : None
1: filter preemphasis is 50/15 usec
COPY (Copyright)
0: Not asserted
1: Asserted
/AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
PRO (Professional or Consumer format)
0: consumer format
1: professional format
ALC202 supports consumer channel status format, this bit is always 0.
ÊThe consumer channel status block (bit0~bit31):
0
1
2
3
4
PRO=0 /AUDIO COPY
PRE
0
8
9
10
11
12
CC0
CC1
CC2
CC3
CC4
16
17
18
19
20
0
0
0
0
0
24
25
26
27
28
Fs0
Fs1
Fs2
Fs3
0
5
0
13
CC5
21
0
29
0
6
0
14
CC6
22
0
30
0
7
0
15
LEVEL
23
0
31
0
Vendor Define Registers:
MX6A
Bit
15:14
13
Miscellaneous Control
Default: 0000h
Type
Function
Reserved.
R/W DAC PCM(n+1) Slot# Select (When DRA=1)
0: PCM(n+1) captured from Slot-10/11. (Default in AC’97 rev2.2)
1: PCM(n+1) captured from Slot-7/8.
12
R/W S/PDIF SourceŒ
0: S/PDIF data is from controller (default)
1: S/PDIF data is from ADC
11:4
Reserved
3
R/W SPDIF Out Volume Control – Mute Bit
0: Normal
1: Clamp SPDIF output data to 0. (Mute)
2:0
R/W SPDIF Out Volume Control – in 6 dB Step Attenuation ·
000: 0dB
001: - 6dB
010: -12dB
…
111: -42dB
ŒThe default source of S/PDIF output is data sent by controller. When this bit is set, S/PDIF data
comes from ALC202’s ADC. To keep data concurrence, software must guarantee the sample rates
in MX32 and MX3A[13:12] are the same. SPCV is no more a validity for S/PDIF configuration. If
- 14 Rev0.62
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Preliminary
Avance Logic, Inc.
ALC202
software doesn’t keep the same sample rates, the S/PDIF output will be auto forbidden by hardware,
and undefined consequence may be occurred.
Extension Registers:
MX76
Bit
15
GPIO Setup
Default: 0000h
Type
Function
R/W GPIO Statue Indication in SDATA_IN
0:The status of GPIO0/GPIO1/JD and its valid tag are not indicated in
SDATA_IN.
1: The status of GPIO0/GPIO1/JD and its valid tag are indicated in SDATA_IN
14:6
Reserved
6
R/W JD (Jack-Detect) interrupt Enable (when pin-47 is used as Jack-Detect)
0: Disable
1: Enable.
A low to high transaction will trigger the JD interrupt in bit0 of SDATA_IN’s
slot-12.¶
5
R/W GPIO1 interrupt Enable (when GPIO1 is used as input)
0: Disable
1: Enable.
A low to high transaction will trigger the GPIO interrupt in bit0 of SDATA_IN’s
slot-12.
4
R/W GPIO0 interrupt Enable (when GPIO0 is used as input)
0: Disable
1: Enable.
A low to high transaction will trigger the GPIO interrupt in bit0 of SDATA_IN’s
slot-12.
3:2
Reserved
1
R/W GPIO1Primitiveness Control
0: Set GPIO1 as input pin.
1: Set GPIO1 as output pin.
0
R/W GPIO0 Primitiveness Control
0: Set GPIO0 as input pin.
1: Set GPIO0 as output pin.
¶Software programmer can enable JD interrupt to know the “Jack Detection” event occurs.
·The Bit-Allocation of GPIO/JD status in AC-LINK:
SYNC
SDATA-IN
(Slot-0)
SDATA-IN
(Slot-12)
15
14
13
12
11
10
9
8
7
6
5
4
GPINT Frame Addr Data PCML PCMR
19
18
17
16
15
14
3
2
1
0
5
4
3
GPIO
13
12
11
10
9
8
7
6
JD
2
GPIO Status
Type
Default: 0000h
Function
- 15 -
http://www.realtek.com.tw
Preliminary
0
GPIO1 GPIO0 GPINT
*GPINT = (MX78.6 | MX78.5 | MX78.4)
MX78
Bit
1
Rev0.62
Avance Logic, Inc.
15:10
9
R/W
MX7A
Bit
15
Type
R
ALC202
Reserved
GPIO1 Output Control
0: Drive GPIO1 low.
1: Drive GPIO1 high.
8
R/W GPIO0 Output Control
0: Drive GPIO0 as low.
1: Drive GPIO0 as high.
7
NA
Reserved
6
R/W JD Interrupt Status (JD_IS)¶
0: Not JD interrupt.
1: JD interrupt.
JD_IS= (MX78.2==1)&(MX76.6==1) & (JD low-to-high transition).
Write 1 to clear this status bit.
5
R/W GPIO1 Interrupt Status (GPIO1_IS). (When GPIO1 is used as input)¶
0: No GPIO1 interrupt.
1: GPIO1 interrupt.
GPIO1_IS= (MX76.1==0)&(MX76.5==1) & (GPIO1 low-to-high transition).
Write 1 to clear this status bit.
4
R/W GPIO0 Interrupt Status (GPIO0_IS). (When GPIO0 is used as input)¶
0: No GPIO0 interrupt.
1: GPIO0 interrupt.
GPIO0_IS= (MX76.0==0)&(MX76.4==1) & (GPIO0 low-to-high transition)
Write 1 to clear this status bit.
3
NA
Reserved
2
R
Jack-Detect Event (JDEVT)
0: No Jack-Detect event occurs.
1: Jack-Detect event occurs.
JDEVT = MX7A.0 & MX7A.1
1
R
GPIO1 Input Status ·
0: GPIO1 is driven low by external device (input).
1: GPIO1 is driven high by external device (input).
0
R
GPIO0 Input Status ·
0: GPIO0 is driven low by external device (input).
1: GPIO0 is driven high by external device (input).
¶GPIO interrupt (GPINT) in bit0 of SDATA_IN’s slot-12 = (MX78.4 | MX78.5 | MX78.6).
·When GPIO1/0 is used as input pin, its status will be also reflected in bit2/1 of SDIN’s slot-12. Once
GPIO1/0 is used as output pin, the bit2/1 of SDATA_IN’s slot-12 is always 0.
The GPIOx is internally pulled high by a weak resistor.
Default: 57C0H
14
R/W
13:8
7
NA
R/W
6
R/W
5
R/W
Function
Clock Source Selection (XTLSEL)
0: 24.576MHz crystal is used. DPLL is bypass. (XTLSEL is floating or open)
1: 14.318MHz crystal is used. 14.318Mà24.576M digital PLL is enabled.
(XTLSEL is pull low)
ENHPF, Digital high-pass filter to eliminate variation in DC offset.
0: Disable 1: Enable (default)
Reserved
Pin-48 Function Selection
0: S/PDIF output (default) 1: TEST
Output value of TEST (when bit-7 is set)
0: ADC CLK 1: DAC CLK
Pin-47 Function Selection
0: EAPD output (default)
1: Jack-Detect input
- 16 -
http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
4
R/W
3
R/W
2
R/W
1
R
0
R/W
ALC202
HP-OUT Control
0: Normal
1: HP-OUT is auto muted by H/W when JDS=1
MONO-OUT Control
0: Normal
1: MONO-OUT is auto muted by H/W when JDS=1
SPDIF Output Gating
0: SPDIF output is not gated with JDS.
1: SPDIF output is gated with JDS.
Jack-Detect status (JDS)
0: JD is pull low
1: JD is floating or pull high
This bit always indicates the JD pin status after power on.
LINE-OUT Control
0: Normal
1: LINE-OUT is auto muted by H/W when JDS=1
MX7C
Bit
15:0
VENDOR ID1
Type
R
Vendor ID “AL”
Default : 414CH
MX7E
Bit
15:8
7:4
3:0
VENDOR ID2
Default : 4740H
Type
Function
R
Vendor ID “G”
R
Chip ID 0100 (ALC202)
R
Version number 00: version A.
For WHQL issue, The version number is always 0.
Function
- 17 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
5. Design Suggestion
5.1 Clocking
The clock source of different configuration is listed below:
CODEC ID[1..0]
BIT-CLK
Clock source
(12.288MHz)
24.576M/14.318M crystal or external clock
00
Output
source input from XTAL-IN*
12.288MHz clock input from BIT-CLK
01
Input
12.288MHz clock input from BIT-CLK
10
Input
12.288MHz clock input from BIT-CLK
11
Input
*The default clock source should be decided by XTLSEL, once 14.318MHz clock is selected,
internal digital PLL transfers it into 24.576MHz clock.
5.2 AC-Link
When ALC202 take serial data from AC97 controller, it sample SDATA_OUT on the falling
edge of BIT_CLK .When ALC202 send serial data to AC97 controller, it start to drive SDATA_IN on
the rising edge of BIT_CLK.
ALC202 will return any uninstalled bits or registers with 0 for read operation.. ALC202 also
stuff the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified.
Refer to “Audio CODEC ’97 Component Specification Revision 2.1/2.2” for detail.
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA PCM PCMR
L
SPDIF SPDIF
L
R
TAG ADDR DATA PCM PCMR
L
Fig5.2-1 Default ALC202 slot arrangement – CODEC ID = 00
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA
SPDIF PCM PCMR SPDIF
L
L
R
TAG ADDR DATA PCM PCMR
L
Fig5.2-2 Default ALC202 slot arrangement – CODEC ID = 01, 10
Slot#
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
SDATA-OUT
SDATA-IN
TAG
CMD DATA
PCM
L
PCMR SPDIF SPDIF
L
R
TAG ADDR DATA PCM PCMR
L
- 18 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
Fig5.2-3 Default ALC202 slot arrangement – CODEC ID = 11
5.3 Reset
There are 3 kinds of reset operation. Cold, Warm and Register reset which listed below:
Reset Type
Trigger condition
CODEC response
Assert RESET# for a specified period Reset all hardware logic and all registers
Cold
to its default value.
Write register indexed 00h
Reset all registers to its default value.
Register
Driven SYNC high for specified period Reactivates AC-LINK, no change to
Warm
without BIT_CLK
register values.
The AC97 controller should drive SYNC and SDATA-OUT low during the period of RESET# assertion to guarantee
ALC202 reset successfully.
5.4 CD Input
Pay attention to differential CD input. Below is an example of differential CD input.
Fig 5.4-1 Example of differential CD input
5.5 Odd Addressed Register Access
ALC202 will return “0000h” when those odd-addressed registers and unimplemented registers
are read.
5.6 Power-down Mode
Pay special attention to power down control register (index 26h), especially PR4 (powerdown
AC-link).
5.7 Test Mode
5.7.1 ATE In Circuit Test Mode:
SDATA_OUT is sampled high at the trailing edge of RESET#. At this mode ALC202 will drive
BIT_CLK, SDATA_IN, EAPD and SPDIFO to high impedance.
5.7.2 Vendor Specific Test Mode:
SYNC is sampled high at the trailing edge of RESET#. At this mode ALC202 will drive BIT_CLK,
SDATA_IN, EAPD and SPDIFO to high impedance.
Note: To make the most compatibility with AC’97 rev2.2, ALC202 will float its digital output pins in
both ATE and Vendor-Specific test mode. Please refer to AC’97 rev2.2 section 9.2 for detail
description about test mode.
- 19 -
http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
5.8 Jack-Detect Function
JD (Jack-Detect) is an internal pull high input pin used to decide whether LINE-OUT should be auto
muted or not. If JDE (Jack Detect Enable) is set and ALC202 detects the JD is floating or pull high
(JDS=1), ALC202 will disable the analog output of LINE-OUT even the MX02 is not muted.
Fig5.8-1 shows the jack detect example to implement this function. If no audio plug is inserted in
HP-OUT jack, JD is detected as low, LINE output normally. If audio plug is inserted, ALC202 disable
LINE output, still output to HP-OUT and MONO-OUT. It’s useful to some PC application especially
in notebook environment.
If headphone output jack is not implemented and HP-OUT kept as floating, once JDE is enable, LINE
output will be muted unless JD is pull low by a 10K ohm resistor (Fig5.8-2). To conquer this
disadvantage, the Jack-Detect mute LINE-OUT function is disable after power up (default JDE is 0),
that make ALC202 compatible with others AC’97. So it is software’s responsibility to enable this
function if headphone jack detection is implemented.
4.7K
JD
+
3.3u
5
4
3
HP-OUT-L
2
1
+
HP-OUT-R
+
+100uf
+100uf
4.7K
4.7K
HP-OUT
Fig5.8-1 Jack detect connection example
JD
10K
HP-OUT-R
HP-OUT-L
If HP-OUT jack is not implemented,
JD must be pulled low to prevent JDS is set
Fig5.8-2 JD is pull low by a 10K ohm resistor
- 20 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
Figure 5.8-3 shows another simple way to implement jack detect function without using ALC202’s JD
pin. It is especially easy for motherboard maker. No extra components needed, just layout issue.
Once the HP-OUT jack is plugged in, output signals to LINE-OUT will be isolated, no signals output at
LINE-OUT jack. The only drawback to this plan is software will not sense the HP-OUT jack is plugged
in. It may be not convenient for software to pay attention to special application.
1
2
3
4
5
LINE-OUT
+100uf
HP-OUT-L
+
1
2
3
4
5
+
HP-OUT-R
+100uf
HP-OUT
A simple way to implement jack-detect function without
using ALC202's JD pin
Fig5.9-3 Implement Jack-Detect function without using ALC202’s pin
- 21 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
6. Electrical Characteristics
6.1 DC Characteristics
6.1.0 Absolute Maximum Ratings:
Parameter
Symbol
Power Supplies
DVdd
Digital
AVdd
Analog
Operating Ambient
Ta
Temperature
Storage Temperature
Ts
ESD (Electrostatic Discharge)
Min
Typ
Max
Units
3.0
4.5
0
3.3
5.0
-
3.6
5.5
+70
V
V
o
C
+125
o
C
Susceptibility Voltage
Over 5000V
Others
6.1.1 Threshold Hold Voltage:
Dvdd= 3.3V±5%, T ambient=250C, with 50pF external load.
Parameter
Symbol
Min
Typ
Input voltage range
Vin
-0.30
Low level input voltage
VIL
0.7
Max
Dvdd+0.30
0.35Dvdd
Units
V
V
Low level input voltage
(XTAL_IN,BIT_CLK)
VIL
-
1.0
0.35Dvdd
V
Low level input voltage
(ID1#,ID0#)
VIL
-
1.2
0.35Dvdd
V
High level input voltage
(SYNC,SDATA_OUT,RESET#)
VIH
0.4DVdd
1.7
-
V
High level input voltage
(XTAL_IN,BIT_CLK)
VIH
0.4DVdd
2.2
-
V
High level input voltage
VIH
0.4DVdd
1.7
-
V
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
(Hi-Z)
Output buffer drive current
Internal pull up resistance
VOH
VOL
-
0.9DVdd
-10
-10
-
0.1DVdd
10
10
V
V
uA
uA
-
50k
5
100k
200k
mA
W
(SYNC,SDATA_OUT,RESET#)
(ID1#,ID0#)
6.1.2 Digital Filter Characteristics:
Filter
ADC Lowpass Filter
Symbol
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
DAC Lowpass Filter
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
Min
0
28.8
- 22 http://www.realtek.com.tw
Preliminary
0
28.8
Typ
-
Max
19.2
Units
KHz
KHz
dB
dB
19.2
KHz
KHz
dB
dB
-76.0
+- 0.15
-78.5
+- 0.15
Rev0.62
Avance Logic, Inc.
ALC202
6.1.3 S/PDIF output Characteristics:
Dvdd= 3.3V, Tambient=250C, with 75 ohm external load.
Parameter
Symbol
Min
Typ
High level output voltage
VOH
3.0
3.3
Low level output voltage
VOL
0
Max
0.5
Units
V
V
6.2 AC Timing Characteristics
6.2.1 Cold Reset:
Parameter
Symbol
RESET# active low pulse width Trst_low
RESET# inactive to BIT_CLK Trst2clk
Startup delay
Min
1.0
162.8
Typ
-
Max
-
Units
us
ns
Max
-
Units
us
ns
Fig 6.2.1-1 Cold reset timing diagram
6.2.2 Warm Reset:
Fig 6.2.2-1 Cold reset timing diagram
Parameter
Symbol
Min
Typ
SYNC active high pulse width Tsync_high
1.0
SYNC inactive to BIT_CLK
Tsync2clk 162.8
Startup delay
6.2.3 AC-Link Clocks:
Fig 6.2.3-1 BIT_CLK and SYNC timing diagram
Parameter
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BIT_CLK high pulse width (note 2)
BIT_CLK low pulse width (note 2)
SYNC frequency
http://www.realtek.com.tw
Preliminary
Symbol
Tclk_period
Tclk_high
Tclk_low
- 23 -
Min
36
36
-
Typ
12.288
81.4
40.7
40.7
48.0
Max
750
45
45
-
Units
MHz
ns
ps
ns
ns
KHz
Rev0.62
Avance Logic, Inc.
ALC202
SYNC period
Tsync_period
SYNC high pulse width
Tsync_high
SYNC low pulse width
Tsync_low
Note 1: Worse case duty cycle restricted to 45/55.
20.8
1.3
19.5
-
us
us
us
6.2.4 Data Output and Input Times:
Fig 6.2.4-1 Data Output and Input timing diagram
Parameter
Symbol Min
Typ
Max Units
Output Valid Delay from rising edge of
tco
15
ns
BIT_CLK
Note 1 : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
device driving the output.
Note 2 : 50pF external load
Parameter
Symbol Min
Typ
Max Units
Input Setup to falling edge of BIT_CLK
tsetup
10
ns
Input Hold from falling edge of BIT_CLK thold
10
ns
Note : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the
device driving the output.
Parameter
Symbol Min
Typ
Max Units
BIT_CLK combined rise or fall plus flight
7
ns
time
SDATA combined rise or fall plus flight
7
ns
time
Note : Combined rise or fall plus flight times are provided for worst case scenario
modeling purpose.
6.2.5 Signal Rise and Fall Times:
Fig 6.2.5-1 Signal Rise and Fall timing diagram
- 24 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
Parameter
Symbol
Min
BIT_CLK rise time
Triseclk
BIT_CLK fall time
Tfallclk
SYNC rise time
Trisesync
SYNC fall time
Tfallsync
SDATA_IN rise time
Trisedin
SDATA_IN fall time
Tfalldin
SDATA_OUT rise time
Trisedout
SDATA_OUT fall time
Tfalldout
Note 1: 75pF external load (50 pF in AC’97 rev2.1)
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
Typ
-
Max
6
6
6
6
6
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
6.2.6 AC-Link Low Power Mode Timing:
Fig 6.2.6-1 AC-Link low power mode timing diagram
Parameter
End of slot 2 to BIT_CLK,
SDATA_IN low
Symbol
Ts2_pdown
Min
-
Typ
-
Max
1.0
Units
us
6.2.7 ATE Test Mode:
Fig 6.2.6-1 ATE test mode timing diagram
*To meet AC’97 rev2.2, there are EAPD, SPDIFO, BIT_CLK and SDATA_IN should be floating in
test mode.
Parameter
Symbol
Min
Typ
Max
Units
Setup to trailing edge of
Tsetup2rst
15.0
ns
RESET# (also applies to SYNC)
Rising edge of RESET# to Hi-Z
Toff
25.0
ns
delay
- 25 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
ALC202
6.2.8 AC-Link IO Pin Capacitance and Loading:
Output Pin
BIT_CLK (must support ³ 2 Codecs)
SDATA_IN
1 Codec
55pF
47.5pF
2 Codec
62.5pF
55pF
3 Codec
75pF
60pF
4 Codec
85pF
62.5pF
Min
0
45
Typ
Max
10
55
Unit
%
%
6.2.9 SPDIF output:
SPDIF_OUT
Rise time/fall time
Duty cycle
Note :
T(h)
T(l)
90%
50%
10%
T(r)
T(f)
Rise time = 100 * T(r)/ (T(l)+ T(h)) %
Fall time = 100 * T(f)/ (T(l)+ T(h)) %
Duty cycle = 100 * T(h)/ (T(l)+ T(h)) %
6.2.10 BIT-CLK and SDATA-IN state when RESET# is active:
When RESET# is active the BIT-CLK and SDATA-IN must be floating by internal pull low 100K
resistors. So the ac-link signals are driven by another AC’97 on CNR board. This requirement is not
mentioned in AC’97 specification rev2.1, please refer CNR (Communication Network Riser)
specification rev1.0 page23~25 to get detail information.
7. Analog Performance Characteristics
Standard test conditions: Tambient=250C, Dvdd=3.3V ±5%,Avdd=5.0V±5%
1KHz input sine wave; Sampling frequency=48KHz; 0dB=1Vrms
10KW/50pF load; Test bench Characterization BW: 10Hz~22KHz
0dB attenuation; tone and 3D disabled
Parameter
Min
Typ
Max
Units
Full scale input voltage
Line inputs (Mixers)
1.6
Vrms
Line inputs (A/D)
1.2
Mic input (0 dB)
1.6
Mic input (20 dB boost)
0.16
Full scale output voltage
LINE-OUT
1.0
1.50
Vrms
HEADPHONE-OUT
1.7
Vrms
- 26 http://www.realtek.com.tw
Preliminary
Rev0.62
Avance Logic, Inc.
Analog to Analog S/N
CD to LINE-OUT
Other to LINE-OUT
Analog frequency response
S/N (A-weighted)
D/A
A/D
Total Harmonic Distortion (A-weighted)
D/A
A/D
D/A & A/D frequency response
Transition Band
Stop Band
Stop Band Rejection
Out-of-Band Rejection
Group delay
Power Supply Rejection
MIC Amplifier 20dB Gain
Master Volume (Mono,Stereo) : 32 step
Step Size
Attenuation Control Range
PC Beep Volume : 16 step
Step Size
Attenuation Control Range
Analog Mixer Volume : 32 step
Step Size
Gain Control Range
Record Gain : 16 step
Step Size
Gain Control Range
Input impedance (gain = 0dB, mixer = off)
LINE-IN
CD-IN, AUX-IN, VIDEO-IN, MIC-IN
PCBEEP, PHONE
Analog Output Impedance (LINE-OUT)
Analog Output Impedance (HP-OUT)
Power Supply Current
VA=5.0v,
VD=3.3v
Power Down Current
VA=5.0v
VD=3.3v
Vrefout
Vrefout Drive Current
ALC202
16
95
95
-
22,000
dB
-
90
90
-
dB
20
19,200
28,800
-75
18
-85
-85
-65
-65
20
19,200
28,800
¥
1
22
dB
Hz
Hz
Hz
dB
dB
ms
dB
dB
0
1.5
-
46.5
dB
dB
0
3.0
-
45
dB
dB
-34.5
1.5
-
+12
dB
dB
0
1.5
-
+22.5
dB
dB
64
32
16
10
10
60
10
-
- 27 http://www.realtek.com.tw
Preliminary
2.50
8
Hz
KW
KW
KW
W
W
70
500
1000
-
mA
mA
uA
uA
V
mA
Rev0.62
Avance Logic, Inc.
ALC202
8. Package:
SYMBOL
A
A1
A2
c
D
D1
D2
E
E1
E2
b
e
TH
L
MIN.
0.05
1.35
0.09
0.17
0o
0.45
MILLIMETER
TYP.
1.40
9.00 BSC
7.00 BSC
5.50
9.00 BSC
7.00BSC
5.50
0.20
0.50 BSC
3.5o
0.60
MAX.
1.60
0.15
1.45
0.20
0.002
0.053
0.004
0.27
0.007
7o
0.75
0o
0.018
- 28 http://www.realtek.com.tw
Preliminary
MIN.
INCH
TYP.
0.055
0.354 BSC
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
0.008
0.016 BSC
3.5o
0.024
MAX
0.063
0.006
0.057
0.008
0.011
7o
0.030
Rev0.62
Avance Logic, Inc.
ALC202
- 29 http://www.realtek.com.tw
Preliminary
Rev0.62