National Semiconductor Application Note 24 M. Yamatake April 1986 INTRODUCTION The test set described in this paper allows complete quantitative characterization of all dc operational amplifier parameters quickly and with a minimum of additional equipment. The method used is accurate and is equally suitable for laboratory or production testÐfor quantitative readout or for limit testing. As embodied here, the test set is conditioned for testing the LM709 and LM101 amplifiers; however, simple changes discussed in the text will allow testing of any of the generally available operational amplifiers. Amplifier parameters are tested over the full range of common mode and power supply voltages with either of two output loads. Test set sensitivity and stability are adequate for testing all presently available integrated amplifiers. The paper will be divided into two sections, i.e., a functional description, and a discussion of circuit operation. Complete construction information will be given including a layout for the tester circuit boards. POWER SUPPLY Basic waveforms and dc operating voltages for the test set are derived from a power supply section comprising a positive and a negative rectifier and filter, a test set voltage regulator, a test circuit voltage regulator, and a function generator. The dc supplies will be discussed in the section dealing with detailed circuit description. The waveform generator provides three output functions, a g 19V square wave, a b 19V to a 19V pulse with a 1% duty cycle, and a g 5V triangular wave. The square wave is the basic waveform from which both the pulse and triangular wave outputs are derived. The square wave generator is an operational amplifier connected as an astable multivibrator. This amplifier provides an output of approximately g 19V at 16 Hz. This square wave is used to drive junction FET switches in the test set and to generate the pulse and triangular waveforms. The pulse generator is a monostable multivibrator driven by the output of the square wave generator. This multivibrator is allowed to swing from negative saturation to positive saturation on the positive going edge of the square wave input and has a time constant which will provide a duty cycle of approximately 1%. The output is approximately b19V to a 19V. FUNCTIONAL DESCRIPTION The test set operates in one of three basic modes. These are: (1) Bias Current Test; (2) Offset Voltage, Offset Current Test; and (3) Transfer Function Test. In the first two of these tests, the amplifier under test is exercised throughout its full common mode range. In all three tests, power supply voltages for the circuit under test may be set at g 5V, g 10V, g 15V, or g 20V. A Simplified Test Set for Op Amp Characterization A Simplified Test Set for Op Amp Characterization TL/H/7190 – 1 FIGURE 1. Functional Diagram of Bias Current Test Circuit AN-24 C1995 National Semiconductor Corporation TL/H/7190 RRD-B30M115/Printed in U. S. A. The bias current display of Figure 2 has the added advantage that incipient breakdown of the input stage of the device under test at the extremes of the common mode range is easily detected. The triangular wave generator is a dc stabilized integrator driven by the output of the square wave generator and provides a g 5V output at the square wave frequency, inverted with respect to the square wave. The purpose of these various outputs from the power supply section will be discussed in the functional description. If either or both the upper or lower trace in the bias current display exhibits curvature near the horizontal ends of the oscilloscope face, then the bias current of that input of the amplifier is shown to be dependent on common mode voltage. The usual causes of this dependency are low breakdown voltage of the differential input stage or current sink. BIAS CURRENT TEST A functional diagram of the bias current test circuit is shown in Figure 1 . The output of the triangular wave generator and the output of the test circuit, respectively, drive the horizontal and vertical deflection of an oscilloscope. The device under test, (cascaded with the integrator, A7), is connected in a differential amplifier configuration by R1, R2, R3, and R4. The inputs of this differential amplifier are driven in common from the output of the triangular wave generator through attenuator R8 and amplifier A8. The inputs of the device under test are connected to the feedback network through resistors R5 and R6, shunted by the switch S5a and S5b. The feedback network provides a closed loop gain of 1,000 and the integrator time constant serves to reduce noise at the output of the test circuit as well as allowing the output of the device under test to remain near zero volts. The bias current test is accomplished by allowing the device under test to draw input current to one of its inputs through the corresponding input resistor on positive going or negative going halves of the triangular wave generator output. This is accomplished by closing S5a or S5b on alternate halves of the triangular wave input. The voltage appearing across the input resistor is equal to input current times the input resistor. This voltage is multiplied by 1,000 by the feedback loop and appears at the integrator output and the vertical input of the oscilloscope. The vertical separaton of the traces representing the two input currents of the amplifier under test is equivalent to the total bias current of the amplifier under test. The bias current over the entire common mode range may be examined by setting the output of A8 equal to the amplifier common mode range. A photograph of the bias current oscilloscope display is given as Figure 2 . In this figure, the total input current of an amplifier is displayed over a g 10V common mode range with a sensitivity of 100 nA per vertical division. OFFSET VOLTAGE, OFFSET CURRENT TEST The offset voltage and offset current tests are performed in the same general way as the bias current test. The only difference is that the switches S5a and S5b are closed on the same half-cycle of the triangular wave input. The synchronous operation of S5a and S5b forces the amplifier under test to draw its input currents through matched high and low input resistors on alternate halves of the input triangular wave. The difference between the voltage drop across the two values of input resistors is proportional to the difference in input current to the two inputs of the amplifier under test and may be measured as the vertical spacing between the two traces appearing on the face of the oscilloscope. Offset voltage is measured as the vertical spacing between the trace corresponding to one of the two values of source resistance and the zero volt baseline. Switch S6 and Resistor R9 are a base line chopper whose purpose is to provide a baseline reference which is independent of test set and oscilloscope drift. S6 is driven from the pulse output of the function generator and has a duty cycle of approximately 1% of the triangular wave. Figure 3 is a photograph of the various waveforms presented during this test. Offset voltage and offset current are displayed at a sensitivity of 1 mV and 100 nA per division, respectively, and both parameters are displayed over a common mode range of g 10V. TL/H/7190 – 3 FIGURE 3. Offset Voltage, Offset Current and Common Mode Rejection Display TL/H/7190–2 FIGURE 2. Bias Current and Common Mode Rejection Display 2 TL/H/7190 – 4 FIGURE 4. Functional Diagram of Transfer Function Circuit TRANSFER FUNCTION TEST A functional diagram of the transfer function test is shown in Figure 4 . The output of the triangular wave generator and the output of the circuit under test, respectively, drive the horizontal and vertical inputs of an oscilloscope. The device under test is driven by a g 2.5 mV triangular wave derived from the g 5V output of the triangular wave generator through the attenuators R11, R12, and R1, R3 and through the voltage follower, A7. The output of the device under test is fed to the vertical input of an oscilloscope. Amplifier A7 performs a dual function in this test. When S7 is closed during the bias current test, a voltage is developed across C1 equal to the amplifier offset voltage multiplied by the gain of the feedback loop. When S7 is opened in the transfer function test, the charge stored in C1 continues to provide this offset correction voltage. In addition, A7 sums the triangular wave test signal with the offset correction voltage and applies this sum to the input of the amplifier under test through the attenuator R1, R3. This input sweeps the input of the amplifier under test g 2.5 mV around its offset voltage. TL/H/7190 – 5 FIGURE 5. Transfer Function Display Gain is displayed as the slope, DVOUT/DVIN of the transfer function. Gain linearity is indicated change in slope of the VOUT/VIN display as a function of output voltage. This display is particularly useful in detecting crossover distortion in a Class B output stage. Output swing is measured as the vertical deflection of the transfer function at the horizontal extremes of the display. Figure 5 is a photograph of the output of the test set during the transfer function test. This figure illustrates the function of amplifier A7 in adjusting the dc input of the test device so that its transfer function is displayed on the center of the oscilloscope face. The transfer function display is a plot of VIN vs VOUT for an amplifier. This display provides information about three amplifier parameters: gain, gain linearity, and output swing. 3 NOTE: All resistor valves in ohms. All resistors (/4W, 5% unless specified otherwise. TL/H/7190 – 6 FIGURE 6. Power Supply and Function Generator comprising R7, R8, R9, R10, and R26. The output of this divider is a 10V to a 2.5V according to the position of S2a and is fed to the non-inverting, gain-of-two amplifier, A2. A2 is powered from a 28V and provides a 20V to a 5V at its output. A3 is a unity gain inverter whose input is the output of A2 and which is powered from b28V. The complementary outputs of amplifiers A2 and A3 provide dc power to the circuit under test. LM101 amplifiers are used as A2 and A3 to allow operation from one ground referenced voltage each and to provide protective current limiting for the device under test. DETAILED CIRCUIT DESCRIPTION POWER SUPPLIES As shown in Figure 6 , which is a complete schematic of the power supply and function generator, two power supplies are provided in the test set. One supply provides a fixed g 20V to power the circuitry in the test set; the other provides g 5V to g 20V to power the circuit under test. The test set power supply regulator accepts a 28V from the positive rectifier and filter and provides a 20V through the LM100 positive regulator. Amplifier A1 is powered from the negative rectifier and filter and operates as a unity gain inverter whose input is a 20V from the positive regulator, and whose output is b20V. The test circuit power supply is referenced to the a 20V output of the positive regulator through the variable divider FUNCTION GENERATOR The function generator provides three outputs, a g 19V square wave, a b19V to a 19V pulse having a 1% duty cycle, and a g 5V triangular wave. The square wave is the 4 operated synchronously from the output of Q11. During the transfer function test, Q6 and Q7 are switched on continuously by turning off Q11. R42 and R45 maintain the gates of the FET switches at zero gate to source voltage for maximum conductance during their on cycle. Since the sources of these switches are at the common mode input voltage of the device under test, these resistors are connected to the output of the common mode driver amplifier, A8. The input for the integrator-feedback buffer, A7, is selected by the FET switches Q4 and Q5. During the bias current and offset voltage offset current tests, A7 is connected as an integrator and receives its input from the output of the device under test. The output of A7 drives the feedback resistor, R40. In this connection, the integrator holds the output of the device under test near ground and serves to amplify the voltages corresponding to bias current, offset current, and offset voltage by a factor of 1,000 before presenting them to the measurement system. FET switches Q4 and Q5 are turned on by switch section S1b during these tests. FET switches Q4 and Q5 are turned off during the transfer function test. This disconnects A7 from the output of the device under test and changes it from an integrator to a non-inverting unity gain amplifier driven from the triangular wave output of the function generator through the attenuator R33 and R34 and switch section S1a. In this connection, amplifier A7 serves two functions; first, to provide an offset voltage correction to the input of the device under test and, second, to drive the input of the device under test with a g 2.5 mV triangular wave centered about the offset voltage. During this test, the common mode driver amplifier is disabled by switch section S1a and the vertical input of the measurement oscilloscope is transferred from the output of the integrator-buffer, A7, to the output of the device under test by switch section S1d. S2a allows supply voltages for the device under test to be set at g 5, g 10, g 15, or g 20V. S2b changes the vertical scale factor for the measurement oscilloscope to maintain optimum vertical deflection for the particular power supply voltage used. S4 is a momentary contact pushbutton switch which is used to change the load on the device under test from 10 kX to 2 kX. A delay must be provided when switching from the input tests to the transfer function tests. The purpose of this delay is to disable the integrator function of A7 before driving it with the triangular wave. If this is not done, the offset correction voltage, stored on C16, will be lost. This delay between opening FET switch Q4, and switch Q5, is provided by the RC filter, R35 and C19. Resistor R41 and diodes D7 and D8 are provided to control the integrator when no test device is present, or when a faulty test device is inserted. R41 provides a dc feedback path in the absence of a test device and resets the integrator to zero. Diodes D7 and D8 clamp the input to the integrator to approximately g .7 volts when a faulty device is inserted. FET switch Q1 and resistor R28 provide a ground reference at the beginning of the 50-ohm-source, offset-voltage trace. This trace provides a ground reference which is independent of instrument or oscilloscope calibration. The gate of Q1 is driven by the output of monostable multivibrator A5, and shorts the vertical oscilloscope drive signal to ground during the time that A5 output is positive. Switch S3, R27, and R28 provide a 5X scale increase during input parameter tests to allow measurement of amplifiers with large offset voltage, offset current, or bias current. Switch S5 allows amplifier compensation to be changed for 101 or 709 type amplifiers. basic function from which the pulse and triangular wave are derived, the pulse is referenced to the leading edge of the square wave, and the triangular wave is the inverted and integrated square wave. Amplifier A4 is an astable multivibrator generating a square wave from positive to negative saturation. The amplitude of this square wave is approximately g 19V. The square wave frequency is determined by the ratio of R18 to R16 and by the time constant, R17C9. The operating frequency is stabilized against temperature and power regulation effects by regulating the feedback signal with the divider R19, D5 and D6. Amplifier A5 is a monostable multivibrator triggered by the positive going output of A4. The pulse width of A5 is determined by the ratio of R20 to R22 and by the time constant R21C10. The output pulse of A5 is an approximately 1% duty cycle pulse from approximately b19V to a 19V. Amplifier A6 is a dc stabilized integrator driven from the amplitude-regulated output of A4. Its output is a g 5V triangular wave. The amplitude of the output of A6 is determined by the square wave voltage developed across D5 and D6 and the time constant Radj C14. DC stabilization is accomplished by the feedback network R24, R25, and C15. The ac attenuation of this feedback network is high enough so that the integrator action at the square wave frequency is not degraded. Operating frequency of the function generator may be varied by adjusting the time constants associated with A4, A5, and A6 in the same ratio. TEST CIRCUIT A complete schematic diagram of the test circuit is shown in Figure 7 . The test circuit accepts the outputs of the power supplies and function generator and provides horizontal and vertical outputs for an X-Y oscilloscope, which is used as the measurement system. The primary elements of the test circuit are the feedback buffer and integrator, comprising amplifier A7 and its feedback network C16, R31, R32, and C17, and the differential amplifier network, comprising the device under test and the feedback network R40, R43, R44, and R52. The remainder of the test circuit provides the proper conditioning for the device under test and scaling for the oscilloscope, on which the test results are displayed. The amplifier A8 provides a variable amplitude source of common mode signal to exercise the amplifier under test over its common mode range. This amplifier is connected as a non-inverting gain-of-3.6 amplifier and receives its input from the triangular wave generator. Potentiometer R37 allows the output of this amplifier to be varied from g 0 volts to g 18 volts. The output of this amplifier drives the differential input resistors, R43 and R44, for the device under test. The resistors R46 and R47 are current sensing resistors which sense the input current of the device under test. These resistors are switched into the circuit in the proper sequence by the field effect transistors Q6 and Q7. Q6 and Q7 are driven from the square wave output of the function generator by the PNP pair, Q10 and Q11, and the NPN pair, Q8 and Q9. Switch sections S1b and S1c select the switching sequence for Q8 and Q9 and hence for Q6 and Q7. In the bias current test, the FET drivers, Q8 and Q9, are switched by out of phase signals from Q10 and Q11. This opens the FET switches Q6 and Q7 on alternate half cycles of the square wave output of the function generator. During the offset voltage, offset current test, the FET drivers are 5 NOTE: All resistors 1/4W, 5% unless specified otherwise *2N3819 matched for on resistance within 200X Select for BVGS l 45V TL/H/7190 – 7 FIGURE 7. Test Circuit 3. Transfer Function (Figure 5 ) VIN 0.5 mV/div. 5V/div. @ Vs VOUT 5V/div. @ Vs 2V/div. @ Vs 1V/div. @ Vs DVOUT Gain e DVIN CALIBRATION Calibration of the test system is relatively simple and requires only two adjustments. First, the output of the main regulator is set up for 20V. Then, the triangular wave generator is adjusted to provide g 5V output by selecting Radj. This sets the horizontal sweep for the X-Y oscilloscope used as the measurement system. The oscilloscope is then set up for 1V/division vertical and for a full 10 division horizontal sweep. Scale factors for the three test positions are: 1. Bias Current Display (Figure 2 ) g 20V g 15V g 10V g 5V CONSTRUCTION Test set construction is simplified through the use of integrated circuits and etched circuit layout. Ibias total 100 nA/div. vertical Common Mode Voltage Variable horizontal 2. Offset Voltage-Offset Current (Figure 3 ) Ioffset 100 nA/div. vertical Voffset 1 mV/div. vertical Common Mode Voltage Variable horizontal Figure 8 gives photographs of the completed tester. Figure 9 shows the parts location for the components on the circuit board layout of Figure 10 . An attempt should be made to 6 adhere to this layout to insure that parasitic coupling between elements will not cause oscillations or give calibration problems. Table I is a listing of special components which are needed to fit the physical layout given for the tester. TABLE I. Partial Parts List T1 Triad F-90X S1 S2 S3, S4 Grayhill 30-1 Series 30 subminiature S5, S6 pushbutton switch Alcoswitch MST-105D SPDT CONCLUSIONS A semi-automatic test system has been described which will completely test the important operational amplifier parameters over the full power supply and common mode ranges. The system is simple, inexpensive, easily calibrated, and is equally suitable for engineering or quality assurance usage. Centralab PA2003 non-shorting Centralab PA2015 non-shorting TL/H/7190 – 8 FIGURE 8a. Bottom of Test Set 7 TL/H/7190 – 9 FIGURE 8b. Front Panel TL/H/7190 – 10 FIGURE 8c. Jacks 8 TL/H/7190 – 11 FIGURE 9. Component Location, Top View 9 A Simplified Test Set for Op Amp Characterization TL/H/7190 – 12 FIGURE 10. Circuit Board Layout LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: AN-24 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.