ETC BC41B143A-DS

_äìÉ`çêÉ»QJolj=mäìÖJåJdç»
Device Features
ƒ
Fully Qualified Bluetooth v2.0+EDR system
ƒ
Full Speed Bluetooth Operation with Full Piconet
Support
ƒ
Scatternet Support
ƒ
Low Power 1.8V operation
ƒ
10 x 10mm 96-ball LFBGA Package
ƒ
Minimum External Components
ƒ
Integrated 1.8V Regulator
ƒ
Dual UART Ports
ƒ
RF Plug-n-Go Package
ƒ
50Ω Matched Connection to Antenna
ƒ
RoHS Compliant
Single Chip Bluetooth®
v2.0 + EDR System
Advance Information Data Sheet For
BC41B143A
July 2005
Applications
The _äìÉ`çêÉ»QJolj=mäìÖJåJdç» is a single
chip radio and baseband IC for Bluetooth 2.4GHz
systems. It is implemented in 0.18µm CMOS
technology.
BC41B143A contains 4Mbit of internal ROM memory.
When used with CSR Bluetooth stack, it provides a
fully compliant Bluetooth system to v2.0 + EDR of the
specification for data and voice.
ƒ
Automotive
ƒ
Mice
ƒ
Keyboards
BlueCore4-ROM Plug-n-Go has the same pinout and
electrical characteristics as available in
BlueCore4-Flash Plug-n-Go to enable development
of custom code before committing to ROM. It also has
the same pinout as BlueCore2-ROM Plug-n-Go and
BlueCore2-Flash Plug-n-Go to keep compatibility.
SPI
RAM
RF IN
RF
OUT
UART/USB
ROM
2.4
GHz
Radio
I/O
Baseband
DSP
PIO
MCU
PCM
BlueCore4-ROM Plug-n-Go has been designed to
reduce the number of external components required
which ensures production costs are minimised. The
0.8mm pitch BlueCore4-ROM Plug-n-Go can be used
on either two or four layer PCB construction.
The device incorporates auto-calibration and built in
self test (BIST) routines to simplify development, type
approval and production test. All hardware and
device firmware is fully compliant with the Bluetooth
v2.0 + EDR specification.
XTAL
System Architecture
Data Sheet
Advance InformationCSR PLC2005
c2005BC41B143A-ds-003P© 2005 Cambridge Silicon Radio Limited
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 1 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
General Description
Contents
1
2
3
4
6
7
8
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 2 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
5
Status Information .......................................................................................................................................... 7
Key Features .................................................................................................................................................... 8
Package Information ....................................................................................................................................... 9
3.1 BC41B143A Pinout Diagram ................................................................................................................... 9
3.2 BC41B143A-ANN-E4 Device Terminal Functions ................................................................................. 10
Electrical Characteristics ............................................................................................................................. 14
4.1 Power Consumption .............................................................................................................................. 19
Radio Characteristics - Basic Data Rate ..................................................................................................... 20
5.1 Temperature +20°C ............................................................................................................................... 20
5.1.1 Transmitter ................................................................................................................................ 20
5.1.2 Receiver .................................................................................................................................... 22
5.2 Temperature -40°C ................................................................................................................................ 24
5.2.1 Transmitter ................................................................................................................................ 24
5.2.2 Receiver .................................................................................................................................... 24
5.3 Temperature -25°C ................................................................................................................................ 25
5.3.1 Transmitter ................................................................................................................................ 25
5.3.2 Receiver .................................................................................................................................... 25
5.4 Temperature +85°C ............................................................................................................................... 26
5.4.1 Transmitter ................................................................................................................................ 26
5.4.2 Receiver .................................................................................................................................... 26
Radio Characteristics - Enhanced Data Rate ............................................................................................. 27
6.1 Temperature +20°C ............................................................................................................................... 27
6.1.1 Transmitter ................................................................................................................................ 27
6.1.2 Receiver .................................................................................................................................... 28
6.2 Temperature -40°C ................................................................................................................................ 29
6.2.1 Transmitter ................................................................................................................................ 29
6.2.2 Receiver .................................................................................................................................... 29
6.3 Temperature -25°C ................................................................................................................................ 30
6.3.1 Transmitter ................................................................................................................................ 30
6.3.2 Receiver .................................................................................................................................... 30
6.4 Temperature +85°C ............................................................................................................................... 31
6.4.1 Transmitter ................................................................................................................................ 31
6.4.2 Receiver .................................................................................................................................... 31
Device Diagram ............................................................................................................................................ 32
Description of Functional Blocks ................................................................................................................ 33
8.1 RF Receiver ........................................................................................................................................... 33
8.1.1 Low Noise Amplifier .................................................................................................................. 33
8.1.2 Analogue to Digital Converter ................................................................................................... 33
8.2 RF Transmitter ....................................................................................................................................... 33
8.2.1 IQ Modulator ............................................................................................................................. 33
8.2.2 Power Amplifier ......................................................................................................................... 33
8.2.3 Auxiliary DAC ............................................................................................................................ 33
8.3 Balun and Filter ..................................................................................................................................... 33
8.4 RF Synthesiser ...................................................................................................................................... 33
8.5 Clock Input and Generation ................................................................................................................... 33
8.6 Baseband and Logic .............................................................................................................................. 34
8.6.1 Memory Management Unit ....................................................................................................... 34
8.6.2 Burst Mode Controller ............................................................................................................... 34
8.6.3 Physical Layer Hardware Engine DSP ..................................................................................... 34
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 3 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
8.6.4 RAM (48Kbytes) ....................................................................................................................... 34
8.6.5 ROM ......................................................................................................................................... 34
8.6.6 USB .......................................................................................................................................... 34
8.6.7 Synchronous Serial Interface .................................................................................................... 34
8.6.8 UART ........................................................................................................................................ 34
8.7 Microcontroller ....................................................................................................................................... 35
8.7.1 Programmable I/O .................................................................................................................... 35
8.7.2 802.11 Co-Existence Interface ................................................................................................. 35
9 CSR Bluetooth Software Stacks .................................................................................................................. 36
9.1 BlueCore HCI Stack ............................................................................................................................. 36
9.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ........................................... 37
9.1.2 Key Features of the HCI Stack: Extra Functionality .................................................................. 38
9.2 BlueCore RFCOMM Stack .................................................................................................................... 39
9.2.1 Key Features of the BlueCore4-ROM Plug-n-Go RFCOMM Stack .......................................... 40
9.3 BlueCore Virtual Machine Stack ............................................................................................................ 41
9.4 BlueCore HID Stack .............................................................................................................................. 42
9.5 Host-Side Software ................................................................................................................................ 43
9.6 Device Firmware Upgrade ..................................................................................................................... 43
9.7 BCHS Software ..................................................................................................................................... 43
9.8 Additional Software for Other Embedded Applications .......................................................................... 43
9.9 CSR Development Systems .................................................................................................................. 43
10 Device Terminal Descriptions ...................................................................................................................... 44
10.1 RF Ports ................................................................................................................................................ 44
10.1.1 RF Plug-n-Go ............................................................................................................................ 44
10.1.2 Single-Ended Input (RF_IN) ..................................................................................................... 45
10.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 46
10.2.1 External Mode ........................................................................................................................... 46
10.2.2 XTAL_IN Impedance in External Mode .................................................................................... 46
10.2.3 Clock Timing Accuracy ............................................................................................................. 46
10.2.4 Clock Start-Up Delay ................................................................................................................ 47
10.2.5 Input Frequencies and PS Key Settings ................................................................................... 48
10.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 49
10.3.1 XTAL Mode ............................................................................................................................... 49
10.3.2 Load Capacitance ..................................................................................................................... 50
10.3.3 Frequency Trim ......................................................................................................................... 51
10.3.4 Transconductance Driver Model ............................................................................................... 52
10.3.5 Negative Resistance Model ...................................................................................................... 52
10.3.6 Crystal PS Key Settings ............................................................................................................ 53
10.3.7 Crystal Oscillator Characteristics .............................................................................................. 53
10.4 UART Interface ...................................................................................................................................... 56
10.4.1 UART Bypass ........................................................................................................................... 58
10.4.2 UART Configuration While RESET is Active ............................................................................ 58
10.4.3 UART Bypass Mode ................................................................................................................. 58
10.4.4 Current Consumption in UART Bypass Mode .......................................................................... 58
10.5 USB Interface ........................................................................................................................................ 59
10.5.1 USB Data Connections ............................................................................................................. 59
10.5.2 USB Pull-Up Resistor ............................................................................................................... 59
10.5.3 Power Supply ............................................................................................................................ 59
10.5.4 Self-Powered Mode .................................................................................................................. 60
10.5.5 Bus-Powered Mode .................................................................................................................. 61
10.5.6 Suspend Current ....................................................................................................................... 62
13
14
15
16
17
18
19
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 4 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
11
12
10.5.7 Detach and Wake_Up Signalling .............................................................................................. 62
10.5.8 USB Driver ................................................................................................................................ 62
10.5.9 USB 1.1 Compliance ................................................................................................................ 63
10.5.10 USB 2.0 Compatibility ............................................................................................................... 63
10.6 Serial Peripheral Interface ..................................................................................................................... 64
10.6.1 Instruction Cycle ....................................................................................................................... 64
10.6.2 Writing to BlueCore4-ROM Plug-n-Go ...................................................................................... 65
10.6.3 Reading from BlueCore4-ROM Plug-n-Go ............................................................................... 65
10.6.4 Multi-Slave Operation ............................................................................................................... 65
10.7 PCM CODEC Interface .......................................................................................................................... 66
10.7.1 PCM Interface Master/Slave ..................................................................................................... 67
10.7.2 Long Frame Sync ..................................................................................................................... 68
10.7.3 Short Frame Sync ..................................................................................................................... 68
10.7.4 Multi-slot Operation ................................................................................................................... 69
10.7.5 GCI Interface ............................................................................................................................ 69
10.7.6 Slots and Sample Formats ....................................................................................................... 70
10.7.7 Additional Features ................................................................................................................... 70
10.7.8 PCM Timing Information ........................................................................................................... 71
10.7.9 PCM Configuration ................................................................................................................... 76
10.8 I/O Parallel Ports ................................................................................................................................... 78
10.8.1 PIO Defaults for BlueCore4-ROM Plug-n-Go ........................................................................... 78
10.9 I2C Interface .......................................................................................................................................... 79
10.10 TCXO Enable OR Function ................................................................................................................... 80
10.11 RESET and RESETB ............................................................................................................................ 81
10.11.1 Pin States on Reset .................................................................................................................. 82
10.11.2 Status after Reset ..................................................................................................................... 82
10.12 Power Supply ........................................................................................................................................ 83
10.12.1 Voltage Regulator (Plug-n-Go) ................................................................................................. 83
10.12.2 Sequencing ............................................................................................................................... 83
10.12.3 Sensitivity to Disturbances ........................................................................................................ 83
10.12.4 VREG_EN Pin .......................................................................................................................... 83
Product Reliability Tests .............................................................................................................................. 84
Product Reliability Tests for BlueCore4-ROM Plug-n-Go Automotive ..................................................... 85
12.1 AEC-Q100 ............................................................................................................................................. 85
Application Schematic .................................................................................................................................. 86
Package Dimensions .................................................................................................................................... 87
14.1 10 x 10 LFBGA 96-Ball 1.6mm Package .............................................................................................. 87
Ordering Information .................................................................................................................................... 88
15.1 BlueCore4-ROM Plug-n-Go ................................................................................................................... 88
Contact Information ...................................................................................................................................... 89
Document References .................................................................................................................................. 90
Terms and Definitions .................................................................................................................................. 91
Document History ......................................................................................................................................... 94
List of Figures
BlueCore4-ROM Plug-n-Go 10 x 10mm LFBGA Package ........................................................... 9
BlueCore4-ROM Plug-n-Go Device Diagram ............................................................................. 32
BlueCore HCI Stack.................................................................................................................... 36
BlueCore RFCOMM Stack.......................................................................................................... 39
Virtual Machine ........................................................................................................................... 41
HID Stack.................................................................................................................................... 42
Circuit for RF_CONNECT ........................................................................................................... 44
Circuit RF_IN .............................................................................................................................. 45
TCXO Clock Accuracy ................................................................................................................ 46
Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting.................................. 47
Crystal Driver Circuit ................................................................................................................... 49
Crystal Equivalent Circuit............................................................................................................ 49
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency...................... 53
Crystal Driver Transconductance vs. Driver Level Register Setting ........................................... 54
Crystal Driver Negative Resistance as a Function of Drive Level Setting .................................. 55
Universal Asynchronous Receiver .............................................................................................. 56
Break Signal................................................................................................................................ 57
UART Bypass Architecture ......................................................................................................... 58
USB Connections for Self-Powered Mode.................................................................................. 60
USB Connections for Bus-Powered Mode.................................................................................. 61
USB_DETACH and USB_WAKE_UP Signal.............................................................................. 62
Write Operation........................................................................................................................... 65
Read Operation........................................................................................................................... 65
BlueCore4-ROM Plug-n-Go as PCM Interface Master ............................................................... 67
BlueCore4-ROM Plug-n-Go as PCM Interface Slave ................................................................. 67
Long Frame Sync (Shown with 8-bit Companded Sample) ........................................................ 68
Short Frame Sync (Shown with 16-bit Sample) .......................................................................... 68
Multi-slot Operation with Two Slots and 8-bit Companded Samples .......................................... 69
GCI Interface............................................................................................................................... 69
16-Bit Slot Length and Sample Formats ..................................................................................... 70
PCM Master Timing Long Frame Sync....................................................................................... 72
PCM Master Timing Short Frame Sync ...................................................................................... 72
PCM Slave Timing Long Frame Sync......................................................................................... 74
PCM Slave Timing Short Frame Sync ........................................................................................ 74
Example EEPROM Connection .................................................................................................. 79
Example TXCO Enable OR Function.......................................................................................... 80
Application Circuit for Radio Characteristics Specification ......................................................... 86
BlueCore4-ROM Plug-n-Go 96-Ball LFBGA 1.6mm Package Dimensions ................................ 87
List of Tables
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
External Clock Specifications...................................................................................................... 46
PS Key Values for CDMA/3G Phone TCXO Frequencies .......................................................... 48
Crystal Specification ................................................................................................................... 50
Possible UART Settings.............................................................................................................. 56
Standard Baud Rates.................................................................................................................. 57
USB Interface Component Values .............................................................................................. 60
Instruction Cycle for an SPI Transaction..................................................................................... 64
PCM Master Timing .................................................................................................................... 71
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 5 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 3.1
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10
Figure 10.11
Figure 10.12
Figure 10.13
Figure 10.14
Figure 10.15
Figure 10.16
Figure 10.17
Figure 10.18
Figure 10.19
Figure 10.20
Figure 10.21
Figure 10.22
Figure 10.23
Figure 10.24
Figure 10.25
Figure 10.26
Figure 10.27
Figure 10.28
Figure 10.29
Figure 10.30
Figure 13.1
Figure 14.1
Table 10.9
Table 10.10
Table 10.11
Table 10.12
PCM Slave Timing ...................................................................................................................... 73
PSKEY_PCM_CONFIG32 Description ....................................................................................... 77
PSKEY_PCM_LOW_JITTER_CONFIG Description................................................................... 77
Pin States of BlueCore4-ROM Plug-n-Go on Reset ................................................................... 82
List of Equations
Load Capacitance ....................................................................................................................... 50
Trim Capacitance........................................................................................................................ 51
Frequency Trim........................................................................................................................... 51
Pullability..................................................................................................................................... 51
Transconductance Required for Oscillation ................................................................................ 52
Equivalent Negative Resistance ................................................................................................. 52
Baud Rate ................................................................................................................................... 57
PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock....................... 75
PCM_SYNC Frequency Relative to PCM_CLK .......................................................................... 75
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 6 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Equation 10.1
Equation 10.2
Equation 10.3
Equation 10.4
Equation 10.5
Equation 10.6
Equation 10.7
Equation 10.8
Equation 10.9
Status Information
1
Status Information
The status of this Data Sheet is Advance Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-Critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done
at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
RoHS Compliance
BlueCore4-ROM Plug-n-Go devices meet the requirements of Directive 2002/95/EC of the European Parliament and
of the Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Patents and Licenses
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by Cambridge
Silicon Radio Limited or its affiliates. Bluetooth® and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc.
and licensed to CSR. Other products, services and names used in this document may have been trademarked by their
respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by Cambridge Silicon Radio Limited.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 7 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Pre-Production Information
Key Features
2
Key Features
Baseband and Software
Radio
Direct 50Ω connection to a common TX/RX antenna ƒ
ƒ
Bluetooth v2.0+EDR specification compliant
ƒ
Extensive built-in self-test minimises production test
time
ƒ
No external trimming is required in production
ƒ
Antenna matching and filtering within IC
Internal programmed 4Mbit ROM for complete
system solution
ƒ
48kbyte on-chip RAM allows full speed Bluetooth
data transfer, mixed voice and data, plus full seven
slave piconet operation
ƒ
Logic for forward error correction, header error
control, access code correlation, demodulation,
CRC, encryption bitstream generation, whitening
and transmit pulse shaping
Transcoders for A-law, µ-law and linear voice from
host and A-law, µ-law and CVSD voice over air
Transmitter
ƒ
+6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
ƒ
ƒ
Class 2 and Class 3 support without the need for an
external power amplifier or TX/RX switch
Physical Interfaces
Receiver
ƒ
Synchronous serial interface up to 4M baud for
system debugging
ƒ
Integrated channel filters
ƒ
ƒ
Digital demodulator for improved sensitivity and
co-channel rejection
UART interface with programmable baud rate up to
3M baud with an optional bypass mode
ƒ
ƒ
Real time digitised RSSI available on HCI interface
Full speed USB interface supports OHCI and UHCI
host interfaces. Compliant with USB v2.0
ƒ
Fast AGC for enhanced dynamic range
ƒ
Synchronous bi-directional serial programmable
audio interface
ƒ
Optional I2C™ compatible interface
Synthesiser
ƒ
Fully integrated synthesiser requires no external
VCO varactor diode, resonator or loop filter
Bluetooth Stack
ƒ
Compatible with crystals between 8 and 32MHz (in
multiples of 250kHz) or an external clock
CSR's Bluetooth Protocol Stack runs on-chip in a variety
of configurations:
ƒ
Accepts 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44,
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic
level signals
ƒ
Standard HCI (UART or USB)
ƒ
Fully embedded to RFCOMM
ƒ
Customer specific builds with embedded application
code
Auxiliary Features
Package Options
ƒ
Crystal oscillator with built-in digital trimming
ƒ
Power management includes digital shutdown, and
wake up commands with an integrated low power
oscillator for ultra low Park/Sniff/Hold mode
ƒ
Clock request output to control external clock
ƒ
On-chip linear regulator, producing 1.8V output from
2.2V to 4.2V input
ƒ
Power on reset cell detects low supply voltage
ƒ
Arbitrary power supply sequencing permitted
ƒ
8-bit ADC and DAC available to application
BC41B143A-ds-003Pc
ƒ
96-ball LFBGA 10 x 10 x 1.6mm 0.8mm pitch
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 8 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
ƒ
Package Information
3
3.1
Package Information
BC41B143A Pinout Diagram
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 3.1: BlueCore4-ROM Plug-n-Go 10 x 10mm LFBGA Package
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 9 of 94
Package Information
3.2
BC41B143A-ANN-E4 Device Terminal Functions
Ball
Pad Type
Description
RF_IN
D2
Analogue
Single ended receiver input
PIO[0]/RXEN
D3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[1]/TXEN
C4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
BAL_MATCH
A1
Analogue
Tie to VSS_RADIO
RF_CONNECT
B1
Analogue
50Ω RF matched I/O
AUX_DAC
C2
Analogue
Voltage DAC output
Synthesiser and
Oscillator
Ball
Pad Type
Description
XTAL_IN
L3
Analogue
For crystal or external clock input
XTAL_OUT
L4
Analogue
Drive for crystal
PCM Interface
Ball
Pad Type
Description
PCM_OUT
G10
CMOS output, tristatable with
weak internal pull-down
Synchronous data output
PCM_IN
H11
CMOS input, with weak
internal pull-down
Synchronous data input
PCM_SYNC
G11
Bi-directional with weak
internal pull-down
Synchronous data sync
PCM_CLK
H10
Bi-directional with weak
internal pull-down
Synchronous data clock
USB and UART
Ball
Pad Type
Description
UART_TX
J10
CMOS output, tri-state with
weak internal pull-up
UART data output active low
UART_RX
J11
CMOS input with weak internal
pull-down
UART data input active low (idle status high)
UART_RTS
L11
CMOS output, tristatable with
weak internal pull-up
UART request to send active low
UART_CTS
K11
CMOS input with weak internal
pull-down
UART clear to send active low
USB_DP
L9
Bi-directional
USB data plus with selectable internal 1.5kΩ
pull-up resistor
USB_DN
L8
Bi-directional
USB data minus
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 10 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Radio
Package Information
Test and Debug
Ball
Pad Type
Description
F9
CMOS input with weak internal
pull-down
Reset if high. Input debounced so must be
high for >5ms to cause a reset
RESETB
G9
CMOS input with weak internal
pull-up
Reset if low. Input debounced so must be low
for >5ms to cause a reset
SPI_CSB
C10
CMOS input with weak internal
pull-up
Chip select for Serial Peripheral Interface,
active low
SPI_CLK
D10
CMOS input with weak internal
pull-down
Serial Peripheral Interface clock
SPI_MOSI
D11
CMOS input with weak internal
pull-down
Serial Peripheral Interface data input
SPI_MISO
C11
CMOS output, tristatable with
weak internal pull-down
Serial Peripheral Interface data output
TEST_EN
E9
CMOS input with strong
internal pull-down
For test purposes only (leave unconnected)
FLASH_EN
B10
No connect
Not available for BlueCore4-ROM Plug-n-Go
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 11 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
RESET
Package Information
Ball
Pad Type
Description
PIO[2]
C3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[3]
B2
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[4]
H9
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[5]
J8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[6]
K8
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[7]
K9
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[8]
B3
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[9]
B4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[10]
A4
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
PIO[11]
A5
Bi-directional with
programmable strength
internal pull-up/down
Programmable input/output line
AIO[0]
K5
Bi-directional
Programmable input/output line
AIO[1]
J6
Bi-directional
Programmable input/output line
AIO[2]
K7
Bi-directional
Programmable input/output line
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PIO Port
Page 12 of 94
Package Information
Power Supplies and
Control
Ball
Pad Type
Description
L7
Regulator input
Linear regulator voltage input
VREG_EN
J2
Digital input
Active high, regulator enable pin with internal
pull-up
VDD_USB
L10
VDD
Positive supply for UART/USB and AIO ports
VDD_PIO
A3
VDD
Positive supply for PIO and AUX DAC(a)
VDD_PADS
E11
VDD
Positive supply for all other digital
input/output ports(b)
VDD_DIG
L6
Regulator output
Positive 1.8V supply output for VDD_MEM
and VDD_CORE
VDD_MEM
B11,
K6
VDD
Positive supply for internal memory
VDD_CORE
F11
VDD
Positive supply for internal digital circuitry
VDD_RADIO
E3
VDD
Positive supply for RF circuitry
VDD_ANA
L5
VDD/Regulator output
Positive supply for analogue circuitry and
1.8V regulated output
VDD_BALUN
F1
VDD
Positive supply for balun
VSS_PADS
A2,
E10,
K10
VSS
Ground connection for input/output
VSS_MEM
D9, J9
VSS
Ground connections for AIO and Extended
PIO ports
VSS_CORE
F10
VSS
Ground connection for internal digital circuitry
VSS_RADIO
E2, F3,
G2
VSS
Ground connections for RF circuitry
VSS_VCO
G3, H2
H3
VSS
Ground connections for VCO and
synthesiser
VSS_ANA
K4
VSS
Ground connection for analogue circuitry
G1,J1,
K1
VSS
Ground connection for balun
VSS_BALUN
(a)
(b)
Positive supply for PIO[3:0] and PIO[11:8]
Positive supply for SPI/PCM ports and PIO[7:4]
Unconnected Terminals
Ball
Description
N/C
A6, A7, A8, A9, A10, A11, B5, B6, B7,
B8, B9, C1, C5, C6, C7, C8, C9, D1, E1,
F2, H1, J3, J4, J5, J7, K2, K3, L1, L2
Leave unconnected
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 13 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
VREG_IN
Electrical Characteristics
4
Electrical Characteristics
Absolute Maximum Ratings
Rating
Max
Storage Temperature
-40°C
+150°C
Supply Voltage: VDD_RADIO, VDD_ANA, VDD_BAL
and VDD_CORE
-0.4V
2.2V
Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and
VDD_USB
-0.4V
3.7V
Supply Voltage: VREG_IN
-0.4V
5.6V
VSS-0.4V
VDD+0.4V
Min
Max
Operating Temperature Range
-40°C
+85°C
Guaranteed RF performance range (a)
-25°C
+85°C
Supply Voltage: VDD_RADIO, VDD_ANA and
VDD_CORE
1.7V
1.9V
Supply Voltage: VDD_MEM, VDD_PADS, VDD_PIO and
VDD_USB
1.7V
3.6V
Supply Voltage: VREG_IN
2.2V
4.2V(b)
Other Terminal Voltages
Recommended Operating Conditions
Operating Condition
(a)
(b)
Typical figures are given for RF performance between -40°C and +85°C.
The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed
above 4.2V.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 14 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
Electrical Characteristics
Input/Output Terminal Characteristics (Supply)
Linear Regulator
Min
Typ
Max
Unit
Output Voltage(a) (Iload = 70 mA)
1.70
1.78
1.85
V
Temperature Coefficient
-250
-
+250
ppm/°C
-
-
1
mV rms
Load Regulation (Iload < 100 mA)
-
-
50
mV/A
Settling Time(b) (d)
-
-
50
µs
140
-
-
mA
5
-
-
µA
Normal Operation
Output
Noise(b) (c)
Minimum Load Current
Input Voltage
-
-
4.2(e)
Dropout Voltage (Iload = 70 mA)
-
-
350
mV
25
35
50
µA
4
7
10
µA
1.5
2.5
3.5
µA
Quiescent Current (excluding Ioad, Iload < 1mA)
Low Power
V
Mode(f)
Quiescent Current (excluding Ioad, Iload < 100µA)
Disabled Mode(g)
Quiescent Current
(a)
(b)
(c)
(d)
(e)
(f)
(g)
For optimum performance, the VDD_ANA ball adjacent to VREG_IN should be used for regulator output,
Regulator output connected to 47nF pure and 4.7µF 2.2Ω ESR capacitors.
Frequency range is 100Hz to 100kHz.
1mA to 70mA pulsed load.
Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest
of BlueCore4-ROM Plug-n-Go, but output regulation and other specifications are no longer guaranteed at input voltages
in excess of 4.2V.
Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode.
Regulator is disabled when VREG_EN is pulled low. It is also disabled when VREG_IN is either open circuit or driven to
the same voltage as VDD_ANA.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 15 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Maximum Output Current
Electrical Characteristics
Input/Output Terminal Characteristics (Digital)
Digital Terminals
Min
Typ
Max
Unit
2.7V ≤ VDD ≤ 3.0V
-0.4
-
+0.8
V
1.7V ≤ VDD ≤ 1.9V
-0.4
-
+0.4
V
0.7VDD
-
VDD+0.4
V
-
-
0.2
V
-
-
0.4
V
VDD-0.2
-
-
V
VDD-0.4
-
-
V
Strong pull-up
-100
-40
-10
µA
Strong pull-down
+10
+40
+100
µA
Weak pull-up
-5.0
-1.0
-0.2
µA
Weak pull-down
+0.2
+1.0
+5.0
µA
I/O pad leakage current
-1
0
+1
µA
CI Input Capacitance
1.0
-
5.0
pF
Input Voltage Levels
VIL input logic level low
VIH input logic level high
VOL output logic level low,
(lo = 4.0mA), 2.7V ≤ VDD ≤ 3.0V
VOL output logic level low,
(lo = 4.0mA), 1.7V ≤ VDD ≤ 1.9V
VOH output logic level high,
(lo = -4.0mA), 2.7V ≤ VDD ≤ 3.0V
VOH output logic level high,
(lo = -4.0mA), 1.7V ≤ VDD ≤ 1.9V
Input and Tri-state Current with:
Input/Output Terminal Characteristics (USB)
USB Terminals
Min
VDD_USB for correct USB operation
3.1
Typ
Max
Unit
3.6
V
Input Threshold
VIL input logic level low
-
-
0.3VDD_USB
V
VIH input logic level high
0.7VDD_USB
-
-
V
VSS_PADS < VIN < VDD_USB(a)
-1
1
5
µA
CI Input capacitance
2.5
-
10.0
pF
VOL output logic level low
0.0
-
0.2
V
VOH output logic level high
2.8
-
VDD_USB
V
Input Leakage Current
Output Voltage Levels to Correctly Terminated
USB Cable
(a)
Internal USB pull-up disabled
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 16 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Output Voltage Levels
Electrical Characteristics
Input/Output Terminal Characteristics (Reset)
Min
Typ
Max
Unit
VDD_CORE falling threshold
1.40
1.50
1.60
V
VDD_CORE rising threshold
1.50
1.60
1.70
V
Hysteresis
0.05
0.10
0.15
V
Min
Typ
Max
Unit
-
-
8
Bits
0
-
VDD_ANA
V
Input/Output Terminal Characteristics (Auxilliary ADC)
Auxiliary ADC
Resolution
Input voltage range
(LSB size = VDD_ANA/255)
Accuracy
INL
-1
-
1
LSB
(Guaranteed monotonic)
DNL
0
-
1
LSB
-1
-
1
LSB
-0.8
-
0.8
%
Input Bandwidth
-
100
-
kHz
Conversion time
-
2.5
-
µs
Sample rate(a)
-
-
700
Samples/s
Offset
Gain Error
(a)
ADC is accessed through the VM function. The sample rate given is achieved as part of this function.
Input/Output Terminal Characteristics (Auxilliary DAC)
Auxiliary DAC
Resolution
Average output step size(a)
Min
Typ
Max
Unit
-
-
8
Bits
12.5
14.5
17.0
mV
monotonic(a)
Output Voltage
Voltage range (IO=0mA)
VSS_PADS
-
VDD_PIO
V
-10.0
-
+0.1
mA
Minimum output voltage (IO=100µA)
0.0
-
0.2
V
Maximum output voltage (IO=10mA)
VDD_PIO-0.3
-
VDD_PIO
V
-1
-
+1
µA
-220
-
+120
mV
Integral non-linearity(a)
-2
-
+2
LSB
Settling time (50pF load)
-
-
10
µs
Current range
High Impedance leakage current
Offset
(a)
Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Output is high impedance when chip is in Deep Sleep
mode.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 17 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Power-on Reset
Electrical Characteristics
Input/Output Terminal Characteristics (Clocks)
Crystal Oscillator
Typ
Max
Unit
8.0
-
32.0
MHz
Digital trim range(b)
5.0
6.2
8.0
pF
-
0.1
-
pF
2.0
-
-
mS
870
1500
2400
Ω
7.5
-
40.0
MHz
0.2
-
VDD_ANA
V pk-pk
Allowable Jitter
-
-
15
ps rms
XTAL_IN input impedance
-
-
-
kΩ
XTAL_IN input capacitance
-
7
-
pF
Crystal
Trim step size(b)
Transconductance
Negative
resistance(c)
External Clock
Input frequency(d)
Clock input
(a)
(b)
(c)
(d)
(e)
level(e)
Integer multiple of 250kHz
The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.
XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
Clock input can be any frequency between 8MHz and 40MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of
7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA.
A DC blocking capacitor is required between the signal and XTAL_IN.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 18 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
frequency(a)
Electrical Characteristics
4.1
Power Consumption
Typical Average Current Consumption
VDD=1.8V
Temperature = +20°C
Mode
Output Power = +4dBm
Unit
SCO connection HV3 (30ms interval Sniff Mode) (Slave)
21
mA
SCO connection HV3 (30ms interval Sniff Mode) (Master)
21
mA
SCO connection HV3 (No Sniff Mode) (Slave)
28
mA
SCO connection HV1 (Slave)
42
mA
SCO connection HV1 (Master)
42
mA
ACL data transfer 115.2kbps UART no traffic (Master)
5
mA
ACL data transfer 115.2kbps UART no traffic (Slave)
22
mA
ACL data transfer 720kbps UART (Master or Slave)
45
mA
ACL data transfer 720kbps USB (Master or Slave)
45
mA
ACL connection, Sniff Mode 40ms interval, 38.4kbps UART
3.2
mA
ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART
0.45
mA
Parked Slave, 1.28s beacon interval, 38.4kbps UART
0.55
mA
Standby Mode (Connected to host, no RF activity)
47.0
µA
Reset (RESET high or RESETB low)
15.0
µA
Typical Peak Current at +20°C
Device Activity/State
Current (mA)
Peak Current during cold boot (100ms sampling interval)
-
Peak TX Current Average across burst)
-
Peak RX Current
-
Average RX Current across burst
-
Conditions
VREG_IN, VDD_PIO, VDD_PADS
-
Host Interface
-
Baud Rate
-
Clock Source
-
Output Power
-
Receive Sensitivity
-
Device Mode
-
Packet Type
-
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 19 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Average
Radio Characteristics - Basic Data Rate
5
Radio Characteristics - Basic Data Rate
5.1
Temperature +20°C
5.1.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Bluetooth
Specification
Typ
Max
TBD
2.5
-
-
1.5
TBD
-
dB
-
2.5
TBD
-
dB
25
35
-
≥16
dB
RF power range control resolution(e)
-
0.5
1.2
-
dB
20dB bandwidth for modulated carrier
-
780
1000
≤1000
kHz
-
-40
-20
≤-20
dBm
-
-45
-40
≤-40
dBm
-50
-40
≤-40
dBm
Maximum RF transmit power(a) (b)
RF power variation over temperature
range with compensation enabled (±)
-6 to +4(c)
Unit
dBm
(d)
RF power variation over temperature
range with compensation disabled (±)(d)
RF power control range
Adjacent channel transmit power
F = F0 ± 2MHz(f) (g)
Adjacent channel transmit power
F = F0 ± 3MHz(f) (g)
Adjacent channel transmit power
F = F0 ± > 3MHz(f) (g)
∆f1avg Maximum Modulation
140
165
175
140<f1avg<175
kHz
∆f2max Minimum Modulation
115
150
-
115
kHz
∆f1avg/∆f2avg
0.8
0.97
-
≥0.80
-
Initial carrier frequency tolerance
-
6
±75
±75
kHz
Drift Rate
-
8
20
≤20
kHz/50µs
Drift (single slot packet)
-
7
25
≤25
kHz
Drift (five slot packet)
-
9
40
≤40
kHz
2nd
Harmonic Content
-
TBD
-30
≤30
dBm
3rd Harmonic Content
-
TBD
-40
≤30
dBm
(a)
(b)
(c)
(d)
(e)
(f)
(g)
The BlueCore4-ROM Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits.
Measurement made using a PSKEY_LC_MAX_TX_POWER setting corresponds to a PSKEY_LC_POWER_TABLE
power table entry of 63
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
To some extent these parameters are dependent on the matching circuit used, and its behaviour over temperature.
Therefore these parameters may be beyond CSR's direct control.
Resolution guaranteed over the range -5dB to -25dB relative to maximum power for Tx Level > 20
Measured at F0 = 2441MHz
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-ROM Plug-n-Go is guaranteed
to meet the ACP performance as specified by the Bluetooth specification v2.0+EDR
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 20 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
Radio Characteristics - Basic Data Rate
Radio Characteristics
VDD = 1.8V
Frequency (GHz)
Typ
Max
Cellular Band
-
TBD
TBD
GSM 850
0.869 - 0.894(b)
-
TBD
TBD
CDMA 850
0.925 - 0.960(a)
-
TBD
TBD
GSM 900
1.580(c)
-
TBD
TBD
GPS
1.805 - 1.880(a)
-
TBD
TBD
GSM 1800 /
DCS 1800
1.930 - 1.990(d)
-
TBD
TBD
PCS 1900
1.930 - 1.990(b)
-
TBD
TBD
GSM 1900
1.930 - 1.990(a)
-
TBD
TBD
CDMA 1900
2.110 -
2.170(b)
-
TBD
TBD
W-CDMA 2000
2.110 -
2.170(e)
-
TBD
TBD
W-CDMA 2000
1.570 -
(a)
(b)
(c)
(d)
(e)
Unit
dBm / Hz
Integrated in 200kHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 1.2MHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 1MHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 30kHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 5MHz bandwidth and then normalised to 1Hz bandwidth
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 21 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
0.894(a)
0.869 -
Emitted power in cellular
bands measured at
RF_CONNECT. Output
power ≤4dBm
Temperature = +20°C
Radio Characteristics - Basic Data Rate
5.1.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Min
Typ
Max
2.402
-
-84
TBD
2.441
-
-84
TBD
2.480
-
-86
TBD
Maximum received signal at 0.1% BER
-20
TBD
Frequency
(MHz)
Min
30-2000
Bluetooth
Specification
Unit
≤-70
dBm
-
≥-20
dBm
Typ
Max
Bluetooth
Specification
Unit
-10
TBD
-
-10
2000-2400
-27
TBD
-
-27
2500-3000
-27
TBD
-
-27
3000-3300
-10
TBD
-
-10
-
6
11
≤11
dB
-
-5
0
≤0
dB
-
-4
0
≤0
dB
-
-38
-30
≤-30
dB
-
-23
-20
≤-20
dB
-
-45
-40
≤-40
dB
-
-44
-40
≤-40
dB
-
-22
-9
≤-9
dB
-39
TBD
-
≥-39
dBm
-
TBD
-
-
dBm/Hz
Sensitivity at 0.1% BER
for all packet types
Continuous power
required to block
Bluetooth reception (for
input power of -67dBm
with 0.1% BER)
measured at the
unbalanced port of the
balun.
C/I co-channel
Adjacent channel selectivity C/I
F = F0 + 1MHz(a) (b)
Adjacent channel selectivity C/I
F = F0 - 1MHz(a) (b)
Adjacent channel selectivity C/I
F = F0 + 2MHz(a) (b)
Adjacent channel selectivity C/I
F = F0 - 2MHz(a) (b)
Adjacent channel selectivity C/I
F ≥ F0 + 3MHz(a) (b)
Adjacent channel selectivity C/I
F ≤ F0 -5MHz(a) (b)
Adjacent channel selectivity C/I
F = FImage(a) (b)
Maximum level of intermodulation
interferers(c)
Spurious output level(d)
(a)
(b)
(c)
(d)
dBm
Up to five exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-ROM Plug-n-Go is guaranteed
to meet the C/I performance as specified by the Bluetooth specification v2.0+EDR.
Measured at F = 2441MHz
Measured at f1 - f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test RCV/CA/05/c., i.e., wanted
signal at -64dBm.
Measured at RF_CONNECT. Integrated in 100kHz bandwidth and normalised to 1Hz. Figure is typically below
TBDdBm/Hz except for peaks of TBDdBm at 1.6GHz, TBDdBm inband at 2.4GHz and TBDdBm at 3.2GHz.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 22 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Frequency
(GHz)
Radio Characteristics - Basic Data Rate
Radio Characteristics
Continuous power in
cellular bands required to
block Bluetooth reception
(for input power of -72dBm
with 0.1% BER) measured
at RF_CONNECT. TBD
(a)
Temperature = +20°C
Frequency
(GHz)
Min
0.824 - 0.849
-
0.824 - 0.849
Typ
Max
Cellular Band
TBD(a)
-
GSM 850
-
TBD
-
CDMA 850
0.880 - 0.915
-
TBD
-
GSM 900
1.710 - 1.785
-
TBD
-
GSM 1800 /
DCS 1800
1.850 - 1.910
-
TBD
-
GSM 1900 /
PCS 1900
1.850 - 1.910
-
TBD
-
CDMA 1900
1.920 - 1.980
-
TBD
-
W-CDMA 2000
0.824 - 0.849
-
TBD
-
GSM 850
0.824 - 0.849
-
TBD
-
CDMA 850
0.880 - 0.915
-
TBD
-
GSM 900
1.710 - 1.785
-
TBD
-
GSM 1800 /
DCS 1800
1.850 - 1.910
-
TBD
-
GSM 1900 /
PCS 1900
1.850 - 1.910
-
TBD
-
CDMA 1900
1.920 - 1.980
-
TBD
-
W-CDMA 2000
Unit
dBm
dBm
TBD dBm if fBLOCKING< 0.831GHz
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 23 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Continuous power in
cellular bands required to
block Bluetooth reception
(for input power of -67dBm
with 0.1% BER) measured
at RF_CONNECT.
VDD = 1.8V
Radio Characteristics - Basic Data Rate
5.2
Temperature -40°C
5.2.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -40°C
Bluetooth
Specification
Min
Typ
Max
TBD
3.5
-
25
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
780
1000
≤1000
kHz
-
-40
-20
≤-20
dBm
-
-45
-40
≤-40
dBm
∆f1avg Maximum Modulation
140
165
175
140<∆f1avg<175
kHz
∆f2max Minimum Modulation
115
151
-
115
kHz
∆f2avg/∆f1avg
0.8
0.97
-
≥0.80
-
Initial carrier frequency tolerance
-
10
±75
±75
kHz
Drift Rate
-
7
20
≤20
kHz/50µs
Drift (single slot packet)
-
8
25
≤25
kHz
Drift (five slot packet)
-
12
40
≤40
kHz
Maximum RF transmit power(a)
Adjacent channel transmit power
F = F0± 2MHz(c) (d)
Adjacent channel transmit power
F = F0± 3MHz(c) (d)
(a)
(b)
(c)
(d)
5.2.2
dBm
BlueCore4-ROM Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits.
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
Measured at F0 = 2441MHz
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification.
Receiver
Radio Characteristics
Sensitivity at 0.1% BER
for all packet types
VDD = 1.8V
Frequency
(GHz)
Min
Typ
Max
2.402
-
-86
TBD
2.441
-
-86
TBD
2.480
-
-88
TBD
-20
TBD
-
Maximum received signal at 0.1% BER
BC41B143A-ds-003Pc
Temperature = -40°C
Advance Information
© Cambridge Silicon Radio Limited 2005
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 24 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
RF power control range
-6 to +4(b)
Unit
Radio Characteristics - Basic Data Rate
5.3
Temperature -25°C
5.3.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -25°C
Bluetooth
Specification
Unit
-6 to +4(b)
dBm
Typ
Max
TBD
3.0
-
25
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
780
1000
≤1000
kHz
-
-40
-20
≤-20
dBm
-
-45
-40
≤-40
dBm
∆f1avg Maximum Modulation
140
165
175
140<∆f1avg<175
kHz
∆f2max Minimum Modulation
115
151
-
115
kHz
∆f2avg/∆f1avg
0.8
0.97
-
≥0.80
-
Initial carrier frequency tolerance
-
8
±75
±75
kHz
Drift Rate
-
7
20
≤20
kHz/50µs
Drift (single slot packet)
-
8
25
≤25
kHz
Drift (five slot packet)
-
12
25
≤40
kHz
Maximum RF transmit power(a)
RF power control range
Adjacent channel transmit power
F = F0± 2MHz(c) (d)
Adjacent channel transmit power
F = F0± 3MHz(c) (d)
(a)
(b)
(c)
(d)
5.3.2
BlueCore4-ROM Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits.
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
Measured at F0 = 2441MHz
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification.
Receiver
Radio Characteristics
Sensitivity at 0.1% BER
for all packet types
VDD = 1.8V
Frequency
(GHz)
Min
Typ
Max
2.402
-
-86
TBD
2.441
-
-86
TBD
2.480
-
-87
TBD
-2 0
TBD
-
Maximum received signal at 0.1% BER
BC41B143A-ds-003Pc
Temperature = -25°C
Advance Information
© Cambridge Silicon Radio Limited 2005
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 25 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
Radio Characteristics - Basic Data Rate
5.4
Temperature +85°C
5.4.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +85°C
Bluetooth
Specification
Unit
-6 to +4(b)
dBm
Typ
Max
TBD
0
-
25
35
-
≥16
dB
RF power range control resolution
-
0.5
-
-
dB
20dB bandwidth for modulated carrier
-
780
1000
≤1000
kHz
-
-40
-20
≤-20
dBm
-
-45
-40
≤-40
dBm
∆f1avg Maximum Modulation
140
165
175
140<∆f1avg<175
kHz
∆f2max Minimum Modulation
115
148
-
115
kHz
∆f2avg/∆f1avg
0.8
0.97
-
≥0.80
-
Initial carrier frequency tolerance
-
7
±75
±75
kHz
Drift Rate
-
7
20
≤20
kHz/50µs
Drift (single slot packet)
-
8
25
≤25
kHz
Drift (five slot packet)
-
9
40
≤40
kHz
Maximum RF transmit power(a)
RF power control range
Adjacent channel transmit power
F = F0± 2MHz(c) (d)
Adjacent channel transmit power
F = F0± 3MHz(c) (d)
(a)
(b)
(c)
(d)
5.4.2
BlueCore4-ROM Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
Measured at F0 = 2441MHz
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification
Receiver
Radio Characteristics
Sensitivity at 0.1% BER
for all packet types
VDD = 1.8V
Frequency
(GHz)
Min
Typ
Max
2.402
-
-81
TBD
2.441
-
-81
TBD
2.480
-
-82
TBD
-20
TBD
-
Maximum received signal at 0.1% BER
BC41B143A-ds-003Pc
Temperature = +85°C
Advance Information
© Cambridge Silicon Radio Limited 2005
Bluetooth
Specification
Unit
≤-70
dBm
≥-20
dBm
Page 26 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
Radio Characteristics - Enhanced Data Rate
6
Radio Characteristics - Enhanced Data Rate
6.1
Temperature +20°C
6.1.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Bluetooth
Specification
Typ
Max
Maximum RF transmit power(a)
-
6
-
-6 to +4(b)
Relative transmit power(c)
-
-1
-
-4 to +1
dB
Carrier frequency stability(c)
-
3
-
≤10
kHz
-
≤13(e)
RMS DEVM
Modulation
(a)
(b)
(c)
(d)
(e)
Accuracy(c) (d)
-
10
99% DEVM
-
15
-
≤20(e)
Peak DEVM
-
20
-
≤25(e)
Unit
dBm
%
%
%
BlueCore4-ROM Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
Measurement methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 27 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Min
Radio Characteristics - Enhanced Data Rate
6.1.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Min
Typ
Max
Bluetooth
Specification
Unit
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
-
-86
-
≤-70
dBm
8DPSK
-
-79
-
≤-70
dBm
Maximum received
signal at 0.1% BER(a)
π/4 DQPSK
-
-6
-
≥-20
dBm
8DPSK
-
-7
-
≥-20
dBm
C/I co-channel at 0.1%
BER(a)
π/4 DQPSK
-
+11
-
≤+13
dB
8DPSK
-
+19
-
≤+21
dB
π/4 DQPSK
-
-8
-
≤0
dB
8DPSK
-
-2
-
≤+5
dB
π/4 DQPSK
-
-8
-
≤0
dB
8DPSK
-
-2
-
≤+5
dB
π/4 DQPSK
-
-35
-
≤-30
dB
8DPSK
-
-35
-
≤-25
dB
π/4 DQPSK
-
-23
-
≤-20
dB
8DPSK
-
-19
-
≤-13
dB
π/4 DQPSK
-
-43
-
≤-40
dB
8DPSK
-
-40
-
≤-33
dB
π/4 DQPSK
-
-43
-
≤-40
dB
8DPSK
-
-38
-
≤-33
dB
π/4 DQPSK
-
-17
-
≤-7
dB
8DPSK
-
-10
-
≤0
dB
Adjacent channel
selectivity
C/I F=F0 +1MHz(a) (b)
(c)
Adjacent channel
selectivity
C/I F=F0 -1MHz (a) (b) (c)
Adjacent channel
selectivity
C/I F=F0 +2MHz(a) (b) (c)
Adjacent channel
selectivity
C/I F=F0 -2MHz(a) (b) (c)
Adjacent channel
selectivity
C/I F≥F0 +3MHz(a) (b) (c)
Adjacent channel
selectivity
C/I F≤F0 5MHz(a) (b) (c)
Adjacent channel
selectivity
C/I F=FImage(a) (b) (c)
(a)
(b)
(c)
Measurements methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
Up to five exceptions are allowed in the Bluetooth v2.0 +EDR RF Test Specification.BlueCore4-ROM Plug-n-Go is
guaranteed to meet the C/I performance as specified by the Bluetooth v2.0 +EDR RF Test Specification
Measured at F0 = 2405MHz, 2441MHz, 2477MHz
Notes:
Results shown are referenced to the unbalanced port of the balun.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 28 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Modulation
Radio Characteristics - Enhanced Data Rate
6.2
Temperature -40°C
6.2.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -40°C
Typ
Max
-
8
-
-6 to +4(b)
-
-1
-
-4 to +1
dB
-
3
-
≤10
kHz
-
10
-
≤13(e)
Maximum RF transmit power(a)
power(c)
Carrier frequency stability(c)
RMS DEVM
Modulation
Accuracy(c) (d)
99% DEVM
-
Peak DEVM
(a)
(b)
(c)
(d)
(e)
-
15
20
Unit
dBm
%
-
≤20(e)
%
-
≤25(e)
%
BlueCore4-ROM Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
Measurements methods are in accordance with the Bluetooth v2.0+EDR RF Test specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.2.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature = -40°C
Modulation
Min
Typ
Max
Bluetooth
Specification
Unit
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
-
-89
-
≤-70
dBm
8DPSK
-
-82
-
≤-70
dBm
Maximum received
signal at 0.1% BER(a)
π/4 DQPSK
-
-10
-
≥-20
dBm
8DPSK
-
-10
-
≥-20
dBm
(a)
Measurements methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 29 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Relative transmit
Bluetooth
Specification
Min
Radio Characteristics - Enhanced Data Rate
6.3
Temperature -25°C
6.3.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = -25°C
Typ
Max
-
7
-
-6 to +4(b)
-
-1
-
-4 to +1
dB
-
3
-
≤10
kHz
-
10
-
≤13(e)
Maximum RF transmit power(a)
power(c)
Carrier frequency stability(c)
RMS DEVM
Modulation
Accuracy(c) (d)
99% DEVM
-
Peak DEVM
(a)
(b)
(c)
(d)
(e)
-
15
20
Unit
dBm
%
-
≤20(e)
%
-
≤25(e)
%
BlueCore4-ROM Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
Measurement methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.3.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature =-25°C
Modulation
Min
Typ
Max
Bluetooth
Specification
Unit
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
-
-87
-
≤-70
dBm
8DPSK
-
-80
-
≤-70
dBm
Maximum received
signal at 0.1% BER(a)
π/4 DQPSK
-
-10
-
≥-20
dBm
8DPSK
-
-10
-
≥20
dBm
(a)
Measurements methods are in accordance with the Bluetooth v2.0 +EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 30 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Relative transmit
Bluetooth
Specification
Min
Radio Characteristics - Enhanced Data Rate
6.4
Temperature +85°C
6.4.1
Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +85°C
Max
-
1
-
-6 to +4(b)
-
-1
-
-4 to +1
dB
-
3
-
≤10
kHz
RMS DEVM
-
10
-
≤13(e)
99% DEVM
-
15
-
≤20(e)
%
-
≤25(e)
%
(a)
stability(c)
Peak DEVM
(a)
(b)
(c)
(d)
(e)
-
20
dBm
%
BlueCore4-ROM Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
Measurement methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.4.2
Receiver
Radio Characteristics
VDD = 1.8V
Temperature = +85°C
Modulation
Min
Typ
Max
Bluetooth
Specification
Unit
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
-
-84
-
≤-70
dBm
8DPSK
-
-77
-
≤-70
dBm
Maximum received
signal at 0.1% BER(a)
π/4 DQPSK
-
0
-
≥-20
dBm
8DPSK
-
-3
-
≥-20
dBm
(a)
Measurements methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 31 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Relative transmit power(c)
Modulation Accuracy(c) (d)
Unit
Typ
Maximum RF transmit power
Carrier frequency
Bluetooth
Specification
Min
AUX
DAC
RF Synthesiser
RF Transmitter
PA
RF Receiver
-45
IQ MOD
+45
Tune
Fref
/N/N+1
RSSI
Loop
Filter
RF
Synthesiser
DAC
ADC
ADC
Interrupt
Controller
TEST_EN
Advance Information
© Cambridge Silicon Radio Limited 2005
Event
Timer
Microcontroller
Physical
Layer
Hardware
Engine
RISC
Microcontroller
Memory
Management
Unit
RAM
Baseband and Logic
Memory
Mapped
Control
Status
Audio PCM
Interface
UART
Synchronous
Serial
Interface
USB
AIO
Programmable I/O
VDD_PIO
VSS_PADS
VSS_MEM
VSS_CORE
VSS_ANA
VSS_VCO
VSS_RADIO
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BC41B143A-ds-003Pc
PIO[1]/TXEN
VDD_RADIO
AUX_DAC
XTAL_IN
VSS_BALUN
XTAL_OUT
RF_CONNECT
VREG_IN
VDD_BALUN
VDD_ANA
ATTENUATOR
VDD_DIG
BAL_MATCH
VREG_EN
Internal
ROM
FLASH_EN
Balun and Filter
VDD_CORE
Demodulator
VDD_MEM
Burst
Mode
Controller
VDD_PADS
VSS_BALUN
Out
RESET
VREG
RESETB
IQ DEMOD
In
VDD_USB
LNA
Clock
Generation
PIO[11]
PIO[10]
PIO[9]
PIO[8]
PIO[7]
PIO[6]
PIO[5]
PIO[4]
PIO[3]
PIO[2]
PCM_CLK
PCM_IN
PCM_SYNC
PCM_OUT
UART_CTS
UART_RX
UART_RTS
UART_TX
SPI_MISO
SPI_CLK
SPI_MOSI
SPI_CSB
USB_DN
USB_DP
7
RF_IN
PIO[0]/RXEN
Device Diagram
Device Diagram
AIO[0]
AIO[1]
AIO[2]
Figure 7.1: BlueCore4-ROM Plug-n-Go Device Diagram
Page 32 of 94
Description of Functional Blocks
8
Description of Functional Blocks
8.1
RF Receiver
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated onto the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the
radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division
Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift
Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence
of noise allows BlueCore4-ROM Plug-n-Go to exceed the Bluetooth requirements for co-channel and adjacent channel
rejection.
8.1.1
Low Noise Amplifier
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1(1)
Bluetooth operation; differential mode is used for Class 2 operation.
8.1.2
Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples
the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed
according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the
dynamic range of the receiver, improving performance in interference limited environments.
8.2
RF Transmitter
8.2.1
IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
8.2.2
Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm. This allows BlueCore4-ROM Plug-n-Go to
be used in Class 2 and Class 3 radios without an external RF PA.
8.2.3
Auxiliary DAC
An 8-bit voltage Auxiliary DAC is provided for power control of an external PA for Class 1 operation or any other
customer specific application.
8.3
Balun and Filter
The Plug-n-Go device incorporates a balun and filter to provide a 50Ω unbalanced antenna port.
8.4
RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator
(VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in
sufficient time across the guaranteed temperature range to meet the Bluetooth v2.0 + EDR specification.
8.5
Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal
reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
(1)
Class 1 operation is not recommended for Plug-n-Go devices and therefore is not recommended for BlueCore4-ROM Plug-n-Go.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 33 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
For EDR, an ADC is used to digitise the IF received signal.
Description of Functional Blocks
8.6
Baseband and Logic
8.6.1
Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data that
is in transit between the host and the air. The dynamic allocation of memory ensures efficient use of the available
Random Access Memory (RAM) and is performed by a hardware MMU to minimise the overheads on the processor
during data/voice transfers.
8.6.2
Burst Mode Controller
8.6.3
Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:
ƒ
Forward error correction
ƒ
Header error control
ƒ
Cyclic redundancy check
ƒ
Encryption
ƒ
Data whitening
ƒ
Access code correlation
ƒ
Audio transcoding
The following voice data translations and operations are performed by firmware:
ƒ
A-law/µ-law/linear voice data (from host)
ƒ
A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air)
ƒ
Voice interpolation for lost packets
ƒ
Rate mismatches
The hardware suports all optional and mandatory features of Bluetooth v2.0 + EDR including AFH and eSCO.
8.6.4
RAM (48Kbytes)
48Kbytes of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to hold
voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
8.6.5
ROM
4Mbits of metal programmable ROM is provided for system firmware implementation.
8.6.6
USB
This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices.
BlueCore4-ROM Plug-n-Go acts as a USB peripheral, responding to requests from a master host controller such as
a PC.
8.6.7
Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for
system debugging. It can also be used for programming the Flash memory.
8.6.8
UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial
devices.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 34 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information previously
loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer
in the RAM. During radio reception, the BMC stores the packet header in memory-mapped registers and the payload
data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor
during transmission and reception.
Description of Functional Blocks
8.7
Microcontroller
The microcontroller (MCU), interrupt controller and event timer run the Bluetooth software stack and control the radio
and host interfaces. A 16-bit reduced instruction set computer (RISC) microcontroller is used for low power
consumption and efficient use of memory.
8.7.1
Programmable I/O
8.7.2
802.11 Co-Existence Interface
Dedicated hardware is provided to implement a variety of co-existence schemes. Channel skipping AFH, priority
signalling, channel signalling and host passing of channel instructions are all supported. The features are configured
in firmware. The details of some methods are proprietary (e.g., Intel WCS). Contact CSR for details.
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 35 of 94
CSR Bluetooth Software Stacks
9
CSR Bluetooth Software Stacks
BlueCore4-ROM Plug-n-Go is supplied with Bluetooth v2.0 + EDR compliant stack firmware, which runs on the internal
RISC microcontroller.
The BlueCore4-ROM Plug-n-Go software architecture allows Bluetooth processing and the application program to be
shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper
layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
BlueCore HCI Stack
LM
LC
48KB RAM
Baseband
MCU
USB
Host
Host I/O
UART
Radio
PCM I/O
Figure 9.1: BlueCore HCI Stack
In the implementation shown in Figure 9.1 the internal processor runs the Bluetooth stack up to the Host Controller
Interface (HCI). The Host processor must provide all upper layers including the application.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 36 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
HCI
Internal ROM
9.1
CSR Bluetooth Software Stacks
9.1.1
Key Features of the HCI Stack: Standard Bluetooth Functionality
Bluetooth v2.0 + EDR mandatory functionality:
ƒ
Adaptive frequency hopping (AFH), including classifier
ƒ
Faster connection - enhanced inquiry scan (immediate FHS response)
ƒ
LMP improvements
ƒ
Parameter ranges
Optional Bluetooth v2.0 + EDR functionality supported:
Adaptive Frequency Hopping (AFH) as Master and Automatic Channel Classification
ƒ
Fast Connect - Interlaced Inquiry and Page Scan plus RSSI during Inquiry
ƒ
Extended SCO (eSCO), eV3 +CRC, eV4, eV5
ƒ
SCO handle
ƒ
Synchronisation
The firmware was written against the Bluetooth v2.0 + EDR specification.
ƒ
Bluetooth components:
ƒ
Baseband (including LC)
ƒ
LM
ƒ
HCI
ƒ
Standard USB v1.1 and UART HCI Transport Layers
ƒ
All standard radio packet types
ƒ
Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps(1)
ƒ
Operation with up to seven active slaves(1)
ƒ
Scatternet v2.5 operation
ƒ
Maximum number of simultaneous active ACL connections: 7(2)
ƒ
Maximum number of simultaneous active SCO connections: 3(2)
ƒ
Operation with up to three SCO links, routed to one or more slaves
ƒ
All standard SCO voice coding, plus transparent SCO
ƒ
Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan
ƒ
All standard pairing, authentication, link key and encryption operations
ƒ
Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold
ƒ
Dynamic control of peers' transmit power via LMP
ƒ
Master/Slave switch
ƒ
Broadcast
ƒ
Channel quality driven data rate
ƒ
All standard Bluetooth test modes
The firmware's supported Bluetooth features are detailed in the standard Protocol Implementation Conformance
Statement (PICS) documents, available from www.csr.com.
(1)
(2)
This is the maximum allowed by Bluetooth v2.0 + EDR specification.
BlueCore4-ROM Plug-n-Go supports all combinations of active ACL and SCO channels for both master and slave operation, as specified
by the Bluetooth v2.0 + EDR specification.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 37 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
ƒ
CSR Bluetooth Software Stacks
9.1.2
Key Features of the HCI Stack: Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features:
ƒ
Supports BlueCore Serial Protocol (BCSP), a proprietary, reliable alternative to the standard Bluetooth UART
Host Transport
ƒ
Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BlueCore Command (BCCMD), provides:
Access to the chip's general-purpose PIO port
ƒ
The negotiated effective encryption key length on established Bluetooth links
ƒ
Access to the firmware's random number generator
ƒ
Controls to set the default and maximum transmit powers; these can help minimise interference
between overlapping, fixed-location piconets
ƒ
Dynamic UART configuration
ƒ
Radio transmitter enable/disable. A simple command connects to a dedicated hardware switch that
determines whether the radio can transmit.
ƒ
The firmware can read the voltage on a pair of the chip's external pins. This is normally used to build a battery
monitor, using either VM or host code
ƒ
A block of BCCMD commands provides access to the chip's Persistent Store configuration database (PS).
The database sets the device's Bluetooth address, Class of Device, radio (transmit class) configuration, SCO
routing, LM, USB and DFU constants, etc.
ƒ
A UART break condition can be used in three ways:
1.
Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
2.
Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
3.
With BCSP, the firmware can be configured to send a break to the host before sending data. (This
is normally used to wake the host from a Deep Sleep state.)
ƒ
The DFU standard has been extended with public/private key authentication, allowing manufacturers to
control the firmware that can be loaded onto their Bluetooth modules
ƒ
A modified version of the DFU protocol allows firmware upgrade via the chip's UART
ƒ
A block of radio test or BIST commands allows direct control of the chip's radio. This aids the development
of modules' radio designs, and can be used to support Bluetooth qualification.
ƒ
Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific code.
Although the VM is mainly used with BlueLab and RFCOMM builds (alternative firmware builds providing
L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such as flashing
LEDs via the chip's PIO port.
ƒ
Hardware low power modes: Shallow Sleep and Deep Sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
ƒ
SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed
over the chip's single PCM port (at the same time as routing any remaining SCO channels over HCI).
Note:
Always refer to the Firmware Release Note for the specific functionality of a particular build.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 38 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
ƒ
CSR Bluetooth Software Stacks
9.2
BlueCore RFCOMM Stack
Internal ROM
RFCOMM
SDP
L2CAP
HCI
LM
48KB RAM
Baseband
MCU
USB
Host
Host I/O
UART
Radio
PCM I/O
Figure 9.2: BlueCore RFCOMM Stack
In the version of the firmware, shown in Figure 9.2 the upper layers of the Bluetooth stack up to RFCOMM are run
on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and
flexibility of the HCI only stack.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 39 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
LC
CSR Bluetooth Software Stacks
9.2.1
Key Features of the BlueCore4-ROM Plug-n-Go RFCOMM Stack
Interfaces to Host:
ƒ
RFCOMM, an RS-232 serial cable emulation protocol
ƒ
SDP, a service database look-up protocol
Connectivity:
Maximum number of active slaves: three
ƒ
Maximum number of simultaneous active ACL connections: three
ƒ
Maximum number of simultaneous active SCO connections: three
ƒ
Data Rate: up to 350kbps(1)
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
ƒ
Security:
ƒ
Full support for all Bluetooth security features up to and including strong (128-bit) encryption.
Power Saving:
ƒ
Full support for all Bluetooth power saving modes (Park, Sniff and Hold).
Data Integrity:
ƒ
CQDDR increases the effective data rate in noisy environments.
ƒ
RSSI used to minimise interference to other radio devices using the ISM band.
(1)
The data rate is with respect to BlueCore4-ROM Plug-n-Go with basic data rate packets.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 40 of 94
CSR Bluetooth Software Stacks
9.3
BlueCore Virtual Machine Stack
RFCOMM
SDP
L2CAP
HCI
LM
LC
48KB RAM
Baseband
MCU
USB
Host (Optional)
Host I/O
UART
Radio
PCM I/O
Figure 9.3: Virtual Machine
In Figure 9.3, this version of the stack firmware shown requires no host processor (but it can use a host processor for
debugging, etc.). All software layers, including application software, run on the internal RISC processor in a protected
user software execution environment known as a Virtual Machine (VM).
The user may write custom application code to run on the BlueCore VM using BlueLab SDK supplied with the BlueLab
Multimedia and Casira development kits, available separately from CSR. This code will then execute alongside the
main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software routines,
thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is
changed.
Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless handsfree kit or other
profiles without the requirement of a host controller. BlueLab is supplied with example code including a full
implementation of the handsfree profile.
Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 41 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Internal ROM
VM Application Software
CSR Bluetooth Software Stacks
9.4
BlueCore HID Stack
HID
SDP
L2CAP
HCI
LM
LC
Sensing
Hardware
(Optical Sensor
etc.)
PIO/UART
48KB RAM
Baseband
MCU
HID I/O
Radio
Figure 9.4: HID Stack
This version of the stack firmware requires no host processor. All software layers, including application software, run
on the internal RISC microcontroller in a protected user software execution environment known as a virtual machine
(VM).
The user may write custom application code to run on the BlueCore VM using BlueLab Professional SDK supplied with
the BlueLab Professional and Casira development kits, available separately from CSR. This code will then execute
alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software routines,
thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is
changed.
Using the VM and the BlueLab Professional SDK the user is able to develop Bluetooth HID devices such as an optical
mouse or keyboard. The user is able to customise features such as power management and connect/reconnect
behaviour.
The HID I/O component in the HID stack controls low latency data acquisition from external sensor hardware. With
this component running in native code, it does not incur the overhead of the VM code interpreter. Supported external
sensors include five mouse buttons, the Agilent ADNS-2030 optical sensor, quadrature scroll wheel, direct coupling
to a keyboard matrix and a UART interface to custom hardware.
A reference schematic for implementing a three button, optical mouse with scroll wheel is available from CSR.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 42 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Internal ROM
VM Application Software
CSR Bluetooth Software Stacks
9.5
Host-Side Software
BlueCore4-ROM Plug-n-Go can be ordered with companion host-side software:
ƒ
BlueCore3-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth
host-side stack together with IC hardware described in this document.
ƒ
BlueCore3-Mobile includes software for a full host-side stack designed for modern ARM chip-based mobile
handsets together with IC hardware described in this document.
9.6
Device Firmware Upgrade
9.7
BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality into
embedded products quickly, cheaply and with low risk.
BCHS is developed to work with CSR's family of BlueCore ICs. BCHS is intended for embedded products that have a
host processor for running BCHS and the Bluetooth application, e.g., a mobile phone or a PDA. BCHS together with
the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete Bluetooth system
solution from RF to profiles.
BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to develop
a Bluetooth product without in-depth Bluetooth knowledge.
The BlueCore Embedded Host Software contains three elements:
ƒ
Example Drivers (BCSP and proxies)
ƒ
Bluetooth Profile Managers
ƒ
Example Applications
The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with source
code (ANSI C). BCHS also comes with example applications in ANSI C, which makes the process of writing the
application easier.
9.8
Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore4-ROM Plug-n-Go, a UART
software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery Protocol (SDP) APIs to higher
Bluetooth stack layers running on the host. The code is provided as C source or object code.
9.9
CSR Development Systems
CSR’s BlueLab Multimedia and Casira development kits are available to allow the evaluation of the BlueCore4-ROM
Plug-n-Go hardware and software, and as toolkits for developing on-chip and host software.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 43 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BlueCore4-ROM Plug-n-Go is supplied with boot loader software, which implements a Device Firmware Upgrade
(DFU) capability. This allows new firmware to be uploaded to the Flash memory through BlueCore4-ROM Plug-n-Go
UART or USB ports.
Device Terminal Descriptions
10 Device Terminal Descriptions
10.1
RF Ports
The BlueCore4-ROM Plug-n-Go RF_IN terminal can be configured as either a single-ended or differential input. The
operational mode is determined by setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x20).
10.1.1 RF Plug-n-Go
The 10 x 10mm 96-ball LFBGA package used on the BlueCore4-ROM Plug-n-Go device is an RF Plug-n-Go package,
where the terminal RF_CONNECT forms an unbalanced ouput with a nominal 50Ω impedance. This terminal can be
directly connected to an antenna requiring no impedance matching network as Figure 10.1 indicates.
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BlueCore
RF_CONNECT
R1
50Ω
Figure 10.1: Circuit for RF_CONNECT
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 44 of 94
Device Terminal Descriptions
10.1.2 Single-Ended Input (RF_IN)
This is the single-ended RF input from the antenna. The input presents a complex impedance that requires a matching
network between the terminal and the antenna. Starting from the substrate (chip) side, the input can be modelled as
a lossy capacitor with the bond wire to the ball grid represented as a series inductance.
The terminal is DC blocked. The DC level must not exceed (VSS_RADIO -0.3V to VDD_RADIO + 0.3V).
BlueCore
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
L1
1.5nH
RF_IN
R1
6.8Ω
C1
0.68pF
Figure 10.2: Circuit RF_IN
Note:
Both terminals must be externally DC biased to VDD_RADIO
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 45 of 94
Device Terminal Descriptions
10.2
External Reference Clock Input (XTAL_IN)
The BlueCore4-ROM Plug-n-Go RF local oscillator and internal digital clocks are derived from the reference clock at
the BlueCore4-ROM Plug-n-Go XTAL_IN input. This reference may be either an external clock or from a crystal
connected between XTAL_IN and XTAL_OUT. The crystal mode is described in section 10.3.
10.2.1 External Mode
The external clock signal should meet the specifications in Table 10.1:
Frequency(a)
Duty cycle
Edge Jitter (At Zero Crossing)
Signal Level
Min
Typ
Max
7.5MHz
16MHz
40MHz
20:80
50:50
80:20
-
-
15ps rms
400mV pk-pk
-
VDD_ANA(b) (c)
Table 10.1: External Clock Specifications
(a)
(b)
(c)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
VDD_ANA is 1.8V nominal
If the external clock is driven through a DC blocking capacitor, then maximum allowable amplitude is reduced from
VDD_ANA to 800mV pk-pk.
10.2.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from Deep Sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
10.2.3 Clock Timing Accuracy
As Figure 10.3 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of the
system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance with the
Bluetooth v2.0 + EDR specification. Radio activity may occur after 11ms, therefore, at this point the timing accuracy
of the external clock source must be within 20ppm.
Figure 10.3: TCXO Clock Accuracy
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 46 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BlueCore4-ROM Plug-n-Go can be configured to accept an external reference clock from another device (such as
TCXO) at XTAL_IN by connecting XTAL_OUT to ground. The external clock can be either a digital level square wave
or sinusoidal, and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks
of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor
(approximately 33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity, as the high
slew rate clock edges have lower voltage to phase conversion.
Device Terminal Descriptions
10.2.4 Clock Start-Up Delay
BlueCore4-ROM Plug-n-Go hardware incorporates an automatic 5ms delay after the assertion of the system clock
request signal before running firmware. This is suitable for most applications using an external clock source. However,
there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these
conditions, BlueCore4-ROM Plug-n-Go firmware provides a software function which will extend the system clock
request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from
5-31ms.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still keeping
the current consumption of BlueCore4-ROM Plug-n-Go as low as possible. BlueCore4-ROM Plug-n-Go will consume
about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Actual Allowable Clock Presence Delay on XTAL_IN vs. PSKey Setting
30.0
25.0
Delay (ms)
20.0
15.0
10.0
5.0
0.0
0.0
5.0
10.0
15.0
20.0
25.0
30.0
PSKEY_CLOCK_STARTUP_DELAY
Figure 10.4: Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 47 of 94
Device Terminal Descriptions
10.2.5 Input Frequencies and PS Key Settings
BlueCore4-ROM Plug-n-Go should be configured to operate with the chosen reference frequency. This is
accomplished by setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of
250kHz. The input frequency default setting in BlueCore4-ROM Plug-n-Go is 26MHz.
The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8
and 38.4MHz.
Reference Crystal Frequency (MHz)
PSKEY_ANA_FREQ (0x1fe)
7.68
7680
14.40
14400
15.36
15360
16.20
16200
16.80
16800
19.20
19200
19.44
19440
19.68
19680
19.80
19800
38.40
38400
n x 250kHz
-
+26.00 Default
26000
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
(Units of 1kHz)
Table 10.2: PS Key Values for CDMA/3G Phone TCXO Frequencies
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 48 of 94
Device Terminal Descriptions
10.3
Crystal Oscillator (XTAL_IN, XTAL_OUT)
This section describes the crystal mode. See section 10.2 for the description of the external reference clock mode.
10.3.1 XTAL Mode
BlueCore4-ROM Plug-n-Go contains a crystal driver circuit. This operates with an external crystal and capacitors to
form a Pierce oscillator.
Cint
Ct2
Ctrim
XTAL_OUT
Ctrim
XTAL_IN
BlueCore
-
Ct1
Figure 10.5: Crystal Driver Circuit
Figure 10.6 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
Figure 10.6: Crystal Equivalent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore4-ROM Plug-n-Go contains
variable internal capacitors to provide a fine trim.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 49 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
gm
Device Terminal Descriptions
Min
Typ
Max
8MHz
16MHz
32MHz
Initial Tolerance
-
±25ppm
-
Pullability
-
±20ppm/pF
-
Frequency
Table 10.3: Crystal Specification
10.3.2 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore4-ROM
Plug-n-Go provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external
capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This maximises
the signal swing, hence, slew rate at XTAL_IN (to which all on-chip clocks are referred). Crystal load capacitance, Cl
is calculated with Equation 10.1:
CI = Cint +
C trim
C C
+ t1• t 2
2
C t1 + C t 2
Equation 10.1: Load Capacitance
Where:
Ctrim = 3.4pF nominal (mid-range setting)
Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance; it is the driver self capacitance.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 50 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
The BlueCore4-ROM Plug-n-Go driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a
current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.
Device Terminal Descriptions
10.3.3 Frequency Trim
BlueCore4-ROM Plug-n-Go enables frequency adjustments to be made. This feature is typically used to remove initial
tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load
capacitance with on-chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the PS Key
PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus:
C trim = 110fF × PSKEY _ AN A _ FT R IM
There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they
appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal of
55fF.
The frequency trim is described by Equation 10.3.
∆ (FX )
= pullability × 55 × 10−3 (ppm / LSB)
FX
Equation 10.3: Frequency Trim
Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63
times the value above.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 10.4.
Cm
∂ (FX )
= FX•
∂ (FX )
4(CI + C0 )2
Equation 10.4: Pullability
Where:
C0 = Crystal self capacitance (shunt capacitance)
Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 10.6.
Note:
It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to
pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with ageing
and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is required.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 51 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Equation 10.2: Trim Capacitance
Device Terminal Descriptions
10.3.4 Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one
terminal generates a voltage at the other. The transconductance amplifier in BlueCore4-ROM Plug-n-Go uses the
voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the
transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product
should be greater than three. The transconductance required for oscillation is defined by the relationship shown in
Equation 10.5:
3(C t1 + C trim )(C t 2 + C trim )
(2πFX )2 Rm ((C0 + Cint )(C t1 + Ct 2 + 2Ctrim ) + (Ct1 + Ctrim )(Ct 2 + Ctrim ))2
Equation 10.5: Transconductance Required for Oscillation
BlueCore4-ROM Plug-n-Go guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher capacitance
loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is
determined by the crystal driver transconductance, by setting the PS Key PSKEY_XTAL_LVL (0x241).
10.3.5 Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The
driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the
negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the BlueCore4-ROM
Plug-n-Go crystal driver circuit is based on a transimpedance amplifier, an equivalent negative resistance may be
calculated for it with the following formula in Equation 10.6:
Rneg >
3(C t1 + Ctrim )(C t 2 + C trim )
gm (2πFX ) (C0 + Cint )((C t1 + C t 2 + 2C trim ) + (C t1 + C trim )(C t 2 + C trim ))2
2
Equation 10.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore4-ROM Plug-n-Go driver as a function of its drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series with
the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the
oscillator.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 52 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
gm >
Device Terminal Descriptions
10.3.6 Crystal PS Key Settings
See tables in section 10.2.5.
10.3.7 Crystal Oscillator Characteristics
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
100.0
10.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
Load Capacitance (pF)
8 MHz
20 MHz
32 MHz
12 MHz
24 MHz
16 MHz
28 MHz
Figure 10.7: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Note:
Graph shows results for BlueCore4-ROM Plug-n-Go crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value
Crystal Co = 2pF
Transconductance setting = 2mA/V
Loop gain = 3
Ct1/Ct2 = 3
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 53 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Max Xtal Rm Value (ESR), (Ohm)
1000.0
Device Terminal Descriptions
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 10.8: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by PS Key PSKEY_XTAL_LVL (0x241).
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 54 of 94
Device Terminal Descriptions
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 10.9: Crystal Driver Negative Resistance as a Function of Drive Level Setting
Crystal parameters:
Crystal frequency 16MHz (refer to your software build release note for supported frequencies ).
Crystal C0 = 0.75pF
Circuit parameters:
Ctrim = 8pF, maximum value
Ct1,Ct2 = 5pF (3.9pF plus 1.1 pF stray)
(Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 55 of 94
Device Terminal Descriptions
10.4
UART Interface
BlueCore4-ROM Plug-n-Go UART interface provides a simple mechanism for communicating with other serial devices
using the RS232 protocol.(1)
BlueCore
UART_RX
UART_RTS
UART_CTS
Figure 10.10: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 10.10. When BlueCore4-ROM Plug-n-Go
is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The
remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where
both are active low indicators. All UART connections are implemented using CMOS technology and have signalling
levels of 0V and VDD_USB.
UART configuration parameters, such as baud rate and packet format, are set using BlueCore4-ROM Plug-n-Go
software.
Note:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port
adapter card is required for the PC.
Parameter
Baud Rate
Possible Values
Minimum
Maximum
1200 baud (≤2%Error)
9600 baud (≤1%Error)
3M baud (≤1%Error)
Flow Control
RTS/CTS or None
Parity
None, Odd or Even
Number of Stop Bits
1 or 2
Bits per Channel
8
Table 10.4: Possible UART Settings
(1)
Uses RS232 protocol, but voltage levels are 0V to VDD_USB (requires external RS232 transceiver chip).
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 56 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
UART_TX
Device Terminal Descriptions
The UART interface is capable of resetting BlueCore4-ROM Plug-n-Go upon reception of a break signal. A break is
identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 10.11. If tBRK is longer than
the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This
feature allows a host to initialise the system to a known state. Also, BlueCore4-ROM Plug-n-Go can emit a break
character that may be used to wake the host.
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used. This
initial flash programming can be done via the SPI.
Table 10.5 shows a list of commonly used baud rates and their associated values for the PS Key
PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any baud rate within
the supported range can be set in the PS Key according to the formula in Equation 10.7.
Baud Rate =
PSKEY _ UART _ BAUD_ RATE
0.004096
Equation 10.7: Baud Rate
Baud Rate
Persistent Store Value
Error
Hex
Dec
1200
0x0005
5
1.73%
2400
0x000a
10
1.73%
4800
0x0014
20
1.73%
9600
0x0027
39
-0.82%
19200
0x004f
79
0.45%
38400
0x009d
157
-0.18%
57600
0x00ec
236
0.03%
76800
0x013b
315
0.14%
115200
0x01d8
472
0.03%
230400
0x03b0
944
0.03%
460800
0x075f
1887
-0.02%
921600
0x0ebf
3775
0.00%
1382400
0x161e
5662
-0.01%
1843200
0x1d7e
7550
0.00%
2764800
0x2c3d
11325
0.00%
Table 10.5: Standard Baud Rates
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 57 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 10.11: Break Signal
Device Terminal Descriptions
10.4.1 UART Bypass
BlueCore
Host Processor
Another Device
RESET
RXD
CTS
RTS
TXD
UART_TX
PIO4
UART_RTS
PIO5
UART_CTS
PIO6
UART_RX
PIO7
TX
RTS
CTS
RX
Test Interface
Figure 10.12: UART Bypass Architecture
10.4.2 UART Configuration While RESET is Active
The UART interface for BlueCore4-ROM Plug-n-Go while the chip is being held in reset is tri-state. This will allow the
user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected
to this bus must tri-state when BlueCore4-ROM Plug-n-Go reset is de-asserted and the firmware begins to run.
10.4.3 UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore4-ROM Plug-n-Go
can be used. The default state of BlueCore4-ROM Plug-n-Go after reset is de-asserted; this is for the host UART bus
to be connected to the BlueCore4-ROM Plug-n-Go UART, thereby allowing communication to BlueCore4-ROM
Plug-n-Go via the UART. All UART bypass mode connections are implemented using CMOS technology and have
signalling levels of 0V and VDD_PADS.(1)
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-ROM Plug-n-Go. Upon
this issue, it will switch the bypass to PIO[7:4] as Figure 10.12 indicates. Once the bypass mode has been invoked,
BlueCore4-ROM Plug-n-Go will enter the Deep Sleep state indefinitely.
In order to re-establish communication with BlueCore4-ROM Plug-n-Go, the chip must be reset so that the default
configuration takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is
invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
10.4.4 Current Consumption in UART Bypass Mode
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby
mode.
(1)
The range of the signalling level for the standard UART described in section 10.4 and the UART bypass may differ between CSR BlueCore
devices, as the power supply configurations are chip dependent. For BlueCore4-ROM Plug-n-Go, the standard UART is supplied by
VDD_USB, so has signalling levels of 0V and VDD_USB. Whereas in the UART bypass mode, the signals appear on PIO[4:7] which are
supplied by VDD_PADS, therefore the signalling levels are 0V and VDD_PADS.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 58 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
UART
Device Terminal Descriptions
10.5
USB Interface
BlueCore4-ROM Plug-n-Go devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB
cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to
requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported. The set
of USB endpoints implemented can behave as specified in the USB section of the Bluetooth specification v2.0+EDR
or alternatively can appear as a set of endpoints appropriate to USB audio devices such as speakers.
As USB is a master/slave oriented system (in common with other USB peripherals), BlueCore4-ROM Plug-n-Go only
supports USB Slave operation.
10.5.1 USB Data Connections
10.5.2 USB Pull-Up Resistor
BlueCore4-ROM Plug-n-Go features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when
BlueCore4-ROM Plug-n-Go is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s) USB device.
The USB internal pull-up is implemented as a current source, and is compliant with section 7.1.5 of the USB
specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15kΩ ±5% pull-down
resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at least 900Ω.
Alternatively, an external 1.5kΩ pull-up resistor can be placed between a PIO line and D+ on the USB cable. The
firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP appropriately. The
default setting uses the internal pull-up resistor.
10.5.3 Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the
USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V. CSR
recommends 3.3V for optimal USB signal quality.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 59 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB I/O
buffers of the BlueCore4-ROM Plug-n-Go, therefore, have a low output impedance. To match the connection to the
characteristic impedance of the USB cable, resistors must be placed in series with USB_DP/USB_DN and the cable.
Device Terminal Descriptions
10.5.4 Self-Powered Mode
In self-powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the USB
cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier mode for
which to design, as the design is not limited by the power that can be drawn from the USB hub or root port. However,
it requires that VBUS be connected to BlueCore4-ROM Plug-n-Go via a resistor network (Rvb1 and Rvb2), so
BlueCore4-ROM Plug-n-Go can detect when VBUS is powered up. BlueCore4-ROM Plug-n-Go will not pull USB_DP
high when VBUS is off.
BlueCore
PIO
USB_DP
1.5KΩ
5%
Rs
D+
Rs
USB_DN
D-
Rvb1
USB_ON
VBUS
Rvb2
GND
Figure 10.13: USB Connections for Self-Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting
PSKEY_USB_PIO_VBUS to the corresponding pin number.
Note:
USB_ON is shared with BlueCore4-ROM Plug-n-Go PIO terminals.
Identifier
Value
Function
Rs
27Ω nominal
Impedance matching to USB cable
Rvb1
22kΩ 5%
VBUS ON sense divider
Rvb2
47kΩ 5%
VBUS ON sense divider
Table 10.6: USB Interface Component Values
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 60 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Self-powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB pull-up
purposes. A 1.5KΩ 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the design.
Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode. The internal pull-up
in BlueCore is only suitable for bus-powered USB devices, e.g., dongles.
Device Terminal Descriptions
10.5.5 Bus-Powered Mode
In bus-powered mode, the application circuit draws its current from the 5V VBUS supply on the USB cable.
BlueCore4-ROM Plug-n-Go negotiates with the PC during the USB enumeration stage about how much current it is
allowed to consume.
For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated at
100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In bus-powered
mode, BlueCore4-ROM Plug-n-Go requests 100mA during enumeration.
When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging reservoir
and supply decoupling capacitors) is limited by the USB specification. See USB Specification v1.1, section 7.2.4.1.
Some applications may require soft start circuitry to limit inrush current if more than 10µF is present between VBUS
and GND.
The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V,
applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator
bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore4-ROM Plug-n-Go will result
in reduced receive sensitivity and a distorted RF transmit signal.
BlueCore
Rs
USB_DP
Rs
USB_DN
Rvb1
USB_ON
D+
DVBUS
GND
Voltage
Regulator
Figure 10.14: USB Connections for Bus-Powered Mode
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 61 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
For Class 1 Bluetooth applications, the USB power descriptor should be altered to reflect the amount of power
required. This is accomplished by setting the PS Key PSKEY_USB_MAX_POWER (0x2c6). This is higher than for a
Class 2 application due to the extra current drawn by the Transmit RF PA.
Device Terminal Descriptions
10.5.6 Suspend Current
All USB devices must permit the USB controller to place them in a USB suspend mode. While in USB Suspend,
bus-powered devices must not draw more than 0.5mA from USB VBUS (self-powered devices may draw more than
0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus-powered devices
during USB Suspend.
The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100µA) to ensure
adherence to the suspend current requirement of the USB specification. This is not normally a problem with modern
regulators. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore4-ROM Plug-n-Go. The entire
circuit must be able to enter the suspend mode. Refer to separate CSR documentation for more details on USB
Suspend.
BlueCore4-ROM Plug-n-Go can provide out-of-band signalling to a host controller by using the control lines called
USB_DETACH and USB_WAKE_UP. These are outside the USB specification (no wires exist for them inside the USB
cable), but can be useful when embedding BlueCore4-ROM Plug-n-Go into a circuit where no external USB is visible
to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the PS Keys
PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number.
USB_DETACH is an input which, when asserted high, causes BlueCore4-ROM Plug-n-Go to put USB_DN and
USB_DP in a high impedance state and turns off the pull-up resistor on DP. This detaches the device from the bus
and is logically equivalent to unplugging the device. When USB_DETACH is taken low, BlueCore4-ROM Plug-n-Go
will connect back to USB and await enumeration by the USB host.
USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and allow USB
communication to recommence. It replaces the function of the software USB WAKE_UP message (which runs over
the USB cable) and cannot be sent while BlueCore4-ROM Plug-n-Go is effectively disconnected from the bus.
Figure 10.15: USB_DETACH and USB_WAKE_UP Signal
10.5.8 USB Driver
A USB Bluetooth device driver is required to provide a software interface between BlueCore4-ROM Plug-n-Go and
Bluetooth software running on the host computer. Suitable drivers are available from http://www.csrsupport.com.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 62 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
10.5.7 Detach and Wake_Up Signalling
Device Terminal Descriptions
10.5.9 USB 1.1 Compliance
BlueCore4-ROM Plug-n-Go is qualified to the USB Specification v1.1, details of which are available from www.usb.org.
The specification contains valuable information on aspects such as PCB track impedance, supply inrush current and
product labelling.
Although BlueCore4-ROM Plug-n-Go meets the USB specification, CSR cannot guarantee that an application circuit
designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout all
affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and
should be read in association with the USB specification, with particular attention being given to Chapter 7.
Independent USB qualification must be sought before an application is deemed USB compliant and can bear the USB
logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
10.5.10 USB 2.0 Compatibility
BlueCore4-ROM Plug-n-Go is compatible with USB v2.0 host controllers; under these circumstances the two ends
agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 63 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Terminals USB_DP and USB_DN adhere to the USB specification v2.0 (Chapter 7) electrical requirements.
Device Terminal Descriptions
10.6
Serial Peripheral Interface
BlueCore4-ROM Plug-n-Go uses 16-bit data and 16-bit address serial peripheral interface, where transactions may
occur when the internal processor is running or is stopped. This section details the considerations required when
interfacing to BlueCore4-ROM Plug-n-Go via the four dedicated serial peripheral interface terminals. Data may be
written or read one word at a time or the auto increment feature may be used to access blocks.
10.6.1 Instruction Cycle
The BlueCore4-ROM Plug-n-Go is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO.
Table 10.7 shows the instruction cycle for an SPI transaction.
Reset the SPI interface
Hold SPI_CSB high for two SPI_CLK cycles
2
Write the command word
Take SPI_CSB low and clock in the 8 bit command
3
Write the address
Clock in the 16-bit address word
4
Write or read data words
Clock in or out 16-bit data word(s)
5
Termination
Take SPI_CSB high
Table 10.7: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the
BlueCore4-ROM Plug-n-Go on the rising edge of the clock line SPI_CLK. When reading, BlueCore4-ROM Plug-n-Go
will reply to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides
the clock on SPI_CLK. The transaction is teminated by taking SPI_CSB high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore4-ROM Plug-n-Go
offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept
low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or
read.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 64 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
1
Device Terminal Descriptions
10.6.2 Writing to BlueCore4-ROM Plug-n-Go
To write to BlueCore4-ROM Plug-n-Go, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit
address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address
(A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to
consecutive locations until the transaction terminates when SPI_CSB is taken high.
10.6.3 Reading from BlueCore4-ROM Plug-n-Go
Reading from BlueCore4-ROM Plug-n-Go is similar to writing to it. An 8-bit read command (00000011) is sent first
(C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore4-ROM Plug-n-Go then outputs on
SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation
to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves,
whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the
slave device not responding.
If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks, until
the transaction terminates when SPI_CSB is taken high.
Figure 10.17: Read Operation
10.6.4 Multi-Slave Operation
BlueCore4-ROM Plug-n-Go should not be connected in a multi-slave arrangement by simple parallel connection of
slave MISO lines. When BlueCore4-ROM Plug-n-Go is deselected (SPI_CSB = 1), the SPI_MISO line does not float.
Instead, BlueCore4-ROM Plug-n-Go outputs 0 if the processor is running or 1 if it is stopped.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 65 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Figure 10.16: Write Operation
Device Terminal Descriptions
10.7
PCM CODEC Interface
Pulse Code Modulation (PCM) is a standard method used to digitise audio (particularly voice) for transmission over
digital communication channels. Through its PCM interface, BlueCore4-ROM Plug-n-Go has hardware support for
continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset
applications. BlueCore4-ROM Plug-n-Go offers a bi-directional digital audio interface that routes directly into the
baseband layer of the on-chip firmware. It does not pass through the HCI protocol layer.
Hardware on BlueCore4-ROM Plug-n-Go allows the data to be sent to and received from a SCO connection. (1)
Up to three SCO connections can be supported by the PCM interface at any one time.
It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats at 8ksamples/s and can receive and
transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are
enabled by setting the PS Key PS KEY_PCM_CONFIG32 (0x1b3).
BlueCore4-ROM Plug-n-Go interfaces directly to PCM audio devices including the following:
ƒ
Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices
ƒ
OKI MSM7705 four channel A-law and µ-law CODEC
ƒ
Motorola MC145481 8-bit A-law and µ-law CODEC
ƒ
Motorola MC145483 13-bit linear CODEC
ƒ
STW 5093 and 5094 14-bit linear CODECs
ƒ
BlueCore4-ROM Plug-n-Go is also compatible with the Motorola SSI™ interface
(1)
Subject to firmware support. Contact CSR for current status.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 66 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BlueCore4-ROM Plug-n-Go can operate as the PCM interface master generating an output clock of 128, 256 or
512kHz. When configured as PCM interface slave, it can operate with an input clock up to 2048kHz. BlueCore4-ROM
Plug-n-Go is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing
environments.
Device Terminal Descriptions
10.7.1 PCM Interface Master/Slave
When configured as the master of the PCM interface, BlueCore4-ROM Plug-n-Go generates PCM_CLK and
PCM_SYNC.
BlueCore
PCM_IN
PCM_CLK
PCM_SYNC
128/256/512kHz
8kHz
Figure 10.18: BlueCore4-ROM Plug-n-Go as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore4-ROM Plug-n-Go accepts PCM_CLK rates up to
2048kHz.
BlueCore
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
Upto 2048kHz
8kHz
Figure 10.19: BlueCore4-ROM Plug-n-Go as PCM Interface Slave
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 67 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PCM_OUT
Device Terminal Descriptions
10.7.2 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In
Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When BlueCore4-ROM
Plug-n-Go is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
When BlueCore4-ROM Plug-n-Go is configured as PCM Slave, PCM_SYNC may be from two consecutive falling
edges of PCM_CLK to half the PCM_SYNC rate, i.e., 62.5µs long.
PCM_SYNC
PCM_OUT
PCM_IN
Undefined
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8
Undefined
Figure 10.20: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore4-ROM Plug-n-Go samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising
edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on
the rising edge.
10.7.3 Short Frame Sync
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one
clock cycle long.
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
Undefined
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Undefined
Figure 10.21: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore4-ROM Plug-n-Go samples PCM_IN on the falling edge of PCM_CLK and
transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of
PCM_CLK in the LSB position or on the rising edge.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 68 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PCM_CLK
Device Terminal Descriptions
10.7.4 Multi-slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections
can be carried over any of the first four slots.
LONG_PCM_SYNC
Or
SHORT_PCM_SYNC
PCM_OUT
1
2
3
4
5
6
7 8
1
2
3
4
5
6
7 8
PCM_IN
Do Not Care 1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
8 Do Not Care
Figure 10.22: Multi-slot Operation with Two Slots and 8-bit Companded Samples
10.7.5 GCI Interface
BlueCore4-ROM Plug-n-Go is compatible with the General Circuit Interface (GCI), a standard synchronous 2B+D
ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured.
PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
Do Not
Care
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
B1 Channel
Do Not
Care
B2 Channel
Figure 10.23: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore4-ROM Plug-n-Go
in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 69 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PCM_CLK
Device Terminal Descriptions
10.7.6 Slots and Sample Formats
BlueCore4-ROM Plug-n-Go can receive and transmit on any selection of the first four slots following each sync pulse.
Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample
formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.
BlueCore4-ROM Plug-n-Go supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. The sample
rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each
slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with
some Motorola CODECs.
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
8-Bit
Sample
A 16-bit slot with 8-bit companded sample and sign extension selected.
8-Bit
Sample
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign
Extension
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
15
16
13-Bit
Sample
A 16-bit slot with 13-bit linear sample and sign extension selected.
13-Bit
Sample
PCM_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.
Figure 10.24: 16-Bit Slot Length and Sample Formats
10.7.7 Additional Features
BlueCore4-ROM Plug-n-Go has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also
be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 70 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Sign
Extension
Device Terminal Descriptions
10.7.8 PCM Timing Information
Symbol
Parameter
Min
-
PCM_SYNC frequency
tmclkh(a)
PCM_CLK high
tmclkl(a)
-
48MHz DDS
generation. Selection
of frequency is
programmable. See
Table 10.11 and
PCM_CLK and
PCM_SYNC
Generation on page
75.
2.9
Max
Unit
-
kHz
-
kHz
128
256
512
-
8
4MHz DDS generation
980
-
PCM_CLK low
4MHz DDS generation
730
-
-
PCM_CLK jitter
48MHz DDS
generation
tdmclksynch
Delay time from PCM_CLK high to PCM_SYNC
high
-
tdmclkpout
Delay time from PCM_CLK high to valid
PCM_OUT
tdmclklsyncl
kHz
-
ns
ns
21
ns pk-pk
-
20
ns
-
-
20
ns
Delay time from PCM_CLK low to PCM_SYNC
low (Long Frame Sync only)
-
-
20
ns
tdmclkhsyncl
Delay time from PCM_CLK high to PCM_SYNC
low
-
-
20
ns
tdmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
tdmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
tsupinclkl
Set-up time for PCM_IN valid to PCM_CLK low
30
-
-
ns
thpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
10
-
-
ns
Table 10.8: PCM Master Timing
(a)
Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are
reduced.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 71 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PCM_CLK frequency
fmclk
4MHz DDS
generation. Selection
of frequency is
programmable. See
Table 10.10.
Typ
Device Terminal Descriptions
t dmclklsyncl
t dmclksynch
t dmclkhsyncl
PCM_SYNC
f mlk
t mclkl
PCM_CLK
t dmclklpoutz
t dmclkpout
PCM_OUT
tr ,t f
MSB (LSB)
t supinclkl
PCM_IN
t dmclkhpoutz
LSB (MSB)
t hpinclkl
MSB (LSB)
LSB (MSB)
Figure 10.25: PCM Master Timing Long Frame Sync
t dmclksynch
t dmclkhsyncl
PCM_SYNC
f mlk
t mclkh
t mclkl
PCM_CLK
t dmclklpoutz
t dmclkpout
PCM_OUT
MSB (LSB)
t supinclkl
PCM_IN
tr ,t f
t dmclkhpoutz
LSB (MSB)
t hpinclkl
MSB (LSB)
LSB (MSB)
Figure 10.26: PCM Master Timing Short Frame Sync
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 72 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
t mclkh
Device Terminal Descriptions
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode: input)
64
-
2048
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
4096
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
30
-
-
ns
tsusclksync
Set-up time for PCM_SYNC high to PCM_CLK low
30
-
-
ns
h
tdpout
Delay time from PCM_SYNC or PCM_CLK whichever is
later, to valid PCM_OUT data (Long Frame Sync only)
-
-
20
ns
tdsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
20
ns
tdpoutz
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_OUT data line high
impedance
-
-
20
ns
tsupinsclkl
Set-up time for PCM_IN valid to CLK low
30
-
-
ns
thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
30
-
-
ns
Table 10.9: PCM Slave Timing
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 73 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Symbol
Device Terminal Descriptions
f sclk
t sclkh
t tsclkl
PCM_CLK
t hsclksynch
t susclksynch
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
PCM_SYNC
t dpoutz
t dpout
PCM_OUT
t dsclkhpout
PCM_IN
t dpoutz
LSB (MSB)
MSB (LSB)
t supinsclkl
tr ,t f
t hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 10.27: PCM Slave Timing Long Frame Sync
f sclk
t sclkh
t tsclkl
PCM_CLK
t susclksynch
t hsclksynch
PCM_SYNC
t dsclkhpout
PCM_OUT
MSB (LSB)
t supinsclkl
PCM_IN
tr ,t f
t dpoutz
t dpoutz
LSB (MSB)
t hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 10.28: PCM Slave Timing Short Frame Sync
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 74 of 94
Device Terminal Descriptions
PCM_CLK and PCM_SYNC Generation
BlueCore4-ROM Plug-n-Go has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis (DDS) from BlueCore4-ROM Plug-n-Go internal 4MHz clock
(which is used in BlueCore2-External). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to
8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a
greater range of frequencies to be generated with low jitter but consumes more power). This second method is
selected by setting bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long
frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by
LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
The Equation 10.8 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
CNT _ RATE
× 24MHz
CNT _ LIMIT
Equation 10.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation 10.9:
f=
PCM _ CLK
SYNC _ LIMIT × 8
Equation 10.9: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 75 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
f=
Device Terminal Descriptions
10.7.9 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 10.10 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 10.11. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e.,
first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz
PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT.
Name
-
Bit Position
0
1
SHORT_SYNC_EN
2
-
3
SIGN_EXTEND_EN
4
Set to 0
0 = master mode with internal generation of PCM_CLK and
PCM_SYNC.
1 = slave mode requiring externally generated PCM_CLK
and PCM_SYNC.
0 = long frame sync (rising edge indicates start of frame).
1 = short frame sync (falling edge indicates start of frame).
Set to 0.
0 = padding of 8 or 13-bit voice sample into a 16-bit slot by
inserting extra LSBs. When padding is selected with 13-bit
voice sample, the 3 padding bits are the audio gain setting;
with 8-bit sample the 8 padding bits are zeroes.
1 = sign-extension.
LSB_FIRST_EN
5
0 = MSB first of transmit and receive voice samples.
1 = LSB first of transmit and receive voice samples.
0 = drive PCM_OUT continuously.
TX_TRISTATE_EN
TX_TRISTATE_RISING_EDGE_EN
6
7
1 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in the last bit of an active slot, assuming the next
slot is not active.
0 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in last bit of an active slot, assuming the next slot
is also not active.
1 = tri-state PCM_OUT after rising edge of PCM_CLK.
0 = enable PCM_SYNC output when master.
SYNC_SUPPRESS_EN
8
1 = suppress PCM_SYNC whilst keeping PCM_CLK running.
Some CODECS utilise this to enter a low power state.
GCI_MODE_EN
9
1 = enable GCI mode
MUTE_EN
10
1 = force PCM_OUT to 0
48M_PCM_CLK_GEN_EN
11
0 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 4 MHz clock.
1 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 48 MHz clock.
0 = set PCM_SYNC length to 8 PCM_CLK cycles.
LONG_LENGTH_SYNC_EN
12
1 = set length to 16 PCM_CLK cycles.
Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.
-
BC41B143A-ds-003Pc
[20:16]
Set to 0b00000
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 76 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
SLAVE_MODE_EN
Description
Device Terminal Descriptions
Name
Bit Position
Description
MASTER_CLK_RATE
[22:21]
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK
frequency when master and 48M_PCM_CLK_GEN_EN (bit
11) is low.
ACTIVE_SLOT
[26:23]
Default is 0001. Ignored by firmware.
SAMPLE_FORMAT
[28:27]
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample
with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle
slot duration.
Table 10.10: PSKEY_PCM_CONFIG32 Description
Bit Position
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Name
Description
CNT_LIMIT
[12:0]
Sets PCM_CLK counter limit
CNT_RATE
[23:16]
Sets PCM_CLK count rate
SYNC_LIMIT
[31:24]
Sets PCM_SYNC division relative to PCM_CLK
Table 10.11: PSKEY_PCM_LOW_JITTER_CONFIG Description
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 77 of 94
Device Terminal Descriptions
10.8
I/O Parallel Ports
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered from
VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_MEM.
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered from
VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_USB.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general use.
BlueCore4-ROM Plug-n-Go has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2] also known
as the extended PIO lines. These are used to access internal circuitry and control signals. One pin is allocated to
decoupling for the on-chip band gap reference voltage; the other two may be configured to provide additional
functionality.
Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for battery
voltage measurement. Signals selectable at these pins include the band gap reference voltage and a variety of clock
signals: 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals, the voltage range is
constrained by the analogue supply voltage (1.8V). When configured to drive out digital level signals (e.g., clocks), the
output voltage level is determined by VDD_USB.
10.8.1 PIO Defaults for BlueCore4-ROM Plug-n-Go
CSR cannot guarantee that these terminal functions remain the same. Refer to the software release note for the
implementation of these PIO lines, as they are firmware build-specific.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 78 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore4-ROM Plug-n-Go is provided from a system application specific integrated circuit (ASIC). Using
PSKEY_CLOCK_REQUEST_ENABLE (0x246), this terminal can be configured to be low when BlueCore4-ROM
Plug-n-Go is in Deep Sleep and high when a clock is required. The clock must be supplied within 4ms of the rising
edge of PIO[6] or PIO[2] to avoid losing timing accuracy in certain Bluetooth operating modes.
Device Terminal Descriptions
10.9
I2C Interface
PIO[8:6] can be used to form a master I2C interface. The interface is formed using software to drive these lines.
Therefore, it is suited only to relatively slow functions such as driving a dot matrix liquid crystal display (LCD), keyboard
scanner or EEPROM.
Notes:
PIO lines need to be pulled-up through 2.2kΩ resistors.
PIO[7:6] dual functions, UART bypass and EEPROM support, therefore, devices using an EEPROM cannot
support UART bypass mode.
+1.8V
10nF
2.2KΩ 2.2KΩ 2.2KΩ
U2
8
PIO[8]
PIO[6]
PIO[7]
7
6
5
VCC
A0
WP
A1
SCL
A2
SDA
GND
1
2
3
4
Serial EEPROM
(AT24C16A)
Figure 10.29: Example EEPROM Connection
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 79 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
For connection to EEPROMs, refer to CSR documentation on I2C EEPROMS for use with BlueCore. This provides
information on the type of devices currently supported.
Device Terminal Descriptions
10.10
TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore4-ROM Plug-n-Go where either
device can turn on the clock without having to wake up the other device. PIO[3] can be used as the host clock enables
input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore4-ROM Plug-n-Go.
VDD
GSM System
TCXO
Enable
CLK REQ OUT
BlueCore System
CLK REQ IN/
PIO[3]
CLK IN
CLK REQ OUT/
PIO[2]
Figure 10.30: Example TXCO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-state. Therefore, the developer must ensure
that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that the
TCXO is oscillating at start up.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 80 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
CLK IN
Device Terminal Descriptions
10.11
RESET and RESETB
BlueCore4-ROM Plug-n-Go may be reset from several sources:
ƒ
RESET or RESETB pins
ƒ
Power on reset
ƒ
A UART break character
ƒ
Via a software configured watchdog timer
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when VDD_CORE
rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The PIOs have weak
pull-downs.
Following a reset, BlueCore4-ROM Plug-n-Go assumes the maximum XTAL_IN frequency, which ensures that the
internal clocks run at a safe (low) frequency until BlueCore4-ROM Plug-n-Go is configured for the actual XTAL_IN
frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore4-ROM Plug-n-Go free runs, again at a safe
frequency.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 81 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A reset
will be performed between 1.5ms and 4.0ms following RESET being active. It is recommended that RESET be applied
for a period greater than 5ms. The RESETB pin is the active low version of RESET and is OR'd on-chip with the active
high RESET, with either causing the reset function.
Device Terminal Descriptions
10.11.1 Pin States on Reset
Table 10.12 shows the pin states of BlueCore4-ROM Plug-n-Go on reset.
State: BlueCore4-ROM Plug-n-Go
PIO[11:0]
Input with weak pull-down
PCM_OUT
Tri-state with weak pull-down
PCM_IN
Input with weak pull-down
PCM_SYNC
Input with weak pull-down
PCM_CLK
Input with weak pull-down
UART_TX
Output tri-state with weak pull-up
UART_RX
Input with weak pull-down
UART_RTS
Output tri-state with weak pull-up
UART_CTS
Input with weak pull-down
USB_DP
Input with weak pull-down
USB_DN
Input with weak pull-down
SPI_CSB
Input with weak pull-up
SPI_CLK
Input with weak pull-down
SPI_MOSI
Input with weak pull-down
SPI_MISO
Output tri-state with weak pull-down
AIO[2:0]
Output, driving low
RESET
Input with weak pull-down
RESETB
Input with weak pull-up
TEST_EN
Input with strong pull-down
AUX_DAC
High impedance
RF_IN
High impedance
XTAL_IN
High impedance, 250k to XTAL_OUT
XTAL_OUT
High impedance, 250k to XTAL_IN
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Pin Name
Table 10.12: Pin States of BlueCore4-ROM Plug-n-Go on Reset
10.11.2 Status after Reset
The chip status after a reset is as follows:
ƒ
Warm Reset: Baud rate and RAM data remain available
ƒ
Cold Reset(1) : Baud rate and RAM data not available
(1)
A Cold Reset is either Power cycle, system reset (firmware fault code) or Reset signal. See section 10.11.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 82 of 94
Device Terminal Descriptions
10.12
Power Supply
10.12.1 Voltage Regulator (Plug-n-Go)
An on-chip linear voltage regulator can be used to power the 1.8V dependent supplies. It is advised that a smoothing
circuit using a 2.2µF low ESR capacitor and 2.2Ω resistor be placed on the output VDD_ANA.
In the Plug-n-Go package, an internal 2.2Ω resistor is provided between the regulator output VDD_ANA and
VDD_DIG.
The regulator is switched into a low power mode when the device is sent into Deep Sleep mode. When the on-chip
regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to VDD_ANA.
It is recommended that VDD_CORE, VDD_RADIO and VDD_ANA be powered at the same time. The order of
powering supplies for VDD_CORE, VDD_PIO, VDD_PADS and VDD_USB is not important. However, if VDD_CORE
is not present, all inputs have a weak pull-down irrespective of the reset state.
10.12.3 Sensitivity to Disturbances
CSR recommends if supplying BlueCore4-ROM Plug-n-Go from an external voltage source that VDD_ANA and
VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. In addition, avoid single tone
frequencies. CSR recommends a simple RC filter for VDD_CORE, as this reduces transients put back onto the power
supply rails.
The remaining supplies VDD_MEM, VDD_PIO, VDD_PADS and VDD_USB can be connected together with the
VREG_IN to the 3.3V supply and simply decoupled as shown in Figure 13.1.
The transient response of the regulator is also important. At the start of a packet, power consumption will jump to high
levels. See the average current consumption section. The regulator should have a response time of 20µs or less; it is
essential that the power rail recovers quickly.
10.12.4 VREG_EN Pin
The regulator enable pin, VREG_EN, can be used to enable and disable the BlueCore4-ROM Plug-n-Go device if the
on-chip regulator is being used. The pin is active high and has an internal weak pull-up to enable the regulator if
VREG_EN is not connected.
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 83 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
10.12.2 Sequencing
Product Reliability Tests
11 Product Reliability Tests
Test Conditions
Specification
Sample Size
ESD
Human Body Model
JEDEC
36
Latch-up
±200mA
JEDEC
6
Early Life
125°C
48 – 168 hours
240
Hot Life Test
125°C
1000 hours
320 (240 FITs)
Package
Test Conditions
Specification
Sample Size
Moisture Sensitivity Precon
JEDEC Level 3
(125°C 24 hours)
30°C/60%RH
192 hours five re-flow
simulation cycles
308
Temperature Cycling
-65°C to +150°C
500 cycles
77
121°C at 100% RH
96 hours
77
130°C/85% RH
96 hours
77
-55/125°C
100 cycles
77
High Temperature Storage
150°C
1000 hours
77
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
AutoClave (Steam)
HAST
Thermal Shock
Page 84 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Die
Product Reliability Tests for BlueCore4-ROM Plug-n-Go Automotive
12 Product Reliability Tests for BlueCore4-ROM Plug-n-Go
Automotive
12.1
AEC-Q100
The reliability tests in this section follow the tests outlined in the AEC-Q100 and were performed on BlueCore4-ROM
Plug-n-Go in VFBGA 10 x 10mm 96 I/O (lead-free solder balls). Samples are electrically tested at ambient
temperature.
This package qualification will (where moisture sensitivity preconditioning is required) use IPC/Jedec MSL3, i.e., the
finished product is allowed a maximum exposure to a ≤30°C/60%RH environment for 168 hours before mounting.
Die
Test Conditions
Specification
Sample Size
ESD
Human Body Model
JEDEC
24
Early Life
125°C VDDmax
48 hours
2400
Hot Life Test
125°C VDDmax
1000 hours
90, 77, 77
Test Conditions
Specification
Sample Size
192 hours five reflow
simulation cycles
783
-65/150°C
500 cycles
231 from Precon
121°C/100%RH
96 hours
231 from Precon
85°C/85%RH Vddmax
1000 hours
231 from Precon
-55/125°C
100 cycles
77 from Precon
150°C
1000 hours
77
Package
Moisture
Sensitivity
Precon
JEDEC Level 3
Temperature Cycling
Autoclave (Steam)
Temperature Humidity Bias
Thermal Shock
High Temperature Storage
Other
(125°C 24 hours)
30°C/60%RH
Test Conditions
Sample Size
Bond Shear
Acid decapsulation of finished product
30 bonds
Wire Pull
Acid decapsulation of finished product
60 wires from Precon and
temperature cycling
Two reflow cycles
150 balls
N/A
30 devices
Solder Ball Shear
Visual Inspection and
Dimensions
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 85 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
As part of CSR's automotive test program, customers will have access to the initial device reliability test report. They
will also have access to a quarterly reliability test report update for automotive parts.
Figure 13.1: Application Circuit for Radio Characteristics Specification
C2
10n
ANTENNA
50 OHMS
K7
B1
D2
J2
C2
AIO[2]
RF_CONNECT
RF_IN
VREG_EN
AUX_DAC
C1
10n
2R2
VSS_BALUN
VSS_BALUN
VSS_BALUN
BAL_MATCH
VSS_RADIO
VSS_RADIO
VSS_RADIO
VSS_VCO
VSS_VCO
VSS_VCO
VSS_ANA
G1
J1
K1
A1
E2
F3
G2
G3
H2
H3
K4
NC
NC
DAC OUTPUT
F1
E3
VDD_BALUN
VDD_RADIO
L5
VDD_ANA
L6
B11
K6
F11
C3
2u2
1.8V REGULATOR
VDD_DIG
VDD_MEM
VDD_MEM
VDD_CORE
VSS_CORE
VSS_MEM
VSS_MEM
VSS_PADS
VSS_PADS
VSS_PADS
F10
D9
J9
A2
E10
K10
C4
2u2
C8
3p3
U1
XT1
XTAL
C9
10p
BlueCore4-ROM Plug-n-Go
BC41B143A
TEST_EN
E9
L7
VREG_IN
B10
FLASH_EN
RESET
G9
E11
A3
L10
RESETB
VDD_PADS
VDD_PIO
VDD_USB
NC
XTAL_IN
L3
XTAL_OUT
L4
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 86 of 94
USB_DP
USB_DN
PCM_OUT
PCM_IN
PCM_SYNC
PCM_CLK
UART_TX
UART_RX
UART_RTS
UART_CTS
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
AIO[0]
AIO[1]
PIO[0]/RXEN
PIO[1]/TXEN
PIO[2]
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
PIO[11]
L9
L8
G10
H11
G11
H10
J10
J11
L11
K11
C10
D10
D11
C11
K5
J6
D3
C4
C3
B2
H9
J8
K8
K9
B3
B4
A4
A5
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
BC41B143A-ds-003Pc
F9
VIO VIN
22R
R2
22R
R1
TP5
TP6
TP7
TP8
TP1
TP2
TP3
TP4
USB_D+
USB_D-
8 BIT ADC INPUTS
GENERAL PURPOSE I/O
Application Schematic
13 Application Schematic
Package Dimensions
14 Package Dimensions
14.1
10 x 10 LFBGA 96-Ball 1.6mm Package
Top View
1 2 3 4 5 6 7 8
Bottom View
10 11
11 10
8 7 6 5 4 3 2
1
PX
X
Y
F
A
B
C
C
D
D
E
E
F
E
E1
SE
F
G
G
H
H
J
J
K
e
L
G
J
3
A3
A1
0.08 Z
Z
2
Øb
SD
D
0.1 Z
A
A2
D1
K
L
1
H
A
Scale = 1mm
SEATING PLANE
1
2
3
4
5
Figure 14.1: BlueCore4-ROM Plug-n-Go 96-Ball LFBGA 1.6mm Package Dimensions
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 87 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
4
PY
B
Ordering Information
15 Ordering Information
15.1
BlueCore4-ROM Plug-n-Go
Package
Interface Version
UART and USB
96-Ball LFBGA
(Pb free)
Size
Shipment Method
10 x 10 x 1.6mm
Tape and reel
Order Number
BC41B143A-ANN-E4 (a)
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
(a)
Type
Until BlueCore4-ROM Plug-n-Go reaches Production status order number is BC41B143AES-ANN-E4.
Minimum Order Quantity
2kpcs taped and reeled
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 88 of 94
Contact Information
16 Contact Information
CSR Denmark
CSR Japan
Churchill House
Novi Science Park
CSR KK
Cambridge Business Park
Niels Jernes Vej 10
9F Kojimachi KS Square 5-3-3,
Cowley Road
9220 Aalborg East
Kojimachi,
Cambridge, CB4 0WZ
Denmark
Chiyoda-ku,
United Kingdom
Tel: +45 72 200 380
Tokyo 102-0083
Tel: +44 (0) 1223 692 000
Fax: +45 96 354 599
Japan
Fax: +44 (0) 1223 692 001
e-mail: [email protected]sr.com
Tel: +81-3-5276-2911
e-mail: [email protected]
Fax: +81-3-5276-2915
e-mail: [email protected]
CSR Korea
CSR Taiwan
CSR U.S.
2nd Floor, Hyo-Bong Building,
6th Floor, No. 407,
2425 N. Central Expressway
1364-1, Seocho-dong,
Rui Guang Road,
Suite 1000
Seocho-gu,
NeiHu,
Richardson
Seoul 137-863,
Taipei 114,
Texas 75080
Korea
Taiwan, R.O.C.
USA
Tel: +82 2 3473 2372-5
Tel: +886 2 7721 5588
Tel: +1 (972) 238 2300
Fax : +82 2 3473 2205
Fax: +886 2 7721 5589
Fax: +1 (972) 231 1440
e-mail: [email protected]
e-mail: [email protected]
e-mail: [email protected]
To contact a CSR representative, go to www.csr.com/contacts.htm
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 89 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
CSR UK
Document References
17 Document References
Reference
Specification of the Bluetooth system
v1.1, 22 February 2001 and v1.2, 05 November 2003
Bluetooth Core Specification v2.0 + EDR
v2.0+EDR, 8 November 2004
Bluetooth Test Document v2.0+EDR
v2.0.e.0, 5 November 2004
Universal Serial Bus Specification
v1.1, 23 September 1998
Selection of Flash Memory for Use with BlueCore
CSR document bcore-an-001P
Selection of I2C EEPROMS for Use with BlueCore
CSR document bcore-an-008P
IA-481-2
16mm, 24mm, 32mm, 44mm and 56mm Embossed
Carrier Taping of Surface Mount Components for
Automatic Handling
EIA-541
Packaging Material Standards for ESD Sensitive Items
EIA-583
Packaging Material Standards for Electrostatic Discharge
(ESD) Sensitive Items
IPC / JEDEC
J-STD-033
BC41B143A-ds-003Pc
Standard for Handling, Packing, Shipping and Use of
Moisture / Reflow Sensitive Surface Mount Devices
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 90 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Document:
Terms and Definitions
18 Terms and Definitions
8 phase Differential Phase Shift Keying
π/4 DQPSK
pi/4 rotated Differential Quaternary Phase Shift Keying
BlueCore®
Group term for CSR’s range of Bluetooth chips
Bluetooth™
Set of technologies providing audio and data transfer over short-range radio connections
ACL
Asynchronous Connection-Less. Bluetooth data packet
ADC
Analogue to Digital Converter
AFH
Adaptive Frequency Hopping
AGC
Automatic Gain Control
A-law
Audio encoding standard
ALU
Arithmetic Logic Unit
API
Application Programming Interface
ASIC
Application Specific Integrated Circuit
BCSP
BlueCore™ Serial Protocol
BER
Bit Error Rate. Used to measure the quality of a link
BIST
Built-In Self-Test
BMC
Burst Mode Controller
CDMA
Code Division Multiple Access
CMOS
Complementary Metal Oxide Semiconductor
CODEC
Coder Decoder
CQDDR
Channel Quality Driven Data Rate
CRC
Cyclic Redundancy Check
CSB
Chip Select (Active Low)
CSR
Cambridge Silicon Radio
CTS
Clear to Send
CVSD
Continuous Variable Slope Delta Modulation
DAC
Digital to Analogue Converter
dBm
Decibels relative to 1mW
DDS
Direct Digital Synthesis
DC
Direct Current
DFU
Device Firmware Upgrade
DNL
Differential Linearity Error
DSP
Digital Signal Processor
EDR
Enhanced Data Rate
eSCO
Extended SCO
ESR
Equivalent Series Resistance
FIR
Finite Impulse Response
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
8DPSK
Page 91 of 94
Terms and Definitions
Frequency Shift Keying
GCI
General Circuit Interface
GFSK
Gaussian Frequency Shift Keying
GSM
Global System for Mobile communications
HCI
Host Controller Interface
I2C™
Inter-Integrated Circuit
IF
Intermediate Frequency
IIR
Infinite Impulse Response
INL
Integral Linearity Error
IQ Modulation
In-Phase and Quadrature Modulation
ISDN
Integrated Services Digital Network
ISM
Industrial, Scientific and Medical
Kalimba
DSP core for CSR’s range of chips
ksps
KiloSamples Per Second
L2CAP
Logical Link Control and Adaptation Protocol (protocol layer)
LC
Link Controller
LCD
Liquid Crystal Display
LFBGA
Low profile Fine Ball Grid Array
LMP
Link Manager Protocol
LNA
Low Noise Amplifier
LPF
Low Pass Filter
LSB
Least-Significant Bit
MCU
MicroController Unit
µ-law
Audio Encoding Standard
MIPS
Million Instructions Per Second
MMU
Memory Management Unit
MISO
Master In Serial Out
NOB
Number Of Bits
OHCI
Open Host Controller Interface
PA
Power Amplifier
PCM
Pulse Code Modulation. Refers to digital voice data
PDA
Personal Digital Assistant
Persistent Store
Storage of BlueCore’s configuration values in non-volatile memory
PIO
Parallel Input Output
PICS
Profile Implementation Confirmation Statement
pk-pk
Peak to Peak
PLL
Phase Lock Loop
ppm
parts per million
PS Key
Persistent Store Key
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
FSK
Page 92 of 94
Terms and Definitions
Random Access Memory
REB
Read enable (Active Low)
REF
Reference. Represents dimension for reference use only.
RF
Radio Frequency
RFCOMM
Protocol layer providing serial port emulation over L2CAP
RISC
Reduced Instruction Set Computer
rms
root mean squared
RSSI
Receive Signal Strength Indication
RTS
Ready To Send
RX
Receive or Receiver
SCO
Synchronous Connection-Oriented. Voice oriented Bluetooth packet
SDK
Software Development Kit
SDP
Service Discovery Protocol
SIG
Special Interest Group
SINAD
SIgnal to Noise ratio And Distortion
SNR
Signal to Noise Ratio
SPDIF
Sony and Philips Interface Specification
SPI
Serial Peripheral Interface
SSI
Synchronous Serial Interface
TBD
To Be Defined
TCXO
Temperature Controlled crystal Oscillator
TX
Transmit or Transmitter
UART
Universal Asynchronous Receiver Transmitter
UHCI
Upper Host Control Interface
USB
Universal Serial Bus or Upper Side Band (depending on context)
VCO
Voltage Controlled Oscillator
VFBGA
Very Fine Ball Grid Array
VM
Virtual Machine
W-CDMA
Wideband Code Division Multiple Access
WEB
Write Enable (Active Low)
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
RAM
Page 93 of 94
Document History
19 Document History
Date
Revision
Reason for Change
FEB 05
a
Original publication of this document. (CSR reference: BC41B143A-ds-001Pa)
MAR 05
a
Document identification number revised to BC41B143A-ds-003Pa. Amended Device
Diagram. Amended VDD_USB terminal function description. Added Balun and Filter
block description. Minor amends.
APR 05
b
Amended maximum baud rate to 3M baud and added additional data rates.
Updated Auxilliary DAC in Description of Functional Blocks
Amendment to note (a) concerning specified output voltage in the Auxilliary DAC
table (Input/Output Terminal Characteristics) in Electrical Characteristics.
JUL 05
c
Amendment to note (g) concerning VREG_EN and VREG_IN in Linear Regulator
table in Electrical Characteristics.
Power Consumption moved from Radio Characteristics to Electrical Characteristics
section.
Changed title of Record of Changes to Document History; changed title of Acronyms
and Abbreviations to Terms and Definitions.
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»
Product Data Sheet
BC41B143A-DS-003Pc
July 2005
BC41B143A-ds-003Pc
Advance Information
© Cambridge Silicon Radio Limited 2005
Page 94 of 94
_äìÉ`çêÉ»QJolj=mäìÖJåJdç»= Data Sheet
Electrical Characteristics and Radio Characteristics - Basic Data Rate updated to
reflect a radio performance temperature range of -40°C to +85°C.