SCAS047D − MARCH 2003 − REVISED JUNE 2005
D Recommended Applications:
D
D
D
D
D
D
D
− DDR Memory Modules
(DDR400/333/266/200)
− Zero Delay Fan-Out Buffer
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle): ±35 ps
Low Static Phase Offset: ±50 ps
Low Jitter (Period): ±30 ps
1-To-10 Differential Clock Distribution
(SSTL2)
Best in Class for VOX = VDD/2 ±0.1 V
D Operates From Dual 2.6-V or 2.5-V Supplies
D Available in a 40-Pin MLF Package, 48-Pin
D
D
D
D
D
TSSOP Package, 56-Ball MicroStar Junior
BGA Package
Consumes < 100-µA Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
Meets/Exceeds JEDEC Standard
(JESD82−1) For DDRI-200/266/333
Specification
Meets/Exceeds Proposed DDRI-400
Specification (JESD82−1A)
Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
description
The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able
to track spread spectrum clocking for reduced EMI.
Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial
and industrial temperature ranges.
AVAILABLE OPTIONS
TA
TSSOP (DGG)
40-Pin MLF
56-Ball BGA †
−40°C to 85°C
CDCVF857DGG
(Pb-Free)
CDCVF857RTB
CDCVF857GQL
CDCVF857RHA
(Pb-Free, Green)
−40°C to 85°C
† Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum TA allowed is 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
! "#$ ! %#&'" ($
(#"! " !%$""! %$ )$ $! $*! !#$!
!(( +, (#" %"$!!- ($! $"$!!', "'#($
$!- '' %$$!
POST OFFICE BOX 655303
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1
SCAS047D − MARCH 2003 − REVISED JUNE 2005
FUNCTION TABLE
(Select Functions)
INPUTS
OUTPUTS
PLL
AVDD
GND
PWRDWN
CLK
CLK
Y[0:9]
Y[0:9]
FBOUT
FBOUT
H
L
H
L
H
L
H
Bypassed/Off
GND
H
H
L
H
L
H
L
Bypassed/Off
X
L
L
H
Z
Z
Z
Z
Off
X
L
H
L
Z
Z
Z
Z
Off
2.5 V (nom)
H
L
H
L
H
L
H
On
2.5 V (nom)
H
H
L
H
L
H
L
On
2.5 V (nom)
X
<20 MHz
<20 MHz
Z
Z
Z
Z
Off
DGG PACKAGE (TSSOP)
(TOP VIEW)
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
13
14
37
36
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
40 39 38 37 36 35 34 33 32 31
GND
Y2
Y2
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
1
30
2
29
3
28
4
27
26
5
GND
6
POST OFFICE BOX 655303
25
7
24
8
23
9
22
21
10
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
VDDQ
FBOUT
FBOUT
11 12 13 14 15 16 17 18 19 20
40-pin HP-VFQFP-N (6,0 x 6,0-mm Body Size,
0,5-mm Pitch, M0#220, Variation VJJD-2,
E2 = D2 = 2,9 mm ± 0,15 mm) Package Pinouts
48-pin TSSOP (MO-153-ED)
2
Y6
4
RHA/RTB PACKAGE (MLF)
(TOP VIEW)
Y8
46
VDDQ
Y8
3
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
Y4
Y9
Y9
47
VDDQ
Y4
48
2
Y1
Y1
VDDQ
Y0
Y0
Y5
Y5
VDDQ
Y6
1
Y3
Y3
GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
• DALLAS, TEXAS 75265
SCAS047D − MARCH 2003 − REVISED JUNE 2005
1
2
3
4
Y5
Y5
GND
V DDQ
GND
V DDQ
Y0
Y0
MicroStar Junior BGA (GQL) Package
(TOP VIEW)
5
6
A
Y1
Y1
B
Y6
Y6
C
Y2
Y2
VDDQ
VDDQ
CLK
CLK
NC
NC
GND
GND
D
NC
GND
GND
NC
Y7
Y7
NB
E
F
NB
NB
G
NC
NC
H
NC
NC
PWRDN
VDDQ
FBIN
FBIN
VDDQ
FBOUT
VDDQ
AVDD
FBOUT
GND
J
Y8
Y8
Y9
Y9
GND
GND
V DDQ
V DDQ
K
Y4
Y3
Y3
Y4
AGND
GND
NB = No ball
NC = No connection
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3
SCAS047D − MARCH 2003 − REVISED JUNE 2005
functional block diagram
3
2
PWRDWN
AVDD
5
37
16
6
Power Down
and Test
Logic
10
9
20
19
22
23
46
47
CLK
CLK
FBIN
FBIN
13
44
14
36
43
PLL
39
35
40
29
30
27
26
32
33
4
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• DALLAS, TEXAS 75265
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
SCAS047D − MARCH 2003 − REVISED JUNE 2005
Terminal Functions
TERMINAL
NAME
AGND
DGG
RHA/RTB
GQL
17
9
H1
I/O
Ground for 2.5-V analog supply
2.5-V analog supply
AVDD
CLK, CLK
16
8
G2
13, 14
5, 6
F1, F2
FBIN, FBIN
35, 36
25, 26
FBOUT, FBOUT
32, 33
21, 22
1, 7, 8, 18, 24,
25, 31, 41, 42, 48
1, 10
A3, A4, C1, C2, C5,
C6, H2, H5, K3, K4
37
27
E6
VDDQ
4, 11, 12, 15, 21,
28, 34, 38, 45
4, 7, 13, 18, 23,
24, 28, 33, 38
B3, B4, E1, E2, E5,
G1, G6, J3, J4
Y0, Y0
3, 2
37, 36
A1, A2
O
Y1, Y1
5, 6
39, 40
B2, B1
O
GND
PWRDWN
DESCRIPTION
I
Differential clock input
F5, F6
I
Feedback differential clock input
H6, G5
O
Feedback differential clock output
Ground
I
Output enable for Y and Y
2.5-V supply
Y2, Y2
10, 9
3, 2
D1, D2
O
Y3, Y3
20, 19
12,11
J2, J1
O
Y4, Y4
22, 23
14, 15
K1, K2
O
Y5, Y5
46, 47
34, 35
A6, A5
O
Y6, Y6
44, 43
32, 31
B5, B6
O
Y7, Y7
39, 40
29, 30
D6, D5
O
Y8, Y8
29, 30
19, 20
J5, J6
O
Y9, Y9
27, 26
17, 16
K6, K5
O
Buffered output copies of input clock, CLK, CLK
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDDQ, AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
qJA For TSSOP (DGG) Package (see Note 3)
Airflow
Low K
High K
qJA For MLF (RHA/RTB) Package
Airflow
With 4 Thermal Vias
0 ft/min
89.1°C/W
70°C/W
0 ft/min
150 ft/min
78.5°C/W
65.3°C/W
150 ft/min
44.7°C/W
qJA For BGA(GQL) Package (see Note 4)
Airflow
High K
0 ft/min
132.2°C/W
150 ft/min
126.4°C/W
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1.
2.
3.
4.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
This value is limited to 3.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
Connecting the NC-balls (C3, C4, D3, D4, G3, G4, H3, H4) to a ground plane improves the θJA to 114.8°C/W (0 airflow).
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5
SCAS047D − MARCH 2003 − REVISED JUNE 2005
recommended operating conditions (see Note 5)
MIN
VDDQ
AVDD
Supply voltage
PC1600 − PC3200
2.3
2.7
2.7
−0.3
VDDQ/2 – 0.18
0.7
PWRDWN
CLK, CLK, FBIN, FBIN
High-level input voltage, VIH
PWRDWN
MAX
VDDQ − 0.12
CLK, CLK, FBIN, FBIN
Low-level input voltage, VIL
TYP
VDDQ/2 + 0.18
1.7
DC input signal voltage (see Note 5)
Differential input signal voltage, VID (see Note 6)
CLK, FBIN
0.36
ac
CLK, FBIN
0.7
Input differential pair cross voltage, VIX (see Notes 7 and 8)
VDDQ/2 – 0.2
V
V
V
VDDQ/2 + 0.2
−12
Low-level output current, IOL
Operating free-air temperature, TA
V
VDDQ + 0.6
VDDQ + 0.6
High-level output current, IOH
Input slew rate, SR
V
VDDQ + 0.3
VDDQ + 0.3
–0.3
dc
UNIT
V
mA
12
mA
1
4
V/ns
−40
85
°C
NOTES: 5. The unused inputs must be held high or low to prevent them from floating.
6. The dc input signal voltage specifies the allowable dc execution of the differential input.
7. The differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input
level and VCP is the complementary input level.
8. The differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must
be crossing.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
VOD
VOX
Output voltage swing}
II
IOZ
Input current
TEST CONDITIONS
All inputs
Output differential cross-voltagew
High-impedance state output current
IDDPD
Power-down current on
VDDQ + AVDD
AIDD
Supply current on AVDD
VDDQ = 2.3 V, II = –18 mA
VDDQ = min to max, IOH = –1 mA
VDDQ = 2.3 V, IOH = –12 mA
VDDQ = min to max, IOL = 1 mA
MIN
TYP†
VDDQ = 2.7 V, VI = 0 V to 2.7 V
VDDQ = 2.7 V, VO= VDDQ or GND
CLK and CLK = 0 MHz;
PWRDWN = Low; Σ of IDD and AIDD
fO = 170 MHz
fO = 200 MHz
UNIT
–1.2
V
VDDQ – 0.1
1.7
V
0.1
VDDQ = 2.3 V, IOL = 12 mA
Differential outputs are terminated with
120 Ω /CL = 14 pF (See Figure 3)
MAX
0.6
1.1
VDDQ/2 – 0.1
VDDQ/2
20
V
VDDQ – 0.4
VDDQ/2 + 0.1
V
±10
µA
±10
µA
100
µA
6
8
8
10
mA
CI
Input capacitance
VDDQ = 2.5 V, VI = VDDQ or GND
2
2.5
3.5
pF
† All typical values are at a respective nominal VDDQ.
‡ The differential output signal voltage specifies the differential voltage VTR − VCP, where VTR is the true output level and VCP is the
complementary output level.
§ The differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
6
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
TYP†
MAX
120
140
Without load
fO = 170 MHz
fO = 200 MHz
125
150
Differential outputs terminated with
120 Ω/CL = 0 pF
fO = 170 MHz
fO = 200 MHz
220
270
230
280
fO = 170 MHz
fO = 200 MHz
280
330
300
350
PARAMETER
IDD
TEST CONDITIONS
Dynamic current on VDDQ
∆C
Part-to-part input capacitance variation
Differential outputs terminated with
120 Ω/CL = 14 pF
VDDQ = 2.5 V, VI = VDDQ or GND
CI(∆)
Input capacitance difference between
CLK and CKB, FBIN, and FBINB
VDDQ = 2.5 V, VI = VDDQ or GND
MIN
UNIT
mA
1
pF
0.25
pF
† All typical values are at a respective nominal VDDQ.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
fCLK
MIN
MAX
Operating clock frequency
60
220
Application clock frequency
90
220
40%
60%
Input clock duty cycle
Stabilization time{ (PLL mode)
Stabilization time} (bypass mode)
UNIT
MHz
10
µs
30
ns
† The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,
a fixed-frequency, fixed-phase reference signal must be present at CLK and VDD must be applied. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply
for input modulation under SSC application.
‡ A recovery time is required when the device goes from power-down mode into bypass mode (AVDD at GND).
switching characteristics
PARAMETER
tPLHw
tPHLw
TEST CONDITIONS
Low-to-high level propagation delay time
Test mode/CLK to any output
High-to-low level propagation delay time
Test mode/CLK to any output
MIN
TYP
MAX
3.5
UNIT
ns
3.5
ns
100 MHz (PC1600)
−65
65
133/167/200 MHz (PC2100/2700/3200)
−30
30
100 MHz (PC1600)
−50
50
133/167/200 MHz (PC2100/2700/3200)
−35
35
−100
100
−75
75
1
2
V/ns
–50
50
ps
40
ps
tjit(per)W
Jitter (period), See Figure 7
tjit(cc)W
Jitter (cycle-to-cycle), See Figure 4
tjit(hper)W
Half-period jitter, See Figure 8
tslr(o)
t(Ø)
Output clock slew rate, See Figure 9
Load: 120 Ω/14 pF
Static phase offset, See Figure 5
100/133/167/200 MHz
100 MHz (PC1600)
133/167/200 MHz (PC2100/2700/3200)
tsk(o)
Output skew, See Figure 6
Load: 120 Ω/14 pF 100/133/167/200 MHz
§ Refers to the transition of the noninverting output.
¶ This parameter is assured by design but can not be 100% production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ps
ps
ps
7
SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VDD
VYx
R = 60 Ω
R = 60 Ω
VDD/2
VYx
CDCVF857
GND
Figure 1. IBIS Model Output Load
VDD/2
CDCVF857
C = 14 pF
R = 10 Ω
Z = 60 Ω
SCOPE
−VDD/2
Z = 50 Ω
R = 50 Ω
V(TT)
Z = 60 Ω
R = 10 Ω
Z = 50 Ω
C = 14 pF
R = 50 Ω
V(TT)
−VDD/2
V(TT) = GND
−VDD/2
Figure 2. Output Load Test Circuit
8
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
VDD
CDCVF857
C = 14 pF
PROBE
GND
Z = 60 Ω
C = 1 pF
R = 120 Ω
R = 1 MΩ
V(TT)
Z = 60 Ω
C = 1 pF
C = 14 pF
R = 1 MΩ
V(TT)
GND
V(TT) = GND
GND
Figure 3. Output Load Test Circuit for Crossing Point
Yx, FBOUT
Yx, FBOUT
tc(n)
tc(n+1)
tjit(cc) = tc(n) − tc(n+1)
Figure 4. Cycle-to-Cycle Jitter
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9
SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
CLK
CLK
FBIN
FBIN
t( ) n
∑1
t ( ) n+1
n=N
t( ) =
t( ) n
N
(N > 1000 Samples)
Figure 5. Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure 6. Output Skew
10
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
Yx, FBOUT
Yx, FBOUT
tc(n)
Yx, FBOUT
Yx, FBOUT
1
fo
tjit(per) = tcn −
1
fo
fO = Average input frequency measured at CLK/CLK
Figure 7. Period Jitter
Yx, FBOUT
Yx, FBOUT
t(hper_n+1)
t(hper_n)
1
fo
tjit(hper) = t(hper_n) − 1
2xfo
n = any half cycle
fO = Average input frequency measured at CLK/CLK
Figure 8. Half-Period Jitter
VOH, VIH
80%
Clock Inputs
and Outputs
80%
20%
20%
VOL, VIL
tr
t
slr(IńO)
V
* V 20%
+ 80%
t
r(IńO)
tf
t
slf(IńO)
V
* V 20%
+ 80%
t
f(IńO)
Figure 9. Input and Output Slew Rates
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11
SCAS047D − MARCH 2003 − REVISED JUNE 2005
CARD
VIA
V
Bead
0603
AV DD
DDQ
4.7 uF
1206
0.1 uF
0603
2200 pF
0603
PLL
GND
AGN D
CARD
VIA
See Notes 9, 10, and 11
Figure 10. Recommended AVDD Filtering
NOTES: 9. Place the 2200-pF capacitor close to the PLL.
10. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND
via (farthest from the PLL).
11. Recommended bead: Fair-Rite P/N 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz).
12
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SCAS047D − MARCH 2003 − REVISED JUNE 2005
THERMAL INFORMATION
This package incorporates an exposed thermal pad that is designed to be attached directly to an external
heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB), the PCB can be used
as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground
plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report,
Quad Flatpack No-Lead Packages, Texas Instruments Literature No. SCBA017. This document is available at
www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
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13
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCVF857DGG
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCVF857DGGG4
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCVF857DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCVF857DGGRG4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCVF857GQLR
ACTIVE
VFBGA
GQL
56
1000
Call TI
Level-2A-220C-4 WKS
CDCVF857RHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCVF857RHARG4
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCVF857RHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCVF857RHATG4
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCVF857RTBR
ACTIVE
QFN
RTB
40
2500
TBD
CU SNPB
Level-3-235C-168 HR
CDCVF857RTBT
ACTIVE
QFN
RTB
40
250
TBD
CU SNPB
Level-3-235C-168 HR
TBD
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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• DALLAS, TEXAS 75265
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