ETC CMI9761A

CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
C-Media CMI9761A / 9761A+
6 Channel AC’97 2.3 Audio Codec
DataSheet, Revision 1.2
Feb. 9, 2004
C-Media Electronics, Inc.
6F, 100, Sec. 4, Civil Boulevard, Taipei, Taiwan 106, R.O.C.
TEL: 886-2-8773-1100
FAX: 886-2-8773-2211
http://www.cmedia.com.tw
For detailed product information, please contact sales@cmedia.com.tw
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
NOTICES
THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES
WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY,
NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY
WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, DOCUMENT
OR SAMPLE.
ALL RIGHTS RESERVED. NO PART OF THIS DOCUMENT MAY BE
REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS,
ELECTRONIC OR MECHANICAL, INCLUDING INFORMATION STORAGE
AND RETRIEVAL SYSTEMS, WITHOUT PERMISSION IN WRITING FROM
THE C-MEDIA ELECTRONICS, INC.
Third-party brands and names are the property of their respective owners.
Copyright 2003-2004 © C-Media Electronics Inc.
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
Contents
0.
1.
2.
3.
4.
5.
Revision History ....................................................................................................3
Product Summary...................................................................................................3
Features ..................................................................................................................4
Overview................................................................................................................6
Pin Assignment ......................................................................................................8
Pin / Signal Descriptions........................................................................................9
5.1
Power / Ground ..........................................................................................9
5.2
AC-Link / Clocking ...................................................................................9
5.3
Digital I/O ................................................................................................10
5.4
Analog I/O ...............................................................................................10
5.5
Filter / Reference...................................................................................... 11
5.6
Configuration ........................................................................................... 11
6. Jack Detection and Configuration Information....................................................12
6.1
Resistors Network Method ......................................................................12
6.2
Configuration Diagram ............................................................................13
7. DC Characteristics ...............................................................................................14
8. AC-Link Timing Characteristics..........................................................................15
8.1
Cold Reset Timing ...................................................................................15
8.2
Warm Reset Timing .................................................................................15
8.3
AC-Link Clocks .......................................................................................16
8.4
Data Output and Input Timing .................................................................17
8.5
Signal Rise and Fall Timing.....................................................................18
8.6
AC-Link Low Power Mode Timing.........................................................19
8.7
ATE Test Mode ........................................................................................19
9. Analog Performance Characteristics....................................................................20
10.
Package Dimension..........................................................................................21
Copyright 2003-2004 © C-Media Electronics Inc.
Page 1
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Pin Assignment ..........................................................................................8
Resistors Network Method for Jack Detection ........................................12
Recommended Configuration Diagram ...................................................13
Cold Reset Timing Diagram ....................................................................15
Warm Reset Timing Diagram ..................................................................15
BIT_CLK and SYNC Timing Diagram ...................................................16
Data Output and Input Timing Diagram ..................................................17
Signal Rise and Fall Timing Diagram......................................................18
AC-Link Low Power Mode Timing Diagram..........................................19
ATE Test Mode Timing Diagram.........................................................19
Mechanical Dimension ........................................................................21
Copyright 2003-2004 © C-Media Electronics Inc.
Page 2
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
0. Revision History
2003/06/23 Rev 1.0
2003/08/26 Rev 1.1
2004/02/09 Rev 1.2
Initial revision
Fixed some typos.
Change datasheet title for both CMI9761A & 9761A+
1. Product Summary
Product
Dolby® Digital real-time Interactive
Content Encoder (DDICE)
9761A+
Yes
9761A
N/A
Copyright 2003-2004 © C-Media Electronics Inc.
Page 3
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
2. Features
Basic features:
6 channel, 16-bits DACs with SNR > 90 dB.
2 channel, 16-bits ADCs with SNR > 85 dB.
New features of AC’97 2.3 codec:
Digital PC Beep support.
2 Stereo microphone support.
Extensive jack detection via proprietary resistors network method
that can monitor plugging status of every jack.
Precise advanced impedance sensing function for audio device
class discoverability.
Miscellaneous features:
Compliant with Intel® AC’97 Rev 2.3 Spec.
Meeting with Microsoft® PC2001 requirements
Built-in 14.318MHz to 24.576MHz PLL, which can save the BOM
cost of external crystal.
Advanced power management and power saving capabilities.
Industry standard 48-lead LQFP package.
Analog power supply is 5V, digital power supply is 3.3V.
Versatile I/O & functionalities support:
Stereo Line-in function shared with Surround out.
Stereo Microphone function shared with Center/LFE out.
High quality pseudo-differential analog CD Audio input.
Dual analog & digital PC BEEP support.
AUX legacy analog I/O support.
2 GPIO (General Purpose I/O) support.
EAPD (External Amplifier Power Down) support.
S/PDIF I/O function:
Output: 96 / 48 kHz with 24 / 20 / 16 bits
Input: 48 / 44.1 / 32 kHz with 20 / 16 bits
S/PDIF In is featured with interrupt, auto-lock, anti-noise, and
anti-distortion functionalities support.
Copyright 2003-2004 © C-Media Electronics Inc.
Page 4
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
Valuable add-on software technology:
CMI9761A+ supports Dolby® Digital Interactive Content Encoder
(DDICE) for easy-connection with consumer acoustics as media
center/game console applications
Xear3D™ sound support, including Earphone Plus and 5.1CH
SPEAKER SHIFTER.
Sensaura® HRTF 3D positional sound support.
Support most industry standards of PC 3D sound for gaming,
including Creative EAX™ 2.0 / 1.0 , Microsoft DirectSound™ 3D,
A3D™ 1.0 and more.
Unique karaoke function support featured with microphone echo,
key shifting, and vocal cancellation.
10-band equalizer with 12 pre-set settings.
27 kinds of listening environments support together with 3 kinds
of room sizes emulation.
Dynamic AGC(auto-gain control) technology.
Copyright 2003-2004 © C-Media Electronics Inc.
Page 5
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
3. Overview
C-Media CMI9761A/9761A+ is a 6 channel, Intel® AC’97 rev 2.3
compliant audio codec. The applicable M/B chipsets are extensive,
including Intel® ICHx series as well as those supplied by SiS®, VIA®,
Ali®, and nVidia®. The excellent audio quality (A/A SNR > 90dB)
makes CMI9761A/9761A+ ideal for designing Microsoft® PC2001
compliant PC multimedia desktops and notebooks.
The various features implemented within CMI9761A/9761A+ can help
users to enjoy the PC audio smoothly without any frustration. The
most important of all is jack detection & impedance sensing that can
minimize user’s intervention and try-and-error during setup. There
are also creative applications such as automatically enabling
pre-defined equalization for different audio devices. With precise
advanced sensing technology, CMI9761A/9761A+ can determine
most device classes without miss. CMI9761A/9761A+ can make a
fantastic impression on end users and also reduce the cost of support
for setup of audio environment. The digital PC Beep support can
further improve the quality of analog output by eliminating the
traditional noisy analog PC Beep.
The S/PDIF out function makes connection easily from PC to CE
products, such as AC3/DTS decoder or Minidisk. The 96 kHz / 24 bits
S/PDIF output capability of CMI9761A/9761A+ can easily distribute
the premium-quality stereo PCM audio to CE equipments. Combining
with value add-on software such as Xear3D™ technology,
CMI9761A/9761A+ is able to fulfill the most rigid requirements of
audiophiles. Not to mention, CMI9761A/9761A+ can transmit DVD
industry standard multi-channel Dolby® Digital audio stream to
external decoder utilizing S/PDIF link and enjoy the Home Theater
concept.
The built-in PLL and earphone buffer can help our customers to save
the BOM cost and create a cost-effective end product. Together with
the flexible shared audio function design and dedicated multi-channel
output, the design of end products can be as versatile and creative as
Copyright 2003-2004 © C-Media Electronics Inc.
Page 6
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
possible.
Copyright 2003-2004 © C-Media Electronics Inc.
Page 7
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
4. Pin Assignment
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal Name
DVDD1
XTL_IN
XTL_OUT
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET#
PCBEEP
SENSE B
AUX_L
AUX_R
NC
NC
CD_L
CD_C
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Name
AVDD1
AVSS1
VREF
VRO1
VRO2
NC
NC
NC
FMIC_R
FMIC_L
LINEOUT_L
LINEOUT_R
EXT_R
AVDD2
REAROUT_L
SENSE A
REAROUT_R
AVSS2
CENTER_OUT
LFE_OUT
HP_ON / GPIO0
XTLSEL / GPIO1
EAPD / SPDIFI
SPDIFO
C-Media
CMI9761A/9761A+
Figure 1. Pin Assignment
Copyright 2003-2004 © C-Media Electronics Inc.
Page 8
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
5. Pin / Signal Descriptions
5.1 Power / Ground
The digital portion of CMI9761A/9761A+ operates at 3.3V and the
analog portion operates at 5V. The grounds should be separated well
to assure the best analog audio quality.
Pin No
Signal Name
Type
Description
1
DVDD1
I
Digital VDD (3.3V)
4
DVSS1
I
Digital ground
7
DVSS2
I
Digital ground
9
DVDD2
I
Digital VDD (3.3V)
25
AVDD1
I
Analog VDD (5V)
26
AVSS1
I
Analog ground
38
AVDD2
I
Analog VDD (5V)
42
AVSS2
I
Analog ground
5.2 AC-Link / Clocking
These signals connect CMI9761A/9761A+ to its AC’97 controller
counterpart and external crystal / oscillator clock source.
Pin No
Signal Name
Type
Description
2
XTL_IN
I
24.576 MHz crystal input or 14.318
MHz oscillator input
3
XTL_OUT
O
24.576 MHz crystal output or NC (for
14.318 MHz oscillator input)
5
SDATA_OUT
I
Serial, time division multiplexed, input
stream from the AC’97 controller.
6
BIT_CLK
O
12.288 MHz bit clock output
8
SDATA_IN
O
Serial, time division multiplexed,
output stream to the AC’97 controller.
10
SYNC
I
48 kHz sample sync
11
RESET#
I
AC’97 master H/W reset
Note: # denotes active low
Copyright 2003-2004 © C-Media Electronics Inc.
Page 9
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
5.3 Digital I/O
These signals are digital inputs and outputs of CMI9761A/9761A+
that includes S/PDIF I/O and GPIO.
Pin No
Signal Name
Type
Description
45
HP_ON/GPIO0 I/O
Headphone ON detection / General
Purpose I/O #0
46
XTLSEL/GPIO1 I/O
Clock source selection / General
Purpose I/O #1
47
EAPD/SPDIFI
External Amplifier Power Down or
S/PDIF input
48
SPDIFO
I/O
O
S/PDIF output
5.4 Analog I/O
These signals connect CMI9761A/9761A+ to analog sources and sinks,
including microphones and speakers.
Pin No
Signal Name
Type
Description
12
PCBEEP
I
Analog PCBEEP input
14
AUX_IN_L
I
Aux input left channel
15
AUX_IN_R
I
Aux input right channel
18
CD_L
I
CD audio input left channel
19
CD_C
I
CD audio common channel
20
CD_R
I
CD audio input right channel
21
MIC1
I/O
Stereo microphone left channel /
Alternative center channel output
22
MIC2
I/O
Stereo microphone right channel /
Alternative LFE channel output
23
LINE_IN_L
I/O
Line-In input left channel /
Alternative rear output left channel
24
LINE_IN_R
I/O
Line-In input right channel /
Alternative rear output right channel
33
FMIC_R
I
Front panel stereo microphone right
channel
34
FMIC_L
I
Front panel stereo microphone left
channel
35
LINEOUT_L
O
Line output left channel
36
LINEOUT_R
O
Line output right channel
39
REAROUT_L
O
Dedicated rear output left channel
Copyright 2003-2004 © C-Media Electronics Inc.
Page 10
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
Pin No
Signal Name
Type
Description
41
REAROUT_R
O
Dedicated rear output right channel
43
CENTER_OUT
O
Dedicated center output channel
44
LFE_OUT
O
Dedicated LFE output channel
5.5 Filter / Reference
These signals of CMI9761A/9761A+ connected to resistors or
capacitors.
Pin No
Signal Name
Type
Description
27
VREF
O
Reference voltage
28
VRO1
O
Reference voltage out for MIC2 bias
29
VRO2
O
Reference voltage out for MIC1 bias
37
EXT_R
O
External 1KΩ precision resistor
calibration for impedance sensing
5.6 Configuration
These pins utilize C-Media proprietary parallel resistors method for
jack detection.
Pin No
Signal Name
Type
Description
13
Sense B
I
Sensing pin B
40
Sense A
I
Sensing pin A
Note: For detailed information, please refer to Sec. 5.1 to facilitate the
implementation of resistors network.
Copyright 2003-2004 © C-Media Electronics Inc.
Page 11
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
6. Jack Detection and Configuration Information
In this section, we describe the resistors network method for jack
detection and configuration identification. And also, due to the design
of CMI9761A/9761A+ with shared audio function and dedicated
multi-channel output, the configuration of audio system can be as
versatile as possible.
6.1 Resistors Network Method
+5VA
1K
To Sense Pin
1K
2K
4K
8K/Open
C
J1
J2
B
J3
A
A. The switch will be closed if audio connector is plugged in.
B. The switch will be open if audio connector is plugged out.
C. The configuration is identified if a weighting resistor is attached.
Figure 2. Resistors Network Method for Jack Detection
The sense pin connects to an ADC internally to measure the resistance
of the network. CMI9761A/9761A+ is able to monitor the plugging
status of each jack according to the resistance measured. To obtain a
correct result, the value of each precision resistor should not be
modified from the specified schematics provided by C-Media for any
reason.
Copyright 2003-2004 © C-Media Electronics Inc.
Page 12
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
6.2 Configuration Diagram
C-Media CMI9761A - Recommended Configuration Diagram
1
Optional front panel : 2 Jacks
HP Out
Front Panel
MIC
Rear Panel : 3 Jacks
CMI9761A
2
Additional Bracket
Line Out
Line-In /
Rear Out
MIC /
C/B Out
Optional bracket : 2 Jacks
Rear Out
C/B Out
3
Optional S/PDIF module
SPI
S/PDIF Module
CD
AUX
SPO
VIDEO
OPT
SPO
OPT
SPI
Internal Analog Input
Figure 3. Recommended Configuration Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 13
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
7. DC Characteristics
Parameter
Symbol
Minimum
Digital power supply
DVdd
3.135
3.3
3.465
V
Input voltage range
Vin
-0.30
-
DVdd+0.3
V
Low level input voltage
Vil
-
-
0.35xDVdd V
High level input voltage
Vih
0.65xDVdd
-
-
V
High level output voltage
Voh
0.90xDVdd
-
-
V
Low level output voltage
Vol
-
-
Input leakage current
(AC-Link inputs)
-
-10
-
10
µA
Output leakage current
(Hi-Z’d AC-Link outputs)
-
-10
-
10
µA
Input/Output Pin
Capacitance
-
-
-
7.5
pF
Copyright 2003-2004 © C-Media Electronics Inc.
Typical Maximum Units
0.10xDVdd V
Page 14
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
8. AC-Link Timing Characteristics
8.1 Cold Reset Timing
Parameter
Symbol Minimum Typical Maximum Units
RESET# active low pulse width Trst_low
1.0
-
-
µs
REEST# inactive to SDATA_IN
Ttri2actv
or BIT_CLK active delay
-
-
25
ns
RESET# inactive to BIT_CLK
startup delay
Trst2clk
162.8
-
-
ns
BITCLK active to RESET#
asserted
Tclk2rst
0.416
-
-
µs
Figure 4. Cold Reset Timing Diagram
8.2 Warm Reset Timing
Parameter
Symbol Minimum Typical Maximum Units
SYNC active high pulse width Tsync_high
SYNC inactive to BIT_CLK
startup delay
Tsync2clk
1.0
-
-
µs
162.8
-
-
ns
Figure 5. Warm Reset Timing Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 15
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
8.3 AC-Link Clocks
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
Tclk_period
BIT_CLK output jitter
Minimum Typical Maximum Units
-
12.288
-
MHz
-
81.4
-
ns
-
-
750.0
ps
BLT_CLK high pulse width
(note 1)
Tclk_high
36.0
40.7
45.0
ns
BIT_CLK low pulse width
(note 1)
Tclk_low
36.0
40.7
45.0
ns
-
48.0
-
kHz
Tsync_period
-
20.8
-
µs
SYNC high pulse width
Tsync_high
-
1.3
-
µs
SYNC low_pulse width
Tsync_low
-
19.5
-
µs
SYNC frequency
SYNC period
Note 1: Worse case duty cycle restricted to 45/55.
Figure 6. BIT_CLK and SYNC Timing Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 16
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
8.4 Data Output and Input Timing
Parameter
Output valid delay from rising
edge of BIT_CLK
Symbol Minimum Typical Maximum Units
Tco
-
-
15.0
ns
Note: 50pF external load.
Parameter
Symbol Minimum Typical Maximum Units
Input Setup to falling edge of
Tsetup
BIT_CLK
10.0
-
-
ns
Input Hold from falling edge of
Thold
BIT_CLK
10.0
-
-
ns
Parameter
Symbol Minimum Typical Maximum Units
BIT_CLK combined rise or fall
plus flight time
-
-
-
7.0
ns
SDATA combined rise or fall
plus flight time
-
-
-
7.0
ns
Note: Combined rise or fall plus flight times are provided for worst case
scenario modeling purposes.
Figure 7. Data Output and Input Timing Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 17
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
8.5 Signal Rise and Fall Timing
The rise time is from 10% to 90% of VDD (Vol to Voh). The fall time is
from 90% to 10% of VDD (Voh to Vol).
Parameter
Symbol Minimum Typical Maximum Units
BIT_CLK rise time (note 1)
Triseclk
-
-
6.0
ns
BIT_CLK fall time (note 1)
Tfallclk
-
-
6.0
ns
SYNC rise time (note 1)
Trisesync
-
-
6.0
ns
SYNC fall time (note 1)
Tfallsync
-
-
6.0
ns
SDATA_IN rise time (note 2)
Trisedin
-
-
6.0
ns
SDATA_IN fall time (note 2)
Tfalldin
-
-
6.0
ns
SDATA_OUT rise time (note 1) Trisedout
-
-
6.0
ns
SDATA_OUT fall time (note 1) Tfalldout
-
-
6.0
ns
Note 1: 75pF external load
Note 2: 60pF external load
Figure 8. Signal Rise and Fall Timing Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 18
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
8.6 AC-Link Low Power Mode Timing
Parameter
Symbol Minimum Typical Maximum Units
End of Slot 2 to BIT_CLK,
SDATA_IN low
Ts2_pdown
-
-
1.0
µs
Figure 9. AC-Link Low Power Mode Timing Diagram
8.7 ATE Test Mode
Parameter
Symbol Minimum Typical Maximum Units
Setup to trailing edge of
RESET# (also applies to
SYNC)
Rising edge of RESET# to Hi-Z
delay
Figure 10.
Tsetup2rst
15.0
-
-
ns
Toff
-
-
25.0
ns
ATE Test Mode Timing Diagram
Copyright 2003-2004 © C-Media Electronics Inc.
Page 19
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
9. Analog Performance Characteristics
The measurements are performed under the circumstance as:
Tambient = 25℃, AVdd = 5.0V ± 5%, DVdd = 3.3V ± 5%, 10kΩ/50pF
external load. Input is 1 kHz sine wave; Sampling frequency = 48 kHz;
Bandwidth = 20 to 20 kHz; 0dB attenuation; All sound effects such as
3D effects are disabled.
Parameter
Minimum Typical Maximum Units
Full Scale Input Voltage:
Line Inputs
Mic Inputs
-
1.1
0.1
1.4
-
Vrms
Vrms
-
1.1
1.1
1.1
1.4
-
Vrms
Vrms
Vrms
20
20
20
-
20,000
20,000
20,000
Hz
Hz
Hz
-
96
92
85
-
dB
dB
dB
Full Scale Output Voltage:
LINEOUT
REAROUT
CENTER_OUT / LFE_OUT
Frequency Response
A/A
D/A
A/D
Dynamic Range
A/A
D/A
A/D
-
95
92
90
-
dB
dB
dB
-
92
75
76
-
dB
dB
dB
-
92
-
dB
-
50
10
-
mA
mA
-
2.25
-
V
SNR
A/A
D/A
A/D
Total Harmonic Distortion Plus Noise
A/A
D/A
A/D
Crosstalk between input channels @ 10KHz
Power Supply Current
AVDD (5.0V)
DVDD (3.3V)
Vrefout
Copyright 2003-2004 © C-Media Electronics Inc.
Page 20
CMI9761A/9761A+ DataSheet
2004/02/09, Rev 1.2
10. Package Dimension
Dimensions are shown in inches (mm)
Figure 11.
Mechanical Dimension
- End of DataSheet -
Copyright 2003-2004 © C-Media Electronics Inc.
Page 21