TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 2.1-GHz to 2.7-GHz 1-W Power Amplifier FEATURES • • • • • • VPOS 1.5 W P-1 dBm Linear, 30-dB Gain Transmitter Operates Over the MMDS, MDS, and WCS Bands (2.1 GHz to 2.7 GHz) Two TTL Controlled, 1-bit, 16-dB Gain Steps Superior Linearity Over the Entire Gain Range PACNT Signal Enables and Disables PA Internally Matched 50-Ω Input and Output VDD VNEG Power Supply Power Amp / Attenuator PACNT LP Driver Amplifier Pre−Amp RFI RFO DETN DETP PAGAIN1 PAGAIN0 DESCRIPTION The TRF1123 is a highly integrated linear transmitter power amplifier MMIC. The chip has two 16-dB gain steps that provide a total of 32-dB gain control via 1-bit TTL control signals. The chip also integrates a TTL mute function that turns off the amplifiers for power critical or TDD applications. A temperature compensated detector is included for output power monitor or ALC applications. The chip has a typical P1dB of 31.5 dBm and a third order intercept of 52 dBm. The TRF1123 is designed to function as a part of Texas Instruments complete 2.5-GHz chip set. The TRF1123 is used as the output power amplifier or a driver amplifier for higher power applications. The linear nature of the transmitter makes it ideal for complex modulations schemes such as high order QAM or OFDM. KEY SPECIFICATIONS • • • • • • OP1dB = 31.5 dBm, Typical Output IP3 = 52 dBm, Typical Gain = 30 dB, Typical Gain Flatness Over Transmit Band ±2.5 dB Frequency Range: 2.1 GHz to 2.7 GHz ±0.5-dB Detected Output voltage vs Temperature BLOCK DIAGRAM The detailed block diagram and the pin-out of the ASIC are shown in Figure 1. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 LP PACNT VADJ3 VADJ2 VADJ1 VPOS VNEG KEY SPECIFICATIONS (continued) VDD1 VDD2 Power Supply VDD3A VDD3B Switched Attn Power Amp / Attenuator Switched Attn Pre−Amp Driver Amp RFI RFO DETN PAGAIN0 PAGAIN1 DETP Figure 1. Detailed Block Diagram of TRF1123 ELECTROSTATIC DISCHARGE NOTE The TRF1223 contain Class 1 devices. The following Electrostatic Discharge (ESD) precautions are recommended: • Protective outer garments • Handling in ESD safeguarded work area • Transporting in ESD shielded containers • Frequent monitoring and testing all ESD protection equipment • Treating the TRF1223 as extremely sensitive to ESD PINOUT TABLE Table 1. Pinout of TRF1123 2 PIN # PIN NAME I/O TYPE DESCRIPTION 1 GND - - Ground 2 GND - - Ground 3 GND - - Ground 4 RFI I Analog 5 GND - - 6 VG1 I/O Analog 7 GND - - RF input to power amplifier, dc blocked internally. Ground No connection required for normal operation. May be used to adjust FET1 bias. DO NOT GROUND THIS PIN. Ground Submit Documentation Feedback TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 KEY SPECIFICATIONS (continued) Table 1. Pinout of TRF1123 (continued) (1) PIN # PIN NAME I/O TYPE DESCRIPTION 8 VNEG I Power Negative power supply –5 V. Used to set gate voltage. This voltage must be sequenced with VDD. See (1). 9 VPOS I Power Positive power supply. Bias is +V. Used to set gate bias and logic input level. 10 PAGAIN0 I Digital First 16-dB attenuator gain control. Logic high is high gain; logic low is low gain. 11 VG2 I/O Analog No connection required for normal operation. May be used to adjust FET2 bias. DO NOT GROUND THIS PIN. 12 PAGAIN1 I Digital Second 16-dB gain control. Logic high is high gain, Logic low is low gain. 13 VG3 I/O 14 LP I Digital Low Power Mode: Active high. Low power mode is lower DC and Pout mode. 15 PACNT I Digital Power amplifier enable, high is PA on, logic low is PA off (low current) 16 GND - - 17 VDD3B I Power 18 GND - - Ground 19 GND - - Ground 20 GND - - Ground 21 RFO O Analog 22 GND - - Ground 23 GND - - Ground 24 VDD3A I Power No connection required for normal operation. May be used to adjust FET3 bias. DO NOT GROUND THIS PIN. Ground Stage 3 dc drain supply power. This pin is internally dc connected to pin 24 (VDD3A). Bias must be provided to both pins for optimal performance. The total dc current through these two pins is typically 70% of IDD. RF output dc block is provided Stage 3 dc drain supply power. This pin is internally dc connected to pin 17 (VDD3B). Bias must be provided to both pins for optimal performance. The total dc current through these two pins is typically 70% of IDD. 25 GND - - 26 DETP O Analog Ground Detector output, positive. Voltage will be 0.5 V with/without RF output 27 DETN O Analog Detector output, negative. Voltage is 0.5 V with no RF and decreases with increasing RF output power. 28 VDD2 I Power Stage 2 dc drain supply power. The dc current through this pin is typically 25% of IDD. 29 GND - - Ground - Ground 30 GND 31 VDD1 - 32 GND - - Ground Back - - Back of package has metal base that must be grounded for thermal and RF performance. Stage 1 dc drain supply power. The dc current through this pin is typically 5% of IDD. Proper Sequencing: In order to avoid permanent damage to the power amplifier, the supply voltages must be sequenced. The proper power up sequence is VNEG, then VPOS, and then VDD. The proper power down sequence is remove VDD, then VPOS, and then VNEG. Submit Documentation Feedback 3 TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 ABSOLUTE MAXIMUM RATINGS PARAMETER TEST CONDITION MIN VDD VPOS DC supply voltage VNEG IDD Current consumption PIN RF input power TJ Junction temperature PD Power dissipation Digital input pins 0 +8 0 5.5 -5.5 0 -0.3 Θjc Thermal resistance junction to case (1) Tstg Storage temperature Top Operating temperature Maximum case temperature derate for PCB thermal resistance Lead temperature 40 sec maximum (1) MAX UNIT V 700 Ma 20 dBm 175 °C 5.5 W 5.5 20 °C/W -40 +105 °C -40 +85 °C 220 °C Thermal resistance is junction to case assuming thermal pad with 25 thermal vias under package metal base. See recommended layout Figure 11 and application note RA1005 for more detail. DC CHARACTERISTICS PARAMETER CONDITIONS MIN TYP MAX 7 7.35 UNIT V 600 700 mA VDD VDD supply voltage IDD VDD supply current VNEG Negative supply voltage INEG Negative supply current VPOS Positive supply digital voltage IPOS Positive supply digital current VIH Input high voltage VIL Input low voltage 0.8 V IIH Input high current 300 µA IIL Input low current -50 µA PACNTRL = High, VDD = 7 V, 25°C -5.25 4.75 -5 -4.75 15 25 5 5.25 25 50 mA 5 V 2.5 V mA V POWER AMPLIFIER CHARACTERISTICS VDD = 7 V, IDD = 600 mA, VPOS = 5 V, VNEG = -5 V, PAGAIN0 = 1, PAGAIN1 = 1, PACNT = 1, T = 25°C, unless otherwise stated PARAMETER MIN TYP F Frequency G Gain GHG Gain flatness full band GNB Gain flatness / 2 MHz OP-1dB Output power at 1-dB compression 30 31.5 OIP3 Output third order intercept point 40 52 Vdet tSTEP 4 TEST CONDITIONS 2100 26 F = 2100 MHz to 2700 MHz 30 3 MAX UNIT 2700 MHz 36 5 dB 0.2 dBm Gain step size 1st step PAGAIN0 = Low, PAGAIN1 = High 15 16 17 Gain step size 2nd step PAGAIN0 = Low, PAGAIN1 = Low 30 32 34 Detector voltage output, differential (DETP-DETN) At Pout = 27 ±0.75 dBm, F = 2100 to 2700 MHz at 25°C Detector accuracy vs temperature F=2500 MHz, -30°C to 75°C Gain step response time 150 Submit Documentation Feedback mV ±0.75 1 dB dB 5 µS TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 POWER AMPLIFIER CHARACTERISTICS (continued) VDD = 7 V, IDD = 600 mA, VPOS = 5 V, VNEG = -5 V, PAGAIN0 = 1, PAGAIN1 = 1, PACNT = 1, T = 25°C, unless otherwise stated PARAMETER TEST CONDITIONS MIN PON/OFF On to off power ratio Max Gain to gain with PACNT = Low NFHG Noise figure, max gain PAGAIN0 = High, PAGAIN1 = High NFLG Noise figure min gain PAGAIN = Low, PAGAIN1 = Low S12 Reverse isolation S11 Input return loss Z = 50 Ω S22 Output return loss Z = 50 Ω TYP MAX UNIT 35 6 7 20 dB 30 -10 -12 -8 TYPICAL PERFORMANCE 35 TA = 55C 36 VDD = 5 V, TA = 55C 7 V, 32 dB Step 30 5 V, 32 dB Step 32 VDD = 7 V Gain Step − dB Gain − dB 25 20 15 28 24 20 10 7 V, 16 dB Step 5 16 0 12 5 V, 16 dB Step 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 f − Frequency − GHz 3 Figure 2. Gain vs Frequency Submit Documentation Feedback 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 f − Frequency − GHz 3 Figure 3. Gain Control 5 TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 TYPICAL PERFORMANCE (continued) 60 22 dBm IP3, VDD = 7 V 50 Notched Depth − dBc Output P-1dB and IP3 − dBm 55 −30 IP3, VDD = 5 V 45 40 35 P-1dB, VDD = 7 V −40 21 dBm 20 dBm −50 19 dBm 30 P-1dB, VDD = 5 V 25 20 PA Notched Test, VDD = 5 V, 1000 Carriers @ 2 kHz Spacing −60 2000 2.150 2.250 2.350 2.450 2.550 2.650 2.686 f − Frequency − GHz PA Notched Test, VDD = 7 V, 1000 Carriers @ 2 kHz Spacing Notched Depth − dBc Notched Depth − dBc 2800 −30 PA Notched Test, VDD = 6 V, 1000 Carriers @ 2 kHz Spacing −40 22 dBm 21 dBm 20 dBm −40 22 dBm 21 dBm −50 19 dBm 19 dBm 2200 2400 2600 f − Frequency − MHz 2800 −60 2000 Figure 6. PA Notched Test (VDD = 6 V) 6 2600 Figure 5. PA Notched Test (VDD = 5 V) −30 −60 2000 2400 f − Frequency − MHz Figure 4. Output P-1 dB and IP3 −50 2200 Submit Documentation Feedback 2200 20 dBm 2400 2600 f − Frequency − MHz Figure 7. PA Notched Test (VDD = 7 V) 2800 TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 TYPICAL PERFORMANCE (continued) Figure 8. Pulse Droop - RF Output With PACNT Pulsed and 20% Duty Cycle Submit Documentation Feedback 7 TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 APPLICATION INFORMATION Figure 9. Package Drawing A typical application schematic is shown in Figure 10 and a mechanical drawing of the package outline (LPCC Quad 5 mm x 5 mm, 32-pin) is shown in Figure 9. The recommended PCB layout mask is shown in Figure 11, along with recommendations on the board material Table 2 and construction Figure 12. VDD 100 pF 100 pF 27 26 GND 25 GND 28 DETP 29 DETN GND 30 VDD2 BASE 31 VDD1 GND 32 1 Vdet 0.1 mF 0.1 mF GND 1 mF 10 mF* VDD3A 24 100 pF 2 3 RFI 4 23 GND 0.1 mF GND GND GND 22 RFI RFO 21 GND GND 20 VG1 GND 19 GND GND 18 VDD3B 17 9 10 11 12 13 14 15 100 pF GND PACNT 100 pF RES 0.1 mF VNEG VPOS 1 mF 8 VG3 VNEG PAGAIN1 7 VG2 6 PAGAIN0 RF_OUT 5 0.1 mF 16 VPOS 1 mF 0.1 mF PACNT 100 pF PAGAIN1 0.1 mF PAGAIN0 *10 mF May Need to be 100 mF For High Speed Pulse Applications Place 100 pF Capacitors Close to Package Pins and Minimize Parstic Inductance Figure 10. Recommended TRF1123 Application Schematic Table 2. PCB Recommendations 8 Board Material FR4 Board Material Core Thickness 10 mil Copper Thickness (starting) 1 oz Submit Documentation Feedback TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 Table 2. PCB Recommendations (continued) Prepreg Thickness 8 mil Recommended Number of Layers 4 Via Plating Thickness 0.5 oz Final Plate White immersion tin Final Board Thickness 33-37 mil 3.80 0.20 TYP 0.50 TYP PIN 1 0.75 TYP 3.80 3.50 0.75 TYP DIA 0.38 TYP 0.60 TYP 0.25 TYP 3.50 SOLDER MASK: NO SOLDERMASK UNDER CHIP, ON LEAD PADS OR ON GROUND CONNECTIONS. 25 VIA HOLES, EACH 0.38 mm. DIMENSIONS in mm Figure 11. Recommended Pad Layout Submit Documentation Feedback 9 TRF1123 www.ti.com SLWS167B – APRIL 2005 – REVISED SEPTEMBER 2006 Dia 15 Mil 1 oz Copper + 1/2 oz Copper Plated Upper and Lower Surfaces 10 Mil Core FR4 1 oz Copper 8 Mil Prepreg 35 Mil 1 oz Copper 10 Mil Core FR4 DuPont CB 100 Conductive Via Plug 1/2 oz Copper Plated Figure 12. PCB Via Cross Section 10 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TRF1123IRTMR ACTIVE QFN RTM 32 3000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TRF1123IRTMRG3 ACTIVE QFN RTM 32 3000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TRF1123IRTMT ACTIVE QFN RTM 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR TRF1123IRTMTG3 ACTIVE QFN RTM 32 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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