TLC5924 DAP www.ti.com RHB SLVS626 – JUNE 2006 16-CHANNEL LED DRIVER WITH DOT CORRECTION AND PRE-CHARGE FET FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • 16 Channels Drive Capability – 0 to 80 mA (Constant-Current Sink) Constant Current Accuracy: ±1% (typical) Serial Data Interface Fast Switching Output: Tr / Tf = 10ns (typical) CMOS Level Input/Output 30 MHz Data Transfer Rate VCC = 3.0 V to 5.5 V Operating Temperature = –40°C to 85°C LED Supply Voltage up to 17 V 32-pin HTSSOP(PowerPAD™) and QFN Packages Dot Correction – 7 bit (128 Steps) – individual adjustable for each channel Controlled In-Rush Current Pre-Charge FET Error Information – LOD: LED Open Detection – TEF: Thermal Error Flag Monocolor, Multicolor, Fullcolor LED Display Monocolor, Multicolor LED Signboard Display Backlighting Multicolor LED lighting applications DESCRIPTION The TLC5924 is a 16 channel constant-current sink driver. Each channel has a On/Off state and a 128-step adjustable constant current sink (dot correction). The dot correction adjusts the brightness variations between LED, LED channels and other LED drivers. Both dot correction and On/Off state are accessible via a serial data interface. A single external resistor sets the maximum current of all 16 channels. Each constant-current output has a pre-charge FET that enables an improvement in image quality of the dynamic-drive LED display. The TLC5924 features two error information circuits. The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag (TEF) indicates an over-temperature condition. FUNCTIONAL BLOCK DIAGRAM VCC GND PGND SCLK SIN MODE VUP XLAT BLANK VUP MODE 0 1 1 LOD 0 0 On/Off Register 0 IREF 0 Max. OUTn Current 0 7−bit DC Register 6 On/Off OUT0 BLANK VUP Input Shift Register 16 LOD 1 16 1 On/Off Register 15 0 LED Open Detection (LOD) BLANK VUP LOD 111 XERR 0 1 MODE OUT1 7 7−bit DC Register 13 BLANK 1 0 Constant Current Driver Delay x1 112 DC Input Shift Register Temperature Error Flag (TEF) Constant Current Driver Delay x0 15 15 On/Off Register Constant Current Driver OUT15 Delay x15 105 7−bit DC Register 111 SOUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TLC5924 www.ti.com SLVS626 – JUNE 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA –40°C to 85°C (1) Part Number (1) Package 32-pin, HTSSOP, PowerPAD™ TLC5924DAP 32-pin, 5 mm x 5 mm QFN TLC5924RHB For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) TLC5924 UNIT VCC Supply voltage (2) –0.3 to 6 V VUP Pre-charge voltage –0.3 to 16 V IO Output current (dc) I(OUT0) to I(OUT15) 90 mA VI Input voltage range (2) V(BLANK), V(XLAT), V(SCLK), V(SIN), V(MODE), V(IREF) –0.3 to VCC + 0.3 V V(SOUT), V(XERR) –0.3 to VCC + 0.3 V -0.3 to VUP V 2 kV VO Output voltage range (2) V(OUT0) to V(OUT15) HBM (JEDEC JESD22-A114, Human Body Model) ESD rating Tstg CDM (JEDEC JESD22-C101, Charged Device Model) (2) (3) V –40 to 150 °C HTSSOP (DAP) 42.54 mW/°C QFN (RHB) 27.86 mW/°C Storage temperature range Power dissipation rating at (or above) TA = 25°C (3) (1) 500 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. See SLMA002 for more information about PowerPAD™ RECOMMENDED OPERATING CONDITIONS—DC Characteristics MIN 2 NOM MAX UNIT VCC Supply voltage 3 5.5 V VUP Pre-charge voltage 3 15 V VO Voltage applied to output, (Out0 - Out15) VUP V VIH High-level input voltage 0.8 VCC VCC V VIL Low-level input voltage GND 0.2 VCC V IOH High-level output current VCC = 5 V at SOUT IOL Low-level output current VCC = 5 V at SOUT, XERR IOLC Constant output current OUT0 to OUT15 TA Operating free-air temperature range -40 Submit Documentation Feedback –1 mA 1 mA 80 mA 85 °C TLC5924 www.ti.com SLVS626 – JUNE 2006 RECOMMENDED OPERATING CONDITIONS—AC Characteristics VCC = 3 V to 5.5 V, TA = -40°C to 85°C (unless otherwise noted) MIN fSCLK Clock frequency TYP SCLK MAX UNIT 30 MHz twh0, twl0 CLK pulse duration SCLK=H/L 16 ns twh1 ns XLAT=H 20 tsu0 XLAT pulse duration SIN to SCLK↑ (1) 10 tsu1 SLCK↑ to XLAT↓(dot correction data) 10 tsu1a SCLK↑to XLAT↑ (ON/OFF data) 10 tsu2 MODE↑↓ to SCLK↑ 10 tsu3 MODE↑↓ to XLAT↑ 10 th0 SCLK↑ to SIN 10 th1 XLAT↓ to SCLK↑ (dot correction data) 10 XLAT↑ to SCLK↑ (ON/OFF data) 10 th2 SCLK↑to MODE↑↓ 10 th3 XLAT↓ to MODE↑↓ 10 th1a (1) Setup time Hold time ns ns "↑" and "↓" indicates a rising edge, and a falling edge respectively. ELECTRICAL CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH = –1 mA, SOUT VOL Low-level output voltage IOL = 1 mA, SOUT II Input current VI = VCC or GND, BLANK, XLAT, SCLK, SIN, MODE ICC Supply current MIN ILO0 MAX V –1 V 1 µA 6 No data transfer, All output OFF, VO = 1 V, R(IREF) = 1.3 kΩ 15 Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF) = 1.3 kΩ 32 Constant sink current All output ON, VO = 1 V, R(IREF) = 600 Ω Leakage output current All output OFF, VO = 15 V, R(IREF) = 600 Ω, OUT0 to OUT15 UNIT 0.5 No data transfer, All output OFF, VO = 1 V, R(IREF) = 10 kΩ mA Data transfer 30 MHz, All output ON, VO = 1 V, R(IREF) = 600 Ω IOLC TYP VCC– 0.5 70 36 65 (1) 80 90 mA 0.1 µA 10 µA ILO1 VXERR = 5.5 V, No TEF and LOD ∆IOLC0 Constant sink current error All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to OUT15 ±1% ± 4% ∆IOLC1 Constant sink current error device to device, averaged current from OUT0 to OUT15, R(IREF) = 600 Ω ±4% ±8.5% ∆IOLC2 Line regulation All output ON, VO = 1 V, R(IREF) = 600 Ω, OUT0 to OUT15, VCC = 3 V to 5.5 V ±1 ±4 %/V ∆IOLC3 Load regulation All output ON, VO = 1 V to 3 V, R(IREF) = 600 Ω, OUT0 to OUT15 ±2 ±6 %/V R(ON) VUP = 3 V, VO = 0 V, OUT0 to OUT15 10 KΩ 160 180 °C 0.3 0.4 V 1.24 1.28 V Pre-charge FET on-resistance T(TEF) Thermal error flag threshold V(LOD) LED open detection threshold V(IREF) Reference voltage output (1) (2) Junction temperature, rising temperature (2) R(IREF) = 600 Ω 150 1.20 Measured at device start-up temperature. Once the IC is operating (self heating), lower ICC values will be seen. See Figure 20. Not tested. Specified by design. Submit Documentation Feedback 3 TLC5924 www.ti.com SLVS626 – JUNE 2006 DISSIPATION RATINGS PACKAGE POWER RATING TA < 25°C DERATING FACTOR ABOVE TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C 32-pin HTSSOP with PowerPAD (1) soldered 5318 mW 42.54 mW/°C 3403 mW 2765 mW 32-pin HTSSOP with PowerPAD (1) unsoldered 2820 mW 22.56 mW/°C 1805 mW 1466 mW 32-pin QFN 3482 mW 27.86 mW/°C 2228 mW 1811 mW (1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information. SWITCHING CHARACTERISTICS PARAMETER tr0 tr1 tf0 tf1 TEST CONDITIONS SOUT(see Rise time SOUT (see SCLK↑ to SOUT↑↓ (see MODE↑↓ to SOUT↑↓ (see tpd2 BLANK↑↓ to OUT0↑↓ (see (5)), (2)) 10 30 OUTn↑↓ to XERR↑↓ (see (6)) tpd5 XLAT↑ to IOUT(dot-correction) (see 80 60 (5)) 14 22 30 4 17 OUT11 18 OUT12 19 OUT13 20 PGND 21 OUT14 22 OUT15 XERR 25 16 OUT10 MODE 26 15 PGND IREF 27 14 OUT9 13 OUT8 12 OUT7 THERMAL PAD (QFN) 11 OUT6 31 10 PGND SCLK 32 9 OUT5 Submit Documentation Feedback OUT4 8 30 XLAT OUT3 7 BLANK OUT2 6 29 OUT1 4 PGND 5 28 OUT0 3 VCC GND SIN 1 VUP 2 VCC IREF MODE XERR SOUT VUP OUT15 OUT14 PGND OUT13 OUT12 OUT11 OUT10 PGND OUT9 OUT8 24 SOUT DAP PACKAGE (TOP VIEW) 23 VUP RHB PACKAGE (TOP VIEW) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ns 1000 OUTn↑ to OUT(n+1)↑, OUTn ↓ to OUT(n+1)↓ (see 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ns 1000 (7)) See Figure 4. Defined as from 10% to 90% See Figure 5. Defined as from 10% to 90% See Figure 4, Figure 16 "↑" and "↓" indicates a rising edge, and a falling edge respectively. See Figure 5 and Figure 16 See Figure 5, Figure 6, and Figure 16 See Figure 5 GND BLANK XLAT SCLK SIN VUP OUT0 OUT1 PGND OUT2 OUT3 OUT4 OUT5 PGND OUT6 OUT7 ns 30 tpd4 Output delay time 30 Sink current On/Off (5)) (1) (2) (3) (4) (5) (6) (7) 10 30 XLAT↑ to OUT0↑↓ (see td ) (3) (4)) tpd1 Propagation delay time (2) 16 (3)) tpd3 MAX UNIT (1)) OUTn, VCC = 5 V, TA = 60°C, DCx = 7F (see tpd0 TYP 16 OUTn, VCC = 5 V, TA = 60°C, DCx = 7F (see Fall time MIN (1)) ns TLC5924 www.ti.com SLVS626 – JUNE 2006 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION TSSOP QFN 2 30 GND 1 29 IREF 31 27 I/O MODE 30 26 I Mode select. When MODE=L, SIN, SOUT, SCLK, XLAT are connected to ON/OFF control logic. When MODE=H, SIN, SOUT, SCLK, XLAT are connected to dot-correction logic. OUT0 7 3 O Constant current output OUT1 8 4 O Constant current output OUT2 10 6 O Constant current output OUT3 11 7 O Constant current output OUT4 12 8 O Constant current output OUT5 13 9 O Constant current output OUT6 15 11 O Constant current output OUT7 16 12 O Constant current output OUT8 17 13 O Constant current output OUT9 18 14 O Constant current output OUT10 20 16 O Constant current output OUT11 21 17 O Constant current output OUT12 22 18 O Constant current output OUT13 23 19 O Constant current output OUT14 25 21 O Constant current output OUT15 26 22 O Constant current output PGND 9, 14, 19, 24 5, 10, 15, 20 Power ground VUP 6, 27 2, 23 Pre-charge power supply voltage SCLK 4 32 BLANK I Blank (Light OFF). When BLANK=H, All OUTn outputs are forced to VUP level. When BLANK=L, ON/OFF of OUTn outputs are controlled by input data. Ground Reference current terminal I Data shift clock. Note that the internal connections are switched by MODE (pin #30). At SCLK↑, the shift-registers selected by MODE shift the data. SIN 5 1 I Data input of serial I/F SOUT 28 24 O Data output of serial I/F VCC 32 28 XERR 29 25 XLAT 3 31 Power supply voltage O Error output. XERR is open drain terminal. XERR transistions from H to L when LOD or TEF detected. I Data latch signal. When MODE = L (ON/OFF data mode), XLAT is an edge-triggered latch signal of ON/OFF registers. The serial data in ON/OFF input shift registers is latched into the ON/OFF registers at the rising edge of XLAT. When MODE = H (DC data mode), XLAT is a level-triggered latch signal of dot correction registers. The serial data in DC input shift registers is written into dot correction registers when XLAT = H. The data in dot correction registers is held constant when XLAT = L. Submit Documentation Feedback 5 TLC5924 www.ti.com SLVS626 – JUNE 2006 PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS (Note: Resistor values are equivalent resistance and not tested). VCC 400 W INPUT GND Figure 1. Input Equivalent Circuit (BLANK, XLAT, SCLK, SIN, MODE) 10 W SOUT GND Figure 2. Output Equivalent Circuit 20 W XERR GND Figure 3. Output Equivalent Circuit (XERR) PARAMETER MEASUREMENT INFORMATION SOUT 15 pF Figure 4. Test Circuit for tr0, tf0, tpd0, tpd1 VUP 51 Ω OUTn 15 pF Figure 5. Test Circuit for tr1, tf1, tpd2, tpd3, tpd5, ttd 6 Submit Documentation Feedback TLC5924 www.ti.com SLVS626 – JUNE 2006 PARAMETER MEASUREMENT INFORMATION (continued) 470 kΩ XERR Figure 6. Test Circuit for tpd4 Submit Documentation Feedback 7 TLC5924 www.ti.com SLVS626 – JUNE 2006 PRINCIPLES OF OPERATION Setting Maximum Channel Current The maximum output current per channel is set by a single external resistor, R(IREF), which is placed between IREF and GND. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 40. The maximum output current per channel can be calculated by Equation 1: V I + IREF 40 MAX R IREF (1) where: VIREF = 1.24V typ. RIREF = User selected external resistor ®IREF should not be smaller than 600 Ω) Figure 17 shows the maximum output current, IOLC, versus R(IREF) . In Figure 17, R(IREF) is the value of the resistor between IREF terminal to ground, and IOLC is the constant output current of OUT0,.....OUT15. A variable power supply may be connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum output per channel is 40 times the current flowing out of the IREF pin. The maximum current from IREF equals 1.24V/600Ω. Setting Dot-Correction The TLC5924 has the capability to fine adjust the current of each channel, OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LED connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 7-bit word. The channel output can be adjusted in 128 steps from 0% to 100% of the maximum output current IMAX. Dot correction for all channels must be entered at the same time. Equation 2 determines the output current for each OUTn: I DCn I + MAX Outn 127 (2) where: IMax = the maximum programmable current of each output DCn = the programmed dot-correction value for output n (DCn = 0, 1, 2 ...127) n = 0, 1, 2 ... 15 Dot correction data are entered for all channels at the same time. The complete dot correction data format consists of 16 x 7-bit words, which forms a 112-bit wide serial data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 7 shows the DC data format. The DC15.6 in Figure 7 stands for the 6th most significant bit for output 15. MSB LSB 111 105 DC 15.0 DC 15.6 DC OUT15 104 7 6 0 DC 14.6 DC 1.0 DC 0.6 DC 0.0 DC OUT14 − DC OUT1 DC OUT0 Figure 7. DC Data Format To input data into dot correction register, MODE must be set to high. The internal input shift register is then set to 112-bit width. After all serial data is clocked in, a high level pulse of XLAT signal connects the serial data to the dot correction register. The dot correction registers are level-triggered latches of XLAT signal. The serial data is latched into the dot correction registers when XLAT goes low. The data in dot correction registers is held constant when XLAT is low. BLANK signal does not need to be high to latch in new data. Since XLAT is a level-triggered signal when MODE is high, SCLK and SIN must not be changed while XLAT is high. (Figure 16). 8 Submit Documentation Feedback TLC5924 www.ti.com SLVS626 – JUNE 2006 PRINCIPLES OF OPERATION (continued) Output Enable When BLANK = H, TLC5924 switches off the sink current of all OUTn with each output delay, then switches on the pre-charge FET of all OUTn. When BLANK = L, the TLC5924 switches off the pre-charge FETs, and enables the sink current set by input data. See "Delay Between Outputs" section for more detail on the output delay. Table 1. BLANK Signal Truth Table BLANK OUT0 - OUT15 LOW Normal condition HIGH VUP Setting Channel On/Off Status All OUTn channels of TLC5924 can be switched on or off independently. Each of the channels can be programmed with a 1-bit word. On/Off data are entered for all channels at the same time. The complete On/Off data format consists of 16 x 1-bit words, which form a 16-bit wide data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 8 shows the On/Off data format. MSB 15 On/Off OUT15 LSB 0 On/Off OUT14 On/Off OUT13 On/Off OUT2 On/Off OUT1 On/Off OUT0 On/Off Data Figure 8. On/Off Data Format To input On/Off data into On/Off register MODE must be set to low. The internal input shift register is then set to 16 bit width. After all serial data is clocked in, a rising edge of XLAT is used to latch data into the On/Off register. The ON/OFF register is an edge-triggered latch of XLAT signal. BLANK signal does not need to be high to latch in new data. Figure 16 shows the On/Off data input timing chart. Delay Between Outputs The TLC5924 has graduated delay circuits between outputs. These delay circuits can be found in the constant current block of the device (see Functional Block Diagram). The fixed delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20 ns delay, OUT2 has 40 ns delay, etc. This delay prevents large inrush currents, which reduce power supply bypass capacitor requirements when the outputs turn on. The delay works during switch on and switch off of each output channel. LEDs that have not turned on before BLANK is pulled high will still turn on and off at the determined delayed time regardless of the state of BLANK. Therefore, every LED will be illuminated for the amount of time BLANK is low. Pre-Charge FET On/Off Timing The pre-charge FETs turn on at the same time; and, they turn on at the time the last output that is on turns off. All pre-charge FETs turn off just after BLANK signal becomes low level, regardless of on/off data of each output. Figure 9 shows the example of BLANK and OUTn timing. Submit Documentation Feedback 9 TLC5924 www.ti.com SLVS626 – JUNE 2006 BLANK VUP Current ON OUT0 OFF ON tpd2 tpd2 td x 14 td x 14 OUT14 OFF ON OUT15 Pre-charge Period Figure 9. Timing Chart of BLANK and OUTn (On/Off Data Condition: OUT0=H, OUT14=H, OUT15=L) VUP: Pre-Charge Power Supply VUP is a pre-charge power supply terminal. The pre-charge voltage should be supplied to this terminal for normal operation. When VUP terminal is open, TLC5924 keeps OUT0-15 open. TLC5924 has two VUP pins as shown in the Terminal Functions Table. Both VUP pins should be connected to the pre-charge power supply as shown in Figure 10. Pre-Charge Power Supply VUP VUP TLC5924 Figure 10. VUP Power Supply Serial Interface Data Transfer Rate The TLC5924 includes a flexible serial interface, which can be connected to a microcontroller or digital signal processor. Only 3 pins are required to input data into the device. The rising edge of SCLK signal shifts the data from SIN pin to internal shift register. After all data is clocked in, a rising edge of XLAT latches the serial data to the internal registers. All data is clocked in with MSB first. Multiple TLC5924 devices can be cascaded by connecting SOUT pin of one device with SIN pin of following device. The SOUT pin can also be connected to controller to receive LOD information from TLC5924. 10 Submit Documentation Feedback TLC5924 www.ti.com SLVS626 – JUNE 2006 VCC V(LED) V(LED) V(LED) V(LED) 100 k OUT0 SIN Controller OUT15 SIN OUT0 SOUT XERR XERR SCLK SCLK XLAT XLAT MODE MODE BLANK BLANK VCC OUT15 SIN SOUT XERR VCC SCLK 100 nF TLC5924 IREF SOUT 100 nF XLAT TLC5924 MODE BLANK IREF IC 0 IC n 5 Figure 11. Cascading Devices Figure 11 shows a example application with n cascaded TLC5924 devices connected to a controller. The maximum number of cascaded TLC5924 devices depends on application system and data transfer rate. Equation 3 calculates the minimum data input frequency needed. f_(SCLK) + 112 f_(update) n (3) where: f_(SCLK): The minimum data input frequency for SCLK and SIN. f_(update): The update rate of the whole cascaded system. n: The number of cascaded TLC5924 devices. Operating Modes The TLC5924 has different operating modes depending on MODE signal. Table 2 shows the available operating modes. The values in the input shift registers, DC register and On/Off register are unknown just after power on. The DC and On/Off register values should be properly stored through the serial interface before starting the operation. Table 2. TLC5924 Operating Modes Truth Table MODE SIGNAL INPUT SHIFT REGISTER MODE LOW 16 bit On/Off Mode HIGH 112 bit Dot Correction Data Input Mode Submit Documentation Feedback 11 TLC5924 www.ti.com SLVS626 – JUNE 2006 Error Information Output The open-drain output XERR is used to report both of the TLC5924 error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to VCC through a external pull-up resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to VCC with a single pull-up resistor. This reduces the number of signals needed to report a system error. To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH. Table 3. XERR Truth Table CONDITION ERROR INFORMATION TEMPERATURE BLANK OUTn VOLTAGE TEF LODn TJ < T(TEF) H Don't Care L L High-Z (1) L OUTn > V(LOD) L High-Z H L L L H L TJ > T(TEF) H TJ < T(TEF) L L OUTn < V(LOD) TJ > T(TEF) OUTn > V(LOD) H OUTn < V(LOD) (1) XERR Note: High-Z means high impedance TEF: Thermal Error Flag The TLC5924 provides a temperature error flag (TEF) circuit to indicate an over-temperature condition of the IC. If the junction temperature exceeds the threshold temperature T(TEF) (160°C typical), TEF becomes H and XERR pin goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes L and XERR pin becomes high impedance. LOD: LED-Open Detection The TLC5924 has an LED-open detector to detect broken or disconnected LEDs, which should be connected to the output. The LED-open detector pulls the XERR pin down to GND when the LED open is detected. An open LED is detected when the following three conditions are met: 1. BLANK is low 2. On/Off data is high 3. The voltage of OUTn is less than 0.3 V (typical) The LOD status of each output can also be read out from the SOUT pin. Figure 12 shows the LOD data format. Table 4 shows the LOD truth table. MSB 15 LOD OUT15 LSB 0 LOD OUT14 LOD OUT13 LOD OUT2 LOD Data Figure 12. LOD Data Format 12 Submit Documentation Feedback LOD OUT1 LOD OUT0 TLC5924 www.ti.com SLVS626 – JUNE 2006 Table 4. LOD Data Truth Table LED ON/OFF LOD BIT Good On 0 Good Off 0 Bad On 1 Bad Off 0 Key Timing Requirements to Reading LOD • LOD status flag The LOD status flag becomes active if the output voltage is <0.3 V (typical) when the output sink current turns on. There is a 1-µs time delay from the time the output sink current turns on until the time the LOD status flag becomes valid. The timing for each channel’s LOD status to become valid is shifted by the 30 ns channel-to-channel turn-on time. After BLANK goes low, OUT0 LOD status is valid when tpd2 + tpd4 = 60 ns + 1 µs = 1.06 µs. OUT1 LOD status is valid when tpd2 + tpd4 + td = 60 ns + 1 µs + 30 ns = 1.09 µs. OUT3 LOD status is valid when tpd2 + tpd4 + 2*td = 1.12 µs, and so on. • LOD internal latch The TLC5924 has an internal latch to hold each channel’s LOD status flag information, as shown in Figure 13. When MODE is low, the LOD status information is latched into this latch on the rising edge of XLAT. This is an edge-triggered latch. To ensure that a valid LOD status flag is latched, BLANK must be low when XLAT goes high. After the rising edge of XLAT, changes in the status flags do not affect the values in the LOD latch. • Loading LOD data to the input shift register The LOD data must be transferred to the input shift register before it is available to be clocked out of SOUT. The internal shift register has a set/reset function that is controlled by the LOD internal latch. While XLAT is high, the LOD internal latch holds the input shift register in either set or reset, depending on the value in the latch. This effectively puts the LOD data into the input shift register where it remains as long as XLAT is high. The values in the input shift register are unaffected by any other signals, including SIN and SCLK while XLAT is high. During this time, the status of OUT15 is present on SOUT. • Latching LOD data into the internal shift register While XLAT is high, the status of OUT15 is present on SOUT. When XLAT transitions low, all data is latched into the Input shift register, and the LOD internal latch is disconnected from the internal shift register. • Clocking LOD data out of SOUT While XLAT is low and SCLK is low, the status of OUT15 is on SOUT. On the next rising edge of SCLK, the status of OUT14 shifts to SOUT. Each subsequent rising edge of SCLK shifts the LOD data out of SOUT. XLAT must stay low until all LOD data is clocked out of SOUT. See Shifting the LOD Data Out section for more details. Submit Documentation Feedback 13 TLC5924 www.ti.com SLVS626 – JUNE 2006 16bit LOD Status Flags 16bit LOD Internal Latch SIN Input Shift Register SOUT (FIFO Register) GS Register Figure 13. LOD Flags and Latches Shifting the LOD Data Out SOUT outputs the LOD data as shown in Figure 14, where: • XLAT rising edge Holds the LOD status flag. SOUT outputs LOD OUT15 data. BLANK must be low. • XLAT = H Sets or resets the input shift register depending on each LOD data. Set/Reset function is higher priority than shifting the register value. If XLAT is high and the SCLK pin is pulsed, all LOD data are kept in the shift register and SOUT keeps the LOD OUT15 data. • XLAT = L Ready to shift out LOD data by SCLK. SOUT contains LOD OUT15 data at this time. BLANK can be high or low during this time. • SCLK rising edge SOUT outputs LOD OUT14 at the first SCLK rising edge. SOUT outputs LOD OUT13 at the second SCLK rising edge, and continues to output the next LOD data at each SCLK rising edge. XLAT SCLK SOUT LOD LOD LOD LOD OUT15 OUT14 OUT13 OUT12 Figure 14. The LOD Data of SOUT 14 Submit Documentation Feedback TLC5924 www.ti.com SLVS626 – JUNE 2006 Figure 15 shows the timing chart of reading LOD data. At the rising edge of XLAT while BLANK=L, LOD status is latched into the internal edge-triggered register. MODE When XLAT=H, the internal edge-triggered register sets or resets the input shift register . XLAT SCLK SIN SOUT 1510ns max 1510ns max tpd2: 60ns max tpd2: 60ns max BLANK OUT0 LED open OUT15 td x 15 = 450ns max td x 15 = 450ns max XERR tpd4: 1000ns max tpd4: 1000ns max >1000ns >1000ns Figure 15. Timing Chart of Reading LOD Data Submit Documentation Feedback 15 16 Submit Documentation Feedback OUT1 (current) OUT0 (current) XERR BLANK SOUT SCLK SIN XLAT MODE t h3 tpd2 On/Off MSB On/Off LSB t pd3 t wh1 On/Off Mode Data Input Cycle td t pd2 DC MSB t pd1 t wl0 t wh0 DC MSB t su3 DC LSB fSCLK DC MSB t su0 DC LSB DC Mode Data Input Cycle h1 t h2 DC LSB t su1 t h0 t pd0 t pd5 t DC MSB t h3 DC Mode Data Input Cycle DC MSB DC LSB t pd5 On/Off MSB t pd1 t su2 On/Off MSB On/Off LSB t su1a tsu3 td On/Off MSB On/Off LSB On/Off Mode Data Input Cycle On/Off MSB−1 t pd4 On/Off MSB t h1a On/Off MSB On/Off Mode Data Input Cycle TLC5924 SLVS626 – JUNE 2006 www.ti.com Figure 16. Timing Chart Example for ON/OFF Setting to Dot-Correction TLC5924 www.ti.com SLVS626 – JUNE 2006 TYPICAL CHARACTERISTICS REFERENCE RESISTOR vs OUTPUT CURRENT OUTPUT CURRENT vs REQUIRED OUTPUTn VOLTAGE 100 100 k 49.6 k 90 VOutn = 1 V DC = 127 I O − Output Current − mA Ω 9.92 k 4.96 k 2.48 k 1.65 k 1.24 k 1k 992 827 IREF − Reference Resistor − 10 k 80 70 IMAX = 60 mA 60 50 IMAX = 40 mA 40 30 IMAX = 20 mA 709 R 20 10 0 100 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 1.50 2 Figure 17. Figure 18. POWER DISSIPATION vs FREE-AIR TEMPERATURE SUPPLY CURRENT(A) vs FREE-AIR TEMPERATURE 6k 2.50 3 70 TLC5924DAP PowerPAD Soldered 60 ICC − Supply Current − mA PD − Power Dissipation − mW 1 VO− Required Output Voltage − V IOLC − Output Current − A 5k 0.50 4k TLC5924RHB 3k 2k TLC5924DAP PowerPAD Unsoldered 50 40 30 20 1k 10 0 −40 −20 0 20 40 60 80 0 −50 −30 −10 10 100 Figure 19. 30 50 70 90 110 130 150 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C A. Data Transfer = 30 MHz / All Outputs, ON/VO = 1 V / RIREF = 600 Ω / AVDD = 5 V Figure 20. Power Rating – Free-Air Temperature Figure 19 shows total power dissipation. Figure 20 shows supply current versus free-air temperature. Submit Documentation Feedback 17 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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