DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz General Description The DS90CR213 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR214 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.386 Gbit/s (173 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cable’s smaller form factor. The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, 5 4-bit nibbles (byte + parity) or 2 9-bit (byte + 3 parity) and 1 control. Features n n n n n n n n n n n 66 MHz Clock Support Up to 173 Mbytes/s bandwidth Low power CMOS design ( < 610 mW) Power-down mode ( < 0.5 mW total) Up to 1.386 Gbit/s data throughput Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI PLL requires no external components Low profile 48-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS Standard Block Diagrams DS90CR214 DS90CR213 01288827 Order Number DS90CR213MTD See NS Package Number MTD48 01288801 Order Number DS90CR214MTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS012888 www.national.com DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz August 2005 DS90CR213/DS90CR214 Connection Diagrams DS90CR213 DS90CR214 01288821 01288822 Typical Application 01288823 www.national.com 2 Package Derating: If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to (VCC + 0.3V) CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V) LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V) LVDS Driver Output Voltage −0.3V to (VCC + 0.3V) 16 mW/˚C above +25˚C DS90CR214 15 mW/˚C above +25˚C ESD Rating (Note 4) −0.3V to +6V CMOS/TTL Input Voltage DS90CR213 This device does not meet 2000V Recommended Operating Conditions Min Nom Max LVDS Output Short Circuit Duration Supply Voltage (VCC) Continuous Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C 5.25 V −10 +25 +70 ˚C Operating Free Air Temperature (TA) Receiver Input Range Lead Temperature (Soldering, 4 sec) +260˚C Maximum Package Power Dissipation Capacity MTD48 (TSSOP) Package: DS90CR213 DS90CR214 Units 4.75 5.0 0 2.4 Supply Noise Voltage (VCC) V 100 mVP-P @ 25˚C 1.98W 1.89W Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units CMOS/TTL DC SPECIFICATIONS VIH High Level Input Voltage 2.0 VCC V VIL Low Level Input Voltage GND 0.8 V VOH High Level Output Voltage IOH = −0.4 mA 3.8 4.9 V VOL Low Level Output Voltage IOL = 2 mA 0.1 0.3 V VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ± 5.1 IOS Output Short Circuit Current VOUT = 0V ± 10 µA −120 mA 450 mV 35 mV LVDS DRIVER DC SPECIFICATIONS VOD Differential Output Voltage ∆VOD Change in VOD between Complimentary Output States RL = 100Ω 250 VOS Offset Voltage ∆VOS Change in Magnitude of VOS between Complimentary Output States 1.1 IOS Output Short Circuit Current VOUT = 0V, R IOZ Output TRI-STATE ® Current Powerdown = 0V, VOUT = 0V or VCC L = 100Ω 290 1.25 1.375 V 35 mV −2.9 −5 mA ±1 ± 10 µA LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current VCM = +1.2V +100 −100 mV mV ± 10 ± 10 VIN = +2.4V, VCC = 5.0V VIN = 0V, VCC = 5.0V µA µA TRANSMITTER SUPPLY CURRENT ICCTW ICCTZ Transmitter Supply Current RL = 100Ω, C f = 32.5 MHz 49 63 mA Worst Case Worst Case Pattern f = 37.5 MHz 51 64 mA (Figure 1 and Figure 2 ) f = 66 MHz 70 84 mA Transmitter Supply Current Powerdown = Low L = 5 pF, 3 www.national.com DS90CR213/DS90CR214 Absolute Maximum Ratings (Note 1) DS90CR213/DS90CR214 Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units 1 25 µA TRANSMITTER SUPPLY CURRENT Power Down Driver Outputs in TRI-STATE under Powerdown Mode RECEIVER SUPPLY CURRENT ICCRW ICCRZ Receiver Supply Current CL = 8 pF, f = 32.5 MHz 64 77 mA Worst Case Worst Case Pattern f = 37.5 MHz 70 85 mA (Figure 1 and Figure 3 ) f = 66 MHz 110 140 mA 1 10 µA Receiver Supply Current Powerdown = Low Power Down Receiver Outputs in Previous State during Power Down Mode. Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VCC = 5.0V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and ∆V OD). Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) PLL VCC ≥ 1000V All Other Pins ≥ 2000V EIAJ (0Ω, 200 pF) ≥ 150V Note 5: VOS previously referred as VCM. Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Typ Max Units LLHT LVDS Low-to-High Transition Time (Figure 2 ) Parameter Min 0.75 1.5 ns LHLT LVDS High-to-Low Transition Time (Figure 2 ) 0.75 1.5 ns TCIT TxCLK IN Transition Time (Figure 4 ) TCCS TxOUT Channel-to-Channel Skew (Note 6) (Figure 5) TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 16 ) −0.30 0 0.30 ns TPPos1 Transmitter Output Pulse Position for Bit 1 1.70 (1/7)Tclk 2.50 ns TPPos2 Transmitter Output Pulse Position for Bit 2 3.60 (2/7)Tclk 4.50 ns TPPos3 Transmitter Output Pulse Position for Bit 3 5.90 (3/7)Tclk 6.75 ns TPPos4 Transmitter Output Pulse Position for Bit 4 8.30 (4/7)Tclk 9.00 ns TPPos5 Transmitter Output Pulse Position for Bit 5 10.40 (5/7)Tclk 11.10 ns TPPos6 Transmitter Output Pulse Position for Bit 6 12.70 (6/7)Tclk 13.40 ns f = 66 MHz 8 ns 350 ps TCIP TxCLK IN Period (Figure 6 ) 15 T 50 ns TCIH TxCLK IN High Time (Figure 6 ) 0.35T 0.5T 0.65T ns TCIL TxCLK IN Low Time (Figure 6 ) 0.35T 0.5T 0.65T ns TSTC TxIN Setup to TxCLK IN (Figure 6 ) 5 3.5 THTC TxIN Hold to TxCLK IN (Figure 6 ) 2.5 1.5 TCCD TxCLK IN to TxCLK OUT Delay @25˚C, VCC = 5.0V (Figure 8 ) 3.5 TPLLS TPDD ns ns 8.5 ns Transmitter Phase Lock Loop Set (Figure 10 ) 10 ms Transmitter Powerdown Delay (Figure 14 ) 100 ns Note 6: This limit based on bench characterization. Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Typ Max Units CLHT Symbol CMOS/TTL Low-to-High Transition Time (Figure 3 ) Parameter 2.5 4.0 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 3 ) 2.0 4.0 ns www.national.com Min 4 (Continued) Over recommended operating supply and temperature ranges unless otherwise specified Symbol RSKM Parameter RxIN Skew Margin (Note 7) V CC RCOP RxCLK OUT Period (Figure 7 ) RCOH RxCLK OUT High Time (Figure 7 ) f = 40 MHz 700 f = 66 MHz 600 Typ RxCLK OUT Low Time (Figure 7 ) RSRC RxOUT Setup to RxCLK OUT (Figure 7 ) RxOUT Hold to RxCLK OUT (Figure 7 ) RCCD RxCLK IN to RxCLK OUT Delay @25˚C, VCC = 5.0V (Figure 9 ) RPLLS RPDD f = 40 MHz 6 f = 66 MHz 4.3 f = 40 MHz 10.5 f = 66 MHz 7.0 f = 40 MHz 4.5 f = 66 MHz 2.5 f = 40 MHz 6.5 f = 66 MHz 4 Max Units ps ps 15 RCOL RHRC Min = 5V,TA = 25˚C(Figure 17) T 50 ns ns 5 ns ns 9 ns ns 4.2 ns ns 5.2 6.4 ns 10.7 ns Receiver Phase Lock Loop Set (Figure 11 ) 10 ms Receiver Powerdown Delay (Figure 15 ) 1 µs Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account for transmitter output skew (TCCS) and the setup and hold time (internal data sampling window), allowing LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter. RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle) AC Timing Diagrams 01288802 FIGURE 1. “Worst Case” Test Pattern 01288803 01288804 FIGURE 2. DS90CR213 (Transmitter) LVDS Output Load and Transition Times 5 www.national.com DS90CR213/DS90CR214 Receiver Switching Characteristics DS90CR213/DS90CR214 AC Timing Diagrams (Continued) 01288805 01288806 FIGURE 3. DS90CR214 (Receiver) CMOS/TTL Output Load and Transition Times 01288807 FIGURE 4. DS90CR213 (Transmitter) Input Clock Transition Time 01288808 Note 8: Measurements at Vdiff = 0V Note 9: TCSS measured between earliest and latest LVDS edges. Note 10: TxCLK Differential Low→High Edge FIGURE 5. DS90CR213 (Transmitter) Channel-to-Channel Skew www.national.com 6 DS90CR213/DS90CR214 AC Timing Diagrams (Continued) 01288809 FIGURE 6. DS90CR213 (Transmitter) Setup/Hold and High/Low Times 01288810 FIGURE 7. DS90CR214 (Receiver) Setup/Hold and High/Low Times 01288811 FIGURE 8. DS90CR213 (Transmitter) Clock In to Clock Out Delay 01288812 FIGURE 9. DS90CR214 (Receiver) Clock In to Clock Out Delay 7 www.national.com DS90CR213/DS90CR214 AC Timing Diagrams (Continued) 01288813 FIGURE 10. DS90CR213 (Transmitter) Phase Lock Loop Set Time 01288814 FIGURE 11. DS90CR214 (Receiver) Phase Lock Loop Set Time 01288815 FIGURE 12. Seven Bits of LVDS in Once Clock Cycle www.national.com 8 DS90CR213/DS90CR214 AC Timing Diagrams (Continued) 01288816 FIGURE 13. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs 01288817 FIGURE 14. Transmitter Powerdown Delay 01288818 FIGURE 15. Receiver Powerdown Delay 9 www.national.com DS90CR213/DS90CR214 AC Timing Diagrams (Continued) 01288819 FIGURE 16. Transmitter LVDS Output Pulse Position Measurement 01288820 SW — Setup and Hold Time (Internal Data Sampling Window) TCCS — Transmitter Output Skew RSKM ≥ Cable Skew (Type, Length) + Source Clock Jitter (Cycle to Cycle) Cable Skew — Typically 10 ps–40 ps per foot FIGURE 17. Receiver LVDS Input Skew Margin DS90CR213 Pin Description—Channel Link Transmitter I/O No. TxIN Pin Name I 21 TTL level inputs. TxOUT+ O 3 Positive LVDS differential data output. TxOUT− O 3 Negative LVDS differentiaI data output. TxCLK IN I 1 TTL level clock input. The rising edge acts as data strobe. TxCLK OUT+ O 1 Positive LVDS differential clock output. TxCLK OUT− O 1 Negative LVDS differential clock output. www.national.com Description 10 Pin Name (Continued) I/O No. PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power down. Description VCC I 4 Power supply pins for TTL inputs. GND I 5 Ground pins for TTL inputs. PLL VCC I 1 Power supply pin for PLL. PLL GND I 2 Ground pins for PLL. LVDS VCC I 1 Power supply pin for LVDS outputs. LVDS GND I 3 Ground pins for LVDS outputs. DS90CR214 Pin Description—Channel Link Receiver Pin Name I/O No. Description RxIN+ I 3 Positive LVDS differential data inputs. RxIN− I 3 Negative LVDS differential data inputs. RxOUT O 21 TTL level outputs. RxCLK IN+ I 1 Positive LVDS differential clock input. RxCLK IN− I 1 Negative LVDS differentiaI clock input. RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. PWR DOWN I 1 TTL Ievel input. Locks the previous receiver output state. VCC I 4 Power supply pins for TTL outputs. GND I 5 Ground pins for TTL outputs. PLL VCC I 1 Power supply for PLL. PLL GND I 2 Ground pin for PLL. LVDS VCC I 1 Power supply pin for LVDS inputs. LVDS GND I 3 Ground pins for LVDS inputs. 284) requires five pairs of signal wires. The ideal cable/ connector interface would have a constant 100Ω differential impedance throughout the path. It is also recommended that cable skew remain below 350 ps (@ 66 MHz clock rate) to maintain a sufficient data sampling window at the receiver. In addition to the four or five cable pairs that carry data and clock, it is recommended to provide at least one additional conductor (or pair) which connects ground between the transmitter and receiver. This low impedance ground provides a common mode return path for the two devices. Some of the more commonly used cable types for point-to-point applications include flat ribbon, flex, twisted pair and TwinCoax. All are available in a variety of configurations and options. Flat ribbon cable, flex and twisted pair generally perform well in short point-to-point applications while TwinCoax is good for short and long applications. When using ribbon cable, it is recommended to place a ground line between each differential pair to act as a barrier to noise coupling between adjacent pairs. For Twin-Coax cable applications, it is recommended to utilize a shield on each cable pair. All extended point-to-point applications should also employ an overall shield surrounding all cable pairs regardless of the cable type. This overall shield results in improved transmission parameters such as faster attainable speeds, longer distances between transmitter and receiver and reduced problems associated with EMS or EMI. The high-speed transport of LVDS signals has been demonstrated on several types of cables with excellent results. However, the best overall performance has been seen when using Twin-Coax cable. Twin-Coax has very low cable skew and EMI due to its construction and double shielding. All of Applications Information The Channel Link devices are intended to be used in a wide variety of data transmission applications. Depending upon the application the interconnecting media may vary. For example, for lower data rate (clock rate) and shorter cable lengths ( < 2m), the media electrical performance is less critical. For higher speed/long distance applications the media’s performance becomes more critical. Certain cable constructions provide tighter skew (matched electrical length between the conductors and pairs). Twin-coax for example, has been demonstrated at distances as great as 5 meters and with the maximum data transfer of 1.38 Gbit/s. Additional applications information can be found in the following National Interface Application Notes: AN = #### Topic AN-1041 Introduction to Channel Link AN-1035 PCB Design Guidelines for LVDS and Link Devices AN-806 Transmission Line Theory AN-905 Transmission Line Calculations and Differential Impedance AN-916 Cable Information CABLES A cable interface between the transmitter and receiver needs to support the differential LVDS pairs. The 21-bit CHANNEL LINK chipset (DS90CR213/214) requires four pairs of signal wires and the 28-bit CHANNEL LINK chipset (DS90CR283/ 11 www.national.com DS90CR213/DS90CR214 DS90CR213 Pin Description—Channel Link Transmitter DS90CR213/DS90CR214 Applications Information TERMINATION Use of current mode drivers requires a terminating resistor across the receiver inputs. The CHANNEL LINK chipset will normally require a single 100Ω resistor between the true and complement lines on each differential pair of the receiver input. The actual value of the termination resistor should be selected to match the differential mode characteristic impedance (90Ω to 120Ω typical) of the cable. Figure 18 shows an example. No additional pull-up or pull-down resistors are necessary as with some other differential technologies such as PECL. Surface mount resistors are recommended to avoid the additional inductance that accompanies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively terminate the differential lines. (Continued) the design considerations discussed here and listed in the supplemental application notes provide the subsystem communications designer with many useful guidelines. It is recommended that the designer assess the tradeoffs of each application thoroughly to arrive at a reliable and economical cable solution. BOARD LAYOUT To obtain the maximum benefit from the noise and EMI reductions of LVDS, attention should be paid to the layout of differential lines. Lines of a differential pair should always be adjacent to eliminate noise interference from other signals and take full advantage of the noise canceling of the differential signals. The board designer should also try to maintain equal length on signal traces for a given differential pair. As with any high speed design, the impedance discontinuities should be limited (reduce the numbers of vias and no 90 degree angles on traces). Any discontinuities which do occur on one signal line should be mirrored in the other line of the differential pair. Care should be taken to ensure that the differential trace impedance match the differential impedance of the selected physical media (this impedance should also match the value of the termination resistor that is connected across the differential pair at the receiver’s input). Finally, the location of the CHANNEL LINK TxOUT/RxIN pins should be as close as possible to the board edge so as to eliminate excessive pcb runs. All of these considerations will limit reflections and crosstalk which adversely effect high frequency performance and EMI. DECOUPLING CAPACITORS Bypassing capacitors are needed to reduce the impact of switching noise which could limit performance. For a conservative approach three parallel-connected decoupling capacitors (Multi-Layered Ceramic type in surface mount form factor) between each VCC and the ground plane(s) are recommended. The three capacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example is shown in Figure 19. The designer should employ wide traces for power and ground and ensure each capacitor has its own via to the ground plane. If board space is limiting the number of bypass capacitors, the PLL VCC should receive the most filtering/ bypassing. Next would be the LVDS VCC pins and finally the logic VCC pins. UNUSED INPUTS All unused inputs at the TxIN inputs of the transmitter must be tied to ground. All unused outputs at the RxOUT outputs of the receiver must then be left floating. 01288824 FIGURE 18. LVDS Serialized Link Termination www.national.com 12 COMMON MODE vs. DIFFERENTIAL MODE NOISE MARGIN (Continued) The typical signal swing for LVDS is 300 mV centered at +1.2V. The CHANNEL LINK receiver supports a 100 mV threshold therefore providing approximately 200 mV of differential noise margin. Common mode protection is of more importance to the system’s operation due to the differential data transmission. LVDS supports an input voltage range of Ground to +2.4V. This allows for a ± 1.0V shifting of the center point due to ground potential differences and common mode noise. POWER SEQUENCING AND POWERDOWN MODE Outputs of the CHANNEL LINK transmitter remain in TRISTATE until the power supply reaches 3V. Clock and data outputs will begin to toggle 10 ms after VCC has reached 4.5V and the Powerdown pin is above 2V. Either device may be placed into a powerdown mode at any time by asserting the Powerdown pin (active low). Total power dissipation for each device will decrease to 5 µW (typical). The CHANNEL LINK chipset is designed to protect itself from accidental loss of power to either the transmitter or receiver. If power to the transmit board is lost, the receiver clocks (input and output) stop. The data outputs (RxOUT) retain the states they were in when the clocks stopped. When the receiver board loses power, the receiver inputs are shorted to V CC through an internal diode. Current is limited (5 mA per input) by the fixed current mode drivers, thus avoiding the potential for latchup when powering the device. 01288825 FIGURE 19. CHANNEL LINK Decoupling Configuration CLOCK JITTER The CHANNEL LINK devices employ a PLL to generate and recover the clock transmitted across the LVDS interface. The width of each bit in the serialized LVDS data stream is one-seventh the clock period. For example, a 66 MHz clock has a period of 15 ns which results in a data bit width of 2.16 ns. Differential skew (∆t within one differential pair), interconnect skew (∆t of one differential pair to another) and clock jitter will all reduce the available window for sampling the LVDS serial data streams. Care must be taken to ensure that the clock input to the transmitter be a clean low noise signal. Individual bypassing of each VCC to ground will minimize the noise passed on to the PLL, thus creating a low jitter LVDS clock. These measures provide more margin for channel-tochannel skew and interconnect skew as a part of the overall jitter/skew budget. 13 www.national.com DS90CR213/DS90CR214 Applications Information DS90CR213/DS90CR214 Applications Information (Continued) 01288826 FIGURE 20. Single-Ended and Differential Waveforms www.national.com 14 DS90CR213/DS90CR214 21-Bit Channel Link—66 MHz Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Molded Thin Shrink Small Outline Package, JEDEC NS Package Number MTD48 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. 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