ETC MX98224EC

PRELIMINARY
MX98224EC
24-port Dual-Speed Ethernet Switch Controller
FEATURES
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Single chip 24-port 10/100M wire speed Ethernet
switching controller with all memory embedded
Integration of 24-port dual speed, full/half duplex
capable Media Access Controllers (MACs) with RMII
interfaces
Support IEEE 802.3x compliant flow control for FDX
and back-pressure flow control for HDX
Auto-negotiation through MDC/MDIO
Support source/destination MAC address lookup and
aging within built-in storage of 8K MAC address (4K
entries each entry table)
Self address learning, forwarding, and filtering
schemes
Store-and-Forward switching operation
12-group port base VLAN with port overlapping
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IEEE 802.1q CoS and two priority queues support
based on port, tagging, and TOS configurations
Address table and PHY register access allowed
through CPU processor
Dynamic buffer management
No head-of-line blocking system support
Power on self diagnostic
Serial EEPROM (93C46) interface for autoconfiguration
Broadcast storm prevention
Serial CPU interface support for system configuration
required
Three alter/self-diagnostic LED interface
CMOS, 1.8/3.3V I/O tolerance
208 PQFP package
GENERAL DESCRIPTION
extracts various packet types in appropriate forwarding
scheme. Now, Voice over IP (VoIP) is applied the
feature for cutting voice packet latency and promise the
quality of service. In addition, port-base VLAN is
another valuable feature for the switches. MX98224EC
offers 12 groups with port overlapping allowed. The
feature can add on more security and data flow in the
same switch with different groups should get connection
through router. The powerful switching architecture
and robust design can easily reach high performance,
non-blocking data flow.
MX98224EC is a stand-alone 10/100M Ethernet switch
controller with SRAM embedded which saves 2-3 extra
64KX64 SRAM cost. Any standalone desktop or
enterprising Ethernet switches can be achieved by
simply combining MX98224EC and quad/octal physical
devices. All 24 ports are full duplex capable to provide
dedicated 20/200M bandwidth connections each port.
MX98224EC basically supports store-and-forward
switching scheme with two address entry tables, 4K size
each. The function modules integrated in controller
include 24-port half/full-duplex compatible media access
controller with RMII interface, address resolution logic
(ARL) for address learning, filtering, recognition, priority
queue manager, port base VLAN. It fully complies with
IEEE Std. 802.3/802.3u/802.1q specifications and
supports MDC/MDIO interface for physical layer
management with industrial standard physical devices.
Head-of-line blocking prevents switch performance, and
operation defective from other port impacts. The switch
architecture provides a clean port independent
operation.
It guarantees port transmission or receive
is not affected by other ports.
Moreover, user can discard broadcast packets regarding
the threshold of system overload.
This prevents
potential broadcast storming from abnormal events.
After buffer fullness drops in the safe margin, the switch
controller jumps into flow control state to allow physical
ports work as normal condition.
The switch architecture adopting dynamic buffer
management shared by 24 ports can reach full-line
speed of high performance application.
To save
system cost, single 50Mhz clock is for RMII and system
requirement. MX98224EC proceeds in advanced
foundry and smaller package which consumes lower
power dissipation.
MX98224EC provides self on test as soon as power on
or reset. It will detect all buffer memory and address
table and others. If defective, LED is automatically on.
Several LEDs are defined in switch controller like status
of broadcast storm, packet loss, and buffer full.
The smart features with low power CPU or EEPROM
are for system configuration and ALR access required.
Also, it emphasizes at Class of Service (CoS) which
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REV. 0.2, Apr, 18, 2001
1
MX98224EC
ECS
EDI
ESK
INCLK
IODATA
CPUSEL
CPU I/F
PRITY0
PRITY23
ENPRITY
Pin Setting
MDC
MDIO
EDO
EEPROM I/F
LEDA LEDB LEDC
LED I/F
Registers
MDC/MDIO I/F
Unicast Link List
Buffer Memory
Multicast Link List
CRSDV_P
RXD_P[1:0]
TXEN_P
TXD_P[1:0]
10/100M
Ethernet
MAC
Empty Table
Address
Resolution
Logic
CLK
4K Address
Table
RESET
Figure 1. MX98224EC Functional Block Diagram
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2
MX98224EC
RS-232
CPU
MXIC
24-port Switch
EEPROM
Octal PHY
Octal PHY
Octal PHY
Transformer
Transformer
Transformer
Figure 2. MX98224EC System Block Diagram
Optional Components
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MX98224EC
TXD_22[1]
TXD_22[0]
TXEN_22
CRSDV_22
RXD_22[0]
RXD_22[1]
TXD_23[1]
TXD_23[0]
TXEN_23
CRSDV_23
RXD_23[0]
RXD_23[1]
Vcc
GND
PRITY23
PRITY22
PRITY21
PRITY20
PRITY19
PRITY18
Vdd
GND
PRITY17
PRITY16
PRITY15
PRITY14
PRITY13
PRITY12
PRITY11
PRITY10
PRITY9
PRITY8
Vcc
GND
PRITY7
PRITY6
PRITY5
PRITY4
PRITY3
PRITY2
PRITY1
PRITY0
ENPRITY
Vdd
GND
LEDC
ENCPU/LEDB
ENROM/LEDA
ECS/CPUSEL
ESK/OUTCLK
EDI/IODATA
EDO/INCLK
159
160
161
162
163
166
167
171
172
174
178
179
180
181
182
183
184
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
187
188
189
190
191
192
195
196
198
199
200
202
203
205
207
208
TXD_0[1]
TXD_0[0]
TXEN_0
CRSDV_0
RXD_0[0]
RXD_0[1]
TXD_1[1]
TXD_1[0]
TXEN_1
CRSDV_1
RXD_1[0]
RXD_1[1]
TXD_2[1]
TXD_2[0]
TXEN_2
Vdd
GND
CRSDV_2
RXD_2[0]
RXD_2[1]
TXD_3[1]
TXD_3[0]
TXEN_3
CRSDV_3
RXD_3[0]
RXD_3[1]
TXD_4[1]
TXD_4[0]
TXEN_4
CRSDV_4
RXD_4[0]
RXD_4[1]
Vcc
GND
TXD_5[1]
TXD_5[0]
TXEN_5
CRSDV_5
RXD_5[0]
RXD_5[1]
TXD_6[1]
TXD_6[0]
TXEN_6
CRSDV_6
RXD_6[0]
RXD_6[1]
Vdd
GND
TXD_7[1]
TXD_7[0]
TXEN_7
CRSDV_7
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
MX98224EC
RXD_21[1]
RXD_21[0]
CRSDV_21
TXEN_21
TXD_21[0]
TXD_21[1]
RESET#
RXD_20[1]
MDIO
MDC
GND
Vdd
RXD_20[0]
CRSDV_20
TXEN_20
TXD_20[0]
TXD_20[1]
RXD_19[1]
RXD_19[0]
CRSDV_19
TXEN_19
GND
Vcc
TXD_19[0]
TXD_19[1]
RXD_18[1]
RXD_18[0]
CRSDV_18
TXEN_18
TXD_18[0]
TXD_18[1]
RXD_17[1]
RXD_17[0]
CRSDV_17
TXEN_17
GND
Vdd
TXD_17[0]
TXD_17[1]
RXD_16[1]
RXD_16[0]
CRSDV_16
TXEN_16
TXD_16[0]
TXD_16[1]
RXD_15[1]
RXD_15[0]
CRSDV_15
TXEN_15
TXD_15[0]
TXD_15[1]
RXD_14[1]
104
103
102
101
100
99
98
97
96
95
94
93
92
91
88
87
86
85
84
83
80
79
78
77
76
75
74
72
71
70
69
68
67
65
64
63
61
60
59
58
57
56
55
54
RXD_14[0]
CRSDV_14
TXEN_14
TXD_14[0]
TXD_14[1]
RXD_13[1]
RXD_13[0]
GND
Vcc
CRSDV_13
TXEN_13
TXD_13[0]
TXD_13[1]
RXD_12[1]
RXD_12[0]
CRSDV_12
TXEN_12
TXD_12[0]
GND
Vdd
TXD_12[1]
RXD_11[1]
RXD_11[0]
CRSDV_11
CLK
TXEN_11
TXD_11[0]
TXD_11[1]
RXD_10[1]
GND
Vcc
RXD_10[0]
CRSDV_10
TXEN_10
TXD_10[0]
TXD_10[1]
RXD_9[1]
RXD_9[0]
CRSDV_9
TXEN_9
TXD_9[0]
GND
Vdd
TXD_9[1]
RXD_8[1]
RXD_8[0]
CRSDV_8
TXEN_8
TXD_8[0]
TXD_8[1]
RXD_7[1]
RXD_7[0]
Figure 3. MX98224EC Pin Diagram Top View
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REV. 0.2, Apr, 18, 2001
4
MX98224EC
PIN DESCRIPTION
10/100Mbps RMII INTERFACE
PIN#
PIN NAME
I/O
DESCRIPTION
4
10
18
24
30
38
44
52
58
66
72
81
89
95
103
109
115
123
129
137
143
154
160
166
CRSDV_0
CRSDV_1
CRSDV_2
CRSDV_3
CRSDV_4
CRSDV_5
CRSDV_6
CRSDV_7
CRSDV_8
CRSDV_9
CRSDV_10
CRSDV_11
CRSDV_12
CRSDV_13
CRSDV_14
CRSDV_15
CRSDV_16
CRSDV_17
CRSDV_18
CRSDV_19
CRSDV_20
CRSDV_21
CRSDV_22
CRSDV_23
I
Carrier Sense/Receive Data Valid
Active high, indicate receive medium is non-idle. CRSDV is asserted
asynchronously with respect to CLK.
6, 5
12, 11
20, 19
26, 25
32, 31
40, 39
46, 45
54, 53
60, 59
68, 67
76, 73
83, 82
91, 90
99, 98
105, 104
111, 110
117, 116
125, 124
131, 130
139, 138
149, 144
156, 155
162, 161
168, 167
RXD_0[1:0]
RXD_1[1:0]
RXD_2[1:0]
RXD_3[1:0]
RXD_4[1:0]
RXD_5[1:0]
RXD_6[1:0]
RXD_7[1:0]
RXD_8[1:0]
RXD_9[1:0]
RXD_10[1:0]
RXD_11[1:0]
RXD_12[1:0]
RXD_13[1:0]
RXD_14[1:0]
RXD_15[1:0]
RXD_16[1:0]
RXD_17[1:0]
RXD_18[1:0]
RXD_19[1:0]
RXD_20[1:0]
RXD_21[1:0]
RXD_22[1:0]
RXD_23[1:0]
I
Receive Data
From Port 0 to Port 23, synchronous to CLK and RXD[1] is MSB.
While CRSDV is deasserted, RXD[1:0] is “00”.
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MX98224EC
3
9
15
23
29
37
43
51
57
65
71
79
88
94
102
108
114
122
128
136
142
153
159
165
1, 2
7, 8
13, 14
21, 22
27, 28
35, 36
41, 42
49, 50
55, 56
61, 64
69, 70
77, 78
84, 87
92, 93
100, 101
106, 107
112, 113
118, 119
126, 127
132, 133
140, 141
151, 152
157, 158
163, 164
80
Subtotal
TXEN_0
TXEN_1
TXEN_2
TXEN_3
TXEN_4
TXEN_5
TXEN_6
TXEN_7
TXEN_8
TXEN_9
TXEN_10
TXEN_11
TXEN_12
TXEN_13
TXEN_14
TXEN_15
TXEN_16
TXEN_17
TXEN_18
TXEN_19
TXEN_20
TXEN_21
TXEN_22
TXEN_23
O
4mA
Transmit Enable
Active high, assertion indicates the MAC is presenting di-bits on
TXD[1:0] for transmission. TXEN is asserted synchronously with first
nibble of preamable and remained asserted while all di-bits transmitted
are presented on RMII. TXEN is negated prior to 1st CLK rising edge
following the final di-bit of frame.
TXD_0[1:0]
TXD_1[1:0]
TXD_2[1:0]
TXD_3[1:0]
TXD_4[1:0]
TXD_5[1:0]
TXD_6[1:0]
TXD_7[1:0]
TXD_8[1:0]
TXD_9[1:0]
TXD_10[1:0]
TXD_11[1:0]
TXD_12[1:0]
TXD_13[1:0]
TXD_14[1:0]
TXD_15[1:0]
TXD_16[1:0]
TXD_17[1:0]
TXD_18[1:0]
TXD_19[1:0]
TXD_20[1:0]
TXD_21[1:0]
TXD_22[1:0]
TXD_23[1:0]
O
4mA
Transmit Data
From Port 0 to Port 23, synchronous to CLK and TXD[1] is MSB.
When TXEN is asserted, TXD[1:0] are accepted fro transmission.
TXD[1:0] is “00” when TXEN is deasserted.
CLK
I
Reference Clock
For RMII and system clock use. 50MHz.
145
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MX98224EC
EEPROM INTERFACE
PIN#
PIN NAME
I/O
DESCRIPTION
I
EEPROM Enable
Internally pull down.
Default disable.
Active high; indicated
configuration data is auto-loaded from EEPROM after reset. Tying
this pin to ground disables EEPROM interface and prevents autoconfiguration.
204
ENROM
205
ECS
O
4mA
EEPROM Chip Select
Active high.
206
ESK
O
8mA
EEPROM Clock
390KHz derived from system clock.
207
EDI
O
4mA
EEPROM Data Input
Output data to the corresponding EDI pin of EEPROM.
208
EDO
I
EEPROM Data Output
Input data to the corresponding EDO pin of EEPROM.
Subtotal
5
CoS PRIORITY SETTING
PIN#
PIN NAME
I/O
DESCRIPTION
199
ENPRITY
I
Priority Queue Enable
Internally pull down. Per port base pin setting priority function enable.
If the pin is enabled, per port base priority settings used by EEPROM or
CPU is invalid. Port base priority settings controlled by EEPROM or
CPU will be valid when the pin is pull down.
198-191
188-179
176-171
PRITY0
PRITY1
PRITY2
PRITY3
PRITY4
PRITY5
PRITY6
PRITY7
PRITY8
PRITY9
PRITY10
PRITY11
PRITY12
PRITY13
PRITY14
PRITY15
PRITY16
PRITY17
PRITY18
PRITY19
PRITY20
PRITY21
PRITY22
PRITY23
I
Per Port Priority Enable
Active low. If pin pull high, the mapped port will act as high priority.
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MX98224EC
Subtotal
25
CPU INTERFACE
PIN#
PIN NAME
I/O
DESCRIPTION
203
ENCPU
I
CPU Interface Enable
Internally pull down. At reset, the pin is latched as CPU interface
enable.
205
CPUSEL
I
CPU Selection
The selected chip enable from CPU.
206
OUTCLK
O
8mA
CPU Input Clock
The switch generates 8.3MHz serial clock to CPU.
207
IODATA
I/O
4mA
CPU Data Input/Output
CPU read/write data & command.
208
INCLK
I
Subtotal
CPU Output Clock
CPU generates 8.3MHz serial clock to Ethernet switch.
5
LED INTERFACE
PIN#
PIN NAME
I/O
DESCRIPTION
204
LEDA
O
8mA
Address Table Self-test/Buffer Full LED
Internally pull down. Initially, after power on or reset, address table
will be tested and LEDC (Reset function) is keeping on until internal
test finished. If any error found in address table, LEDA will keep on.
After LEDC off, the switch is functional. If global buffer utilization is
full within previous 40ms intervals, LEDA will be on 40ms. It will keep
on if the buffer utilization keeps full within current intervals.
203
LEDB
O
8mA
Buffer Memory Test/Packet Loss LED
Internally pull down. If power on or reset, LEDC (Reset function) is
keeping on and all buffer memory will be tested. If buffer memory has
an error found, LEDB will be on.
After LEDB and LEDC off, switch self-test is done. If packet loss
found, LEDB is keeping on 40ms within each 40ms time intervals.
202
LEDC
O
8mA
Reset/Broadcast Storm LED
Internally pull up. If reset, LEDC is on until all internal memory test
finished. Then, the pin will show the status of broadcast storm
packets. If the number of broadcast packets stored in switch over
threshold within 40ms time intervals, LEDC will be on 40ms. It will be
shown until broadcast storm released.
3
Subtotal
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MX98224EC
MISCELLANEOUS
PIN#
PIN NAME
I/O
DESCRIPTION
147
MDC
I/O
16mA
Management Data Clock
Internal pull down. The pin provides 2.5MHz clock for MDIO.
148
MDIO
I/O
16mA
Management Data
Bi-directional RMII management port data pin. MDIO is synchronous
with respect to MDC and is sampled on the rising edge of MDC.
150
RESET#
33, 74, 96,
134, 169,
189,
Vcc
I
Chip Reset
Active low; be held low for some time after power-on.
1.8V Core Power
16, 47, 62,
Vdd
85, 120, 145,
177, 200
3.3V I/O Power
GND
17, 34, 48,
63, 75, 86,
97, 121, 135,
146, 170,
178, 190,
201
Ground
Subtotal
31
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MX98224EC
EEPROM AND CPU CONTROL REGISTERS
OFFSET
REGISTER
OFFSET
REGISTER
0x00H
Port Base VLAN Group 0 (0-11)
0x1BH
Aging Timer
0x01H
Port Base VLAN Group 0 (12-23)
0x1CH
Reserved
0x02H
Port Base VLAN Group 1 (0-11)
0x1DH
802.3x Pause Frame Timer
0x03H
Port Base VLAN Group 1 (12-23)
0x1EH
MAC Address 0
0x04H
Port Base VLAN Group 2 (0-11)
0x1FH
MAC Address 1
0x05H
Port Base VLAN Group 2 (12-23)
0x20H
MAC Address 2
0x06H
Port Base VLAN Group 3 (0-11)
0x21H
IP/VLAN Tagging Base Priority (0-7)
0x07H
Port Base VLAN Group 3 (12-23)
0x22H
IP/VLAN Tagging Base Priority (8-15)
0x08H
Port Base VLAN Group 4 (0-11)
0x23H
IP/VLAN Tagging Base Priority (16-23)
0x09H
Port Base VLAN Group 4 (12-23)
0x24H
Reserved
0x0AH
Port Base VLAN Group 5 (0-11)
0x25H
Reserved
0x0BH
Port Base VLAN Group 5 (12-23)
0x26H
Reserved
0x0CH
Port Base VLAN Group 6 (0-11)
0x27H
LED Control & VLAN Group Reset
0x0DH
Port Base VLAN Group 6 (12-23)
0x28H
CPU Access Data
0x0EH
Port Base VLAN Group 7 (0-11)
0x29H
PHY/Address Table Operation Command
0x0FH
Port Base VLAN Group 7 (12-23)
0x2AH
Flow Control Enable (8-23)
0x10H
Port Base VLAN Group 8 (0-11)
0x2BH
Reserved
0x11H
Port Base VLAN Group 8 (12-23)
0x2CH
Flow Control Enable (0-7)
0x12H
Port Base VLAN Group 9 (0-11)
0x2DH
Reserved
0x13H
Port Base VLAN Group 9 (12-23)
0x2EH
Reserved
0x14H
Port Base VLAN Group 10 (0-11)
0x2FH
Reserved
0x15H
Port Base VLAN Group 10 (12-23)
0x30H
Auto-negotiation Disable (0-15)
0x16H
Port Base VLAN Group 11 (0-11)
0x31H
0x17H
Port Base VLAN Group 11 (12-23)
Auto-negotiation (16-23) & Force Speed
Setting (0-7)
0x18H
Configuration 0 & Port Base Priority (0-7)
0x32H
Force Speed Setting (8-23)
0x19H
Port Base Priority (8-23)
0x33H
Force Half/Full Duplex Setting (0-15)
0x1AH
Configuration 1
0x34H
Force Half/Full Duplex Setting (16-23)
Note : 1. 93C46 EEPROM must be in 16-bit mode
2. The contents of EEPROM and CPU access registers are the same as following descriptions
3. (A-B) means port number setting from A to B
P/N:PM0782
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10
MX98224EC
Port Base VLAN Group 0 (0-11) (Reg00H), default = 0x0FFFH
BIT
0.11-0
0.15-12
DESCRIPTION
Port 0-11 VLAN Group 0
Default 1; all ports are into single group.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 0 member
TYPE
DEFAULT
R/W
0xFFF
TYPE
DEFAULT
R/W
0xFFF
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 0 (12-23) (Reg01H), default = 0x0FFFH
BIT
1.11-0
1.15-12
DESCRIPTION
Port 12-23 VLAN Group 0
Default 1; all ports are into single group.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 0 member
N/A
Port Base VLAN Group 1 (0-11) (Reg02H), default = 0x0000H
BIT
2.11-0
2.15-12
DESCRIPTION
Port 0-11 VLAN Group 1
Default 0; group 1 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 1 member
N/A
Port Base VLAN Group 1 (12-23) (Reg03H), default = 0x0000H
BIT
3.11-0
3.15-12
DESCRIPTION
Port 12-23 VLAN Group 1
Default 0; group 1 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 1 member
N/A
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11
MX98224EC
Port Base VLAN Group 2 (0-11) (Reg04H), default = 0x0000H
BIT
4.11-0
4.15-12
DESCRIPTION
Port 0-11 VLAN Group 2
Default 0; group 2 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 2 member
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 2 (12-23) (Reg05H), default = 0x0000H
BIT
5.11-0
5.15-12
DESCRIPTION
Port 12-23 VLAN Group 2
Default 0; group 2 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 2 member
N/A
Port Base VLAN Group 3 (0-11) (Reg06H), default = 0x0000H
BIT
6.11-0
6.15-12
DESCRIPTION
Port 0-11 VLAN Group 3
Default 0; group 3 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 3 member
N/A
Port Base VLAN Group 3 (12-23) (Reg07H), default = 0x0000H
BIT
7.11-0
7.15-12
DESCRIPTION
Port 12-23 VLAN Group 3
Default 0; group 3 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 3 member
N/A
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Port Base VLAN Group 4 (0-11) (Reg08H), default = 0x0000H
BIT
8.11-0
8.15-12
DESCRIPTION
Port 0-11 VLAN Group 4
Default 0; group 4 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 4 member
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 4 (12-23) (Reg09H), default = 0x0000H
BIT
9.11-0
9.15-12
DESCRIPTION
Port 12-23 VLAN Group 4
Default 0; group 4 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 4 member
N/A
Port Base VLAN Group 5 (0-11) (Reg0AH), default = 0x0000H
BIT
A.11-0
A.15-12
DESCRIPTION
Port 0-11 VLAN Group 5
Default 0; group 5 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 5 member
N/A
Port Base VLAN Group 5 (12-23) (Reg0BH), default = 0x0000H
BIT
B.11-0
B.15-12
DESCRIPTION
Port 12-23 VLAN Group 5
Default 0; group 5 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 5 member
N/A
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MX98224EC
Port Base VLAN Group 6 (0-11) (Reg0CH), default = 0x0000H
BIT
C.11-0
C.15-12
DESCRIPTION
Port 0-11 VLAN Group 6
Default 0; group 6 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 6 member
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 6 (12-23) (Reg0DH), default = 0x0000H
BIT
D.11-0
D.15-12
DESCRIPTION
Port 12-23 VLAN Group 6
Default 0; group 6 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 6 member
N/A
Port Base VLAN Group 7 (0-11) (Reg0EH), default = 0x0000H
BIT
E.11-0
E.15-12
DESCRIPTION
Port 0-11 VLAN Group 7
Default 0; group 7 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 7 member
N/A
Port Base VLAN Group 7 (12-23) (Reg0FH), default = 0x0000H
BIT
F.11-0
F.15-12
DESCRIPTION
Port 12-23 VLAN Group 7
Default 0; group 7 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 7 member
N/A
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MX98224EC
Port Base VLAN Group 8 (0-11) (Reg10H), default = 0x0000H
BIT
10.11-0
10.15-12
DESCRIPTION
Port 0-11 VLAN Group 8
Default 0; group 8 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 8 member
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 8 (12-23) (Reg11H), default = 0x0000H
BIT
11.11-0
11.15-12
DESCRIPTION
Port 12-23 VLAN Group 8
Default 0; group 8 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 8 member
N/A
Port Base VLAN Group 9 (0-11) (Reg12H), default = 0x0000H
BIT
12.11-0
12.15-12
DESCRIPTION
Port 0-11 VLAN Group 9
Default 0; group 9 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 9 member
N/A
Port Base VLAN Group 9 (12-23) (Reg13H), default = 0x0000H
BIT
13.11-0
13.15-12
DESCRIPTION
Port 12-23 VLAN Group 9
Default 0; group 9 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 9 member
N/A
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MX98224EC
Port Base VLAN Group 10 (0-11) (Reg14H), default = 0x0000H
BIT
14.11-0
14.15-12
DESCRIPTION
Port 0-11 VLAN Group 10
Default 0; group 10 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 10 member
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
TYPE
DEFAULT
R/W
0x000
N/A
Port Base VLAN Group 10 (12-23) (Reg15H), default = 0x0000H
BIT
15.11-0
15.15-12
DESCRIPTION
Port 12-23 VLAN Group 10
Default 0; group 10 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 10 member
N/A
Port Base VLAN Group 11 (0-11) (Reg16H), default = 0x0000H
BIT
16.11-0
16.15-12
DESCRIPTION
Port 0-11 VLAN Group 11
Default 0; group 11 not in use if all zero.
One bit per port; e.g. bit 0 for port 0 and bit 11 for port 11
0 : disable; to be treat as an isolated port
1 : enable; to be a group 11 member
N/A
Port Base VLAN Group 11 (12-23) (Reg17H), default = 0x0000H
BIT
17.11-0
17.15-12
DESCRIPTION
Port 12-23 VLAN Group 11
Default 0; group 11 not in use if all zero.
One bit per port; e.g. bit 0 for port 12 and bit 11 for port 23
0 : disable; to be treat as an isolated port
1 : enable; to be a group 11 member
N/A
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MX98224EC
Configuration 0 and Port Base Priority (0-7) (Reg18H), default = 0x0022H
BIT
DESCRIPTION
TYPE
DEFAULT
18.0
Continuous 16-time Collision Drop Disable
0 : packet that runs into 16 consecutive collision will be dropped
1 : packet that runs into 16 consecutive collision will NOT be dropped
R/W
0
18.1
Timeout disable
0 : packet will NOT be dropped if packet has been queued over 1 second
1 : packet will be dropped in spite of packet being queue over 1 second
R/W
1
18.3-2
CRC Hashing Selection
48-bit DA/SA address is translated separated into 12-bit entry pointer of
address table for address learning and recognition. The translation is by
aid of CRC generator within the switch controller. The index of entry
pointer selection is defined by:
00 : bit [11:0] of CRC are selected
01 : bit [16:5] of CRC are selected
10 : bit [24:13] of CRC are selected
11 : bit [30:19] of CRC are selected
R/W
00
18.4
Direct Mapping
It means bit [63:52] of DA/SA address directly as an index of address
table.
0 : CRC calculation to get the hashing index of address table
1 : direct mapping enable
R/W
1
18.5
Reserved
R/W
0
18.6
N/A
18.7
Reserved
R/W
1
Port 0-7 Priority
Port base priority settings from port 0 to port 7. If external pins of port
base priority are set, the content of EEPROM or CPU will be overridden.
One bit per port; e.g. bit 8 for port 0 and bit 15 for port 7.
0 : disable
1 : enable, the port of packets always in high priority
R/W
0x00H
18.15-8
Port Base Priority (8-23) (Reg19H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
19.15-0
Port 8-23 Priority
Port base priority settings from port 8 to port 23. If external pins of port
base priority are set, the content of EEPROM or CPU will be overridden.
One bit per port; e.g. bit 0 for port 8 and bit 15 for port 23.
0 : disable
1 : enable, the port of packets always in high priority
R/W
0x0000H
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MX98224EC
Configuration 1 (Reg1AH), default = 0x502EH
BIT
DESCRIPTION
TYPE
DEFAULT
1A.3-0
Reserved
R/W
0xFH
1A.5-4
Backoff Operation Mode
In normal backoff algorithm, packet transmission delays a random time
within 2n –1 slot time (1 slot time = 512 bit times) when collision occurs.
The switch provides some modification of backoff algorithm to improve
Ethernet performance on half- duplex connection.
00 : standard operation.
01 : first two collisions follow standard backoff. More than two collisions
in transmission, packet resend delays 0-3 slot times.
10 : packet resend delays 0 slot time only when port buffer full.
11 : packet resend delays 0 slot time all the time.
R/W
00
1A.6
Back Pressure Disable
Enable back pressure on half duplex connection for all ports
0 : enable
1 : disable
R/W
0
1A.7
N/A
1A.8
Reserved
R/W
0
High/Low Priority Ratio
Bit 9 to 11 means a decimal value for low priority packets to be
transmitted whereas bit 12 to 14 to a decimal value for high priority
packets. Followings are some example of high to low priority value.
R/W
0x28H
R/W
0
1A.14-9
High Priority Value
Bit 14 Bit 13 Bit 12
1A.15
Low Priority Value
Bit 11 Bit 10 Bit 9
Meaning
0/1
0/1
0/1
0
0
0
High priority port packets need
to be sent first until empty;
then, low priority packets
0
1
1
0
0
1
The transmission ratio of high
to low priority packets is 3 : 1
Aging Out
Enable the function of aging out from address table.
0 : enable
1 : disable
Aging Timer (Reg1BH), default = 0x0005H
BIT
DESCRIPTION
TYPE
DEFAULT
1B.15-0
Aging timer provides for address table. The timer period is defined to
age out the least unused entries on address table. The formula is
age_timer (bit 0-15) X 65536 X 1ms. Here are some examples:
R/W
0x0005H
Bit 15 – Bit 0
0x0001H
0x0005H
0x001BH
0x0037H
Aging Timer
65.5 sec
327.7 sec
1769.5 sec
3604.5 sec
(around 1 min)
(around 5.5 min)
(around 30 min)
(around 1 hr)
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Reserved (Reg1CH), default = 0xC350H
BIT
1C.15-0
DESCRIPTION
Reserved
TYPE
DEFAULT
R/W
0xC350H
TYPE
DEFAULT
802.3x Pause Frame Timer (Reg1DH), default = 0x01FFH
BIT
DESCRIPTION
1D.4-0
Reserved
R/W
0x1FH
1D.15-5
Flow Control Counter
The timer determines the period, namely “pause time”, to inhibit packet
transmission from attached host for flow control. The variable pause
time of pause frame is equal to the decimal value times 32 plus 31 slot
time.
R/W
0x1E0H
TYPE
DEFAULT
R/W
0x0000H
TYPE
DEFAULT
R/W
0x0000H
TYPE
DEFAULT
R/W
0x0000H
MAC Address 0 (Reg1EH), default = 0x0000H
BIT
1E.15-0
DESCRIPTION
Switch’ s MAC ID for address bit [15:0]
MAC Address 1 (Reg1FH), default = 0x0000H
BIT
1F.15-0
DESCRIPTION
Switch’ s MAC ID for address bit [31:16]
MAC Address 2 (Reg20H), default = 0x0000H
BIT
20.15-0
DESCRIPTION
Switch’ s MAC ID for address bit [47:32]
IP/VLAN Tagging Base Priority (0-7) (Reg21H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
21.7-0
TOS (IP Base)
Enable for port 0-7 to recognize the TOS field of IP priority packets. One
bit per port; e.g. bit 0 for port 0 and bit 7 for port 7.
0 : disable
1 : enable
R/W
0x00H
21.15-8
TCI (VLAN Tagging Base)
Enable for port 0-7 to recognize the TCI field of VLAN priority packets.
One bit per port; e.g. bit 8 for port 0 and bit 15 for port 7.
0 : disable
1 : enable
R/W
0x00H
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IP/VLAN Tagging Base Priority (8-15) (Reg22H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
22.7-0
TOS (IP Base)
Enable for port 8-15 to recognize the TOS field of IP priority packets.
One bit per port; e.g. bit 0 for port 8 and bit 7 for port 15.
0 : disable
1 : enable
R/W
0x00H
22.15-8
TCI (VLAN Tagging Base)
Enable for port 8-15 to recognize the TCI field of VLAN priority packets.
One bit per port; e.g. bit 8 for port 8 and bit 15 for port 15.
0 : disable
1 : enable
R/W
0x00H
IP/VLAN Tagging Base Priority (16-23) (Reg23H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
23.7-0
TOS (IP Base)
Enable for port 16-23 to recognize the TOS field of IP priority packets.
One bit per port; e.g. bit 0 for port 16 and bit 7 for port 23.
0 : disable
1 : enable
R/W
0x00H
23.15-8
TCI (VLAN Tagging Base)
Enable for port 8-15 to recognize the TCI field of VLAN priority packets.
One bit per port; e.g. bit 8 for port 16 and bit 15 for port 23.
0 : disable
1 : enable
R/W
0x00H
TYPE
DEFAULT
R/W
0xB081H
TYPE
DEFAULT
R/W
0x0040H
TYPE
DEFAULT
R/W
0x0082H
Reserved (Reg24H), default = 0xB081H
BIT
24.15-0
DESCRIPTION
Reserved
Reserved (Reg25H), default = 0x0040H
BIT
25.15-0
DESCRIPTION
Reserved
Reserved (Reg26H), default = 0x0082H
BIT
26.15-0
DESCRIPTION
Reserved
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LED Control and VLAN Group Reset (Reg27H), default = 0x0200H
BIT
DESCRIPTION
TYPE
DEFAULT
27.0
Port Grouping Command
When, initially, the execution of default values of the VLAN registers
(Reg00H-17H) or VLAN grouping settings required via CPU/EEPROM,
VLAN grouping contents need to write into the registers; then, grouping
command is put into action. After grouping command is done, the bit will
be self-clean to 0.
0 : Idle
1 : Port regrouping enable
Reserved
R/W
0
R/W
00
27.3
Broadcast Storm LED
0 : LED displays the broadcast storm symptom in high priority packets
1 : LED displays the broadcast storm symptom of all packets
R/W
1
27.4
Packet Loss LED
0 : LED displays the high priority packet loss
1 : LED displays all packet loss
R/W
1
27.2-1
27.15-5
N/A
0x010H
CPU Access Data (Reg28H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
28.15-0
Access Data
Generally, bit 15-0 is the access data for PHY registers and address table.
In case, CPU requires to select PHY ID and register number before PHY
register access. The starting PHY ID for the switch is 0. Bit 4-0 can be
presented for PHY register number and bit 9-5 for PHY ID in address
selection of PHY registers operation.
R/W
0x0000H
PHY/Address Table Operation Command (Reg29H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
29.0
CPU Action
If CPU takes read/write actions to address table or PHY registers, set the
bit on. After action done, the bit will be self-clean to 0.
0 : Idle
1 : CPU action
R/W
0
29.1
CPU Read/Write
Read or write action set to address table or PHY registers.
0 : Read operation
1 : Write operation
R/W
0
29.2
PHY/ALR Selection
CPU access to PHY or address table
0 : PHY access
1 : Address table access
R/W
0
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29.5-3
PHY/ALR Command
In PHY register access
000 : A searching function for PHY ID and PHY register number when
CPU access data filled relevant information.
001 : A command for switch internal control register to CPU access data
based on read operation or a command for CPU access data to
register to switch internal control register based on write operation.
100 : A command for content of PHY register to switch internal control
register based on read operation or a command for switch internal
control register to PHY register based on write operation.
In address table access
000 : MAC ID for address bit [15:0] access from CPU access data to
switch internal control register based on CPU write operation. It
also can be MAC ID access bit [15:0] from switch internal control
register to CPU access data based on CPU read operation.
001 : MAC ID for address bit [31:16] access from CPU access data to
internal control register and based on CPU write operation; and vice
versa.
010 : MAC ID for address bit [47:32] access from CPU access data to
switch internal control register based on CPU write operation; and
vice versa.
011 : Status of address table entry access like port number bit [8:4], aging
timer bit [3:1], and valid bit [0] from switch internal control register to
CPU access data based on CPU read operation.
100 : Based on read operation from content of an address table entry to
switch internal control register or write operation from switch internal
control register to content of an address table entry.
R/W
0x0H
29.10-6
Frozen Port
The switch provides frozen function for an entry in address table; that is,
an entry with learned MAC address and port number as an input will
protect not to be aging out when the port number and assigned MAC have
been set. Frozen function can only work on the first layer of address
table. It’ s because the entry of second-layer of address table should be
for dynamic MAC address. If frozen port sets to all one and CPU
read/write command is one, the frozen MAC address will be released. If
frozen port sets all one and CPU read/write command is zero, the host
processor will read the content of second layer of address table.
R/W
0x00H
29.15-11
Reserved
R/W
0x00H
Flow Control Enable (8-23) (Reg2AH), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
2A.15-0
Flow Control Enable
IEEE 802.3x flow control for port 8-23. One bit per port; e.g. bit 0 for port
8 and bit 15 for port 23.
0 : disable
1 : enable
R/W
0x0000H
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Reserved (Reg2BH), default = 0xFFFFH
BIT
2B.15-0
DESCRIPTION
Reserved
TYPE
DEFAULT
R/W
0xFFFFH
TYPE
DEFAULT
Flow Control Enable (0-7) (Reg2CH), default = 0x00FFH
BIT
DESCRIPTION
2C.7-0
Reserved
R/W
0xFFH
2C15-8
Flow Control Enable
IEEE 802.3x flow control for port 0-7. One bit per port; e.g. bit 8 for port
0 and bit 15 for port 7.
0 : disable
1 : enable
R/W
0x00H
TYPE
DEFAULT
R/W
0x0000H
TYPE
DEFAULT
RO
N/A
TYPE
DEFAULT
RO
N/A
Reserved (Reg2DH), default = 0x0000H
BIT
2D.15-0
DESCRIPTION
Reserved
Reserved (Reg2EH), default = N/A
BIT
2E.15-0
DESCRIPTION
Reserved
Reserved (Reg2FH), default = N/A
BIT
2F.15-0
DESCRIPTION
Reserved
Auto-negotiation (0-15) (Reg30H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
30.15-0
Auto-negotiation Disable
Auto-negotiation operation of MDIO. When port base auto-negotiation
disable, the switch port will not listen the final response from PHY. One
bit per port; e.g. bit 0 for port 0 and bit 15 for port 15.
0 : enable auto-negotiation
1 : disable auto-negotiation
R/W
0x0000H
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Auto-negotiation (16-23) & Force Speed Setting (0-7) (Reg31H), default = 0xFF00H
BIT
DESCRIPTION
TYPE
DEFAULT
31.7-0
Auto-negotiation Disable
Auto-negotiation operation of MDIO. When port base auto-negotiation
disable, the switch port will not listen the final response from PHY. One
bit per port; e.g. bit 0 for port 16 and bit 7 for port 23.
0 : enable auto-negotiation
1 : disable auto-negotiation
R/W
0x00H
31.15-8
Force Speed Operation
When auto-negotiation off, the port will be set at fixed speed. In
EEPROM, force settings will be automatically written into PHY registers at
initialization. Force settings by CPU requires extra CPU write operation
into PHY; so port-base speed operations can keep consistency. One bit
per port; e.g. bit 8 for port 0 and bit 15 for port 7.
0 : force 10Mbps
1 : force 100Mbps
R/W
0xFFH
TYPE
DEFAULT
R/W
0xFFFFH
Force Speed Setting (8-23) (Reg32H), default = 0xFFFFH
BIT
32.15-0
DESCRIPTION
Force Speed Operation
One bit per port; e.g. bit 0 for port 8 and bit 15 for port 23.
0 : force 10Mbps
1 : force 100Mbps
Force Half Duplex Setting (0-15) (Reg33H), default = 0xFFFFH
BIT
DESCRIPTION
TYPE
DEFAULT
33.15-0
Force Half Duplex Operation
When auto-negotiation off, the port will be set at fixed duplex. In
EEPROM, force settings will be automatically written into PHY registers at
initialization. Force settings by CPU requires extra CPU write operation
into PHY; so port-base duplex operations can keep consistency. One bit
per port; e.g. bit 0 for port 0 and bit 15 for port 15.
0 : force half duplex
1 : force full duplex
R/W
0xFFFFH
TYPE
DEFAULT
R/W
0xFF
Force Half Duplex Setting (16-23) (Reg34H), default = 0x00FFH
BIT
DESCRIPTION
34.7-0
Force Half Duplex Operation
One bit per port; e.g. bit 0 for port 16 and bit 7 for port 23.
0 : force half duplex
1 : force full duplex
34.15-8
N/A
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FUNCTIONAL DESCRIPTION
Clocks
MX98224EC requires a unique 50MHz clock signal for both RMII and system requirement at CLK input pin. Also, the
switch generates an 8.3MHz output clock to CPU and the processor feedback the same clock rate back to the switch.
The 2.5MHz clock applies on MDC/MDIO interface and 390KHz refers EEPROM interface.
Reset
When power on, a hard reset is initiated by an active low pulse on RESET# pin. The initialization process loads all
ports configurable parameters, resets internal state machines to idle, initializes embedded memory and address table.
At the completion of the reset sequence, all ports are presented for packet transmission and reception.
RMII Interface
Reduced Media Independent Interface (RMII) comprises a low pin count intended for use between Ethernet PHYs and
switch ASICs. The management interface (MDC/MDIO) is assumed to be identical to that defined in IEEE 802.3u.
The RMII specification has been optimized for using in high port density interconnect devices which require
independent treatment of the data paths. The primary motivator is a switch ASIC which requires independent data
streams between the MAC and PHY.
CLK
CLK is a continuous clock that provides the timing reference for CRSDV_0-23, RXD_0-23[1:0], TXEN_0-23, and
TXD_0-23[1:0]. The switch choose to provide CLK as an input for system and RMII use and each PHY device shall
have an input corresponding to this clock but may use a single clock input for multiple PHYs implemented on a single
IC.
Carrier Sense/Receive Data Valid
CRSDV_0-23 shall be asserted by the PHY when the receive medium is non-idle. The specifics of the definition of
idle for 10BASE-T and 100BASE-X are contained in IEEE 802.3 and IEEE 802.3u. CRSDV0-23 is asserted
asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode,
when squelch is passed or, in 100BASE-X mode, when 2 non-contiguous zeroes in 10 bits are detected carrier is said
to be detected. If the PHY has additional bits to be presented on RXD_0-23[1:0] following the initial deassertion of
CRSDV_0-23, then the PHY shall assert CRSDV_0-23 on cycles of CLK which present the second di-bit of each
nibble and deassert CRSDV_0-23 on cycles of CLK which present the first di-bit of a nibble.
Receive Data
RXD_0-23[1:0] shall transition synchronously to CLK. For each clock period in which CRSDV_0-23 is asserted,
RXD_0-23[1:0] transfers two bits of recovered data from the PHY. In some cases, for example before data recovery
or during error conditions, a pre-determined value for RXD_0-23[1:0] is transferred instead of recovered data.
RXD_0-23[1:0] shall be “00” to indicate idle when CRSDV_0-23 is deasserted. Values other than “00” on RXD_023[1:0] while recovered from CRSDV_0-23 is de-asserted shall be ignored by the MAC. Upon assertion of
CRSDV_0-23, the PHY shall ensure that RXD_0-23[1:0] is equal to ”00” until proper receive decoding takes place.
Transmit Enable
TXEN_0-23 indicates that the MAC is presenting di-bits on TXD_0-23[1:0] for transmission. TXEN_0-23 shall be
asserted synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be
transmitted are presented. TXEN_0-23 shall be negated prior to the first CLK rising edge following the final di-bit of a
frame. TXEN_0-23 shall transition synchronously with respect to CLK.
Transmit Data
TXD_0-23[1:0] shall transition synchronously with respect to CLK. When TXEN_0-23 is asserted, TXD[1:0] are
accepted for transmission by the PHY. TXD_0-23[1:0] shall be “00” to indicate idle when TXEN_0-23 is deasserted.
Values other than “00” on TXD_0-23[1:0] while TXEN_0-23 is deasserted shall be ignored by the PHY.
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MX98224EC
PHY Management
The PHY determines the operation mode of each port, which are classified as 10Mbps-half duplex, 10Mbps-full duplex,
100Mbps-half duplex, 100Mbps-full duplex. The MAC of each port is connected to the PHY through RMII interface.
The PHY starting ID mapped to the switch is zero. The switch supports PHY management through the serial
MDC/MDIO interface. The switch will continuously read the registers of each PHY based on PHY ID to get the latest
information such as link status, speed, operation mode of each port while it is in auto-negotiation. When a port of the
switch forced at fixed operation mode, it will not listen any response from the PHY through MDC/MDIO so that
consistent speed and duplex in PHY as well as switch is required in force operation mode.
Frame Reception
The frame received on 2-bit wide receive channel of RMII interface is queued in receive FIFO, and then stored into
embedded buffer memory. Several error conditions will be identified during data reception.
1.Runt frame error, if the frame size is less than 64 bytes;
2.CRC error, if FCS is not matched to the result of CRC calculation;
3.Long frame error, if frame size is larger than 1536 bytes;
4.Alignment error, if frame length is of non-integral number of octets;
The above frames will be discarded. If no errors have been detected, the frame is stored and forwarded to egress
port at wire speed. Several pages of buffer memory could be occupied for frame storage, on each page free memory
is allocated. The data link management frames, namely IEEE 802.3x "pause" frame is recognized and no frame
storage occurs.
Frame Transmission
Frame transmission begins while the output queue of physical port is not empty. The frame data is moved to output
FIFO from embedded buffer memory, and converted to 2-bit stream through transmit channel of RMII interface.
MX98224EC transmits frames in accordance to IEEE 802.3 standard. The egress port is responsible for preamble
insertion, collision back-off, and inter packet gap keeping. While late collision happens on half-duplex port, the
transmitted frame is aborted. If a packet has continuously met 16-time collisions, it will be dropped and the packet
will be recovered by upper protocol. In full-duplex mode, the egress port ignores the signaling of carrier activity and
collision detection on channel media.
Broadcast Storm Control
Three types of frames are viewed as broadcast frames in MX98224EC:
1. Received frame with DL_DA as FF-FF-FF-FF-FF-FF
2. Received frame with DL_DA as 1?-??-??-??-??-??
3. Received frame with unknown destination (unicast or multicast) address
To prevent network melted down, a state of complete network overload, due to broadcast storm (incorrect packet
broadcast on a network that cause almost all hosts respond at once and hence storming the network with broadcast
packets), users can program to restrict the storage amount of broadcast frames in MX98224EC. While the storage of
broadcast frame goes over the threshold, the next coming broadcast frame(s) is dropped.
Flow Control
Flow control is implemented to avoid abnormal packet drop due to traffic congestion on egress ports. Basically,
alternative back-pressure mechanism uses jam packet in half-duplex and 802.3x pause frame does in full-duplex
mode. Flow control is active or inactive based on the internal per port and global reception thresholds in buffer.
The switch implements standard 802.3x flow control whose frame is defined as follow.
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MX98224EC
6 Octets
DA
6 Octets
SA
2 Octets
Type
2 Octets
2 Octets
Opcode Pause_Time
42 Octets
PAD
802.3x PAUSE Frame Format
The diagram shown above is IEEE 802.3x pause frame format whereas DA presented for destination MAC adress, SA
for source MAC address, pause frame type defined as 0x8808, opcode for pause operation (0x0001), default pause
time for the switch to be 0x1FFF, and pad for all zero. The value of pause timer is changable by EEPROM or CPU.
DA field of pause frame should be 0x0180C2000001 before transmission.
Address Learning and Recognition
After a good packet is received, address resolution logic begins address lookup. The destination MAC address and
source MAC address associated are retrieved. The source MAC address is used to build up an address table. By
searching the address table, if a unicast destination MAC address is recognized, the stored frame is forwarded to
destined port. Initially, a unicast destination MAC address of a packet does not know the outgoing port number so
that the stored frame is forwarded as a broadcast packet. In both of address learning and recognition, 48-bit MAC
address is converted into a 12-bit search index via hash transformation. The switch offers two different hashing
schemes; one is called direct mapping and the other is CRC mapping. In learning, an entry designated by the search
index is checked to be valid or not. If non-valid, a new entry is generated with putting the information of source MAC
address and ingress port number. A 2-layer structure is provided in learning mechanism. If valid, the 2-layer
mechanism can keep 2 different MAC addresses in one certain entry to increase hashing resolution. If congestion
found for an entry of the 2-layer structure, switch will compare the two numbers of the aging timer and replace the
MAC record with older aging time to the new MAC. In recognition, the MAC address in table entry designated by
search index is used to compare with destination MAC address. If both are matched, the associated port number in
address table entry is the destination port. Otherwise, the received frame will be classified as a broadcast frame, and
be flooded through every port (except source port). The memory space within MX98224EC can keep up to 8K MAC
addresses. Aging mechanism is supported, namely the address information is aged out if not be referred in 300sec
(default, the parameter is programmable). And, the entry of the record can be for newly learnt MACs kept in table.
2-priority Queue Class of Service (CoS)
Class of Service denotes the classification of traffic used to differentiate services among traffic classes. MX98224EC
offers 2-level priority (High and Low) queues, which catch the priority information in the TOS field, port base, or VLAN
tag in the incoming frames as standard IEEE 802.1Q defines. In this way, the switch controller guarantees the
service for high priority frames to some extent, depending on the load condition of incoming traffic. (At least, the high
priority service offers better than that of best effort service.) It also provides different service ratio settings for users to
shape the prioritized frames on the streams in the incoming traffic.
Port-based VLAN
A Virtual LAN (VLAN) is a broadcast domain or a network segment which enables multiple stations on different
physical locations to communicate with each other as if they were on the same LAN. With all the advantages such as
increasing performance, bandwidth utilization efficiency and security as well as preventing broadcast storm, PortBased VLAN is the most practical and economical form of VLAN.
MX98224EC supports up to 12 port-based VLAN groups which applies the overlapped VLAN scheme. That is, the
24 switch ports can be divided into 12 VLAN port-groups. By configuring the port with its VLAN membership, each
port is assigned to one or more (up to 12) groups. Ports belonging to different groups are independent, which means
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MX98224EC
their network activity or fundamental network broadcasting will not affect or get distributed across those VLAN groups
to each other. In this way, it can reduce the need for unwanted traffic in the network. Moreover, the
damaged/abnormal ports can be isolated by removing them from VLAN groups' list, so as to prevent network
meltdown. Port-based VLAN in MX98224EC is also very flexible that every port can be shared by multiple groups as
the "trunk port" while the other unshared ports are remained independent.
Queue Management
MX98224EC utilizes the store-and-forward switching scheme, which needs memory for frame reception and
transmission buffering. In MX98224EC, the embedded buffer memory is partitioned into pages which dynamically
allocates the related frame data and switching information. The buffer management control unit dispatches pointers
pointing to those pages upon frames reception of the egress ports.
For unicast frames, the occupied buffer pages are released after the corresponding ports complete transmission.
Their pointers are returned to buffer management control unit for reuse. For broadcast frames, the switch controller
count the times of transmission of the same broadcast frame till all ports finish the broadcast transmission, then the
occupied memory space are released to the free buffer pool.
Since there are various kinds of page/pointer requests for the buffer management, a queue manager is used in
MX98224EC to handle those access requests. Via a proprietary arbitration method, the queue manager grants fair
enough throughput for each port to transmit at wire speed.
93C46 EEPROM Interface
Provide serial interface to load the values of external EEPROM which switch can configure in advance. At initial
stage, switch will loads the data to internal registers and operates as expected. Either EEPROM or CPU interface
can be used once a time.
CPU Interface
MX98224EC provides another powerful way to configure the value of register via CPU, which can access its as well as
PHY registers and the address table at any time. Basically, MAC address look up, content of address table status
and frozen a dedicated address are the major function for CPU access through address table. Following is the basic
system diagram for the connection of host processor, switch, and PHY.
Octal PHY
OUTCLK
Host
Processor
INCLK
IODATA
MX98224EC
Switch
Octal PHY
MDC
Octal PHY
MDIO
Serial Management Block Diagram via Switch and PHY
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MX98224EC
The switch generates an OUTCLK clock to host processor and the same frequency will be back to the switch via
INCLK pin. There is a data format defined under below table which specifies a communication between the host
processor and switch at serial IODATA pin. IODATA and MDIO are bi-direction I/O. The serial management format
starts with start bit, then, follows operator, 10-bit register address, turn around, 16-bit content of data, and an idle bit.
A command/response from host processor to the switch registers, Reg28H and Reg29H, can be given based on
read/write operation, register address selection, and data.
Command
Read
Write
Start Bit
01
01
Operator
10
01
Register Address
AAAAAAAAAA
AAAAAAAAAA
Turn Around
Z0
10
Data
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Idle
Z
Z
LED Interface
MX98224EC has three LEDs. At initial stage, these represent address table self-test, memory test, and reset status
respectively. And at normal state, these represent buffer full, packet loss, and broadcast storm status. Users can
monitor the status of switch network via the LEDs.
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MX98224EC
TIMING DIAGRAM
Reset and Clock Timing
t03
t01
t02
CLK
RESET#
T#
DESCRIPTION
MIN
TYP
.t01
System clock period
20
20.2
.t02
System clock high time
9
10
.t03
RESET# low pulse duration
1
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MAX
UNIT
ns
11
ns
ms
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30
MX98224EC
PHY Management (MDIO) Reading Timing
t11
MDC
t15 t16
t12
t13
MDIO
t14
Register
Address
T#
TA
Q15
DESCRIPTION
Q0
MIN
TYP
MAX
UNIT
.t11
MDC high time
200
ns
.t12
MDC clock period
400
ns
.t13
MDC falling edge to MDIO delay
3
8
ns
.t14
MDC falling edge to MDIO Hi-Z
3
8
ns
.t15
MDIO setup time
2
ns
.t16
MDIO hold time
2
ns
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MX98224EC
RMII Interface Timing
CLK
t21
t22
TXEN
t23
t24
TXD
t25
t26
CSRSDV
t27
t28
RXD
T#
DESCRIPTION
MIN
TYP
MAX
UNIT
9
10
11
ns
.t21
CLK high time
.t22
CLK clock period
.t23
CLK to TXEN delay
3.5
10.5
ns
.t24
CLK to TXD delay
3.5
11.5
ns
.t25
CRSDV setup time
0
ns
.t26
CRSDV hold time
4
ns
.t27
RXD setup time
0
ns
.t28
RXD hold time
4
ns
20
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MX98224EC
EEPROM Interface Timing
t31
ESK
t37
t38
t32
ECS
t35
EDI
t36
t33
SB
OP
OP
A5
A0
t39
t310
t34
EDO
0
T#
DESCRIPTION
.t31
ESK clock
.t32
MIN
D15
D0
TYP
MAX
UNIT
2560
ns
93C46 chip enable
27
ESK
.t33
93C46 command input cycle
10
ESK
.t34
93C46 data output cycle
17
ESK
.t35
93C46 data input setup time
3
ns
.t36
93C46 data input hold time
.t37
93C46 chip select setup time
.t38
93C46 chip select hold time
.t39
93C46 data output setup time
.t310
93C46 data output hold time
ns
3
ns
ns
3
ns
ns
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MX98224EC
CPU Interface Timing
t41
CLK
t44
t42
Data IO
t46
CPUSEL
t45
t43
T#
DESCRIPTION
MIN
TYP
MAX
UNIT
.t41
CPU clock period
120
ns
.t42
Data IO setup timing
10
ns
.t43
Chip select setup timing
10
ns
.t44
Data IO hold timing
10
ns
.t45
Chip select hold timing
10
ns
.t46
Chip select period
3840
ns
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MX98224EC
ELECTRONICAL SPECIFICATION
Absolute Maximum Rating
Parameter
SYMBOL
MIN
MAX
UNIT
I/O Supply Voltage
Vdd
-0.5
4.6
V
Core Supply Voltage
VCC
-0.5
2.5
V
Input Voltage
VI
-0.5
6
V
Output Voltage
VO
-0.5
6
V
Storage Temperature
TSTG
-65
150
C
Operation Temperature
TOPR
-40
125
C
latch-up Current
TLAT
mA
Recommended Operating Conditions
Parameter
SYMBOL
MIN
MAX
UNIT
I/O Supply Voltage
Vdd
3.0
3.6
V
Core Supply Voltage
VCC
1.62
1.98
V
TOPR
0
70
C
Junction Temperature
Tj
0
125
C
Low-level Input Voltage
VIL
-0.3
0.8
V
High-level Input Voltage
VIH
2.0
5.5
V
SYMBOL
MIN
MAX
UNIT
Output High Voltage
VOH
2.4
Output Low Voltage
VOL
0.4
V
High Impedance State Output Current
IOZ
±1
µA
Output High Current (@VOH = 2.4V )
IOH
6.2
76.0
mA
Output Low Current (@VOL = 0.4V)
IOL
4.5
30.3
mA
Input High Voltage
VIH
Input Low Voltage
VIL
Supply Current
ICC
Operating Temperature
Power Dissipation
DC Characteristics
Parameter
V
mA
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MX98224EC
PACKAGE INFORMATION
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MX98224EC
REVISION HISTORY
Revision
0.2
Description
Speed/duplex settings change to FORCE from REG31H to REG34H
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Page
Date
24
04/18/2001
REV. 0.2, Apr, 18, 2001
37
MX98224EC
TOP SIDE MARKING
MX98224EC
line 1 :
MX98224EC is MXIC part No.
“E” : PQFP
“C” : Commercial grade
line 2 : Assembly Date Code.
line 3 : Wafer Lot No.
line 4 : “36C” : Revision code
“A” : Bonding option
“X” : Not used
line 5 : State
C0013
F40044937B1
36CAX
TAIWAN
MACRONIX INTERNATIONAL CO.,LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROP OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http://www.macronix.com
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38