OZ6933 ACPI CardBus Controller FEATURES • • • • • • • • • • • • • • • • • • • ACPI-PCI Bus Power Management Interface Specification Rev 1.1 Compliant Supports OnNow LAN wakeup, OnNow Ring Indicate, PCI CLKRUN#, PME#, and CardBus CCLKRUN# Compliant with PCI specification v2.2, 2000 PC Card Standard 7.1 Yenta™ PCI to PCMCIA CardBus Bridge register compatible ExCA (Exchangeable Card Architecture) compatible registers mappable in memory and I/O space TM Intel 82365SL PCIC Register Compatible Supports PCMCIA_ATA Specification Supports 5V/3.3V PC Cards and 3.3V CardBus cards Supports two PC Card or CardBus slots with hot insertion and removal Supports multiple FIFOs for PCI/CardBus data transfer Supports Direct Memory Access for PC/PCI and PCI/Way on PC Card socket Programmable interrupt protocol: PCI, PCI+ISA, PCI/Way, or PC/PCI interrupt signaling modes Win’98 IRQ and PC-98/99 compliant Supports parallel or serial interface for socket power control including devices from Micrel and TI Zoomed Video Support; Zoomed Video Buffer Enable Pins D3cold state PME# wakeup support 3.3Vaux Power Support Integrated PC 98/99 -Subsystem Vendor ID support, with auto lock bit LED Activity Pins ORDERING INFORMATION OZ6933T – 208 pin TQFP OZ6933B – 208 pin Mini-BGA GENERAL DESCRIPTION The OZ6933 is an ACPI and PC98/99 logo certified, high performance, dual slot PC Card controller with a synchronous 32-bit bus master/target PCI interface. This PC Card to PCI bridge host controller is compliant with the 2000 PC Card Standard. This standard incorporates the new 32-bit 07/20/00 Copyright 2000 by O2Micro CardBus while retaining the 16-bit PC Card specification as defined by PCMCIA release 2.1. CardBus is intended to support “temporal” add-in functions on PC Cards, such as Memory cards, Network interfaces, FAX/Modems and other wireless communication cards, etc. The high performance and capability of the CardBus interface will enable the new development of many new functions and applications. The OZ6933 CardBus controller is compliant with the latest ACPI-PCI Bus Power Management Interface Specification. It supports all four power states and the PME# function for maximum power savings and ACPI compliance. Additional compliance to OnNow Power Management includes D3cold state support, paving the way for low sleep state power consumption and minimized resume times. To allow host software to reduce power consumption further, the OZ6933 provides a power-down mode in which internal clock distribution and the PC Card socket clocks are stopped. An advanced CMOS process is also used to minimize system power consumption. The OZ6933 dual PCMCIA socket supports two 3.3V/5V 8/16-bit PC Card R2 cards or 32-bit CardBus R3 cards. The R2 card support is compatible with the Intel 82365SL PCIC controller, and the R3 card support is fully compliant with the 2000 PC Card Standard CardBus specification. The OZ6933 is a stand alone device, which means that it does not require an additional buffer chip for the PC Card socket interface. In addition, the OZ6933 supports dynamic PC Card hot insertion and removal, with auto configuration capabilities. The OZ6933 is fully compliant with the 33Mhz PCI Bus specification, v2.2. It supports a master device with internal CardBus direct data transfer. The OZ6933 implements a FIFO data buffer architecture between the PCI bus and CardBus socket interface to enhance data transfers to CardBus devices. The bi-directional FIFO buffer permits the OZ6933 to accept data from a target bus (PCI or CardBus interface) while simultaneously transferring data. This architecture not only speeds up data transfers but also prevents system deadlocks. The OZ6933 is a PCMCIA R2/CardBus controller, providing the most advanced design flexibility for PC Cards that interface with advanced notebook designs. OZ6933-SF-1.7 All Rights Reserved Page 1 OZ6933 FUNCTIONAL BLOCK DIAGRAM PCI Interface PCI PCI Arbite Arbiter r PCI Configuration/ PCI Function Control Registers Function Control Configuration/ Registers CardBus CardBu FIFO FIFO DatasBuffering Power Switch Power Control Contro Switch l EXCA 8/16-Bit 16PC PC Card Bit Machin Card State e Machine Powe Power Switc r Switch h Interface CardBus PC Card State Machine and Arbiter PC Card Socket A PC Card Interface Interface OZ6933-SF-1.7 ACPI/ OnNow Power Management for PC99 Interrupt Subsystem Interrup t EXCA 8/16 Bit PC Card State Machine CardBus PC Card State Machine and Arbiter Socket B PC Card Interface Page 2 OZ6933 SYSTEM BLOCK DIAGRAM The following diagram is a typical system block diagram utilizing the OZ6933 ACPI CardBus controller with other related chipsets. CPU VGA Memory AGP North Bridge PCI Bus OZ6933 CardBus Controller PC Card South Bridge PC Card ISA OZ6933-SF-1.7 Page 3 OZ6933 PIN DIAGRAM - 208 PIN TQFP B_A8/CCBE1# B_A17/CAD16 B_A13/CPAR B_SOCKET_VCC B_A18/RFU B_A14/CPERR# IRQ12/PME# B_A19/CBLOCK# B_WE#/CGNT# B_A20/CSTOP# B_RDY_IREQ#/CINT# B_A21/CDEVSEL# B_A16/CCLK B_A22/CTRDY# B_A15/CIRDY# B_A23/CFRAME# B_A12/CCBE2# B_A24/CAD17 B_A7/CAD18 B_A25/CAD19 GND B_A6/CAD20 B_VS2/CVS2 CORE_VCC B_A5/CAD21 B_RESET/CRESET# B_A4/CAD22 B_WAIT#/CSERR# B_A3/CAD23 B_INPACK#/CREQ# B_A2/CAD224 B_REG#/CC_BE3# B_A1/CAD25 B_BVD2/CAUDIO B_A0/CAD26 B_BVD1/CSTCHG IRQ11/SKTB_ACTV B_D0/CAD27 B_D8/CAD28 B_D1/CAD29 B_D9/CAD30 B_D2/RFU B_D10/CAD31 B_SOCKET_VCC B_WP/CCLKRUN# B_CD2#/CCD2# INTA# IRQ4/INTB# IRQ5/SERIRQ IRQ7/SIN#/B_VPP_PGM RST# IRQ14/CLKRUN# PCI_CLK PCI_GNT# PCI_REQ# AD31 AD30 PCI_VCC AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# CORE_GND IDSEL AD23 AD22 AD21 AD20 AD19 PCI_VCC AD18 AD17 AD16 C/BE2# CORE_GND FRAME# CORE_GND IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR C/BE1# PCI_VCC AD15 AD14 AD13 AD12 AD11 AD10 CORE_GND AD9 AD8 C/BE0# AD7 AD6 PCI_VCC AD5 AD4 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 1 156 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 2 155 3 154 4 153 5 152 6 151 7 150 8 149 9 148 10 147 11 146 12 145 13 144 14 143 15 142 16 141 17 140 18 139 19 138 20 137 21 136 22 135 23 134 24 133 2 25 132 26 131 27 130 28 129 29 128 30 127 31 126 32 125 33 124 34 123 35 122 36 121 37 120 38 119 39 118 40 117 41 116 42 115 43 114 44 113 45 112 46 111 47 110 48 109 49 108 50 107 51 106 1 1 1 1 1 52 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 105 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 O Micro, Inc. OZ6933 B_IOWR#/CAD15 B_A9/CAD14 B_IORD#/CAD13 B_A11/CAD12 B_VS1/CVS1 B_OE#/CAD11 B_CE2#/CAD10 B_A10/CAD9 B_D15/CAD8 B_CE1#/CCBE0# B_VPP_VCC B_D14/RFU B_D7/CAD7 B_SOCKET_VCC B_D13/CAD6 B_D6/CAD5 B_D12/CAD4 B_D5/CAD3 B_D11/CAD2 B_D4/CAD1 B_CD1#/CCD1# B_D3/CAD0 CORE_VCC LED_OUT/SKT_ACTIVITY SCLK/A_VCC5# SDATA/B_VCC3# SLATCH/B_VCC_5# CORE_GND SPKR_OUT# AUX_VCC A_CD2#/CCD2# A_WP/CCLKRUN# A_D10/CAD31 A_D2/RFU A_D9/CAD30 A_D1/CAD29 A_D8/CAD28 A_D0/CAD27 A_BVD1/STSCHG G_RST# A_A0/CAD26 A_VPP_VCC A_BVD2/CAUDIO A_A1/CAD25 A_REG#/CCBE3# A_A2/CAD24 A_INPACK#/CREQ# A_A3/CAD23 A_WAIT#/CSERR# A_A4/CAD22 A_RESET/CRESET# A_A5/CAD21 A_VS2/CVS2 A_A6/CAD20 A_A25/CAD19 GND A_A7/CAD18 A_A24/CAD17 SOCKET_VCC A_A12/CCBE2# A_A23/CFRAME# A_A15/CIRDY# A_A22/CTRDY# A_A16/CCLK A_A21/CDEVSEL# A_RDY_IREQ#/CINT# A_A20/CSTOP# A_WE#/CGNT# A_A19/CBLOCK# IRQ3/VCC3# A_A14/CPERR# A_A18/RFU A_A13/CPAR A_A17/CAD16 A_A8/CCBE1# A_IOWR/CAD15 A_A9/CAD14 CORE_VCC A_IORD#/CAD13 A_A11/CAD12 A_VS1/CVS1 A_OE#/CAD11 A_CE2#/CAD10 A_A10/CAD9 IRQ15/RING_OUT A_D15/CAD8 A_CE1#/CCBE0# A_D14/RFU A_D7/CAD7 A_D13/CAD6 A_D6/CAD5 A_D12/CAD4 A_D5/CAD3 A_D11/CAD2 A_D4/CAD1 A_CD1#/CCD1# A_SOCKET_VCC A_D3/CAD0 LOCK# CORE_GND AD0 AD1 AD2 AD3 OZ6933-SF-1.7 Page 4 OZ6933 PIN LIST Bold Text = Normal Default Pin Name PCI Bus Interface Pins Pin Name Description AD[31:0] PCI Bus Address Input/Data: These pins connect to PCI bus signals AD[31:0]. A Bus transaction consists of an address phase followed by one or more data phases. C/BE[3:0]# PCI Bus Command/Byte Enable: The command signaling and byte enables are multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# are interpreted as the bus commands. During the data phase, C/BE[3:0]# are interpreted as byte enables. The byte enables are to be valid for the entirety of each data phase, and they indicate which bytes in the 32-bit data path are to carry meaningful data for the current data phase. Cycle Frame: This input indicates to the OZ6933 that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is de-asserted, the transaction is in its final phases. Initiator Ready: This input indicates the initiating agent’s ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. Target Ready: This output indicates target Agent’s the OZ6933’s ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. Stop: This output indicates the current target is requesting the master to stop the current transaction. Initialization Device Select: This input is used as chip select during configuration read and write transactions. This is a point-to-point signal. IDSEL can be used as a chip select during configuration read and write transactions. Device Select: This output is driven active LOW when the PCI address is recognized as supported, thereby acting as the target for the current PCI cycle. The Target must respond before timeout occurs or the cycle will terminate. Parity Error: The output is driven active LOW when a data parity error is detected during a write phase. FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# PERR# Pin Number TQFP BGA 4-5, 7-12, 16E1, E2, F3, F1, 20, 22-24, 38G5, H6, G3, 43, 45-46, 48G2, H2, H1, J1, 49, 51-56 J2, J3, J6, K1, K2, M5, N2, N1, N3, N6, P1, P3, N5, P6, R2, R3, T1, W4, R6, U5, P7 13, 25, 36, 47 G1, K3, M3, R1 Input Type Power Rail Drive TTL I/O 4 PCI Spec TTL I/O 4 - 27 K6 TTL I/O 4 - 29 L1 TTL I/O 4 - 30 L2 TTL I/O 4 PCI Spec 32 L5 TTL I/O 4 PCI Spec 15 H5 TTL I 4 - 31 L3 TTL I/O 4 PCI Spec 33 L6 - TO 4 PCI Spec OZ6933-SF-1.7 Page 5 OZ6933 Pin Name SERR# PAR PCI_CLK RST# RI_OUT CLKRUN# PME# SKTB_ACTV INTA# Description System Error: This output is driven active LOW to indicate an address parity error. Parity: This pin generates PCI parity and ensures even parity across AD[31:0] and C/BE[3:0]#. During the address phase, PAR is valid after one clock. With data phases, PAR is stable one clock after a write or read transaction. PCI Clock: This input provides timing for all transactions on the PCI bus to and from the OZ6933. All PCI bus signals, except RST#, are sampled and driven on the rising edge of PCI_CLK. This input can be operated at frequencies from 0 to 33MHz. Device Reset: This input is used to initialize all registers and internal logic to their reset states and place most OZ6933 pins in a HIGH-impedance state. Ring Indicate Out: This pin is Ring Indicate when the following occurs while O2 Mode Control B Register (index 2Eh) bit 7 is set to 1: 1) Power Control (Index+02h) bit 7 set to 1 2) Interrupt and General Control (Index+03h) bit 7 set to 1 3) PCI O2Micro Control 2 (Offset: D4h) bit X = 0 PCI Clock Run Request: This signal is used by the central resource to request permission to stop the PCI clock or to slow it down, and the OZ6933 responds accordingly. To enable the CLKRUN# signal, you need to enable ExCA register 3B bit[3:2]. Power Management Event: A power management event is the process by which the OZ6933 can request a change of its power consumption state. Usually, a PME occurs during a request to change from a power saving state to the fully operational state. Socket B Activity: This signal indicates that there is any activity on the socket B read/write access. Refer to PCI Configuration Register 90h. PCI Bus Interrupt A: This output indicates a programmable interrupt request generated from any of a number of card actions. Although there is no specific mapping requirement for connecting interrupt lines from the OZ6933 to the system, a common use is to connect this pin to the system PCI bus INTA# signal. Pin Number Input Type Power Rail Drive - TO 4 PCI Spec M2 TTL I/O 4 PCI Spec 1 E3 TTL I 4 - 207 D1 TTL I 1 - 72 V9 - TO 1 6mA 208 A4 TTL I/O 4 PCI Spec 163 B14 - TO 1 6mA 193 E8 - TO 1 6mA 203 B5 - TO 4 PCI Spec TQFP 34 BGA M1 35 OZ6933-SF-1.7 Page 6 OZ6933 Pin Name INTB# IRQSER/ SOUT#/ IRQ5 IRQ7/SIN#/ B_VPP_PGM GNT# REQ# LOCK# PCI_VCC Pin Number Input Type Power Rail Drive - TO 4 PCI Spec C5 TTL I/O 4 PCI Spec 206 E6 TTL I/O 1 6mA 2 F5 TTL I 4 PCI Spec 3 G6 N/A TO 4 PCI Spec 58 V5 TTL I/O 4 PCI Spec 6, 21, 37, 50 F2, J5, M6, P5 - PWR - - Description PCI Bus Interrupt B: This output indicates a programmable interrupt request generated from any of a number of card actions. Although there is no specific mapping requirement for connecting interrupt lines from the OZ6933 to the system, a common use is to connect this pin to the system PCI bus INTB# signal. IRQSER/SOUT#/IRQ5: In PC/PCI Serial Interrupt Signaling mode, this pin is the serial interrupt output, SOUT#. In PC/Way mode, this pin is the IRQ serializer pin to the interrupt controller. In the parallel ISA mode, this pin is the ISA IRQ5 IRQ7/SIN#/B_VPP_PGM: In PC/PCI Serial Input Signaling mode, this pin is the serial interrupt input, SIN#. In the parallel ISA mode, this pin is the ISA IRQ7. This pin also can be configured as parallel power control pin B_VPP_PGM Grant: This signal indicates that access to the bus has been granted. Request: This signal indicates to the arbiter that the OZ6933 requests use of the bus. PCI LOCK#: This signal is used by a PCI master to perform a locked transaction to a target memory. LOCK# is used to prevent more than one master from using a particular system resource. PCI Bus VCC: These pins must be connected to a 3.3-volt power supply. The PCI bus interface pin outputs listed in this table (Table 2-1) will operate at the voltage applied to these pins, independent of the voltage applied to other OZ6933 pin groups. TQFP 204 BGA F6 205 PCMCIA Sockets Interface Pins Socket A pin number --- Socket B pin number Name1 Description2 -REG#/ CCBE3# Register Access: During PCMCIA memory cycles, this output chooses between attribute and common memory. During I/O cycles for non-DMA transfers, this signal is active (low). During ATA mode, this signal is always inactive. For DMA cycles on the OZ6933 to a DMA-capable card, -REG is inactive during I/O cycles to indicate DACK to the PCMCIA card. CardBus Command Byte Enable: In CardBus mode, this pin is the CCBE3#. A[25:24]/ CAD[19, 17] PCMCIA socket address 25:24 outputs. CardBus Address/Data: CardBus mode, these pins are the CAD bits 19 and 17. PCMCIA socket address 23 output. CardBus Frame: In CardBus mode, this pin is the CFRAME# signal. A23/ CFRAME# Pin Number Socket A Socket B TQFP BGA TQFP BGA 112 N15 188 F9 102, 99 96 U15, W15 U14 OZ6933-SF-1.7 Qty I/O Pwr Drive 1 I/O 2 or 3 CardBus spec. 176, 174 C11, A11 2 I/O 2 or 3 CardBus spec. 172 B12 1 I/O 2 or 3 CardBus spec. Page 7 OZ6933 Name1 A22/ CTRDY# A21/ CDEVSEL# A20/ CSTOP# A19/ CBLOCK# A18/ RFU A17/ CAD16 A16/ CCLK# A15/ CIRDY# A14/ CPERR# A13/ CPAR A12/ CCBE2# A[11:9]/ CAD[12, 9, 14] A8/ CCBE1# A[7:0]/ CAD[18, 2026] D15/ CAD8 D14/ RFU Description2 PCMCIA socket address 22 output. CardBus Target Ready: In CardBus mode, this pin is the CTRDY# signal. PCMCIA socket address 21 output. CardBus Device Select: In CardBus mode, this pin is the CDEVSEL# signal. PCMCIA socket address 20 output. CardBus Stop: In CardBus mode, this pin is the CSTOP# signal. PCMCIA socket address 19 output. CardBus Lock: In CardBus mode, this signal is the CBLOCK# signal used for locked transactions. PCMCIA socket address 18 output. Reserved: In CardBus mode, this pin is reserved for future use. PCMCIA socket address 17 output. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 16. PCMCIA socket address 16 output. CardBus Clock: In CardBus mode, this pin supplies the clock to the inserted card. PCMCIA socket address 15 output. CardBus Initiator Ready: In CardBus mode, this pin is the CIRDY# signal. PCMCIA socket address 14 output. CardBus Parity Error: CardBus mode, this pin is the CPERR# signal. PCMCIA socket address 13 output. CardBus Parity:b In CardBus mode, this pin is the CPAR signal. PCMCIA socket address 12 output. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBE2# signal. PCMCIA socket address 11:9 output. CardBus Address/Data: In CardBus mode, these pin are the CAD bits 12, 9 and 14. PCMCIA socket address 8 output. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBE1# signal. PCMCIA socket address 7:0 outputs. CardBus Address/Data: In CardBus mode, these pins are the CAD bits 18 and 20:26. PCMCIA socket data/0 bit 15. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 8. PCMCIA socket data I/0 bit 14. Reserved: In CardBus mode, this pin is reserved for future use. Pin Number Socket A Socket B TQFP BGA TQFP BGA 94 W14 170 A13 Qty I/O Pwr Drive 1 I/O-PU 2 or 3 CardBus spec. 92 U13 168 B13 1 I/O-PU 2 or 3 CardBus spec. 90 W13 166 C13 1 I/O-PU 2 or 3 CardBus spec. 88 U12 164 A14 1 I/O-PU 2 or 3 CardBus spec. 85 D11 161 C14 1 TO 2 or 3 CardBus spec. 83 U11 158 E14 1 I/O 2 or 3 CardBus spec. 93 V13 169 E12 1 I/O 2 or 3 CardBus spec. 95 P13 171 C12 1 I/O-PU 2 or 3 CardBus spec. 86 V12 162 A15 1 I/O-PU 2 or 3 CardBus spec. 84 R11 159 C15 1 I/O 2 or 3 CardBus spec. 97 V14 173 A12 1 I/O 2 or 3 CardBus spec. 77, 73, 80 V10, U9, W11 153, 149, 155 F14, F18, F15 3 I/O 2 or 3 CardBus spec. 82 V11 157 A16 1 I/O 2 or 3 CardBus spec. 100, 103, 105, 107, 109, 111, 113, 116 71 P14, R14, T19, R17, N14, R19, P18, N17 W9 175, 178, 181, 183, 185, 187, 189, 191 148 B11, F11, E10, F10, B9, E9, A8, B8 8 I/O 2 or 3 CardBus spec. F17 1 I/O 2 or 3 CardBus spec. 69 V8 145 G17 1 I/O 2 or 3 2 mA OZ6933-SF-1.7 Page 8 OZ6933 Name1 Description2 D[13:3]/ CAD[6, 4, 2, 31, 30, 28, 7, 5, 3, 1, 0] PCMCIA socket data I/0 bits 13:3. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 6 4, 2, 31, 30, 28, 7, 5, 3, 1, and 0, respectively. D2/ RFU PCMCIA socket data I/O bit 2. Reserved: In CardBus mode, this pin is reserved for future use. PCMCIA socket data I/O bits 1:0. CardBus Address/Data: In CardBus mode, these pins are the CAD bits 29 and 27, respectively. Output Enable: This output goes active (low) to indicate a memory read from the PCMCIA socket to the OZ6933. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 11. Write Enable: This output goes active (low) to indicate a memory write from the OZ6933 to the PCMCIA socket. CardBus Grant: In CardBus mode, this pin is the CGNT# signal. I/O Read: This output goes active (low) for I/O reads from the socket to the OZ6933. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 13. I/O Write: This output goes active (low) for I/O writes from the OZ6933 to the socket. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 15. Write Protect/ I/O Is 16-Bit: In Memory Card Interface mode, this inputs is interpreted as the status of the write protect switch on the PCMCIA card. In I/O Card Interface mode, this input indicates the size of the I/O data at the current address on the PCMCIA card. CardBus Clock Run: In CardBus mode, this pin is the CCLKRUN# signal, which starts and stops the CardBus CCLK. To enable the CLKRUN# signal, ExCA register 3Bh/7Bh bit[3:2] must be enabled. D[1:0]/ CAD[29,27] -OE/ CAD11 -WE/ CGNT# -IORD/ CAD13 -IOWR/ CAD15 WP/ -IOIS16/ CCLKRUN# Pin Number Socket A Socket B TQFP BGA TQFP BGA 67, 65, P8, 142, H15, 63, V7, 140, H17, 124, W6, 138, H19, 122, L18, 199, B6, 120, M19, 197, A6, 68, 66, M15, 195, C7, 64, 62, U8, 144, G18, 59 W7, 141, H14, U7, 139, H18, P8, U6 137, J14, 135 J17 123 L19 198 F7 Qty I/O Pwr Drive 11 I/O 2 or 3 CardBus spec. 1 I/O 2 or 3 CardBus spec. 121, 119 M18, M17 196, 194 B7, A7 2 I/O 2 or 3 CardBus spec. 75 P9 151 G15 1 I/O 2 or 3 CardBus spec. 89 R12 165 E13 1 TO 2 or 3 CardBus spec. 78 U10 154 E17 1 I/O 2 or 3 CardBus spec. 81 P10 156 D19 1 I/O 2 or 3 CardBus spec. 125 L17 201 A5 1 I/O-PU 2 or 3 CardBus spec. OZ6933-SF-1.7 Page 9 OZ6933 Name1 -INPACK/ CREQ# RDY/ -IREQ/ CINT# -WAIT/ CSERR# CD[2:1]/ CCD[2:1]# -CE2/ CAD10 Description2 Input Acknowledge: The -INPACK function is not applicable in PCI bus environments. However, for compatibility with other Cirrus Logic products, this pin should be connected to the PCMCIA socket’s -INPACK pin. CardBus Request: In CardBus mode, this pin is the CREQ# signal. Ready/Interrupt Request: In Memory Card Interface mode, this input indicates to the OZ6933 that the card is either ready or busy. In I/O Card Interface mode, this input indicates a card interrupt request. CardBus Interrupt: In CardBus mode, this pin is the CINT# signal. This signal is active-low and level-sensitive. Wait: This input indicates a request by the card to the OZ6933 to halt the cycle in progress until this signal is deactivated. CardBus System Error: In CardBus mode, this pin is the CSERR# signal. Card Detect: These inputs indicate to the OZ6933 that a card is in the socket. They are internally pulled high to the voltage of the AuxVCC power pin. CardBus Card Detect: In CardBus mode, these inputs are used with CVS[2:1] to detect presence and type of card. Card Enable pin is driven low by the OZ6933 during card access cycles to control byte/word card access. -CE1 enables even-numbered address bytes, and -CE2 enables odd-numbered address bytes. When configured for 8bit cards, only -CE1 is active and A0 is used to indicate access of odd- or evennumbered bytes. CardBus Address/Data: In CardBus mode, this pin is the CAD bit 10. Pin Number Socket A Socket B TQFP BGA TQFP BGA 110 P17 186 C9 Qty I/O Pwr Drive 1 I-PU 2 or 3 CardBus spec. 91 P12 167 F12 1 I-PU 2 or 3 CardBus spec. 108 R18 184 A9 1 I-PU 2 or 3 CardBus spec. 126, 61 L14, V6 202, 136 C6, J15 2 I-PUSchmitt 1 CardBus spec. 74 R9 150 E19 1 I/O 2 or 3 CardBus spec. -CE1/ CCBE0# Card Enable pin is driven low by the OZ6933 during card access cycles to control byte/word card access. -CE1 enables even-numbered address bytes, and -CE2 enables odd-numbered address bytes. When configured for 8bit cards, only -CE1 is active and A0 is used to indicate access of odd- or evennumbered bytes. CardBus Command/Byte Enable: In CardBus mode, this pin is the CCBEO# signal. 70 W8 147 G14 1 I/O 2 or 3 CardBus spec. RESET/ CRST# Card Reset: This output is low for normal operation and goes high to reset the card. To prevent reset glitches to a card, this signal is high-impedance unless a card is seated in the socket, card power is applied, and the card’s interface signals are enabled. CardBus Reset: In CardBus mode, this pin is the CRST# output. 106 P15 182 C10 1 TO 2 or 3 CardBus spec. OZ6933-SF-1.7 Page 10 OZ6933 Name1 BVD2/ -SPKR/ -LED/ CAUDIO Description2 Battery Voltage Detect 2/Speaker/ LED: In Memory Card Interface mode, this input serves as the BVD2 (battery warning status) input. In I/O Card Interface mode, this input can be configured as a card’s -SPKR binary audio input. For ATA or non-ATA (SFF-68) disk-drive support, this input can also be configured as a drivestatus LED input. CardBus Audio: In CardBus mode, this pin is the CAUDIO input. Pin Number Socket A Socket B TQFP BGA TQFP BGA 114 M14 190 C8 Qty I/O Pwr Drive 1 I-PU 2 or 3 - BVD1/ -STSCHG/ -RI/ CSTSCHG 118 N19 192 F8 1 I-PU 2 or 3 Battery Voltage Detect 1/Status Change/Ring Indicate: In Memory Card Interface mode, this input serves as the BVD1 (battery-dead status) input. In I/O Card Interface mode, this input is the -STSCHG input, which indicates to the OZ6933 that the card’s internal status has changed. If bit 7 of the Interrupt and General Control register is set to `1`, this pin serves as the ring indicate input for wakeup-onring system power management support. CardBus Status Change: In CardBus mode, this pin is the CSTSCHG. This pin can be used to generate PME#. Voltage Sense 2: This pin is used in VS2/ 104 W16 179 A10 1 I/O-PU 1 CB-spec CVS2 conjunction with VS1 to determine the operating voltage of the card. This pin is internally pulled high to the voltage of the AuxVCC power pin under the combined control of the external data write bits and the CD pull up control bits. This pin connects to PCMCIA socket pin 57. CardBus Voltage Sense: In CardBus mode, these pins are the CVS2 pins. Voltage Sense 1: This pin is used in VS1/ 76 W10 152 E18 1 I/O-PU 1 CB-spec CVS1 conjunction with VS2 to determine the operating voltage of the card. This pin is internally pulled high to the voltage of the AuxVCC power pin under the combined control of the external data write bits and the CD pull up control bits. This pin connects to PCMCIA socket pin 43. CardBus Voltage Sense: In CardBus mode, these pins are the CVS1 pins. SOCKET_VCC Connect these pins to the Vcc supply 60, R7, 200, E7, 2, 3 PWR of the socket (pins 17 and 51 of the 198 R13 160, F13, respective PCMCIA socket). These 143 G19 pins can be 0, 3.3, or 5 V, depending on card presence, card type, and system configuration. The socket interface outputs (listed in this table, Table 2-2) will operate at the voltage applied to these pins, independent of the voltage applied to other OZ6933 pin groups. 1 To differentiate the sockets in the pin diagram, all socket- specific pins have either A_ or B_ prefixes to the pin names indicated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. 2 When a socket is configured as an ATA drive interface, socket interface pin functions change. OZ6933-SF-1.7 Page 11 OZ6933 Power Control and General Interface Pins Pin Name SPKR_OUT LED_OUT/ SKTA_ACTV CPWRCLK/ A_VCC5# CPWRDATA/ B_VCC3# CPWRLATC/ B_VCC5# Description Speaker Output: This output can be used as a digital output to a speaker to allow a system to support PC Card fax/modem/voice and audio sound output. This output is enabled by setting the socket’s Misc Control 1 register bit 4 to “1” (for the socket whose speaker signal is to be directed from BVD2/SPKR/-Led to this pin). LED Output/SKTA_ACTV: This output can be used as an LED driver to indicate disk activity when a socket’s BVD2/SPKR/-LED pin has been programmed for LED support. In the O2 Mode(Index 3B/7B bit 5) , this pin indicates the socket A activity. The socket B activity refers to PCI Configuration Register offset 90h (Mux Control register) Card Power Clock: This input is used as a reference clock (10-100 kHz, usually 32 kHz) to control the serial interface of the socket power control chips. A_VCC5#: This active-LOW output controls the 5 -volt supply to the A socket’s VCC pins. The active-LOW level of this output is mutually exclusive with that of A_VCC3#. Card Power Serial Data: This pin serves as output DATA pin when used with the serial interface of Texas Instruments’ TPS2206IDF & Micrel 2564 socket power control chip. B_VCC3#: This active-LOW output controls the 3.3-volt supply to the A socket’s VCC pins. The active-LOW level of this output is mutually exclusive with that of B_VCC5#. Card Power Serial Latch: This pin serves as output LATCH pin when used with the serial interface of Texas Instruments’ TPS2206IDF & Micrel 2564 socket power control chip. B_VCC5#: This active-LOW output controls the 5 -volt supply to the A socket’s VCC pins. The active-LOW level of this output is mutually exclusive with that of B_VCC3#. Pin Number Input Type Power Rail Drive TTL I/O 1 6mA J19 TTL I/O 1 6mA 132 K14 TTL I/O 1 6mA 131 K15 TTL I/O 1 6mA 130 K17 N/A I/O 1 6mA TQFP 128 BGA K19 133 OZ6933-SF-1.7 Page 12 OZ6933 Pin Name Description IRQ3/ A_VCC3# A_VCC3#/IRQ3: This active-LOW output controls of the 3.3-volt supply to the socket’s VCC pins. The active-LOW level of this output is mutually exclusive with of VCC_5#. This mode active only in SktPwr Parallel mode enabled. This pin can be IRQ3 in parallel IRQ mode. VPP_VCC/IRQ9: This active-HIGH output controls the socket A VCC supply to the socket’s VPP1 and VPP2 pins. The active-HIGH level of this output is mutually exclusive with that of VPP_PGM. This mode active only in SktPwr Parallel mode enabled This pin can be configured as IRQ9 in parallel IRQ mode. VPP_VCC/IRQ10: This active-HIGH output controls the socket B VCC supply to the socket’s VPP1 and VPP2 pins. The active-HIGH level of this output is mutually exclusive with that of VPP_PGM. This mode active only in SktPwr Parallel mode enabled. This pin can be configured as IRQ10 in parallel IRQ mode. Global_Reset#: This signal can be connected to either PCI reset or ACPI reset depending on system implementation. If the D3 cold state is implemented, this signal should be connected to the ACPI reset, otherwise, connect to PCI reset. This signal can reset the PME content under the D3 cold state if AUX_VCC is provided IRQ9/ A_VPP_VCC IRQ10/ B_VPP_VCC G_RST# Pin Number Input Type Power Rail Drive N/A TO 1 6mA P19 N/A TO 1 6mA 146 F19 N/A TO 1 6mA 117 N18 TTL I 1 - Input Type Power Rail Drive N/A PWR - - TQFP 87 BGA W12 115 Power, Ground, and Reserved Pins Pin Name Description AUX_VCC This pin must be connected to the system’s 3.3-volt supply. This pin provides power to the core circuitry of the OZ6933. It must be connected to a 3.3 power supply. All OZ6933 ground pins must be connected to system ground. CORE_VCC GND Pin Number TQFP 127 BGA L15 180, 134, 79 B10, J18, R10 N/A PWR - - 14, 26, 28, 44, 57, 101, 129, 177 H3, K5, K5, P2, W5, V15, K18, E11 N/A GND - - Legend I/O Type I I-PU O OD TO TO-PU OD-PU PW Description Input Pin Input pin with internal pull-up Output Open-drain Tri-state output Tri-state output with internal pull-up Open-drain output with internal pull-up Power pin Power Rail 1 2 3 4 5 OZ6933-SF-1.7 Source of Output’s Power AUX_VCC: outputs powered from AUX_VCC A_SLOT_VCC: outputs powered from the socket A B_SLOT_VCC: outputs powered from the socket B PCI_VCC: outputs powered from PCI bus power supply CORE_VCC: outputs powered from the CORE_VCC Page 13 OZ6933 PACKAGE SPECIFICATIONS D D1 156 105 157 104 E E1 OZ6933 208-PIN TQFP O2MICRO, INC. F F 208 53 52 SEATING PLANE A1 A b A2 e 1 Symbol INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX A - - 0.063 - - 1.60 A1 0.002 - 0.006 0.05 - 0.15 A2 0.053 0.055 0.057 1.35 1.40 1.45 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 0.09 - 0.20 - 0.008 D 1.181 30.00 BSC. D1 1.102 28.00 BSC. E 1.181 30.00 BSC. E1 1.102 28.00 BSC. e 0.020 BSC. 0.50 BSC. L 0.018 0.024 0.030 L1 θ 0.45 0.039 REF 0° 3.5° 0.60 0.25 GAGE PLANE B SEC: F-F 0° 3.5° θ L 0.75 L1 1.00 REF 7° B 7° OZ6933-SF-1.7 Page 14 OZ6933 208 PIN – BGA NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 3. "N" REPRESENTS THE MAXIMUM NUMBER OF SOLDER BALLS FOR MATRIX SIZE M1 AND M2. 4. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER AFTER REFLOW AND PARALLEL TO PRIMARY DATUM Z, THE ORIGINAL SOLDER BALL DIAMETER IS 0.45 mm. 5. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 6. A1 CORNER MUST BE IDENTIFIED BY INK MARK, METALLIZED MARKINGS, IDENTATION OR OTHER FEATURE OF PACKAGE BODY, LID OR INTEGRAL HEATSLUG, ON THE TOP SURFACE OF THE PACKAGE. 7. SOLDER BALL DEPOPULATION IS ALLOWED. DEPOPULATION IS THE OMISSION OF BALLS FROM A FULL MATRIX (M1 OR M2). 8. BALL PAD A1 CORNER INDICATOR (NC) SOLDER BALL OZ6933-SF-1.7 Page 15