HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 D Compliant With PCI Hot-Plug Specification, D D D D D D Revision 1.0 Supports up to Four Independently Controlled Hot-Plug Slots Provides Register Accessing Through Both Generic Parallel Bus and Two-Wire Serial Interface Provides Interrupt and Event Status/Enable State Compliant With ACPI Specification 1.0 Provides an Automatic Bus Connection Sequencing Feature Supports 66-MHz PCI Clock Frequency Features Two Attention Indicators With Variable LED Blinking Rates per Slot D Provides an Easy Scheme to Cascade the HPC3130A for Compact PCI Applications D Provides Card Detection Mechanism D D D D Independent of PCI Present Signals for Advanced Card Protection Provides Path to Guarantee Idle State During PCI Bus Connections Fabricated in Advanced Low-Power CMOS Process Features a CBT Switch† Control Feature for REQ64 Implementation Package Options: – 120-pin QFP Package – 128-pin LQFP Package – 144-pin LQFP Package Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Assignments (120-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Assignments (128-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Assignments (144-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal Name/Pin Number Sort Table (120-Pin) . . . . . . . . . . . . . . . . . 6 Signal Name/Pin Number Sort Table (128-Pin) . . . . . . . . . . . . . . . . . 8 Signal Name/Pin Number Sort Table (144-Pin) . . . . . . . . . . . . . . . . 10 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 HPC3130A Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 64-Bit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 66 MHz PCI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (120-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (128-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data (144-Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 32 33 34 34 35 36 37 38 39 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Contact Texas Instrument’s Bus Interface product group for information related to CBT switches. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 description The Texas Instruments HPC3130A is a peripheral component interconnect (PCI) hot-plug controller, compliant with PCI Hot-Plug Specification, Revision 1.0. This device supports hot insertion/removal of up to four hot-plug slots on a PCI bus, provides a 64-bit data path in any of the four hot-plug slots, and supports 66-MHz systems for two slots. The primary function of the HPC3130A is to allow noninterfering hot-plug slot connection/disconnection with the other PCI devices on the bus. The HPC3130A provides automatic bus connection sequencing and supports a protocol for connection during bus idle conditions. It also supports an interrupt pin to report hot-plug slot events. The interrupt event status and enable state are compliant with the Advanced Configuration and Power Interface (ACPI) Specification. Internal registers may be accessed through either a two-signal serial interface or a generic parallel bus. The serial interface slave decoding circuit supports up to eight different controllers or other serial bus devices with the same system base. Decoding through the parallel interface supports multiple controllers with external chip-select logic. Two double-words of configuration and control registers are provided per slot. As a result, the HPC3130A decodes an address range of 32 bytes. An advanced complementary metal-oxide semiconductor (CMOS) process provides low system power consumption while operating at PCI clock rates up to 66 MHz. functional block diagram A simplified block diagram of the HPC3130A is provided below. The block diagram illustrates the HPC3130A functionality on a per slot basis. The SMODE chip input, not shown, is used for terminal multiplexing of the serial and parallel bus slave interfaces. SYSTEM INTERFACE CS RD WR DATA 7–0 A 4–0 SDA SCL ADD 6–0 SYSM66EN INTR PRST IDLEREQ IDLEGNT FRAME IRDY SREQ SGNT SLOT INTERFACE Parallel Bus Slave Interface Serial Bus Slave I/F Control and Status Registers Switch Timing Slot Power I/F PWRON/OFF PWRFAULT PWRGOOD Card Detection PRSNT1 PRSNT2 DETECT M66EN CBT-Switch Control and Slot Reset Attention Indicators PCLK 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 BUSON REQ64ON REQ64ON CLKON SLOTRST SLOTREQ64 ATTN0 ATTN1 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 terminal assignments (120-terminal package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 30 RSVD RSVD DETECT1[1] DETECT0[1] M66EN[1] VCC ATTN1[1] ATTN0[1] CLKON[1] BUSON[1] REQ64ON[1] GND REQ64ON[1] SLOTRST[1] PRSNT2[1] PRSNT1[1] VCC5V PWRGOOD[1] PWRFAULT[1] PWRON/OFF[1] DETECT1[0] DETECT0[0] GND M66EN[0] ATTN1[0] ATTN0[0] CLKON[0] BUSON[0] RSVD RSVD RSVD RSVD RSVD CS DATA7 VCC DATA6 DATA5 DATA4 DATA3 GND DATA2 DATA1/ADD6 DATA0/ADD5 A4/ADD4 VCC 5V A3/ADD3 A2/ADD2 A1/ADD1 A0/ADD0 GND PWRON/OFF[0] PWRFAULT[0] PWRGOOD[0] PRSNT1[0] VCC PRSNT2[0] SLOTRST[0] REQ64ON[0] REQ64ON[0] ATTN0[3] ATTN1[3] M66EN[3] DETECT0[3] DETECT1[3] VCC SLOTREQ64[3] SLOTREQ64[2] SLOTREQ64[1] SLOTREQ64[0] GND SREQ SGNT PRST VCC5V PCLK GND IDLEREQ IDLEGNT FRAME IRDY VCCP INTR INTR SYSM66EN GND SMODE VCC5V RD/SDA WR/SCL 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 CLKON[3] BUSON[3] REQ64ON[3] GND REQ64ON[3] SLOTRST[3] PRSNT2[3] PRSNT1[3] GND PWRGOOD[3] PWRFAULT[3] PWRON/OFF[3] DETECT1[2] VCC 5V DETECT0[2] M66EN[2] ATTN1[2] ATTN0[2] CLKON[2] GND BUSON[2] REQ640N[2] REQ64ON[2] SLOTRST[2] PRSNT2[2] VCC PRSNT1[2] PWRGOOD[2] PWRFAULT[2] PWRON/OFF[2] PBM QUAD FLAT PACKAGE TOP VIEW POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 terminal assignments (128-terminal package) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 30 31 32 NC RSVD RSVD RSVD CS DATA7 VCC DATA6 DATA5 DATA4 DATA3 GND DATA2 DATA1/ADD6 DATA0/ADD5 A4/ADD4 VCC 5V A3/ADD3 A2/ADD2 A1/ADD1 A0/ADD0 GND PWRON/OFF[0] PWRFAULT[0] PWRGOOD[0] PRSNT1[0] VCC PRSNT2[0] SLOTRS[0] REQ64ON[0] REQ64ON[0] NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC ATTN0[3] ATTN1[3] M66EN[3] DETECT0[3] DETECT1[3] VCC SLOTREQ64[3] SLOTREQ64[2] SLOTREQ64[1] SLOTREQ64[0] GND SREQ SGNT PRST VCC5V PCLK GND IDLEREQ IDLEGNT FRAME IRDY VCCP INTR INTR SYSM66EN GND SMODE VCC5V RD/SDA WR/SCL NC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 NC CLKON[3] BUSON[3] REQ64ON[3] GND REQ64ON[3] SLOTRST[3] PRSNT2[3] PRSNT1[3] GND PWRGOOD[3] PWRFAULT[3] PWRON/OFF[3] DETECT1[2] VCC 5V DETECT0[2] M66EN[2] ATTN1[2] ATTN0[2] CLKON[2] GND BUSON[2] REQ64ON[2] REQ64ON[2] SLOTRST[2] PRSNT2[2] VCC PRSNT1[2] PWRGOOD[2] PWRFAULT[2] PWRON/OFF[2] NC PBK LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NC RSVD RSVD DETECT1[1] DETECT0[1] M66EN[1] VCC ATTN1[1] ATTN0[1] CLKON[1] BUSON[1] REQ64ON[1] GND REQ64ON[1] SLOTRST[1] PRSNT2[1] PRSNT1[1] VCC5V PWRGOOD[1] PWRFAULT[1] PWRON/OFF[1] DETECT1[0] DETECT0[0] GND M66EN[0] ATTN1[0] ATTN0[0] CLKON[0] BUSON[0] RSVD RSVD NC HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 terminal assignments (144-terminal package) CLKON[0] NC BUSON[0] NC RSVD NC RSVD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 RSVD NC RSVD NC DETECT1[1] NC DETECT0[1] M66EN[1] VCC ATTN1[1] ATTN0[1] CLKON[1] BUSON[1] REQ64ON[1] GND REQ64ON[1] SLOTRST[1] PRSNT2[1] PRSNT1[1] V CC5V PWRGOOD[1] PWRFAULT[1] PWRON/OFF[1] DETECT1[0] DETECT0[0] GND M66EN[0] ATTN1[0] ATTN0[0] PGE LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 143 144 REQ64ON[0] NC REQ64ON[0] NC SLOTRST[0] NC PRSNT2[0] VCC PRSNT1[0] PWRGOOD[0] PWRFAULT[0] PWRON/OFF[0] GND A0/ADD0 A1/ADD1 A2/ADD2 A3/ADD3 VCC5V A4/ADD4 DATA0/ADD5 DATA1/ADD6 DATA2 GND DATA3 DATA4 DATA5 DATA6 VCC DATA7 CS NC RSVD NC RSVD NC RSVD ATTN0[3] NC ATTN1[3] NC M66EN[3] NC DETECT0[3] DETECT1[3] VCC SLOTREQ64[3] SLOTREQ64[2] SLOTREQ64[1] SLOTREQ64[0] GND SREQ SGNT PRST VCC5V PCLK GND IDLEREQ IDLEGNT FRAME IRDY V CCP INTR INTR SYSM66EN GND SMODE NC VCC5V NC RD/SDA NC WR/SCL PWRON/OFF[2] NC PWRFAULT[2] NC PWRGOOD[2] NC PRSNT1[2] VCC PRSNT2[2] SLOTRST[2] REQ64ON[2] REQ64ON[2] BUSON[2] GND CLKON[2] ATTN0[2] ATTN1[2] M66EN[2] DETECT0[2] VCC5V DETECT1[2] PWRON/OFF[3] PWRFAULT[3] PWRGOOD[3] GND PRSNT1[3] PRSNT2[3] SLOTRST[3] REQ64ON[3] GND NC REQ64ON[3] NC BUSON[3] NC CLKON[3] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal name Table 1. Signals Sorted Alphabetically by Terminal Name (120-Terminal Package) 6 TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. A0/ADD0 50 GND A1/ADD1 49 GND 17 RD/SDA 29 26 REQ64ON[0] A2/ADD2 48 59 GND 41 REQ64ON[1] A3/ADD3 78 47 GND 51 REQ64ON[2] 98 A4/ADD4 45 GND 68 REQ64ON[3] 116 ATTN0[0] 65 GND 79 REQ64ON[0] 60 ATTN0[1] 83 GND 101 REQ64ON[1] 80 ATTN0[2] 103 GND 112 REQ64ON[2] 99 ATTN0[3] 1 GND 117 REQ64ON[3] 118 ATTN1[0] 66 IDLEGNT 19 RSVD 31 ATTN1[1] 84 IDLEREQ 18 RSVD 32 ATTN1[2] 104 INTR 24 RSVD 33 ATTN1[3] 2 INTR 23 RSVD 61 BUSON[0] 63 IRDY 21 RSVD 62 BUSON[1] 81 M66EN[0] 67 RSVD 89 BUSON[2] 100 M66EN[1] 86 RSVD 90 BUSON[3] 119 M66EN[2] 105 SGNT 13 CLKON[0] 64 M66EN[3] 3 SLOTREQ64[0] 10 CLKON[1] 82 PCLK 16 SLOTREQ64[1] 9 CLKON[2] 102 PRSNT1[0] 55 SLOTREQ64[2] 8 CLKON[3] 120 PRSNT1[1] 75 SLOTREQ64[3] 7 CS 34 PRSNT1[2] 94 SLOTRST[0] 58 DATA0/ADD5 44 PRSNT1[3] 113 SLOTRST[1] 77 DATA1/ADD6 43 PRSNT2[0] 57 SLOTRST[2] 97 DATA2 42 PRSNT2[1] 76 SLOTRST[3] 115 DATA3 40 PRSNT2[2] 96 SMODE 27 DATA4 39 PRSNT2[3] 114 SREQ 12 DATA5 38 PRST 14 SYSM66EN 25 DATA6 37 PWRFAULT[0] 53 DATA7 35 PWRFAULT[1] 72 VCC VCC 36 DETECT0[0] 69 PWRFAULT[2] 92 DETECT0[1] 87 PWRFAULT[3] 110 DETECT0[2] 106 PWRGOOD[0] 54 DETECT0[3] 4 PWRGOOD[1] 73 DETECT1[0] 70 PWRGOOD[2] 93 DETECT1[1] 88 PWRGOOD[3] 111 DETECT1[2] 108 PWRON/OFF[0] 52 DETECT1[3] 5 PWRON/OFF[1] 71 FRAME 20 PWRON/OFF[2] 91 GND 11 PWRON/OFF[3] 109 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 VCC VCC 56 VCC VCC5V 95 VCC5V VCC5V 28 VCC5V VCC5V 74 VCCP WR/SCL 85 15 46 107 22 30 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal number Table 2. Signals Sorted Numerically by Terminal Number (120-Terminal Package) NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 ATTN0[3] 2 ATTN1[3] 41 GND 81 BUSON[1] 42 DATA2 82 3 CLKON[1] M66EN[3] 43 DATA1/ADD6 83 ATTN0[1] 4 DETECT0[3] 44 DATA0/ADD5 84 ATTN1[1] 5 DETECT1[3] 45 A4/ADD4 85 6 46 VCC M66EN[1] 47 VCC5V A3/ADD3 86 7 VCC SLOTREQ64[3] 87 DETECT0[1] 8 SLOTREQ64[2] 48 A2/ADD2 88 DETECT1[1] 9 SLOTREQ64[1] 49 A1/ADD1 89 RSVD 10 SLOTREQ64[0] 50 A0/ADD0 90 RSVD PWRON/OFF[2] 11 GND 51 GND 91 12 SREQ 52 PWRON/OFF[0] 92 PWRFAULT[2] 13 SGNT 53 PWRFAULT[0] 93 PWRGOOD[2] 14 PRST 54 PWRGOOD[0] 94 PRSNT1[2] 15 VCC5V PCLK 55 PRSNT1[0] 95 16 56 96 VCC PRSNT2[2] 17 GND 57 VCC PRSNT2[0] 97 SLOTRST[2] 18 IDLEREQ 58 SLOTRST[0] 98 REQ64ON[2] 19 IDLEGNT 59 REQ64ON[0] 99 REQ64ON[2] 20 FRAME 60 REQ64ON[0] 100 BUSON[2] 21 IRDY 61 RSVD 101 GND 22 62 RSVD 102 CLKON[2] 23 VCCP INTR 63 BUSON[0] 103 ATTN0[2] 24 INTR 64 CLKON[0] 104 ATTN1[2] 25 SYSM66EN 65 ATTN0[0] 105 M66EN[2] 26 GND 66 ATTN1[0] 106 DETECT0[2] 27 SMODE 67 M66EN[0] 107 28 68 GND 108 29 VCC5V RD/SDA VCC5V DETECT1[2] 69 DETECT0[0] 109 PWRON/OFF[3] 30 WR/SCL 70 DETECT1[0] 110 PWRFAULT[3] 31 RSVD 71 PWRON/OFF[1] 111 PWRGOOD[3] 32 RSVD 72 PWRFAULT[1] 112 GND 33 RSVD 73 PWRGOOD[1] 113 PRSNT1[3] 34 CS 74 114 PRSNT2[3] 35 DATA7 75 VCC5V PRSNT1[1] 115 SLOTRST[3] 36 76 PRSNT2[1] 116 REQ64ON[3] 37 VCC DATA6 77 SLOTRST[1] 117 GND 38 DATA5 78 REQ64ON[1] 118 REQ64ON[3] 39 DATA4 79 GND 119 BUSON[3] 40 DATA3 80 REQ64ON[1] 120 CLKON[3] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal name Table 3. Signals Sorted Alphabetically by Terminal Name (128-Terminal Package) 8 TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. A0/ADD0 53 DETECT0[2] 113 A1/ADD1 52 DETECT0[3] 5 NC 97 REQ64ON[3] 125 NC 128 RSVD A2/ADD2 51 DETECT1[0] 75 34 PCLK 17 RSVD 35 A3/ADD3 50 DETECT1[1] A4/ADD4 48 DETECT1[2] 93 PRSNT1[0] 58 RSVD 36 115 PRSNT1[1] 80 RSVD 66 ATTN0[0] 70 DETECT1[3] ATTN0[1] 88 FRAME 6 PRSNT1[2] 101 RSVD 67 21 PRSNT1[3] 120 RSVD ATTN0[2] 110 GND 94 12 PRSNT2[0] 60 RSVD 95 ATTN0[3] 2 ATTN1[0] 71 GND 18 PRSNT2[1] 81 SGNT 14 GND 27 PRSNT2[2] 103 SLOTREQ64[0] 11 ATTN1[1] ATTN1[2] 89 GND 44 PRSNT2[3] 121 SLOTREQ64[1] 10 111 GND 54 PRST 15 SLOTREQ64[2] ATTN1[3] 9 3 GND 73 PWRFAULT[0] 56 SLOTREQ64[3] 8 BUSON[0] 68 GND 84 PWRFAULT[1] 77 SLOTRST[0] 61 BUSON[1] 86 GND 108 PWRFAULT[2] 99 SLOTRST[1] 82 BUSON[2] 107 GND 119 PWRFAULT[3] 117 SLOTRST[2] 104 BUSON[3] 126 GND 124 PWRGOOD[0] 57 SLOTRST[3] 122 CLKON[0] 69 IDLEGNT 20 PWRGOOD[1] 78 SMODE 28 CLKON[1] 87 IDLEREQ 19 PWRGOOD[2] 100 SREQ 13 CLKON[2] 109 INTR 25 PWRGOOD[3] 118 SYSM66EN 26 CLKON[3] 127 INTR 24 PWRON/OFF[0] 55 VCC VCC 7 CS 37 IRDY 22 PWRON/OFF[1] 76 DATA0/ADD5 47 M66EN[0] 72 PWRON/OFF[2] 98 DATA1/ADD6 46 M66EN[1] 91 PWRON/OFF[3] 116 DATA2 45 M66EN[2] 112 RD/SDA 30 DATA3 43 M66EN[3] 4 REQ64ON[0] 62 DATA4 42 NC 1 REQ64ON[1] 83 DATA5 41 NC 32 REQ64ON[2] 105 DATA6 40 NC 33 REQ64ON[3] 123 DATA7 38 NC 64 REQ64ON[0] 63 DETECT0[0] 74 NC 65 REQ64ON[1] DETECT0[1] 92 NC 96 REQ64ON[2] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 VCC VCC 59 VCC VCC5V 102 VCC5V VCC5V 29 90 16 49 114 85 VCC5V VCC5V VCCP 79 106 WR/SCL 31 23 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal number Table 4. Signals Sorted Numerically by Terminal Number (128-Terminal Package) NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 NC 33 NC 65 NC 97 NC 2 ATTN0[3] 34 RSVD 66 RSVD 98 PWRON/OFF[2] 3 ATTN1[3] 35 RSVD 67 RSVD 99 PWRFAULT[2] 4 M66EN[3] 36 RSVD 68 BUSON[0] 100 PWRGOOD[2] 5 DETECT0[3] 37 CS 69 CLKON[0] 101 PRSNT1[2] 6 DETECT1[3] 38 DATA7 70 ATTN0[0] 102 7 VCC SLOTREQ64[3] 39 71 ATTN1[0] 103 VCC PRSNT2[2] 40 VCC DATA6 72 M66EN[0] 104 SLOTRST[2] 8 9 SLOTREQ64[2 41 DATA5 73 GND 105 REQ64ON[2] 10 SLOTREQ64[1] 42 DATA4 74 DETECT0[0] 106 REQ64ON[2] BUSON[2] 11 SLOTREQ64[0] 43 DATA3 75 DETECT1[0] 107 12 GND 44 GND 76 PWRON/OFF[1] 108 GND 13 SREQ 45 DATA2 77 PWRFAULT[1] 109 CLKON[2] 14 SGNT 46 DATA1/ADD6 78 PWRGOOD[1] 110 ATTN0[2] 15 PRST 47 DATA0/ADD5 79 111 ATTN1[2] 16 48 A4/ADD4 80 112 M66EN[2] 17 VCC5V PCLK VCC5V PRSNT1[1] 49 81 PRSNT2[1] 113 DETECT0[2] 18 GND 50 VCC5V A3/ADD3 82 SLOTRST[1] 114 19 IDLEREQ 51 A2/ADD2 83 REQ64ON[1] 115 VCC5V DETECT1[2] 20 IDLEGNT 52 A1/ADD1 84 GND 116 PWRON/OFF[3] 21 FRAME 53 A0/ADD0 85 REQ64ON[1] 117 PWRFAULT[3] 22 IRDY 54 GND 86 BUSON[1] 118 PWRGOOD[3] 23 55 PWRON/OFF[0] 87 CLKON[1] 119 GND 24 VCCP INTR 56 PWRFAULT[0] 88 ATTN0[1] 120 PRSNT1[3] 25 INTR 57 PWRGOOD[0] 89 ATTN1[1] 121 PRSNT2[3 26 SYSM66EN 58 PRSNT1[0] 90 122 SLOTRST[3] 27 GND 59 91 123 REQ64ON[3] 28 SMODE 60 VCC PRSNT2[0] VCC M66EN[1] 92 DETECT0[1] 124 GND 29 VCC5V RD/SDA 61 SLOTRST[0] 93 DETECT1[1] 125 REQ64ON[3] 30 62 REQ64ON[0] 94 RSVD 126 BUSON[3] 31 WR/SCL 63 REQ64ON[0] 95 RSVD 127 CLKON[3] 32 NC 64 NC 96 NC 128 NC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal name Table 5. Signals Sorted Alphabetically by Terminal Name (144-Terminal Package) 10 TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. A0/ADD0 59 DETECT1[2] 129 A1/ADD1 58 DETECT1[3] 8 NC 78 REQ64ON[3] 137 NC 103 REQ64ON[0] A2/ADD2 57 FRAME 72 23 NC 105 REQ64ON[1] 95 A3/ADD3 56 A4/ADD4 54 GND 14 NC 107 REQ64ON[2] 120 GND 20 NC 110 REQ64ON[3] 140 ATTN0[0] ATTN0[1] 80 GND 29 NC 112 RSVD 37 98 GND 50 NC 114 RSVD ATTN0[2] 39 124 GND 60 NC 139 RSVD 41 ATTN0[3] 1 GND 83 NC 141 RSVD 73 ATTN1[0] 81 GND 94 NC 143 RSVD 75 ATTN1[1] 99 GND 122 PCLK 19 RSVD 106 ATTN1[2] 125 GND 133 PRSNT1[0] 64 RSVD 108 ATTN1[3] 3 GND 138 PRSNT1[1] 90 SGNT 16 BUSON[0] 77 IDLEGNT 22 PRSNT1[2] 115 SLOTREQ64[0] 13 BUSON[1] 96 IDLEREQ 21 PRSNT1[3] 134 SLOTREQ64[1] 12 BUSON[2] 121 INTR 27 PRSNT2[0] 66 SLOTREQ64[2] 11 BUSON[3] 142 INTR 26 PRSNT2[1] 91 SLOTREQ64[3] 10 CLKON[0] 79 IRDY 24 PRSNT2[2] 117 SLOTRST[0] 68 CLKON[1] 97 M66EN[0] 82 PRSNT2[3] 135 SLOTRST[1] 92 CLKON[2] 123 M66EN[1] 101 PRST 17 SLOTRST[2] 118 CLKON[3] 144 M66EN[2] 126 PWRFAULT[0] 62 SLOTRST[3] 136 CS 43 M66EN[3] 5 PWRFAULT[1] 87 SMODE 30 DATA0/ADD5 53 NC 2 PWRFAULT[2] 111 SREQ 15 DATA1/ADD6 52 NC 4 PWRFAULT[3] 131 SYSM66EN 28 DATA2 51 NC 6 PWRGOOD[0] 63 DATA3 49 NC 31 PWRGOOD[1] 88 VCC VCC 45 DATA4 48 NC 33 PWRGOOD[2] 113 DATA5 47 NC 35 PWRGOOD[3] 132 DATA6 46 NC 38 PWRON/OFF[0] 61 DATA7 44 NC 40 PWRON/OFF[1] 86 DETECT0[0] 84 NC 42 PWRON/OFF[2] 109 DETECT0[1] 102 NC 67 PWRON/OFF[3] 130 DETECT0[2] 127 NC 69 RD/SDA 34 DETECT0[3] 7 NC 71 REQ64ON[0] 70 DETECT1[0] 85 NC 74 REQ64ON[1] 93 DETECT1[1] 104 NC 76 REQ64ON[2] 119 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC VCC VCC 9 65 100 116 VCC5V VCC5V 18 VCC5V VCC5V VCC5V 55 VCCP WR/SCL 32 89 128 25 36 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 signal names by terminal number Table 6. Signals Sorted Numerically by Terminal Number (144-Terminal Package) NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME 1 ATTN0[3] 37 RSVD 73 RSVD 109 PWRON/OFF[2] 2 NC 38 NC 74 NC 110 NC 3 ATTN1[3] 39 RSVD 75 RSVD 111 PWRFAULT[2] 4 NC 40 NC 76 NC 112 NC 5 M66EN[3] 41 RSVD 77 BUSON[0] 113 PWRGOOD[2] 6 NC 42 NC 78 NC 114 NC 7 DETECT0[3] 43 CS 79 CLKON[0] 115 PRSNT1[2] 8 DETECT1[3] 44 DATA7 80 ATTN0[0] 116 9 45 ATTN1[0] 117 46 VCC DATA6 81 10 VCC SLOTREQ64[3] VCC PRSNT2[2] 82 M66EN[0] 118 SLOTRST[2] 11 SLOTREQ64[2] 47 DATA5 83 GND 119 REQ64ON[2] 12 SLOTREQ64[1] 48 DATA4 84 DETECT0[0] 120 REQ64ON[2] 13 SLOTREQ64[0] 49 DATA3 85 DETECT1[0] 121 BUSON[2] 14 GND 50 GND 86 PWRON/OFF[1] 122 GND 15 SREQ 51 DATA2 87 PWRFAULT[1] 123 CLKON[2] 16 SGNT 52 DATA1/ADD6 88 PWRGOOD[1] 124 ATTN0[2] 17 PRST 53 DATA0/ADD5 89 125 ATTN1[2] 18 54 A4/ADD4 90 126 M66EN[2] 19 VCC5V PCLK VCC5V PRSNT1[1] 55 PRSNT2[1] 127 DETECT0[2] GND 56 VCC5V A3/ADD3 91 20 92 SLOTRST[1] 128 21 IDLEREQ 57 A2/ADD2 93 REQ64ON[1] 129 VCC5V DETECT1[2] 22 IDLEGNT 58 A1/ADD1 94 GND 130 PWRON/OFF[3] 23 FRAME 59 A0/ADD0 95 REQ64ON[1] 131 PWRFAULT[3] PWRGOOD[3] 24 IRDY 60 GND 96 BUSON[1] 132 25 VCCP INTR 61 PWRON/OFF[0] 97 CLKON[1] 133 GND 62 PWRFAULT[0] 98 ATTN0[1] 134 PRSNT1[3] 27 INTR 63 PWRGOOD[0] 99 ATTN1[1] 135 PRSNT2[3] 28 SYSM66EN 64 PRSNT1[0] 100 136 SLOTRST[3] 29 GND 65 101 137 REQ64ON[3] 30 SMODE 66 VCC PRSNT2[0] VCC M66EN[1] 102 DETECT0[1] 138 GND 31 NC 67 NC 103 NC 139 NC 32 VCC5V NC 68 SLOTRST[0] 104 DETECT1[1] 140 REQ64ON[3] 33 69 NC 105 NC 141 NC 34 RD/SDA 70 REQ64ON[0] 106 RSVD 142 BUSON[3] 35 NC 71 NC 107 NC 143 NC 36 WR/SCL 72 REQ64ON[0] 108 RSVD 144 CLKON[3] 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 Terminal Functions This section describes the HPC3130A terminal functions. The terminals are grouped in tables by function. power supply terminal functions TERMINAL NO. 120 NO. 128 NO. 144 I/O 11, 17, 26, 41, 51, 68, 79, 101, 112, 117 12, 18, 27, 44, 54, 73, 84, 108, 119, 124 14, 20, 29, 50, 60, 83, 94, 122, 133, 138 I Device ground terminals NAME GND FUNCTION VCC VCC5V 6, 36, 56, 85, 95 7, 39, 59, 90, 102 9, 45, 65, 100, 116 I 3.3-V power supply 15, 28, 46, 74, 107 16, 29, 49, 79, 114 18, 32, 55, 89, 128 I 5-V clamp-rail voltage supply VCCP 22 23 25 I Clamp rail voltage for PCI signaling (5V or 3.3V) control bus interface TERMINAL NAME A2/ADD2 A1/ADD1 A0/ADD0 NO. 120 NO. 128 NO. 144 48 49 50 51 52 53 57 58 59 I/O FUNCTION I Parallel bus address. These terminals are address inputs in generic parallel bus cycles and are only used when the SMODE is input low. These lower address terminals select one of the eight registers for read/write access. Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A when the SMODE is input high. A4/ADD4 A3/ADD3 45 47 48 50 54 56 I CS 34 37 43 I Serial bus address select. These terminals indicate the full serial bus address of the HPC3130A when the SMODE is input high. DATA1/ADD6 DATA0/ADD5 43 44 46 47 52 53 I/O DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 35 37 38 39 40 42 38 40 41 42 43 45 44 46 47 48 49 51 I/O RD/SDA WR/SCL 12 29 30 30 31 34 36 Parallel bus address. These terminals are address inputs in generic parallel bus cycles, and are only used when SMODE is input low. These upper address terminals select one of four hot-plug slots supported by the HPC3130A. Chip selection. This active low input selects the HPC3130A chip as addressed in the current generic parallel bus cycle. This chip input is only valid if the SMODE is input low. Multiple HPC3130A chips may exist in a system with external logic driving this signal. Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the SMODE is input low. The data path is used during both read and write transactions to internal registers when the parallel control bus interface is implemented. Serial bus address selection. These terminals indicate the full serial bus address of the HPC3130A when the SMODE is input high. I/O I Parallel bus data. This bus is the data bus in generic parallel bus cycles and is selected when the SMODE is input low. The data path is used during both read and write transactions to internal registers when the parallel control bus interface is implemented. Read selection. This terminal indicates a register read cycle when the SMODE input is low and the CS terminal input is asserted. This is used to read an internal HPC3130A register. Serial bus data. This terminal signals the serial bus data when the SMODE input is high. It is used during internal register read and write transactions. Write selection. This terminal indicates a register write cycle when the SMODE input is low and the CS terminal input is asserted. This input is used to write to an internal HPC3130A register. Serial bus clock. This terminal inputs serial bus clock in when the SMODE input is high. It is used during internal register read and write transactions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 Terminal Functions (Continued) system interface TERMINAL NO. 120 NO. 128 NO. 144 I/O FUNCTION FRAME 20 21 23 I Frame. This input and the IRDY input indicate that the PCI bus is idle. When the HPC3130A senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot can be connected to the PCI bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented. IDLEGNT 19 20 22 I Idle grant. This input indicates when the PCI bus is idled by the HOST-PCI bridge after a request is made by IDLEREQ. The protocol is identical to PCI request/grant. This input must be wired to a valid logic level if the bus idling procedure is not implemented. IDLEREQ 18 19 21 O Idle request. This output is driven to request the HOST-PCI bridge to idle the PCI bus before connecting a hot-plug slot. The protocol is identical to PCI request/grant. A pullup resistor must be implemented on this terminal if the bus idling procedure is not implemented. O System interrupt. This output provides a system interrupt. The HPC3130A can be programmed to assert this interrupt under various conditions, which may be serviced by the hot-plug service. Furthermore, the event status/enable state is compliant with the ACPI Specification and, as a result, supports ACPI control methods for switching the HPC3130A. NAME INTR 24 25 27 INTR 23 24 26 O System interrupt. This open drain output provides a system interrupt. The HPC3130A can be programmed to assert this interrupt under various conditions, which may be serviced by the hot-plug. Furthermore, the event status/enable state is compliant with the ACPI Specification and, as a result, supports ACPI control methods for switching the HPC3130A. IRDY 21 22 24 I Initiator ready. This and the FRAME input indicate that the PCI bus is idle. When the HPC3130A senses the PCI bus is idle after IDLEGNT is low, a hot-plug slot may be connected to the PCI bus. This input must be wired to a valid logic level if the bus idling procedure is not implemented. PCLK 16 17 19 I PCI clock input. These terminals provide the PCI clock to the HPC3130A, which uses it only for activity indicator timing, IDLEREQ/IDLEGNT protocol, and connection sequencing. PRST 14 15 17 I PCI reset. This signal provides the PCI reset to the HPC3130A. After a PCI reset, the HPC3130A resides in a state where all slots are enabled, as in a non-hot-plug system. The HPC3130A passes PCI resets from the host to all hot-plug slots. SGNT 13 14 16 O Secondary grant. This output provides a scheme to cascade a secondary HPC3130A device in order to provide more than four slots. The SGNT output from the primary HPC3130A is input to the IDLEGNT terminal for the secondary HPC3130A. After the secondary HPC3130A requests the primary HPC3130A to idle the bus, the primary HPC3130A arbitrates for the bus using IDLEREQ. Once IDLEGNT is asserted, the primary HPC3130A asserts its SGNT output. This indicates to the secondary HPC3130A device that it can connect to the bus. SMODE 27 28 30 I Serial bus mode. When this input is asserted high, the internal HPC3130A registers are accessible through the serial bus interface; otherwise, they are accessed through the generic parallel bus interface. This input selects the control bus interface. SREQ 12 13 15 I Secondary request. This input provides a scheme to cascade a second HPC3130A device in order to provide more than four slots. The IDLEREQ from the second HPC3130A device is input to the SREQ terminal of the primary HPC3130A. If the second HPC3130A device arbitrates for the bus by asserting its IDLEREQ output, this scheme causes the primary HPC3130A to assert its IDLEREQ. If cascading is not used, this input is pulled high. SYSM66EN 25 26 28 I/O PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the hot-plug slots, and must be tied to the system PCI bus M66EN signal. The output from this terminal only changes state after a PCI reset and is only required in a 66-MHz system. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 Terminal Functions (Continued) slot control and status functions TERMINAL I/O FUNCTION 1 124 98 80 3 125 99 81 O Attention indicators. These two outputs are provided per slot as attention indicators and can be independently programmed to drive high, low, fast blink, and slow blink. The timer is based on the PCI clock frequency and the state of SYSM66EN. 126 107 86 68 142 121 96 77 O CBT switch control for PCI bus. This output controls the CBT switch that connects the hot-plug slot to the system PCI bus. This output is only driven by the HPC3130A under programmed control. 120 102 82 64 127 109 87 69 144 123 97 79 O PCI clock connection control. This output is used to control the CBT switch or clock driver that connects the hot-plug slot to the system PCI clock. This output is only driven by the HPC3130A under programmed control. DETECT0[3] DETECT0[2] DETECT0[1] DETECT0[0] DETECT1[3] DETECT1[2] DETECT1[1] DETECT1[0] 4 106 87 69 5 108 88 70 5 113 92 74 6 115 93 75 7 127 102 84 8 129 104 85 I Card detection signals. These two card detect input signals, DETECT0 and DETECT1, are provided as additional card detection signals to the PRSNT1 and PRSNT2. Since only one present input must be tied to ground to indicate a card is present per the PCI Specification, these optional inputs are provided for designers of a more mechanically robust system. If the protection enable bit is set to 1 in the general configuration register, the HPC3130A does not power a hot-plug slot unless DETECT0 and DETECT1 are input low. A design not implementing additional card detection must tie these signals to ground. When this feature is utilized, the HPC3130A guarantees that power can not be applied to an empty slot or a slot with a partially inserted card. M66EN[3] M66EN[2] M66EN[1] M66EN[0] 3 105 86 67 4 112 91 72 5 126 101 82 I PCI bus frequency indicator. This signal indicates the PCI clock frequency requirements of the hot-plug slots and is only required in a 66-MHz system (two slot maximum electrical loading limits). The two slot interfaces that provide the M66EN terminals are sensed at PCI reset and are driven afterwards. PRSNT1[3] PRSNT1[2] PRSNT1[1] PRSNT1[0] PRSNT2[3] PRSNT2[2] PRSNT2[1] PRSNT2[0] 113 94 75 55 114 96 76 57 120 101 80 58 121 103 81 60 134 115 90 64 135 117 91 66 I Present signals. These inputs are provided by hot-plug slots to indicate that an add-in card is physically present in the slot and to power requirements to the system. Only one of these signals must be tied to ground to indicate a card is present in an expansion slot. A set of PRSNT1 and PRSNT2 inputs are provided for each hot-plug slot. PWRFAULT[3] PWRFAULT[2] PWRFAULT[1] PWRFAULT[0] 110 92 72 53 117 99 77 56 131 111 87 62 I Power fault. This input is provided per slot power switch to indicate if there is a power fault. The HPC3130A can be programmed to generate an interrupt through INTR when this input is asserted. PWRGOOD[3] PWRGOOD[2] PWRGOOD[1] PWRGOOD[0] 111 93 73 54 118 100 78 57 132 113 88 63 I Power good. This input is provided per slot power switch to indicate when power is successfully switched. The HPC3130A can be programmed to generate an interrupt through INTR when this input is asserted. NAME NO. 120 NO. 128 NO. 144 ATTN0[3] ATTN0[2] ATTN0[1] ATTN0[0] ATTN1[3] ATTN1[2] ATTN1[1] ATTN1[0] 1 103 83 65 2 104 84 66 2 110 88 70 3 111 89 71 BUSON[3] BUSON[2] BUSON[1] BUSON[0] 119 100 81 63 CLKON[3] CLKON[2] CLKON[1] CLKON[0] 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 Terminal Functions (Continued) slot control and status functions (continued) TERMINAL I/O FUNCTION 130 109 86 61 O Power ON/OFF. This output is provided per slot and is driven to the power switch to control the slot power state. 123 105 83 62 137 119 93 70 O CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace loading of the additional REQ64 signal inherent to the HPC3130A controller. This output can be used to control the CBT switch. This output is only driven by the HPC3130A under programmed control. 118 99 80 60 125 106 85 63 140 120 95 72 O CBT switch control for SLOTREQ64. A CBT switch can be implemented to reduce trace loading of the additional REQ64 signal inherent to the HPC3130A controller. This output can be used to control the CBT switch. This output is only driven by the HPC3130A under programmed control. SLOTREQ64[3] SLOTREQ64[2] SLOTREQ64[1] SLOTREQ64[0] 7 8 9 10 8 9 10 11 10 11 12 13 O Slot request 64. This output is driven in conjunction with SLOTRST to the hot-plug slot to indicate to option cards whether or not they are plugged into a 64-bit slot. If a 64-bit device is plugged into a 32-bit slot, then it must ensure that its high-word path inputs do not oscillate and that there is not a significant power drain through the input buffer. This output is only driven by the HPC3130A under programmed control. SLOTRST[3] SLOTRST[2] SLOTRST[1] SLOTRST[0] 115 97 77 58 122 104 82 61 136 118 92 68 O Slot PCI reset. This output is driven to the hot-plug slot to reset it after power up. When a card is inserted into a hot-plug slot it must be reset independent of the other PCI devices on the bus. This output is only driven by the HPC3130A under programmed control. NAME NO. 120 NO. 128 NO. 144 PWRON/OFF[3] PWRON/OFF[2] PWRON/OFF[1] PWRON/OFF[0] 109 91 71 52 116 98 76 55 REQ64ON[3] REQ64ON[2] REQ64ON[1] REQ64ON[0] 116 98 78 59 REQ64ON[3] REQ64ON[2] REQ64ON[1] REQ64ON[0] HPC3130A applications This section discusses the various features of the HPC3130A in detail, and presents design considerations including a general connection sequencing guideline. system implementation Figure 1 illustrates the HPC3130A implementation. The PCI bus signals are switched to the hot–plug PCI slot by the BUSON output, which controls a CBT switch. The PCI clock, PCI reset, M66EN, and REQ64 must not be routed through the CBT switch. The HPC3130A drives the slot PCI reset and SLOTREQ64, which can be controlled by internal HPC3130A registers. The SLOTREQ64 requires special consideration during reset, as described. The PCI clock to the slot is driven by a clock driver, which is enabled by the HPC3130A CLKON output. The HPC3130A also provides other features such as mechanical detection circuits, attention indicators, and interrupt signaling. The mechanical detection circuitry using the DETECT[1,0] inputs is displayed as a dotted line and is an optional feature. Two attention indicator outputs, ATTN[1,0], are provided: one indicator to draw the attention of the user to a particular slot for insertion/removal, and one optional indicator that can be used to indicate fault conditions. Additional features, such as 66-MHz capability and automatic sequencing, are discussed in the following sections. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 Motherboard PCI Device PCI Bus HOST/PCI 8–BIT PORT PCLK PRST SYSM66EN PCI Bus Less PRST and REQ64 BUSON INTR CBT–SW CLKON CBT–SW REQ64ON P C I CBT–SW HPC–PCI SLOTREQ64 M66EN IDLEREQ PRSNT(1–2) IDLEGNT S L O T SLOTRST FRAME IRDY PWRON/OFF PERFAULT PWRGOOD PWR–SW DETECT(0–1) ATTN(0–1) Figure 1. HPC3130A Implementation The HPC3130A internal registers can be accessed through either a two-wire serial interface or an 8-bit generic parallel bus (ISA-like). The above figure illustrates the 8-bit port configuration. Not shown in the diagram is the SMODE chip input that must be wired low to indicate parallel bus interface mode. Also not shown in the diagram is the external chip-select logic required to select the HPC3130A in ISA bus cycles. serial interface The internal registers can be accessed either through a two-wire serial interface or through an 8-bit generic parallel interface. The SMODE input selects one of these modes. The HPC3130A implements a two-pin serial slave interface with one clock signal (SCL) and one data signal (SDA). This serial interface can operate with a serial clock frequency up to 400 kHz. Both SCL and SDA require pullup resistors for the serial slave interface to function properly. All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a START condition (S) when the SDA line transitions to a low state while SCL is in a high state as illustrated in Figure 2. The end of a requested data transfer is indicated by a STOP condition (P), which is the low-to-high transition of SDA while SCL is in the high state. Data on SDA must remain stable during the high state of the SCL signal. Changes on the SDA signal during the high state of SCL will be interpreted as control signals, that is, a START or STOP condition. The SCL is an input into the HPC3130A and SDA is bidirectional. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 SDA SCL Start Condition Stop Condition Change of Data Allowed Data Line Stable, Data Valid Figure 2. Serial Bus Start/Stop Conditions and Bit Transfers Data is transferred on the bus in 8-bit bytes. The number of bytes that can be transmitted during a data transfer is unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by the receiver pulling down the SDA signal so that it remains low during the high state of the SCL signal as shown in Figure 3. SCL From Master 1 2 3 7 8 9 SDA Output By Transmitter SDA Output By Receiver Figure 3. Serial Bus Protocol – Acknowledge The HPC3130A serial bus slave interface protocol for write transactions is illustrated in Figure 4. The R/W command bit is set to zero to indicate a write transaction. For a write operation, the HPC3130A requires a word address field after the slave address. This address field is comprised of eight bits. Upon receipt of the word address, the HPC3130A responds with an acknowledge, and waits for the next eight bits of data, again responding with an acknowledge. After all the data bytes are transferred, the master then terminates the transfer by generating a STOP condition. The device automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. Slave Address S Word Address b6 b5 b4 b3 b2 b1 b0 0 A Data Byte b7 b6 b5 b4 b3 b2 b1 b0 A b7 b6 b5 b4 b3 b2 b1 b0 A P R/W A = Slave acknowledgment S/P = Start/stop condition Figure 4. Serial Bus Protocol – Byte Write A byte read operation is illustrated in Figure 5. The read protocol is very similar to the write protocol, except the R/W command bit must be set to one to indicate a read data transfer. First the master issues a write command that includes the START condition and the slave address field (with the R/W bit set to write), followed by the address of the word it is to read. This procedure sets the internal address counter of the HPC3130A to the desired address. After the word address acknowledgment is received by the master, the master immediately reissues a START condition followed by another slave address field with the R/W bit set to read. The HPC3130A responds with an acknowledgment and transmits the eight data bits stored in the addressed location. If the POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 master responds with an acknowledge signal, indicating that it requires additional data, the HPC3130A continues to output data for each received acknowledge signal. The master terminates the sequential read operation by not responding with an acknowledge signal, and issues a STOP condition. Slave Address Word Address S b6 b5 b4 b3 b2 b1 b0 0 Start Slave Address Data Byte A b7 b6 b5 b4 b3 b2 b1 b0 A S b6 b5 b4 b3 b2 b1 b0 1 R/W A = Slave acknowledgment Restart M = Master acknowledgment A b7 b6 b5 b4 b3 b2 b1 b0 M P R/W Stop S/P = Start/stop condition Figure 5. Serial Bus Protocol – Byte Read parallel interface The HPC3130A also implements an 8-bit parallel interface mode. When this mode is selected, the HPC3130A internal register addressed by the A[4:0] inputs can be accessed for a read/write transaction using the CS, RD, WR strobes. The following signals have pullups on the mother board: IO16, M16, NOWS, CHRDY, MEMR, MEMW, IOR, IOW, SD[15:0] to implement default states. Figure 6 shows write access using the default 8-bit standard ISA bus cycle with four wait states. A read cycle is similar. BCLK CS WR A(0–4) D(0–7) Figure 6. Parallel Bus Write Cycle connection sequencing Before an add-in card is hot plugged and made available to the slot, the various pins in the HPC3130A have to be controlled in a specific sequence. The HPC3130A provides the software interface to sequence the power to the slot, clocks, and signals to the add-in cards that are being live inserted. The switch-timing block is used to control the exact timing when the CBT switches are enabled. The initial software sequencing is done by setting individual bits in the hot plug control register in the following sequence. First, the SLTPWR_CTL bit is set high to drive the PWRON/OFF signal high. After the power to the slot is applied, the SLOTRST_O bit is set low to drive the SLOTRST output. Next the CLKON_O bit is set low to enable the PCI clock to the slot. Also, the REQ64_O bit is set to a value of 0 and the SLOTREQ64 bit is set to indicate to the add-in card whether it is inserted into a 64-bit or 32-bit slot. SLOTREQ64 is set low for a 64-bit slot and is set high for a 32-bit slot. After initial software sequencing of the above signals is complete, the next step is to enable the CBT switches. This can be done either by using the software to manually set the BUS_CTL bit or using the HPC3130A via the automatic connection sequence mode located in the general configuration register. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 connection sequencing (continued) If automatic sequencing mode 1 is selected, then the BUS_CTL bit controls the sequencing by using idling protocol. When this bit is set to zero, the switch–timing block will arbitrate for the PCI bus by asserting IDLEREQ. Subsequently, IDLEGNT is asserted and the HPC3130A waits for bus idle condition. When FRAME and IRDY are deasserted, the CBT switches are enabled. Following this, the SLOTRST, SLOTREQ64 and REQ64ON are deasserted. Figure 7 depicts the sequencing of events when automatic sequencing mode 1 is enabled. PCI_CLK PWRON/OFF PWRGOOD SLOTRST CLKON REQ64ON SLOTREQ64 BUS_CTL IDLEREQ IDLEGNT FRAME IRDY BUSON Figure 7. Automatic Connection Sequencing Mode 1 If automatic sequencing mode 2 is selected, then the BUS_CTL bit controls the sequencing by using idling protocol. When this bit is set to zero, the switch timing block arbitrates for the PCI bus by asserting IDLEREQ. Subsequently, IDLEGNT is asserted and the HPC3130A waits for the bus idle condition. When FRAME and IRDY are deasserted, the SLOTRST is deasserted. Following this, the SLOTREQ64 and REQ64ON are deasserted and the CBT switches are enabled. Figure 8 depicts the sequencing of events when automatic sequencing mode 2 is enabled. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 connection sequencing (continued) PCI_CLK PWRON/OFF PWRGOOD SLOTRST CLKON REQ64ON SLOTREQ64 BUS_CTL IDLEREQ IDLEGNT FRAME IRDY BUSON Figure 8. Automatic Connection Sequencing Mode 2 The protocol described above is identical to the PCI REQ/GNT protocol used by PCI bus masters, which also must wait for bus idle through PCI FRAME and IRDY before initiating a PCI cycle. If the HPC3130A is connected to PCI FRAME and IRDY, the HPC3130A arbitrates for the bus; although it does not drive the PCI bus or assert FRAME to start a cycle. There are some issues with this implementation such as bus parking and additional loading on the PCI FRAME and IRDY signals, which need to be considered when designing a system. The system designer may have a level of confidence that PCI adapter cards can tolerate connection to a non-idle bus. In the scenario where the HPC3130A is not connected to the bus, then the FRAME, IRDY, and IDLEGNT must be wired to valid logic levels and the automatic sequencing will start without any relationship to the bus. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 connection sequencing (continued) IDLEREQ, IDLEGNT, FRAME, and IRDY pins are not connected in manual mode. In contrast, during automatic connection, the HPC3130A requests the PCIBus to make sure it is idle before it sequences through the connection sequence. In manual mode, software has to perform each part of the connection sequence. Figure 9 is an example of the manual connection sequence. There could be several other ways to implement this protocol. PCI_CLK PWRON/OFF PWRGOOD SLOTRST CLKON REQ64ON SLOTREQ64 BUS_CTL BUSON Figure 9. Manual Connection Sequencing disconnecting sequence The HPC3130A provides two mechanisms to isolate a PCI slot from the PCI bus so an add–in card can be removed. One of the mechanisms is called manual sequencing and is enabled by default. This mechanism allows the software to control the entire disconnect sequence. This means it is the software’s responsibility to remove a powered slot from the PCI bus without any impact to the system. The second mechanism is called autosequencing and can be enabled by programming either Auto-Sequence 1 or Auto-Sequence 2 in the general configuration register. Unlike the connection sequence, which has two different autoconnection sequencing modes, the autodisconnect sequence has only one mode of operation. The steps in the autodisconnect sequence are as follows: 1. Software may assert SLOTRST to the appropriate slot by writing a 0 to the SLOTRST_O bit in the hot-plug control register. This is optional. 2. Next the software must set the BUS_CTL bit in the hot-plug control register to a 1. 3. Once the BUS_CTL bit is set to a 1, the HPC3130A asserts IDLEREQ. 4. Once IDLEGNT is asserted and FRAME and IRDY are deasserted, the HPC3130A deasserts BUSON and CLKON and asserts REQ64ON to isolate the slot from the PCI bus. 5. The HPC3130A then drives PWRON/OFF low to power off the slot. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 disconnecting sequence (continued) PCI_CLK PWRON/OFF PWRGOOD SLOTRST CLKON REQ64ON SLOTREQ64 BUS_CTL IDLEREQ IDLEGNT FRAME IRDY BUSON Figure 10. Automatic Disconnect Sequencing Mode In manual disconnect mode, software has to perform each part of the disconnection sequence. Figure 11 is an example of the manual disconnection sequence. There could be several other ways to implement this protocol. During manual disconnection, the PCI bus may or may not idle; it will depend on the software implementation of the system. PCI_CLK PWRON/OFF PWRGOOD SLOTRST CLKON REQ64ON SLOTREQ64 BUS_CTL BUSON Figure 11. Manual Disconnect Sequencing Mode 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 64-bit implementation When inserted into a slot, a 64-bit PCI card tests whether that slot is 64-bit or 32-bit. If REQ64 is low when PCI_RST is deasserted, that signals the card that the slot is 64-bit; otherwise, the slot is 32-bit. The HPC3130A provides a mechanism to notify the PCI card it is connected to a 64-bit PCI slot. The mechanism uses REQ64ON and REQ64ON as CBT switch enables and SLOTREQ64 as the slot specific REQ64 signal. As depicted in figures 12 and 13, REQ64ON enables the CBT switch that routes SLOTREQ64 to the slot, and REQ64ON enables the CBT switch that routes SYSTEMREQ64 to the slot. SYSTEMREQ64 will always be routed to the slot except when the slot is disconnected from the bus or during a connection sequence. It is very important during a connection sequence that the software clears bit 3 in the hot plug control register to drive SLOTREQ64 low. The HPC3130A will deassert SLOTREQ64 during the automatic connection sequence. In a 32-bit PCI bus implementation, the SLOTREQ64, REQ64ON, and REQ64ON outputs are not connected. BUSON HPC_PCI System PCI Bus REQ64ON PCI SLOT SYSTEMREQ64 REQ64ON SLOTREQ64 CBT3306 Figure 12. SLOTREQ64 Implementation Using CBT3306 BUSON HPC_PCI System PCI Bus SYSTEMREQ64 SLOTREQ64 PCI SLOT S OE CBT3257 REQ64ON Figure 13. SLOTREQ64 Implementation Using CBT3257 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 66-MHz PCI support The HPC3130A supports up to two slots in a 66-MHz system: slot 0 and slot 1. These hot-plug slot interfaces include the M66EN signal and the SYSM66EN signal communicates hot-plug slot capability to the system. Figure 14 illustrates the 66-MHz support function in the HPC3130A. HPC–PCI M66EN FUNCTION M66EN_I M66EN_0 P C CO CLKON 0 PRST CB1G1257 SYSM66EN System PCI Bus 33 MHz PCI SLOT Motherboard PCI Device 66 MHz PCLK DRIVER Figure 14. HPC3130A 66-MHz System Support When the PCIRST signal is deasserted, the SYSM66EN signal is latched and selects the system frequency. Before an adapter card can be inserted, the slot is prepared for insertion by deasserting BUSON, deasserting CLKON, and powering down the slot. When an adapter card is inserted into either hot-plug slot 0 or slot 1, PWRON/OFF is high, and power is applied, the value M66EN from the card can be read through internal registers. If the bus is operating at 66-MHz and a 33-MHz adapter card is inserted, then the software ensures that the card is never connected to the bus. If the bus is operating at 33 MHz and a 66-MHz adapter card is inserted, then the latched SYSM66EN state can be driven to the slot by enabling the CBT switch using CLKON. SYSM66EN and CLKON input to a clock driver circuit to control the PCI clock frequency. The 66-MHz support designed into the HPC3130A allows option cards to indicate PCI clock frequency capabilities upon PCI reset; however, does not allow an inserted hot-plug card to alter the clock frequency of an operating PCI bus. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers The HPC3130A register set is accessible through either a generic parallel bus interface or a two-wire serial interface. Eight bytes of register space are provided per slot. Since the HPC3130A supports four slots, a total of 32 bytes of registers is implemented. Register and bit descriptions are provided in the following sections and indicate the bits that are common to all slots. The bit default values are given, which represent the state of the HPC3130A after a PCI reset event. After a PCI reset, the HPC3130A drives outputs to a state such that the slots appear as if they were not a hot-plug platform. The register map that follows provides the register overview. Byte addressing is required when accessing the internal registers. Read transactions from reserved registers return zeros. Table 7. Register Map SLOT REGISTER NAME ADDRESS SLOT REGISTER NAME ADDRESS Slot 0 General configuration register 0x00 Slot 2 General configuration register Slot 0 Hot-plug slot status register 0x01 Slot 2 Hot-plug slot status register 0x11 Slot 0 Hot-plug slot control register 0x02 Slot 2 Hot-plug slot control register 0x12 Slot 0 Attention indicator control 0x03 Slot 2 Attention indicator control 0x13 Slot 0 Reserved 0x04 Slot 2 Reserved 0x14 Slot 0 Reserved 0x05 Slot 2 Reserved 0x15 Slot 0 Interrupt event status register 0x06 Slot 2 Interrupt event status register 0x16 Slot 0 Interrupt event enable register 0x07 Slot 2 Interrupt event enable register 0x17 Slot 1 General configuration register 0x08 Slot 3 General configuration register 0x18 Slot 1 Hot-plug slot status register 0x09 Slot 3 Hot-plug slot status register 0x19 Slot 1 Hot-plug slot control register 0x0A Slot 3 Hot-plug slot control register 0x1A Slot 1 Attention indicator control 0x0B Slot 3 Attention indicator control 0x1B Slot 1 Reserved 0x0C Slot 3 Reserved 0x1C Slot 1 Reserved 0x0D Slot 3 Reserved 0x1D Slot 1 Interrupt event status register 0x0E Slot 3 Interrupt event status register 0x1E Slot 1 Interrupt event enable register 0x0F Slot 3 Interrupt event enable register 0x1F POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0x10 25 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) general configuration register Bit 7 6 5 Name 4 3 2 1 0 General configuration register Type R R R R R/W R/W R R/W Default 0 0 1 1 0 0 X 0 Register: Type: Offset: Default: Description: General configuration Read-only, Read/Write 00h (slot 0), 08h (slot 1), 10h (slot 2), 18h (slot 3) 0Xh This register is for general configurations and indications. The automatic PCI bus connection sequencing is enabled through this register, and the register access mode is indicated. This register is shared among all four slots. Table 8. General Configuration Register 26 BIT TYPE NAME 7–4 R RSVD FUNCTION Reserved for revision ID. These bits return 0011b for this device. 3–2 R/W SEQUENCING Automatic PCI bus connection sequencing. These bits control the sequencing used to connect the hotplug slot to the PCI bus. 00 = Manual sequencing through register accesses 01 = Auto–Sequence 1: Enable CBT switches before deasserting RST 10 = Auto–Sequence 2: Enable CBT switches after deasserting RST 11 = Reserved 1 R SYSM66STAT Status of SYSM66EN. This bit represents the latched value of SYSM66EN during a PCI reset. A value of 1 indicates the PCI bus is operating at a frequency greater than 33 MHz. A value of 0 indicates the PCI bus is operating at 33 MHz or less. 0 R/W PROTECTEN Protection enable. This bit enables a protection mechanism provided by the HPC3130A. When this bit is enabled and either of the DETECT[1:0] inputs are high, the HPC3130A drives the BUS_ON and CLKON outputs high. The HPC3130A also drives PWRON/OFF and REQ64ON outputs low. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) hot-plug slot status register Bit 7 6 5 Name 4 3 2 1 0 Hot-plug slot status register Type R R R R R R R R Default X X X X X X X X Register: Type: Offset: Default: Description: Hot-plug slot status Read-only 01h (slot 0), 09h (slot 1), 11h (slot 2), 19h (slot 3) XXh This register reports card detection, power status, and other chip input from the hot-plug slot interface. All bits in this register are read only, and the data read from each bit represents the logical value of the data input from the corresponding terminal. Table 9. Hot-Plug Slot Status Register BIT TYPE NAME 7 R BUSON Bus on. This bit returns the logical value of the BUSON terminal output. FUNCTION 6 R M66EN_I M66EN input. This bit returns the logical value of the M66EN terminal input. 5 R PWRGOOD_I Power good input. This bit returns the logical value of the PWRGOOD terminal input. 4 R PWRFAULT_I Power fault input. This bit returns the logical value of the PWRFAULT terminal input. 3 R DETECT1_I Mech detect 1 input. This bit returns the logical value of the DETECT1 terminal input. 2 R DETECT0_I Mech detect 0 input. This bit returns the logical value of the DETECT0 terminal input. 1 R PRSNT2_I Card present 2 input. This bit returns the logical value of the PRSNT2 terminal input. 0 R PRSNT1_I Card present 1 input. This bit returns the logical value of the PRSNT1 terminal input. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) hot-plug slot control register Bit 7 6 5 Name 4 3 2 1 0 Hot-plug slot control register Type R R R/W R/W R/W R/W R/W R/W Default 0 0 1 0 1 1 0 1 Register: Type: Offset: Default: Description: Hot-plug slot control Read-only, Read/Write 02 (slot 0), 0Ah (slot 1), 12h (slot 2), 1Ah (slot 3) 2Dh This register applies power, resets, and provides general control of a hot-plug slot connection to the system PCI bus. Table 10. Hot-Plug Slot Control Register BIT TYPE NAME FUNCTION 7 R RSVD Reserved. This bit returns 0 when read. 6 R RSVD Reserved. This bit returns 0 when read. 5 R/W SLTPWR_CTL Slot power On/Off control. The data written to this bit represents the logical value of the data to drive the PWRON/OFF output and is used to control the power state of a hot-plug slot. If the PROTECTEN bit in the general configuration register is set to 1, then a logic high can only be driven by the PWRON/OFF output if the DETECT[1:0] inputs are low. PCI bus CBT-switch control. When manual sequencing is enabled, then the value written to this bit represents the logical value of the data driven to the BUSON output, and it is used to connect/disconnect a hot-plug slot to/from the PCI bus. 28 If an auto sequencing mode is enabled in the general configuration register, then this bit functions as follows: 1 = By setting this bit, the hot-plug slot gets disconnected from the PCI bus. This is accomplished by asserting IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY before driving BUSON high, CLKON high, REQ64ON low, and PWRON/OFF low. 0 = By clearing this bit, the hot-plug slot gets connected to the PCI bus. This is accomplished by asserting IDLEREQ, then waiting for IDLEGNT assertion and deassertion of FRAME and IRDY before driving BUSON low. Also verifies assertion of DETECT[1:0] if the protection enable bit is enabled in the general configuration register. 4 R/W BUS_CTL 3 R/W SLOTREQ64 Slot request 64-bit control. The data written to this bit represents the logical value of the data driven to the SLOTREQ64 output and is used during reset of a slot after power is applied. This input indicates to an option card whether or not it is connected to a 64-bit slot. 2 R/W REQ64_O REQ64 CBT switch control. The data written to this bit represents the logical value of the data driven to the REQ64ON output and is used to control the CBT switch that implements the REQ64 PCI signal. 1 R/W CLKON_O CLKON CBT switch control. The data written to this bit represents the logical value of the data driven to the CLKON output and is used to control the clock driver to the hot-plug slot. 0 R/W SLOTRST_O Slot reset control. The data written to this bit represents the logical value of the data driven to the SLOTRST output and is used to reset a hot-plug slot after power is applied. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) attention indicator control register Bit 7 6 5 Name 4 3 2 1 0 Attention indicator control register Type R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Attention indicator control Read-only, Read/Write 03 (slot 0), 0Bh (slot 1), 13h (slot 2), 1Bh (slot 3) 00h This register controls the attention indicators. The timing for the indicators is based upon the PCI clock and the M66EN input. Table 11. Attention Indicator Control Register BIT TYPE NAME 7 R RSVD Reserved. This bit returns 0 when read. 6 R RSVD Reserved. This bit returns 0 when read. 5 R RSVD Reserved. This bit returns 0 when read. 4 R RSVD Reserved. This bit returns 0 when read. 3–2 1–0 R/W R/W FUNCTION ATTN1_CTL Attention indicator 1 control. These bits control the state of ATTN1 per slot and are programmed as follows: 00 = Drive low 01 = Slow blink – 1 cycle per second 10 = Fast blink – 2 cycles per second 11 = Drive high ATTN0_CTL Attention indicator 0 control. These bits control the state of ATTN0 per slot and are programmed as follows: 00 = Drive low 01 = Slow blink – 1 cycle per second 10 = Fast blink – 2 cycles per second 11 = Drive high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) interrupt event status register Bit 7 6 5 Name 4 3 2 1 0 Interrupt event status register Type R R/C R/C R/C R/C R/C R/C R/C Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Interrupt event status Read-only, Read/Clear 06h (slot 0), 0Eh (slot 1), 16h (slot 2), 1Eh (slot 3) 00h This register reads interrupt status, and clears the interrupt. All functional bits in this register are readable and cleared by a write back of 1. The HPC3130A can be programmed to generate an interrupt, signaled through the open-drain INTR, after detecting various events. Each event is individually enabled through the interrupt event enable register. Table 12. Interrupt Event Status Register 30 BIT TYPE NAME 7 R RSVD Reserved. This bit returns 0 when read. FUNCTION 6 R/C BUS_S PCI Bus CBT switch status. This bit is set when the BUSON output changes state, and is cleared by a write back of 1. The BUS event is intended for use with the idling protocol. 5 R/C PWRGOOD_S Power good status. This bit is set when the PWRGOOD input changes state. 4 R/C PWRFAULT_S Power fault status. This bit is set when the PWRFAULT input is asserted. 3 R/C DETECT1_S Mechanical detect 1 status. This bit is set when the DETECT1 input changes state. 2 R/C DETECT0_S Mechanical detect 0 status. This bit is set when the DETECT0 input changes state. 1 R/C PRSNT2_S Card present 2 status. This bit is set when the PRSNT2 input changes state. 0 R/C PRSNT1_S Card present 1 status. This bit is set when the PRSNT1 input changes state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 configuration and control registers (continued) interrupt event enable register Bit 7 6 5 Name 4 3 2 1 0 Interrupt event enable register Type R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Type: Offset: Default: Description: Interrupt event enable Read-only, Read/Write 07h (slot 0), 0Fh (slot 1), 17h (slot 2), 1Fh (slot 3) 00h This register is used to enable interrupts, signaled through the open-drain INTR, after detecting various events. Event status is reported through the interrupt event status register. Table 13. Interrupt Event Enable Register BIT TYPE NAME 7 R RSVD Reserved. This bit returns 0 when read. FUNCTION 6 R/W BUS_E PCI bus CBT switch event enable. When this bit is set, an INTR is signaled when the BUSON output changes state. The BUS event is intended for use with the idling protocol. 5 R/W PWRGOOD_E Power good event enable. When this bit is set, an INTR is signaled when the PWRGOOD input changes state. 4 R/W PWRFAULT_E Power fault event enable. When this bit is set, an INTR is signaled when PWRFAULT input is asserted. 3 R/W DETECT1_E Mechanical detect 1 event enable. Enables INTR events on DETECT1 input state changes. 2 R/W DETECT0_E Mechanical detect 0 event enable. Enables INTR events on DETECT0 input state changes. 1 R/W PRSNT2_E Card present 2 event enable. Enables INTR events on PRSNT2 input state changes. 0 R/W PRSNT1_E Card present 1 event enable. Enables INTR events on PRSNT1 input state changes. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V VCCP and VCC5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V SLOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V BUSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Parallel/serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V SLOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V BUSON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Parallel/serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC5V + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. For 5-V tolerant use VI > VCC5V. For universal PCI, use VI > VCCP. 2. Applies to external output and bidirectional buffers. For 5-V tolerant use VO > VCC5V. For universal PCI, use VO > VCCP. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 recommended operating conditions MIN NOM MAX VCC VCCP Core voltage Commercial 3 3.3 3.6 V PCI I/O voltage Commercial 3 5 5.5 V VCC5V VCC5V Slot I/O voltage Commercial 3 5 5.5 V Parallel I/O voltage Commercial 3 5 5.5 V VCC5V VCC5V Serial I/O voltage Commercial 3 5 5.5 V Miscellaneous I/O voltage Commercial 3 5 5.5 V PCI 0 Slot 0 BUSON 0 Parallel 0 Parallel/Serial 0 Miscellaneous 0 PCI 0 Slot 0 BUSON 0 Parallel 0 Parallel/Serial 0 Miscellaneous 0 PCI 2 Slot 2 BUSON 2 Parallel 2 Parallel/Serial 2 Miscellaneous 2 VCC5V VCC5V PCI 0 0.8 Slot 0 0.8 BUSON 0 Parallel 0 0.8 0.8 Parallel/Serial 0 0.8 Miscellaneous 0 PCI 0 0.8 6 Slot 0 6 BUSON 0 6 Parallel/Serial 0 6 Miscellaneous 0 VI VO VIH VII tt Input voltage Output voltage† High level input voltage High-level Low level input voltage Low-level Input In ut transition time (tr and tf) (10% to 90%) TA Operating ambient temperature range 0 25 ‡ TJ Virtual junction temperature 0 25 † Applies to external output buffers. ‡ These junction temperatures reflect simulation conditions. Customer is responsible for verifying junction temperature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCCP VCC5V VCC5V VCC5V VCC5V UNIT V VCC5V VCC VCC VCC VCC VCC V VCC VCCP VCC5V VCC5V VCC5V V V ns 6 70 °C 115 °C 33 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 serial bus interface STANDARD MODE FAST MODE MIN MAX MIN MAX UNIT VIL Low-level input voltage Fixed: VCC5V related: –0.5 –0.5 1.5 0.3 VCC5V –0.5 –0.5 1.5 0.3 VCC5V V VIH High-level input voltage Fixed: VCC5V related: 0 0.7 VCC5V VCC5V max + 0.5 VCC5V max + 0.5 3 0.7 VCC5V VCC5V max + 0.5 VCC5V max + 0.5 V electrical characteristics over recommended operating conditions PARAMETER PINS PCIh OPERATION 3.3 V 5V Slot§ VOH High-level High level out output ut voltage IOH = –8mA IOH = –8mA BUSON¶ Parallel# IOH = –4mA IOH = –4mA Parallel/Serial|| Miscellaneousk PCIh VOL IIL† IIH† Low-level Low level out output ut voltage Low level input current‡ Low-level High level input current‡ High-level 3.3 V 5V IOH = –8mA IOL = 1.5 mA MIN MAX VCC – 0.6 VCC – 0.6 VCC – 0.6 VCC – 0.6 V VCC – 0.6 VCC – 0.6 0.1 VCC 0.55 Slot§ BUSON¶ Parallel# IOL = 8mA IOL = 4mA 0.5 Parallel/Serial|| IOL = 4mA IOL = 2mA 0.5 Miscellaneousk PCIh Slot§ VI = GND VI = GND –20 BUSON¶ Parallel# VI = GND VI = GND –20 Parallel/Serial|| VI = GND VI = GND –20 Miscellaneousk PCIh Slot§ VI = VCC VI = VCC 20 BUSON¶ Parallel# VI = VCC VI = VCC 20 Parallel/Serial|| VI = VCC VI = VCC 20 VI = VCC or GND ±20 High-impedance-state output current UNIT 0.9 VCC IOL = 6 mA IOL = 8mA Miscellaneousk IOZ TEST CONDITIONS IOH = –0.5 mA IOH = –2 mA 0.5 V 0.5 0.5 –20 –20 µA –20 20 20 µA A 20 µA † Specifications apply only when pullup terminator is turned off. ‡ For I/O pins, the imput leakage current includes the off state output current IOZ. h PCI terminals: 120 PBM — 12, 13, 14, 16, 18, 19, 20, 21, 23, 24, 25, 27. 128 PBK — 13, 14, 15, 17, 19, 20, 21, 22, 24, 25, 26, 28. 144 PGE — 15, 16, 17, 19, 21, 22, 23, 24, 26, 27, 28, 30. § Slot terminals: 120 PBM — 7, 8, 9, 10, 58, 77, 97, 115. 128 PBK — 8, 9, 10, 11, 61, 82, 104, 122. 144 PGE — 10, 11, 12, 13, 68, 92, 118, 136. ¶ BUSON terminals: 120 PBM — 63, 81, 100, 119. 128 PBK — 68, 86, 107, 126. 144 PGE — 77, 96, 121, 142 # Parallel terminals: 120 PBM — 35, 37, 38, 39, 40, 42. 128 PBK — 38, 40, 41, 42, 43, 45. 144 PGE — 44, 46, 47, 48, 49, 51 || Parallel/serial terminals: 120 PBM — 43, 44, 45, 47, 48, 49, 50. 128 PBK — 46, 47, 48, 50, 51, 52, 53. 144 PGE — 52, 53, 54, 56, 57, 58, 59. k Miscellaneous terminals: All terminals other than PCI, slot, BUSON, parallel, and parallel/serial. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature ALTERNATE SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS tc PCLK cycle time tcyc 15 ns twH PCLK high time thigh 6 ns twL PCLK low time tlow 6 dv/dt PCLK slew rate tr, tf 1.5 tw RSTIN pulse width trst 1 ms tsu PCLK active time at end of RSTIN trst–clk 100 ms ns 4 V/ns Pin definitions for 120-pin PBM package PARAMETER PIN NUMBER PCI 14, 16, 18, 19, 20, 21, 25, 27 Slot 1, 2, 3, 4, 5, 7, 8, 9, 10, 52, 53, 54, 55, 57, 58, 59, 60, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76, 77, 78, 80, 82, 83, 84, 86, 87, 88, 91, 92, 93, 94, 96, 97, 98, 99, 102, 103, 104, 105, 106, 108, 109, 110, 111, 113, 114, 115, 116, 118, 120 BUSON 63, 81, 100, 119 Parallel 34, 35, 37, 38, 39, 40, 42 Parallel/serial 23, 24, 29, 30, 43, 44, 45, 47, 48, 49, 50 Miscellaneous 12, 13 Pin definitions for 128-pin PBK package PARAMETER PIN NUMBER PCI 15, 17, 19, 20, 21, 22, 26, 28, Slot 2, 3, 4, 5, 6, 8, 9, 10, 11, 55, 56, 57, 58, 60, 61, 62, 63, 69, 70, 71, 72, 74, 75, 76, 77, 78, 80, 81, 82, 83, 85, 87, 88, 89, 91, 92, 93, 98, 99, 100, 101, 103, 104, 105, 106, 109, 110, 111, 112, 113, 115, 116, 117, 118, 120, 121, 122, 123, 125, 127 BUSON 68, 86, 107, 126 Parallel 37, 38, 40, 41, 42, 43, 45, Parallel/serial 24, 25, 30, 31, 46, 47, 48, 50, 51, 52, 53 Miscellaneous 13, 14 Pin definitions for 144-pin PGE package PARAMETER PIN NUMBER PCI 17, 19, 21, 22, 23, 24, 28, 30 Slot 1, 3, 5, 7, 8, 10, 11, 12, 13, 61, 62, 63, 64, 66, 68, 70, 72, 79, 80, 81, 82, 84, 85, 86, 87, 88, 90, 91, 92, 93, 95, 97, 98, 99, 101, 102, 104, 109, 111, 113, 115, 117, 118, 119, 120, 123, 124, 125, 126, 127, 129, 130, 131, 132, 134, 135, 136, 137, 140, 144 BUSON 77, 96, 121, 142 Parallel 43, 44, 46, 47, 48, 49, 51 Parallel/serial 26, 27, 34, 36, 52, 53, 54, 56, 57, 58, 59 Miscellaneous 15, 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 PCI timing requirements over recommended ranges of supply voltage and operating free–air temperature† (see Note 3) ALTERNATE SYMBOL PARAMETER PCLK to shared signal valid delay time tpd Propagation delay time ten tdis Enable time, high-impedance-to-active delay time from PCLK Disable time, active-to-high-impedance delay time from PCLK tval TEST CONDITIONS CL = 50 pF, See Note 4, 1,2,3 ton toff MIN MAX 2 11 2 UNITS ns ns 28 ns tsu Valid setup time, before PCLK tsu 3,4 3 ns th Hold time, after PCLK high th 4 0 ns † Applies to external output buffers. NOTES: 3. This data sheet uses the following conventions to describe time ( t ) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, PCIFRAME, PCITRDY, PCIIRDY, PCISTOP, IDSEL, PCIDEVSEL, and PCIPAR. serial bus interface† STANDARD MODE fSCL tBUF tHD;STA SCL clock frequency (see Note 5) Bus free time between a STOP and START condition Hold time (repeated) START condition. After this period, the first clock pulse is generated. FAST MODE MIN MAX MIN MAX 0 100 0 400 UNIT kHz 4.7 1.3 µs 4 0.6 µs tLOW tHIGH LOW period of the SCL clock 4.7 1.3 µs HIGH period of the SCL clock 4 0.6 µs tSU;STA Setup time for a repeated START condition 4.7 0.6 µs tHD;DAT Data hold time (see Note 6) tSU;DAT tR Data setup time (see Note 7) For CBUS compatible masters: 5 For serial bus devices: 01 250 Rise time of both SDA and SCL signals 1000 01 1003 0.92 20 300 µs µs µs tF Fall time of both SDA and SCL signals 300 20 300 µs tFSU;STO Setup time for STOP condition 4 0.6 µs † All values refer to serial bus interface VIH MIN and VIL MAX levels NOTES: 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 6. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW ) of the SDL signal. 7. A fast mode serial bus device can be used in a standard mode serial bus system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode Serial Bus Specification) before the SCL line is released. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 MECHANICAL DATA PBM (S-PQFP-G***) PLASTIC QUAD FLATPACK 120-PIN SHOWN 90 61 NO. OF PINS*** 120QFP A 23,20 TYP 60 91 0,45 0,30 0,20 M 0,80 31 120 0,16 NOM 1 30 A 28,20 SQ 27,80 Gage Plane 31,45 SQ 30,95 3,60 3,20 0,25 0,25 MIN 0°–ā7° 1,03 0,73 Seating Plane 0,10 4,10 MAX 4040023 / D 06/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-022 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 MECHANICAL DATA PBK (S-PQFP-G128) PLASTIC QUAD FLATPACK 128-PIN SHOWN 0,23 0,13 0,40 96 NO. OF PINS*** 0,07 M A 128 LQFP 65 24,80 TYP 64 97 128 33 1 0,13 NOM 32 Gage Plane 12,40 TYP 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 0,25 0°–ā7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040279-3 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 MECHANICAL DATA PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 144-PIN SHOWN 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°–ā7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 HPC3130A PCI HOT PLUG CONTROLLER SCPS055 – NOVEMBER 1999 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated