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SLOS405A - DECEMBER 2002– REVISED APRIL 2003
FEATURES
D Low Noise: Vn = 1.1 nV/ Hz,
D
D
D
DESCRIPTION
The THS7530 is fabricated using Texas Instruments’
state-of-the-art BiCom III SiGe complementary bipolar
process. The THS7530 is a dc-coupled wide bandwidth
amplifier with voltage-controlled gain. The amplifier has
high impedance differential inputs and low impedance
differential outputs with high bandwidth gain control,
output common mode control, and output voltage
clamping.
Noise Figure = 9 dB
Low Distortion:
– HD2 = –65 dBc, HD3 = –61 dBc at 32 MHz
– IMD3 = –62 dBc, OIP3 = 21 dBm at 70 MHz
300 MHz Bandwidth
Continuously Variable Gain Range: 11.6 dB to
46.5 dB
Gain Slope: 38.8 dB/V
Fully Differential Input and Output
D
D
D Output Common-Mode Voltage Control
D Output Voltage Limiting
Signal channel performance is exceptional with 300-MHz
bandwidth, and third harmonic distortion of –61 dBc at
32 MHz with 1 VPP output into 400 Ω.
Gain control is linear in dB with 0 V to 0.9 V varying the gain
from 11.6 dB to 46.5 dB with 38.8-dB/V gain slope.
APPLICATIONS
D Time Gain Amplifiers in Ultra Sound, Sonar,
D
D
D
Output voltage limiting is provided to limit the output
voltage swing, and prevent saturating following stages.
and Radar
Automatic Gain Control in Communication
and Video
System Gain Calibration in Communications
Variable Gain in Instrumentation
The device is characterized for operation over the
industrial temperature range: –40°C to 85°C.
AGC APPLICATION
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
24.9 Ω
0.1 µF
VCL+
24.9 Ω
6.8 µF
33 pF
VCL–
0.1 µF
24.9 Ω
0.1 µF
VOUT+
VIN+
VIN–
THS7530
VOCM
0.1 µF
PD
VG–
0.1 µF
VS–
24.9 Ω
VOUT–
0.1 µF
33 pF
VG+
AGC detect
VREF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002 – 2003, Texas Instruments Incorporated
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
SYMBOL
TEMPERATURE
RANGE, TA
THS7530
TSSOP PowerPAD
PWP 14
PWP-14
THS7530
–40°C
40°C to 85°C
ORDERING
NUMBER
TRANSPORT
MEDIA
THS7530PWP
Tube
THS7530PWPR
Tape and reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
THS7530
Supply voltage, VS+ – Vs–
5.5 V
Input voltage, VI
±VS
65 mA
Output current, IO (2)
Differential input voltage, VID
±4 V
Continuous power dissipation
See Dissipation Rating Table
Maximum junction temperature, TJ
150°C
Maximum junction temperature for long term stability, TJ
125°C
Operating free-air temperature range, TA
–40°C to 85°C
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD
300°C
HBM
3000 V
CDM
1500 V
MM
200 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS7530 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative
plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage
the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package.
RECOMMENDED OPERATING CONDITIONS
TEST CONDITIONS
Supply voltage, [VS– to VS+]
Operating free–air temperature, TA
MIN
TYP
MAX
4.5
5
5.5
V
85
°C
–40
Input common mode voltage
[VS– to VS+] = 5 V
[VS– to VS+] = 5 V
Output common mode voltage
2.5
V
2.5
V
PACKAGE THERMAL DATA
PACKAGE
PCB
ΘJA
( C/W)
ΘJC
( C/W)
TA = 25°C
POWER RATING
14PWP
See Layout Considerations in the application
section of this data sheet.
37.5
2.07
3W
PowerPAD is a trademark of Texas Instruments.
2
UNIT
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
SPECIFICATIONS: MAIN AMPLIFIER
VS+ = 5 V, VS– = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG– = 0 V, VG+ = 1 V (maximum gain), TA = 25°C, ac performance measured using the ac test
circuit shown in Figure 1 (unless otherwise noted). DC performance is measured using the dc test circuit shown in Figure 2 (unless otherwise
noted)
TYP
PARAMETER
TEST CONDITIONS
25 C
OVER TEMPERATURE
25 C
–40 C to
85 C
UNITS
MIN/
MAX
AC PERFORMANCE (See Figure 1)
Small-signal bandwidth
All gains, PIN = –45 dBm
300
MHz
Typ
Slew rate(1)
1 VPP Step, 25% to 75%,
minimum gain
1250
V/µs
Typ
Settling time to 1%(1)
1 VPP Step, minimum gain
11
ns
Typ
Harmonic distortion
2nd Harmonic
VO(PP) = 1 V, RL(diff)= 400 Ω
f = 32 MHz
–65
dBc
Typ
f = 32 MHz
–61
dBc
Typ
Third-order intermodulation distortion
PO = –10 dBm each tone,
fC=70 MHz,
200 kHz tone spacing
–62
dBc
Typ
Third-order output intercept point
fC=70 MHz,
200 kHz tone spacing
21
dBm
Typ
Noise figure (with input termination)
Source impedance: 50 Ω
9
dB
Typ
Total input voltage noise
f > 100 kHz
1.1
nV/√Hz
Typ
µA
Max
3rd Harmonic
DC PERFORMANCE—INPUTS (See Figure 2)
Input bias current
20
Input bias current offset
39
40
1.5
1.6
1.7
3.5
3.35
114
56
<150
Minimum input voltage
Minimum gain
Maximum input voltage
Minimum gain
Common-mode rejection ratio
Differential input impedance
pA
Typ
V
Max
3.2
V
Min
44
dB
Min
kΩ || pF
Typ
Max
8.5 || 3.0
DC PERFORMANCE—OUTPUTS (See Figure 2)
±100
±340
±480
mV
Maximum output voltage high
3.5
3.275
3.25
V
Min
Minimum output voltage low
1.5
1.7
1.8
V
Max
Output current
±37
±16
±16
mA
Min
Output impedance
15
Ω
Typ
32
MHz
Typ
Output offset voltage
All gains
OUTPUT COMMON-MODE VOLTAGE CONTROL (See Figure 2)
Small-signal bandwidth
Gain
1.00
Common-mode offset voltage
4.5
Minimum input voltage
Maximum input voltage
Input impedance
V/V
Typ
mV
Max
1.75
V
Typ
3.25
V
Typ
25 || 1
kΩ || pF
Typ
12
13.8
Default voltage, with no connect
2.5
V
Typ
Input bias current
<1
µA
Typ
(1) Slew rate and settling time measured at amplifier output.
3
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
SPECIFICATIONS: MAIN AMPLIFIER (CONTINUED)
VS+ = 5 V, VS– = 0 V, VOCM = 2.5 V, VICM = 2.5 V, VG– = 0 V, VG+ = 1 V (maximum gain), TA = 25°C, ac performance measured using the ac test
circuit shown in Figure 1 (unless otherwise noted). DC performance is measured using the dc test circuit shown in Figure 2 (unless otherwise
noted)
TYP
PARAMETER
TEST CONDITIONS
25 C
OVER TEMPERATURE
25 C
–40 C to
85 C
UNITS
MIN/
MAX
GAIN CONTROL (See Figure 2)
Gain control differential voltage range
Minus gain control voltage
Minimum gain
Maximum gain
Gain slope
Gain slope variation
G i error
Gain
VG+
VG– – VS–
0 to 1
V
Typ
–0.6 to 0.8
V
Typ
VG+ = 0 V
VG+ = 0.9 V
11.6
dB
Typ
46.5
dB
Typ
38.8
dB/V
Typ
±1.5
dB/V
Typ
±4
dB
Typ
VG+ = 0 V to 0.9 V
VG+ = 0 V to 0.9 V
VG+ = 0 V to 0.15 V
VG+ = 0.15 V to 0.9 V
±2.25
dB
Typ
Gain control input bias current
<1
µA
Typ
Gain control input resistance
40
kΩ
Typ
15
MHz
Typ
mV
Max
3.3
kΩ
Typ
Vs– to Vs+
V
Typ
Gain control bandwith
Small signal –3 dB
VOLTAGE CLAMPING (See Figure 2)
Output voltages (VOUT±) relative to clamp
voltages (VCL±)
In voltage limiting mode
VCL± input resistance
VCL± voltage limits
±25
±38
±60
POWER SUPPLY (See Figure 2)
Specified operating voltage
5
5.5
5.5
V
Max
Maximum quiescent current
40
48
49
mA
Max
Power supply rejection (±PSRR)
77
70
45
dB
Min
1.0
V
Min
POWERDOWN (See Figure 2)
Enable voltage threshold
TTL low = normal operation
Disable voltage threshold
TTL high = shut down
1.65
V
Max
0.35
0.4
0.45
mA
Max
9
16
19
µA
Max
Input current low
109
116
119
µA
Max
Input impedance
50 || 1
kΩ || pF
Typ
Turnon time delay
820
ns
Typ
Power-down quiescent current
Input current high
Turnoff time delay
4
1.4
Measured to 50% quiescent
current
1.4
500
ns
Typ
Forward isolation in power down
80
dB
Typ
Input resistance in power down
>1
MΩ
Typ
Output resistance in power down
16
kΩ
Typ
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
50 Ω
Source
Coax
VIN
0.1 µF
VCL+
VCL–
50 Ω
1:1
6.8 µF
33 pF
24.9 Ω
1:1
VOUT
Coax
50 Ω
Load
THS7530
VOCM
24.9 Ω
PD
VG–
0.1 µF
VS–
33 pF
VG+
Figure 1. AC Test Circuit
VS+ = 5 V
VCL+
VCL–
VIN+
VOCM
VIN–
0.1 µF
6.8 µF
VOUT+
THS7530
800
VOUT–
PD
VG–
0.1 µF
VS–
VG+
Figure 2. DC Test Circuit
5
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
PIN ASSIGNMENTS
THD7530PWP
(TOP VIEW)
NC
NC
VIN+
VIN–
VG+
VG–
PD
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCL+
VCL–
VOCM
VOUT–
VOUT +
VS+
VS–
NC – No internal connection
Terminal Functions
TERMINAL
NAME
1
NC
No internal connection
2
NC
No internal connection
3
VIN+
VIN–
Noninverting amplifier input
VG+
VG–
Gain setting positive input
7
PD
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
8
VS–
VS+
Negative amplifier power supply input
4
5
6
9
10
Inverting amplifier input
Gain setting negative input
Positive amplifier power supply input
VOUT+
VOUT–
Noninverted amplifier output
VOCM
VCL–
Output common-mode voltage input
13
14
VCL+
Output positive clamp voltage input
11
12
6
DESCRIPTION
NO.
Inverted amplifier output
Output negative clamp voltage input
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
Measured using the ac test circuit shown in Figure 1 (unless otherwise noted).
FIGURE
Voltage Gain to Load
vs Frequency (Input at 45 dBm)
3
Gain and Gain Error
vs VG+
4
Noise Figure
vs Frequency
5
Output Intercept Point
vs Frequency
6
1-dB Compression Point
vs Frequency
7
Total Input Voltage Noise
vs Frequency
8
Intermodulation Distortion
vs Frequency
9
Harmonic Distortion
vs Frequency
10
S–Parameters
vs Frequency
11
Differential Input Impedance of Main Amplifier
vs Frequency
12
Differential Output Impedance of Main Amplifier
vs Frequency
13
VG+ Input Impedance
VOCM Input Impedance
vs Frequency
14
vs Frequency
15
Common-Mode Rejection Ratio
vs Frequency
16
Step Response – 2 VPP
vs Time
17
Step Response – Rising Edge
vs Time
18
Step Response – Falling Edge
vs Time
19
VOLTAGE GAIN TO LOAD
vs
FREQUENCY (PIN = –45 dBm)
GAIN AND GAIN ERROR
vs
VG+
45
50
40
Maximum Gain
0.2
40
30
30
20
0
Gain
25
–0.2
20
15
10
–0.6
Gain is taken at load. Add 6 dB
to refer to amplifier output.
–10
1
10
100
f – Frequency – MHz
Figure 3
–0.4
10
Minimum Gain
0
Gain Error
Gain Error – dB
35
Gain – dB
Voltage Gain to Load – dB
0.4
5
0
1000
0
200
400
600
800
–0.8
1000
V – VG+ – mV
Figure 4
7
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
35
60
55
Output Intercept Point – dBm
25
Gain = 30 dB
20
15
Gain = 40 dB
10
50
100
150
200
250
45
40
35
30
25
OIP3
20
Taken at load. Add
3 dB to refer to amplifier output
15
Terminated Input
5
0
OIP2
50
10
300
0
50
100
Figure 5
Hz
250
9
8
7
6
5
4
3
2
1
0
0
300
IMD 2 and IMD 3 – dBc
–60
IMD3
–65
–70
VG+ = 1 V, VO = 1 VPP
(Composite), RL = 400 Ω
f – Frequency – Hz
50
100
150
0
S22
S11
–50
S12
–60
10
f – Frequency – MHz
Figure 11
20
30
40
50
60
70
Figure 10
DIFFERENTIAL OUTPUT IMPEDANCE
OF MAIN AMPLIFIER
vs
FREQUENCY
50
9
8
7
6
5
4
3
2
1
45
40
35
30
25
20
15
10
5
0
100 300
10
f – Frequency – MHz
Differential Output Impedance – Ω
–20
Differential Input Impedance – kΩ
–10
1
HD2
–64
200
10
0.1
–62
–68
DIFFERENTIAL INPUT IMPEDANCE
OF MAIN AMPLIFIER
vs
FREQUENCY
0
–70
HD3
–60
Figure 9
S-PARAMETERS
vs
FREQUENCY
–40
–58
f – Frequency – MHz
Figure 8
–30
–56
–70
0
10 k 100 k 1 M 10 M 100 M
300
–66
–80
1k
250
RL = 400 Ω
VO = 1 Vpp,
VG+ = 1 V
–54
IMD2
–55
–75
100
200
–50
–52
10
150
HARMONIC DISTORTION
vs
FREQUENCY
–45
10
100
Figure 7
–50
1
50
f – Frequency – MHz
INTERMODULATION DISTORTION
vs
FREQUENCY
100
nV /
V n – Total Input Voltage Noise –
200
Taken at load. Add 3 dB to refer
to amplifier output
Figure 6
TOTAL INPUT VOLTAGE NOISE
vs
FREQUENCY
Differential Input Impedance – kΩ
150
15
14
13
12
11
10
f – Frequency – MHz
f – Frequency – MHz
HD2 and HD3 – dBc
NF – Noise Figure – dB
30
1 dB Compression Point – dBm
Gain = 20 dB
8
1 dB COMPRESSION POINT
vs
FREQUENCY
OUTPUT INTERCEPT POINT
vs
FREQUENCY
NOISE FIGURE
vs
FREQUENCY
0.1
1
10
f – Frequency – MHz
Figure 12
100
1000
0
1
10
100
f – Frequency – MHz
Figure 13
1000
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
VG+ INPUT INPEDANCE
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR – Common-Mode Rejection Ratio – dB
VOCM INPUT IMPEDANCE
vs
FREQUENCY
25
100
80
V OCM – Input Impedance – kΩ
70
60
50
40
30
20
10
0
0.1
1
10
5
–30
–40
–50
–60
0.1
100
1
10
100
f – Frequency – MHz
Figure 14
Figure 15
Figure 16
STEP RESPONSE – RISING EDGE
1
0.5
0
–0.5
1.5
1
1
0.5
0
–0.5
400
600
t – Time – ns
Figure 17
800
1000
0
2
4
6
t – Time – ns
Figure 18
8
Amplifier Output at Minimum Gain
RL = 400 Ω
0.5
0
–0.5
–1
Amplifier Output at Minimum Gain
RL = 400 Ω
–1.5
–1.5
1000
STEP RESPONSE – FALLING EDGE
1.5
–1
–1
200
10
–20
f – Frequency – MHz
At Amplifier Output and Minimum Gain
RL = 400 Ω
0
1
–10
f – Frequency – MHz
V O – Output Voltage – V
Step Response – 2VPP
15
0
0.1
10
STEP RESPONSE
1.5
20
V O – Output Voltage – V
V G+ – Input Inpedance – k Ω
90
–1.5
10
12
0
2
4
6
8
10
12
t – Time – ns
Figure 19
9
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
APPLICATION INFORMATION
The THS7530 is designed for nominal 5-V power supply from VS+ to VS–.
The amplifier has fully differential inputs, VIN+ and VIN–, and fully differential outputs, VOUT+ and VOUT– The
inputs are high impedance and outputs are low impedance. External resistors are recommended for impedance
matching and termination purposes.
The inputs and outputs can be dc-coupled, but for best performance, the input and output common-mode
voltage should be maintained at the midpoint between the two supply pins. The output common-mode voltage
is controlled by the voltage applied to VOCM. Left unterminated, VOCM is set to midsupply by internal resistors.
A 0.1-µF bypass capacitor should be placed between VOCM and ground to reduce common-mode noise. The
input common-mode voltage defaults to midrail when left unconnected. For voltages other than midrail, VOCM
must be biased by external means. VIN+ and VIN– both require a nominal 30-µA bias current for proper operation.
Therefore, insure equal input impedance at each input to avoid generating an offset voltage that varies with gain.
Voltage applied from VG– to VG+ controls the gain of the part with 38.8-dB/V gain slope. The input can be
differential or single ended. VG– must be maintained within –0.6 V and +0.8 V of VS– for proper operation. The
negative gain input should typically be tied directly to the negative power supply.
VCL+ and VCL– are inputs that limit the output voltage swing of the amplifier. The voltages applied set an absolute
limit on the voltages at the output. Input voltages at VCL+ and VCL– clamp the output insuring that neither output
exceeds those values.
The power-down input is a TTL compatible input, referenced to the negative supply voltage. A logic low puts
the THS7530 in power savings mode. In power-down mode the part consumes less than 1-mA current, the
output goes high impedance, and a high amount of isolation is maintained between the input and output.
Power supply bypass capacitors are required for proper operation. A 6.8-µF tantalum bulk capacitor is
recommended if the amplifier is located far from the power supply and may be shared among other devices.
A ceramic 0.1-µF capacitor is recommended within 0.1” of the device power pin. The ceramic capacitors should
be located on the same layer as the amplifier to eliminate the use of vias between the capacitors and the power
pin.
The following circuits show some basic circuit configurations.
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
0.1 µF
VCL+
50 Ω
6.8 µF
33 pF
VCL–
1:1
24.9 Ω
VIN
VOUT
THS7530
VOCM
PD
24.9 Ω
VG–
0.1 µF
VS–
VG+
33 pF
Figure 20. EVM Schematic: Designed for Use With Typical 50-
10
1:1
RF Test Equipment
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
49.9 Ω
0.1 µF
VCL+
49.9 Ω
6.8 µF
33 pF
VCL–
24.9 Ω
0.1 µF
VOUT+
VIN
THS7530
VOCM
24.9 Ω
PD
VOUT–
0.1 µF
VG–
0.1 µF
33 pF
VG+
VS–
Figure 21. AC-Coupled Single-Ended Input With AC-Coupled Differential Output
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
24.9 Ω
0.1 µF
VCL+
24.9 Ω
6.8 µF
33 pF
VCL–
0.1 µF
24.9 Ω
0.1 µF
VOUT+
VIN+
THS7530
VOCM
VIN–
24.9 Ω
PD
0.1 µF
0.1 µF
VOUT–
VG–
0.1 µF
33 pF
VG+
VS–
Figure 22. AC-Coupled Diferential Input With AC-Coupled Differential Output
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
49.9 Ω
0.1 µF
VCL+
49.9 Ω
6.8 µF
33 pF
VCL–
24.9 Ω
VOUT+
VIN
THS7530
VOCM
VOUT–
PD
24.9 Ω
VG–
0.1 µF
VS–
VG+
33 pF
Figure 23. DC-Coupled Single-Ended Input With DC-Coupled Differential Output
11
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SLOS405A DECEMBER 2002– REVISED APRIL 2003
VS+ = 5 V
1 kΩ
1 kΩ
0.1 µF
24.9 Ω
0.1 µF
VCL+
24.9 Ω
6.8 µF
33 pF
VCL–
24.9 Ω
VOUT+
VIN+
VIN–
THS7530
VOCM
24.9 Ω
PD
VOUT–
VG–
0.1 µF
VS–
VG+
33 pF
Figure 24. DC-Coupled Differential Input With DC-Coupled Differential Output
LAYOUT CONSIDERATIONS
The THS7530 comes in a thermally enhance PowerPADt package. Figure 25 shows the recommended number of
vias and thermal land size recommended for best performance. Thermal vias connect the thermal land to internal
or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged
when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the
interface between the package body and the thermal land on the surface of the board during solder reflow. The
experiments conducted jointly with Solectron Texas indicate that a via drill diameter of 0.33mm (13 mils) or smaller
works well when 1 ounce copper is plated at the surface of the board and simultaneously plating the barrel of the via.
If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used
to cap the vias with a dimension equal to the via diameter + 0,1 mm minimum. This prevents the solder from being
wicked through the thermal via and potentially creating a solder void in the region between the package bottom and
the thermal land on the surface of the PCB.
TSSOP
14 Pin PWP
2X3
3.4
5
Figure 25. Recommended Thermal Land Size and Thermal Via Patterns (dimensions in mm)
See TI’s Technical Brief titled PowerPADt Thermally Enhanced Package (SLMA002) for a detailed discussion of
the PowerPADt package, its dimensions, and recommended use.
12
www.ti.com
SLOS405A DECEMBER 2002– REVISED APRIL 2003
THEORY OF OPERATION
Figure 26 shows a simplified schematic of the THS7530.
The input architecture is a modified Gilbert Cell. The output from the Gilbert Cell is converted to a voltage and buffered
to the output as a fully-differential signal. A summing node between the outputs is used to compare the output
common-mode voltage to the VOCM input. The VOCM error amplifier then servos the output common-mode voltage
to maintain it equal to the VOCM input. Left unterminated, VOCM is set to midsupply by internal resistors.
The gain control input is conditioned to give linear in dB gain control (block H). The gain control input is a differential
signal from 0 V to 0.9 V which varies the gain from 11.6 dB to 46.5 dB.
VCL+ and VCL– provide inputs that limit the output voltage swing of the amplifier.
VCL+
VCL–
VS+
Output
Buffer
x1
VOUT+
VOCM Error
Amplifier
VOUT–
VIN+
VOCM
VIN–
PD
Power
Control
VS–
VG+
VG–
H
THS7530
Figure 26. THS7530 Simplified Schematic
13
www.ti.com
SLOS405A DECEMBER 2002– REVISED APRIL 2003
SPICE MODEL
* [Disclaimer] (C) Copyright Texas Instruments Incorporated 1999–2002 All rights reserved
* Texas Instruments Incorporated hereby grants the user of this SPICE Macro-model a
* non–exclusive, nontransferable license to use this SPICE Macro-model under the following
* terms. Before using this SPICE Macro–model, the user should read this license. If the
* user does not accept these terms, the SPICE Macro–model should be returned to Texas
* Instruments within 30 days. The user is granted this license only to use the SPICE
* Macro–model and is not granted rights to sell, load, rent, lease or license the SPICE
* Macro–model in whole or in part, or in modified form to anyone other than user. User may
* modify the SPICE Macro–model to suit its specific applications but rights to derivative
* works and such modifications shall belong to Texas Instruments. This SPICE Macro-model is
* provided on an ”AS IS” basis and Texas Instruments makes absolutely no warranty with
* respect to the information contained herein. TEXAS INSTRUMENTS DISCLAIMS AND CUSTOMER
* WAIVES ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY
* OR FITNESS FOR A PARTICULAR PURPOSE. The entire risk as to quality and performance is with
* the Customer. ACCORDINGLY, IN NO EVENT SHALL THE COMPANY BE LIABLE FOR ANY DAMAGES,
* WHETHER IN CONTRACT OR TORT,INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL, CONSEQUENTIAL,
* EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR APPLICATION OF THE SPICE
* Macro–model provided in this package. Further, Texas Instruments reserves the right to
* discontinue or make changes without notice to any product herein to improve reliability,
* function, or design. Texas Instruments does not convey any license under patent rights or
* any other intellectual property rights, including those of third parties.
*
* THS7530 SUBCIRCUIT
* HIGH SPEED FULLY DIFFERENTIAL VARIABLE AMPLIFIER
* WRITTEN 11/26/02
* VG– is tied to VS– and output clamping is not modeled
* CONNECTIONS:
IN+
*
|
IN–
*
|
|
VS+
*
|
|
|
VS–
*
|
|
|
|
OUT–
*
|
|
|
|
|
OUT+
*
|
|
|
|
|
|
VOCM
*
|
|
|
|
|
|
|
VG+
*
|
|
|
|
|
|
|
|
.SUBCKT THS7530
1
2
3
4
5
6
7
8
*
*INPUT*
14
Q1
122 1 101 NPN_IN
16
Q2
123 2 102 NPN_IN
16
R1
102 101
I1
101 4 DC 4.85e–3
I2
102 4 DC 4.85e–3
25
www.ti.com
SLOS405A DECEMBER 2002– REVISED APRIL 2003
*QUAD*
Q3
132 120 122 NPN
16
Q4
121 119 122 NPN
16
Q5
132 119 123 NPN
16
Q6
121 120 123 NPN
16
R2
132 3
250
R3
121 3
250
*CURRENT AMP*
F1
128 129 VF1 6
VF1
132 121 0V
*Z NODE*
R4
128 129
2k
I3
129 4 DC 0.75e–3
I4
128 4 DC 0.75e–3
V9
128 328 0.7
V10
129 329 0.7
*FREQUENCY SHAPING*
E3
131 0 329 0 1
R5
131 140
30
L3
140 133
7.5n
C6
133 0
E4
130 0 328 0 1
R9
130 141
30
L4
141 125
10n
C7
125 0
24p
27p
*OUTPUT BUFFER*
Q9
4 133 117 PNP
5.12
Q10
3 133 127 NPN
5.12
Q11
3 117 134 NPN
81.92
Q12
4 127 135 PNP
81.92
Q13
4 125 116 PNP
5.12
Q14
3 125 126 NPN
5.12
Q15
3 116 136 NPN
81.92
Q16
4 126 137 PNP
81.92
R6
138 134
5
R7
135 138
5
R10
139 136
5
R11
137 139
5
I5
3 117 DC 0.4e–3
I6
127 4 DC 0.4e–3
I7
3 116 DC 0.4e–3
I8
126 4 DC 0.4e–3
15
www.ti.com
SLOS405A DECEMBER 2002– REVISED APRIL 2003
*OUTPUT Z*
R8
113 138
2
R12
115 139
2
L1
113 5
4n
L2
115 6
4n
C1
6 5
2p
*VOCM
Rcm1
115 114
8k
Ccm1
115 114
0.1p
Rcm2
114 113
8k
Ccm2
114 113
0.1p
E1
118 0 114 7 1e3
Rtop
3 7
50k
Rbot
4 7
50k
Q7
128 118 3 PNP
16
Q8
129 118 3 PNP
16
*GAIN CONTROL*
V8
235 8 0.454
E5
231 0 235 4 0.51
E6
232 0 POLY(1) 231 0 0.0 1 1 0.5 3.5
E7
233 0 232 0 0.115
E8
234 0 POLY(1) 233 0 0.0 0 1 0 0.333
E9
120 119 234 0 0.42
V7
3 120 1.6
Rsupply 3 4 310
.MODEL NPN_IN NPN
+
KF=1E–12
.MODEL NPN NPN
.MODEL PNP PNP
.ENDS
16
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS7530PWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS7530PWPG4
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS7530PWPR
ACTIVE
HTSSOP
PWP
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS7530PWPRG4
ACTIVE
HTSSOP
PWP
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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