Preliminary Product Description SXA-3318B Sirenza Microdevices’ SXA-3318B amplifier is a high efficiency GaAs Heterojunction Bipolar Transistor (HBT) MMIC housed in a low-cost surface-mountable plastic package. These HBT MMICs are fabricated using molecular beam epitaxial growth technology which produces reliable and consistent performance from wafer to wafer and lot to lot. 400-2500 MHz Balanced ½ W Medium Power GaAs HBT Amplifier with Active Bias These amplifiers are specially designed for use as driver devices for infrastructure equipment in the 400-2500 MHz cellular, ISM, WLL, PCS, W-CDMA applications. Product Features Its high linearity makes it an ideal choice for multi-carrier as well as digital applications. • On-chip Active Bias Control • Balanced for excellent input/output VSWR and 5V minimized reflections • High OIP3 : +47 dBm typ. SXA-3318B RFin 1 8 2 7 3 6 4 5 • High P1dB : +28 dBm typ. • Patented High Reliability GaAs HBT Technology • Surface-Mountable Power Plastic Package RFout Applications • W-CDMA, PCS, Cellular Systems • High Linearity IF Amplifiers • Multi-Carrier Applications Symbol Parameters: Test Conditions: Z0 = 50 Ohms, Ta = 25°C Units Min. Typ. 27.0 27.5 28.0 28.0 10.5 17.5 12.8 12.0 Output Power at 1dB Compression f = 850 MHz f = 1960 MHz f = 2140 MHz dB m Small signal gain f = 850 MHz f = 1960 MHz f = 2140 MHz dB Input/Output VSWR f = 850 MHz f = 1960 MHz f = 2140 MHz - 1.3:1 1.2:1 1.2:1 OIP3 Output Third Order Intercept Point (Pout/Tone = +11 dBm, Tone spacing = 1 MHz) f = 850 MHz f = 1960 MHz f = 2140 MHz dB m 47 47 48 AC P Adjacent Channel Power: IS-95 at POUT = 19 dBm IS-95 at POUT = 19 dBm W-CDMA at POUT = 18 dBm f = 880 MHz f = 1960 MHz f = 2140 MHz dB c -55 -55 -50 Noise Figure f = 850 MHz f = 1960 MHz f = 2140 MHz dB 4.5 5.1 5.1 Device Current (120 mA per amplifier) V cc = 5 V mA 240 ° C/W 70* P 1dB S 21 S11,S22 NF ID Rth, j-l Thermal Resistance (junction - lead) per amplifier *Note: 2 amplifiers per packaged part 45 Max. 13.5 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 South Technology Ct., Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-103164 Rev A Preliminary 850 MHz Application Circuit Data, VCC= 5V, ID= 240mA Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3 Gain vs. Frequency 25 29 22 28 19 dB dBm P1dB vs. Frequency 30 27 16 2 5C -40 C 2 5C -40 C 26 13 8 5C 8 5C 25 10 0 .8 0 .8 5 0 .9 0 .9 5 0 .8 0 .9 0 .95 GHz GHz Input/Output Return Loss, Isolation vs. Frequency, T=25°C Third Order Intercept vs. Frequency (POUT per tone = 11dBm) 55 0 S 11 -5 50 S 22 -1 0 S 12 dBm -1 5 dB 0 .85 -2 0 -2 5 -3 0 45 40 25C -40C 35 -3 5 85C 30 -4 0 0 .8 55 0 .8 5 0 .9 0.8 0 .9 5 0.9 0.95 GHz GHz Third Order Intercept vs. Tone Power Frequency = 880 MHz 880 MHz Adjacent Channel Power vs. Channel Output Power -40 25C 50 -45 -40C -50 85C -55 45 dBc dBm 0.85 40 -60 -65 25C -40C 85C -70 35 -75 30 -80 5 10 15 20 25 15 POUT per tone (dBm) 303 South Technology Ct., Broomfield, CO 80021 16 17 18 19 20 21 22 Channel Output Power (dBm) IS-95, 9 Channels Forward Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-103164 Rev A Preliminary 1960 MHz Application Circuit Data, VCC= 5V, ID= 240mA Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3 Gain vs. Frequency 20 29 17 28 14 dB dBm P1dB vs. Frequency 30 27 11 25 C -40C 85 C 26 25 1.9 3 1.9 4 1.9 5 1.9 6 1.9 7 1.9 8 85 C 5 1.9 3 1.9 9 1.9 4 1.9 5 1.9 6 1.9 7 1.9 8 GHz GHz Input/Output Return Loss, Isolation vs. Frequency, T=25°C Third Order Intercept vs. Frequency (POUT per tone = 11dBm) 1.9 9 55 0 S11 -5 50 S22 -1 0 S12 dBm -1 5 dB 25 C -40C 8 -2 0 45 40 -2 5 -3 0 25C -40C 35 -3 5 85C -4 0 1 .9 3 1 .9 4 1 .9 5 1 .9 6 1 .9 7 1 .9 8 30 1.93 1 .9 9 1.94 1.95 1.96 1.97 1.98 GHz GHz Third Order Intercept vs. Tone Power Frequency = 1.96 GHz 1960 MHz Adjacent Channel Power vs. Channel Output Power 1.99 -4 0 55 -4 5 -5 0 -5 5 45 dBc dBm 50 40 -6 0 -6 5 25C 35 25C -7 0 -40C 85C -4 0C -7 5 85C -8 0 30 5 10 15 20 15 25 17 18 19 20 21 22 Channel Output Power (dBm) IS-95, 9 Channels Forward POUT per tone (dBm) 303 South Technology Ct., Broomfield, CO 80021 16 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-103164 Rev A Preliminary 2140 MHz Application Circuit Data, VCC= 5V, ID= 240mA Note: Tested in Balanced Configuration shown in Application Circuit, tuned for Output IP3 Gain vs. Frequency 20 29 17 28 14 dB dBm P1dB vs. Frequency 30 11 27 25 C 26 25C -40C 8 -40C 85 C 25 2.1 1 2.1 2 2.1 3 2.1 4 2.1 5 2.1 6 85C 5 2.11 2.1 7 2.13 2.14 2.15 Input/Output Return Loss, Isolation vs. Frequency, T=25°C Third Order Intercept vs. Frequency (POUT per tone = 11dBm) 2.17 55 0 S 11 S 22 S 12 -10 50 -15 dBm 45 -20 -25 -30 40 25C -40C 85C 35 -35 -40 2.11 2.12 2.13 2.14 2.15 2.16 30 2.11 2.17 2.12 2.13 2.14 GHz 2.15 2.16 2.17 GHz Third Order Intercept vs. Tone Power Frequency = 2.14 GHz 2140 MHz Adjacent Channel Power vs. Channel Output Power -40 55 25C -40C 85C 50 -45 45 -50 dBc dBm 2.16 GHz -5 dB 2.12 GHz 40 -55 35 -60 30 25C -40C 85C -65 5 10 15 20 15 25 POUT per tone (dBm) 303 South Technology Ct., Broomfield, CO 80021 16 17 18 19 20 21 22 Channel Output Power (dBm) W-CDMA, 64 DPCH + Overhead Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-103164 Rev A Preliminary Application Schematic (850 MHz) VCC C6 RF IN C1 X1 C2 Z=50Ω, EL1 C2 Z=50Ω, EL1 C3 L2 Z=50Ω, EL2 4 C3 Z=50Ω, EL3 8 6,7 1 2,3 L1 C1 R1 x2 C4 SXA-3318B L1 Z=50Ω, EL2 C5 5 Z=50Ω, EL3 L2 C6 C5 R1 x2 C7 C7 C3 X1 RF OUT C3 C4 VCC Ref. Des. Vendor Series 850 MHz Ref. Des. Vendor Series 850 MHz C 1, C 3 Rohm MCH18 47pF, 5% L2 Toko LL1608-FS 33nH, 5% C2 Rohm MCH18 3.9pF, ±0.25pF E L1 50 Ohms 9.9° C4 Rohm MCH18 1000pF, 5% E L2 50 Ohms 4.4° C5 Rohm TAJB104KLRH 0.1uF, 10% E L3 50 Ohms 11° C6 Rohm TAJB106K020R 10uF, 10% X1 Sirenza Coupler AH03L C7 Rohm MCH18 3.3pF, ±0.25pF R1 Rohm MCR100J 100 Ohm, 5% L1 Toko LL1608-FS 1.2nH, ±0.3nH Evaluation Board Layout (850 MHz) Vcc SIRENZA R1 x2 C6 X1 + MICRODEVICES X1 L2 C1 C2 C5 C4 C3 L1 C7 C3 C4 C5 Balanced SOIC-8 Eval Board ECB-103109-A + R1 x2 C6 Vcc 303 South Technology Ct., Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-103164 Rev A Preliminary Application Schematic (1960 MHz, 2140 MHz) VCC C5 RF IN X1 C1 C2 Z=50Ω, EL1 C1 R1 x2 C2 Z=50Ω, EL1 C4 C3 L1 SXA-3318B C3 Z=50Ω, EL2 8 6,7 1 2,3 4 5 Z=50Ω, EL2 L1 C5 C4 R1 x2 C7 C7 C3 X1 RF OUT C3 VCC Ref. Des. Vendor Series 1960 MHz 2140 MHz Ref. Des. Vendor Series 1960 MHz 2140 MHz C 1, C 3 Rohm MCH18 22pF, 5% 22pF, 5% L1 Toko LL1608-FS 18nH, 5% 18nH, 5% C2 Rohm MCH18 1.2pF, ±0.25pF 1.2pF, ±0.25pF E L1 50 Ohms 10.1° 11° C4 Rohm MCH18 1000pF, 5% 1000pF, 5% E L2 50 Ohms 20.9° 22.8° C5 Rohm TAJB104KLRH 0.1uF, 10% 0.1uF, 10% X1 Sirenza Coupler AM03M AM03M Rohm MCR100J 100 Ohm, 5% 100 Ohm, 5% C7 Rohm MCH18 1.0pF, ±0.25pF 1.0pF, ±0.25pF R1 Evaluation Board Layout (1960 MHz, 2140 MHz) Vcc X1 X1 L1 C1 R1 x2 C5 C4 C3 C2 C7 C3 C4 C5 R1 x2 ECB-102363 Rev. A Balanced SOIC-8 Eval Board Vcc 303 South Technology Ct., Broomfield, CO 80021 Phone: (800) SMI-MMIC 6 Sirenza Microdevices http://www.sirenza.com EDS-103164 Rev A Preliminary Pin # Function 1, 4 RF In RF input pin. This pin requires the use of an external DC blocking capacitor. 2, 3, 6, 7 GND Connection to ground. Use via holes to reduce lead inductance. Place vias as close to ground leads as possible. 5, 8 Description Device Schematic RF Out/Vcc RF output and bias pin. Bias should be supplied to this pin through an external RF choke. Because DC biasing is present on this pin, a DC blocking capacitor should be used in most applications (see application schematic). The supply side of the bias network should be well bypassed. An output matching network is necessary for optimum performance. EPAD GND Device Current vs. Source Voltage Device Current (mA) 8 7 3 4 6 Active Bias 5 Input Match Absolute Maximum Ratings Parameter -40 C 25 C 85 C 250 2 Input Match Active Bias Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for thermal and RF performance. Several vias should be located under the EPAD as shown in the recommended land pattern (page 8). 350 300 1 Absolute Limit Max. Supply Current (ID) per amplifier (2 amplifiers per packaged part) 240 mA Max. Device Voltage (VCC) 200 150 100 50 6.0 V Max. Power Dissipation per amplifier (2 amplifiers per packaged part) 1500 mW Max. RF Input Power per amplifier (2 amplifiers per packaged part) 100 mW Max. Junction Temp. (TJ) 0 0 1 2 3 4 5 Operating Lead Temp. (TL) 6 +160 ºC -40 to +85 ºC Max. Storage Temp. VS (V) +150 ºC Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation, the device voltage and current must not exceed the maximum operating values specified in the table on page one. Bias Conditions should also satisfy the following expression: IDVCC (max) < (TJ - TL)/Rth,j-l ESD: Class 1B (Passes 500V ESD pulse) Appropriate precautions in handling, packaging and testing devices must be observed. Moisture Sensitivity Level: Level 1 (MSL-1) No special moisture packaging/handling is required during storage, shipment, or installation of the devices. 303 South Technology Ct., Broomfield, CO 80021 Phone: (800) SMI-MMIC 7 http://www.sirenza.com EDS-103164 Rev A Preliminary Part Number Ordering Information Recommended Land Pattern Part Number Devices Per Reel Reel Siz e 0.150 [3.81] SXA-3318B Plated-Thru Holes (0.015" Dia, 0.030" Pitch) 500 7" 0.140 [3.56] Part Symbolization Machine Screws The part will be symbolized with a “SXA3318B” designator on the top surface of the package. 0.300 [7.62] 0.080 [2.03] 0.020 [0.51] 0.050 [1.27] Package Outline Drawing (See SMDI MPO-101644 for tolerances) 8 7 6 5 .194 [4.93] XXXX SXA 3318B .236 [5.994] .155 [3.937] 1 2 3 EXPOSED PAD .09 [2.286] 4 Beveled Edge .045 [1.143] .035 [.889] .130 [3.302] TOP VIEW BOTTOM VIEW .050 [1.27] .016 [.406] .061 [1.549] .058 [1.473] .013 [.33] x 45° .008 .008 [.203] .194 [4.928] .003 [.076] .155 [3.937] SEATING PLANE SEE DETAIL A SIDE VIEW END VIEW PARTING LINE Note: XXXX represents the lot code DIMENSIONS ARE IN INCHES [MM] .025 5° DETAIL A 303 South Technology Ct., Broomfield, CO 80021 Phone: (800) SMI-MMIC 8 http://www.sirenza.com EDS-103164 Rev A