TECHNICAL INFORMATION Stereo 10W (4Ω Ω) Class-T™ Digital Audio Amplifier using Digital Power Processing™ Technology TA1101B September 2000 General Description The TA1101B is a 10W continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. Applications Features !"Computer/PC Multimedia !"DVD Players !"Cable Set-Top Products !"Televisions !"Video CD Players !"Battery Powered Systems !"Class-T architecture !"Single Supply Operation !"“Audiophile” Quality Sound !"0.04% THD+N @ 9W, 4Ω !"0.18% IHF-IM @ 1W, 4Ω !"6W @ 8Ω, 0.1% THD+N !"11W @ 4Ω, 0.1% THD+N !"High Power !"10W @ 8Ω, 10% THD+N !"15W @ 4Ω, 10% THD+N !"High Efficiency !"88% @ 10W, 8Ω !"81% @ 15W, 4Ω !"Dynamic Range = 102 dB !"Mute and Sleep inputs !"Turn-on & turn-off pop suppression !"Over-current protection !"Over-temperature protection !"Bridged outputs !"30-pin Power SOP package Benefits !"Fully integrated solution with FETs !"Easier to design-in than Class-D !"Reduced system cost with no heat sink !"Dramatically improves efficiency versus Class-AB !"Signal fidelity equal to high quality linear amplifiers !"High dynamic range compatible with digital media such as CD, DVD, and Internet audio Typical Performance THD+N versus Output Power 10 5 VDD = 12V f = 1kHz Av = 12 BW = 22Hz - 22kHz 2 THD+N (%) 1 0.5 0.2 RL= 8Ω 0.1 RL= 4Ω 0.05 0.02 0.01 500m 1 2 5 10 20 Output Power (W) TA1101B, Rev. 2.2, 08.17.00 1 TECHNICAL INFORMATION Absolute Maximum Ratings (Note 1) SYMBOL PARAMETER VDD Supply Voltage TSTORE Storage Temperature Range TA Operating Free-air Temperature Range PDISS Continuous Total Power Dissipation Value UNITS 16 V -40° to 150° C 0° to 70° Note 2 C W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: See Power Dissipation Derating in the Applications Information section. Operating Conditions (Note 3) MIN. TYP. MAX. UNITS VDD SYMBOL Supply Voltage PARAMETER 8.5 12 13.2 V VIH High-level Input Voltage (MUTE, SLEEP) 3.5 VIL Low-level Input Voltage (MUTE, SLEEP) 1 V V Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits. Electrical Characteristics See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement Bandwidth = 22kHz, RL = 4Ω, TA = 25 °C, Package heat slug soldered to 2.8 square-inch PC pad. SYMBOL PO PARAMETER Output Power (Continuous Average/Channel) CONDITIONS THD+N = 0.1% THD+N = 10% RL = 4Ω RL = 8Ω RL = 4Ω RL = 8Ω MIN. TYP. 9 5.5 12 8 11 6 16 10 MAX. UNITS W W W W IDD,MUTE Mute Supply Current MUTE = VIH 5.5 7 mA IDD, SLEEP Sleep Supply Current SLEEP = VIH 0.25 2 mA Iq Quiescent Current VIN = 0 V 61 75 mA THD + N PO = 9W/Channel 0.04 IHF-IM Total Harmonic Distortion Plus Noise IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF) 0.18 SNR Signal-to-Noise Ratio A-Weighted, POUT = 1W, RL = 8Ω 89 dB CS Channel Separation 30kHz Bandwidth 50 55 dB PSRR Power Supply Rejection Ratio Vripple = 100mV. 60 80 dB η Power Efficiency POUT = 10W/Channel, RL = 8Ω 88 VOFFSET Output Offset Voltage No Load, MUTE = Logic Low 50 VOH High-level output voltage (FAULT & OVERLOAD) Low-level output voltage (FAULT & OVERLOAD) Output Noise Voltage VOL eOUT Note: 2 % 0.5 % 150 3.5 mV V 1 A-Weighted, input AC grounded % 100 V µV Minimum and maximum limits are guaranteed but may not be 100% tested. TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION Pin Description Pin 1, 2 Function DCAP2, DCAP1 Description Charge pump switching pins. DCAP1 (pin 2) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 1) is level shifted 10 volts above DCAP1 (pin 2) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. Digital 5VDC, Analog 5VDC Analog Ground 3, 8 4, 7, 15 5 6 9, 12 10, 13 V5D, V5A AGND1, AGND2, AGND3 REF OVERLOADB VP1, VP2 IN1, IN2 11 MUTE 14 16 BIASCAP SLEEP 17 FAULT 18, 28 19 20, 22; 25, 23 21, 24 26 27 29 30 PGND2, PGND1 DGND OUTP2 & OUTM2; OUTP1 & OUTM1 VDD2, VDD1 NC VDDA CPUMP 5VGEN Internal reference voltage; approximately 1.0 VDC. A logic low output indicates the input signal has overloaded the amplifier. Input stage output pins. Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with approximately 2.4VDC bias. When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. Ground if not used. Input stage bias voltage (approximately 2.4VDC). When set to logic high, device goes into low power mode. If not used, this pin should be grounded A logic high output indicates thermal overload, or an output is shorted to ground, or another output. Power Grounds (high current) Digital Ground Bridged outputs Supply pins for high current H-bridges, nominally 12VDC. Not connected Analog 12VDC Charge pump output (nominally 10V above VDDA) Regulated 5VDC source used to supply power to the input section (pins 3 and 8). 30-pin Power SOP Package (Top View) DCAP2 DCAP1 1 2 30 29 5VGEN CPUMP V5D AGND1 3 4 28 27 PGND1 VDDA REF OVERLOADB AGND2 V5A 5 6 7 8 26 25 24 23 NC OUTP1 VDD1 OUTM1 VP1 IN1 9 10 22 21 OUTM2 VDD2 MUTE VP2 11 12 20 19 OUTP2 DGND IN2 BIASCAP 13 14 18 17 PGND2 FAULT AGND3 15 16 SLEEP TA1101B, Rev. 2.2, 08.17.00 3 TECHNICAL INFORMATION Application / Test Circuit 4 TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION TA1101B VDD1 RF 20KΩ CI 2.2uF + VP1 9 IN1 10 25 DO Processing & Modulation RI 20KΩ CA 0.1uF (Pin 7) BIASCAP 14 PGND1 (Pin 28) 11 PGND1 6 VP2 12 13 Lo 10uH, 2A DO 2 Processing & Modulation REF PGND2 DCAP1 22 (Pin 18) *Co 0.47uF CZ 0.47uF PGND2 RZ *Co 0.47uF 10Ω, 1/2W OUTM2 DO DCAP2 1megΩ 16 (Pin 18) VDD2 CD 0.1uF 1 RL 4Ω or *8Ω RZ 10Ω, 1/2W FAULT OVERLOADB 20 OUTP2 RREF 8.25KΩ, 1% +12V CCM 0.1uF Lo 10uH, 2A DO (Pin 28) RI 20KΩ 5 CZ 0.47uF VDD2 RF 20KΩ (Pin 7) *Co 0.47uF *Co 0.47uF 23 OUTM1 5V 17 IN2 (Pin 28) VDD1 5V MUTE CI 2.2uF + Lo 10uH, 2A OUTP1 CCM 0.1uF RL 4Ω or *8Ω Lo 10uH, 2A (Pin 18) SLEEP CPUMP 29 0.1uF 5V VDDA 3 CS 0.1uF 4 8 To Pin 30 CS 0.1uF 27 CP 1uF 19 CS 0.1uF 30 CS 0.1uF + 26 NC V5D DGND AGND1 V5A 5VGEN VDD1 7 AGND2 15 AGND3 24 PGND1 28 VDD2 PGND2 To Pin 3,8 CSW 0.1uF + VDD (+12V) CSW 180uF, 16V 21 18 CSW 0.1uF + CSW 180uF, 16V Note: Analog and Digital/Power Grounds must be connected locally at the TA1101B Analog Ground Digital/Power Ground All Diodes Motorola MBRS130T3 * Use Co = 0.22µF for 8 Ohm loads TA1101B, Rev. 2.2, 08.17.00 5 TECHNICAL INFORMATION External Components Description (Refer to the Application/Test Circuit) Components RI RF CI RREF CA CD CP CS CSW CZ RZ DO LO CO CCM 6 Description Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at the BIASCAP voltage (approximately 2.4VDC). Feedback resistor to set AC gain in conjunction with RI; A V = 12(RF / RI ) . Please refer to the Amplifier Gain paragraph in the Application Information section. AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at fC = 1 ( 2πRICI ) Bias resistor. Locate close to pin 5 and ground at pin 7. BIASCAP decoupling capacitor. Should be located close to pin 14. Charge pump input capacitor. This capacitor should be connected directly between pins 1 and 2 and located physically close to the TA1101B. Charge pump output capacitor that enables efficient high side gate drive for the internal Hbridges. To maximize performance, this capacitor should be connected directly between pin 29 (CPUMP) and pin 27 (VDDA). Please observe the polarity shown in the Application/ Test Circuit. Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (180uF) should have good high frequency performance including low ESR and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor. Zobel Capacitor. Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. Schottky diodes that minimize undershoots of the outputs with respect to power ground during switching transitions. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin. Output inductor, which in conjunction with CO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f C = 1 ( 2 π L O C O ) and a quality factor of Q = R L C O LOCO . Output capacitor. Common Mode Capacitor. TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION Typical Performance Characteristics Frequency Response Efficiency versus Output Power +3 100 +2.5 90 RL = 8Ω +2 Output Amplitude (dBr) 80 70 Efficiency (%) RL = 4Ω 60 50 40 30 VDD = 12V f = 1kHz Av = 12 THD+N < 10% 20 10 +1.5 VDD = 12V Pout = 1W RLoad = 4Ω Av = 12 BW = 22Hz - 22kHz +1 +0.5 +0 -0.5 -1 -1.5 -2 0 -2.5 0 5 10 15 20 -3 10 Output Power (W) 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Intermodulation Performance Noise Floor +0 +0 VDD = 12V Pout = 1W/Channel RLoad = 4Ω 0dBr = 12Vrms 19kHz, 20kHz, 1:1 Av = 11.7 BW = 10Hz - 80kHz -20 FFT (dBr) -30 VDD = 12V Pout = 0W RLoad = 4Ω Av = 12 BW = 22Hz - 22kHz A-Weighted Filter -20 Noise FFT (dBV) -10 -40 -50 -60 -40 -60 -80 -100 -70 -80 -120 -90 -140 -100 50 1k 2k 5k 10k 20k 30k 20 100 50 Frequency (Hz) 500 1k 2k 5k 10k 20k Frequency (Hz) Channel Separation versus Frequency THD+N versus Frequency 10 +0 VDD = 12V Pout = 5W/Channel Av = 12 BW = 22Hz - 22kHz 2 1 0.5 0.2 0.1 RL = 4Ω 0.05 VDD = 12V Pout = 1W/Channel RLoad = 4Ω Av = 12 BW = 22Hz - 22kHz -10 Channel Separation (dBr) 5 THD+N (%) 200 -20 -30 -40 -50 -60 -70 -80 RL = 8Ω 0.02 -90 0.01 -100 10 20 50 100 200 500 1k 2k Frequency (Hz) TA1101B, Rev. 2.2, 08.17.00 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 7 TECHNICAL INFORMATION Application Information Layout Recommendations The TA1101B is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground at high speeds while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TA1101B to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath’s layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. The figure below is the Tripath TA1101B evaluation board. Some of the most critical components on the board are the power supply decoupling capacitors. C7 and C18 must be placed right next to pins 24 and 28 as shown. C8 and C19 must be placed right next to pins 21 and 18 as shown. These power supply decoupling capacitors from the output stage not only help reject power supply noise, but they also absorb voltage spikes on the VDD pins caused by overshoots of the outputs of the amplifiers. Output overshoots include those caused by output inductor flyback during high current switching events such as shorted outputs or driving low impedances at high levels. If the supply capacitors are not close enough to the pins, electrical overstress to the part can occur from the voltage spikes on the VDD pins. This may result in permanent damage or destruction to the TA1101B. The copper slug of the TA1101B must be soldered onto the PC board. This board uses a 5 x 16 array of 0.013” vias on the copper below the TA1101 that allow the heat to conduct to 4 sq. in. of copper on the bottom side ground plane of the PC board. 8 TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION Amplifier Gain The gain of the TA1101B is set by the ratio of two external resistors, RI and RF, and is given by the following formula: VO R = 12 F VI RI where VI is the input signal level and VO is the differential output signal level across the speaker. 9 Watts of RMS output power results from an 8.485V RMS signal across an 8Ω speaker load. RF = RI, then 9 Watts will be achieved with 0.707V RMS of input signal. If 8.485 VRMS = (R L ∗ PO ) = (8Ω ∗ 9 W ) Protection Circuits The TA1101B is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI-STATED, and will float to 1/2 of VDD. Over-temperature Protection An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155°C. The thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically clear when the junction temperature drops below 110°C. Over-current Protection An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition. Overload The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit, as the OVERLOADB cannot drive an LED directly. TA1101B, Rev. 2.2, 08.17.00 9 TECHNICAL INFORMATION Sleep Pin The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1MΩ recommended) to VDD. To disable SLEEP mode, the sleep pin should be grounded. Fault Pin The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155°C. All faults except overcurrent all reset upon removal of the condition. The FAULT output is capable of directly driving an LED through a series 200Ω resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an over-current condition. Power Dissipation Derating For operating at ambient temperatures above 25°C the device must be derated based on a 150°C maximum junction temperature, TJMAX as given by the following equation: PDISS = (TJMAX − TA ) θ JA Where θJA of the package is determined from the following graph: Θ JA vs Copper Area JA ( o C/W) 50 40 Pdiss - 1.35W 30 Pdiss - 2W Pdiss - 3.4W 20 10 0 1 2 3 4 5 6 Copper Area (square inches) In the above graph Copper Area is the size of the copper pad on the PC board to which the heat slug of the TA1101B is soldered. The heat slug must be soldered to the PCB to increase the maximum power dissipation capability of the TA1101B package. Soldering will minimize the likelihood of an overtemperature fault occurring during continuous heavy load conditions. The vias used for connecting the heatslug to the copper area on the PCB should be 0.013” diameter. 10 TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION Performance Measurements of the TA1101B The TA1101B operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifier switching pattern will degrade the measurement. One feature of the TA1101B is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TA1101B Evaluation Board uses the Test/Application Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument. TA1101B, Rev. 2.2, 08.17.00 11 TECHNICAL INFORMATION Package Information 30-Lead Power Small Outline Package (PSOP), compliant with JEDEC outline MO-166, variation AD: 2.24 3.10 REF. E3 0.20 +/- 0.10 3.15 +/- 0.15 E E2 2 PLACES E1 3 2 1 30 D1 D2 2 PLACES TOP VIEW BOTTOM VIEW SEE DETAIL "A" 3.35 REF. D e b c 0.15 REF. 4º +/- 4º END VIEW L1 GAUGE PLANE SIDE VIEW L 1.60 REF DETAIL "A" 12 TA1101B, Rev. 2.2, 08.17.00 TECHNICAL INFORMATION Package Dimensions Dimension b c D D1 D2 E E1 E2 E3 e L1 L Min. 0.35 0.23 15.80 12.60 --13.90 10.90 --5.80 0.70 Nom. ----15.90 ----14.20 11.00 ----0.80 BSC. 0.25 BSC. --- Max. 0.48 0.32 16.00 13.00 1.10 14.50 11.10 2.90 6.20 1.00 Note: All dimensions are in millimeters. Tripath, Class T, Combinant Digital, DPP and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies. Tripath Technology Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. For more information on Tripath products, visit our web site at: www.tripath.com TRIPATH TECHNOLOGY, INC. 3900 Freedom Circle Santa Clara, California 95054 408-567-3000 TA1101B, Rev. 2.2, 08.17.00 13