TP112 100Base-TX/FX Converter Feature General Description n 100Base-TX IEEE 802.3u compatible The TP112 is a single chip media converter for n Full and Half duplex with Auto-negotiation 100Base-TX to 100Base-FX. The TP112 support one n Fully integrated adaptive equalizers 100Base-TX port over CAT5 twisted pair cable and one n 125MHz clock generator and clock recovery ECL interface to connect with fiber module to apply in n Include transmit waveform shaping to reduce EMI and 100Base-TX/FX converter application. On the filter 100Base-TX side, The TP112 is directly connected to n Include baseline wander correction external transformers n Support one TX interface and one Fiber module The chip performs data recovery, clock recovery, interface(ECL interface). adaptive equalization, auto negotiation, and baseline n Support transmit, receive/link, full duplex LED wander correction function. The TP112 is compliant with n Single 5 Voltage supply operation the IEEE 802.3u standard. n 128-pin PQFP Typical Application n 100Base-TX to 100Base-FX Converter FX Fiber Module TP112 TX 1 TP112-DS-P02 Jan 5, 2000 TP112 AVCC AGND AGND RXIM 108 107 106 105 AVCC AGND 109 RXIP TXOM 110 103 TXOP 111 104 AGND AVCC 114 112 AVCC 115 113 AVCC AGND 116 NC NC 119 AVCC AGND 120 117 AVCC 121 118 AGND AGND NC 124 122 NC 125 123 AGND AVCC 126 AGND 127 128 PIN Assignments FXRDP 1 102 AGND FXRDM 2 101 AGND FXSD 3 100 NC AVCC 4 99 NC AVCC 5 98 AVCC 97 AVCC NC 6 FXTDM 7 96 NC FXTDP 8 95 NC AGND 9 94 NC BGRES 10 93 AGND BGGND 11 92 DVCC AVCC 12 91 OSCI/X1 DVCC 13 90 X2 DGND 14 89 DGNC FORCEON 15 88 DVCC 16 87 DGND 86 DVCC DGND DVCC DVCC 17 HALFONLY 18 85 TMODE 19 84 NC NC 20 83 DVCC NC 21 82 NC NC 22 81 NC DVCC 23 80 RESET* TP112 58 59 60 61 62 63 64 TXD30 TXER0 NC DVCC DVCC DGND NC RXDV0 57 65 56 38 TXD20 NC NC TXD10 66 55 NC 37 TXD00 MDC MDIO 54 NC 67 53 68 36 DGND 35 TXCLK0 TXCLK1 52 FDXLED* 51 RXER0 69 RXD01 70 34 TXEN0 33 TXD01 50 32 TXD11 RXD11 TXD21 DGND 49 RXCLK0 71 RXD21 72 48 31 RXD31 RXD30 TXD31 47 73 46 RXD20 30 RXER1 DGND TXER1 RXCLK1 RXD10 74 45 75 29 RXDV1 28 44 FXLRLED* NC RXD00 43 76 42 27 DVCC DVCC FXTLED* DGND 77 41 26 DVCC LRLED* DVCC 40 TXLED* 78 39 79 25 NC 24 TXEN1 NC DVCC 2 TP112-DS-P02 Jan 5, 2000 TP112 PIN Description TYPE I O I/O O DESCRIPTION Used as Input pin Used as Output pin Used as Input and Output pin Used as Output with Open Drain PIN NO. Media Connections 104,105 LABEL TYPE RXIP,RXIM I 111,110 TXOP,TXOM O 1,2 FXRDP,FXRDM I 8,7 FXTDP,FXTDM O 3 FXSD I TXER0 TXER1 I 52 39 53 35 58,57,56,55 31,32,33,34 65 45 TXEN0 TXEN1 TXCLK0 TXCLK1 TXD[3:0]0 TXD[3:0]1 RXDV0 RXDV1 I 70 46 RXER0 RXER1 O 72 47 RXCLK0 RXCLK1 O 73,74,75,76 48,49,50,51 RXD[3:0]0 RXD[3:0]1 O MII Interface 59 30 I/O I O3s DESCRIPTION Receiver Pair Differential data from external transformers RD± pair. Transmit Pair Differential data to external transformers TD± pair. Fiber Receiver Data Pair Used to receiver the data from the fiber transceiver module, need external pull high resistor and pull low resistor, depend on impedance match of the fiber transceiver module. Fiber Transmit Data Pair It used as output the data into the fiber transceiver module, need external pull high resistor and pull low resistor, depend on impedance match of the fiber transceiver module. Fiber Signal Detect Used as an input pin from the Fiber transceiver module to indicate a valid signal quality had been detect. Transmit Error Active high. When an error happened in the transmit data stream. Transmit Enable Active high. Indicate 4B data valid on TXD[3:0] Transmit Clock Output is 25MHz continuous clock. Transmit Data Input 4B transmit data. Receive Data valid Active high. Indicates that a received frame is in progress, and data on RXD pin is valid Receive Error It Indicate that there's an error during a receive frame when high Receive Clock 25MHz output. The clock is recovered from the incoming data on the cable inputs Receive Data Output 4B data output and synchronously to RXCLK. 3 TP112-DS-P02 Jan 5, 2000 TP112 PIN Description (continued) PIN NO. Modes 36 LABEL TYPE MDC I 37 MDIO I/O 19 TMODE I 18 HALFONLY I/IPL 15 FORCEON I/IPL 69 FDXLED* O 78 28 LRLED* FXLRLED* O 79 27 Reset & Clock 80 TXLED* FXTLED* O RESET* I 91 OSCI/X1 I 90 X2 O BGRES I BGGND I DESCRIPTION Management Data Clock MII management data clock input, maximum clock rate is 2.5MHz Management Data I/O MII management data input/output Test Mode Active high. Set TP112 into test mode, and low for normal operation. There’s an internal pull low resistor so default is normal operation Half Duplex Mode Only 1: half duplex 0: full duplex Force Mode Enable 1: force mode enable 0: auto negotiation mode enable LEDs Current Reference 10 11 Full Duplex LED Before link OK, this pin is tri-stated. After link OK this pin indicate current duplex operation for TP112. High for half duplex and low for full duplex Link/Receive LED Active low. Indicates the link status of the port, driven low when link to the port is good. Output for 20mS clock while the TP112 is receiving data from external media Transmit LED Active low. Indicates that data is being transmitting Reset Active low. Reset TP112, remain low at least 1us. Oscillator input or crystal input (25MHz±50ppm). Crystal output. Leave it unconnected (i.e., as a NC pin) when oscillator is used. Band Gap Resistor A 6.2KOhm 1% resistor that supply 200uA reference current for receive Band Gap Resistor Ground Band gap resistor ground reference input 4 TP112-DS-P02 Jan 5, 2000 TP112 PIN Description (continued) PIN NO. Power & Ground 4,5,12,97,98, 103,108,112, 114,117,116 121,126 9,93,101,102, 106,107,109, 113,115,120, 122,123,127, 128 13,16,17,23, 25,26,41,43, 61,62,77,83, 86,88,92, 14,29, 42,54,63,71, 85,87,89 6,20,21,22,24, 38,40,44,60,64, 66,67,68,81,82, 84,94,95,96, 99,100,118,119, 124,125 LABEL TYPE AVCC I Analog VCC +5V AGND I Analog Ground 0V DVCC I Digital VCC +5V DGND I Digital Ground 0V NC DESCRIPTION No Connection 5 TP112-DS-P02 Jan 5, 2000 TP112 Absolute Maximum Rating Supply Voltage ....................... VCC –0.25 to VDD +0.25V Stresses above those listed under Absolute Maximum Storage Temperature ....................................-65 to 150°C Ratings may cause permanent damage to the device. Ambient Operating Temperature (Ta).................0 to 70°C Functional operation under these conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect product reliability. Electrical n Operating Conditions Parameter Sym. AVCC DVCC ICC Supply Voltage Power Consumption n Sym. Frequency Frequency Tolerance Max. 5.25 5.25 Unit V V W Conditions VCC=5.0V Min. Typ. 25 -50 Max. Unit MHz PPM Conditions Unit V V V V Conditions IOH=4mA, VCC=5.0V IOL=4mA, VCC=5.0V Max. Unit Conditions 1.05 102 5 0.5 0.5 5 V % ns ns ns % +50 I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High voltage n Typ. 5 5 TBD Input Clock Parameter n Min. 4.75 4.75 I I O O Sym. VIL VIH VOL VOH Min. Typ. Max. 0.8 2.0 0.4 2.4 TX Transceiver Electrical Characteristics Parameter Peak Differential Output Voltage Signal Amplitude Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot Sym. VP TRF TRFS VO Min. Typ. Transmitter 0.95 1.0 98 100 3 4 6 TP112-DS-P02 Jan 5, 2000 TP112 Order Information Part No. TP112 PIN 128 PIN PQFP Notice - 7 TP112-DS-P02 Jan 5, 2000 TP112 Package Detail QFP 128L Outline Dimensions Unit: Inches/mm HD D 103 128 E HE 102 1 65 38 39 64 b GAGE PLANE D L1 Symbol L A1 c A2 e y Dimensions In Inches Dimensions In mm Min. Nom. Max. Min. Nom. Max. A1 0.010 0.014 0.018 0.25 0.35 0.45 A2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c HD 0.004 0.006 0.008 0.09 0.15 0.20 0.669 0.677 0.685 17.00 17.20 17.40 D 0.547 0.551 0.555 13.90 14.00 14.10 HE 0.906 0.913 0.921 23.00 23.20 23.40 E 0.783 0.787 0.791 19.90 20.00 20.10 e - 0.020 - - 0.50 1.03 L 0.025 0.035 0.041 0.65 0.88 L1 - 0.063 - - 1.60 - y - - 0.004 - - 0.10 θ 0° - 12° 0° - 12° Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 8 TP112-DS-P02 Jan 5, 2000