EM MICROELECTRONIC-MARIN SA V6118 2, 4 and 8 Multiplex LCD Driver Typical Operating Configuration Features nV 6118 2 is 2 way multiplex with 2 rows and 38 columns nV 6118 4 is 4 way multiplex with 4 rows and 36 columns nV 6118 8 is 8 way multiplex with 8 rows and 32 columns nLow dynamic current, 150 µA max. o nLow standby current, 1 µA max. at 25 C nVoltage bias and mux signal generation on chip nDisplay refresh on chip, 40 x 8 RAM for display storage nDisplay RAM addressable as 8, 40 bit words nColumn driver only mode to have 40 column outputs nCrossfree cascadable for large LCD applications nSeparate logic and LCD supply voltage pins nWide power supply range, VDD: 2 to 6 V, VLCD: 2 to 8 V nBLANK function for LCD blanking on power up etc. nVoltage bias inputs for applications with large pixel sizes nBit mapped nSerial input / output nVery low external component count o o n-40 C to +85 C temperature range nNo busy states nLCD updating synchronized to the LCD refresh signal n QFP52 and TAB packages V6118 8 Description The V 6118 is a universal low multiplex LCD driver. The Version V 6118 2 drives two ways multiplex (two blackplanes) LCD, the version V 6118 4, four way multiplex LCD, and the V 6118 8, eight way multiplex LCD. The display refresh is handled on chip via a 40 x 8 bit RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 40 x 8 bit RAM ( a set bit corresponds to an activated LCD pixel). The V 6118 has very low dynamic current consumption, 150 µA max., making it particularly attractive for portable and battery powered applications. The wide operating range on both the logic (VDD) and the LCD (VLCD) supply voltages offers much application flexibility. The LCD bias generation is internal. The voltage bias levels can also be provided externnally for applications having large pixels sizes. The V 6118 can be used as a column only driver for cascading in large display applications. In the column only mode, 40 column Outputs available to address the display. A BLANK function is provided to blank the LCD, useful at power up to hold the display blank until the microprocessor has updated the display RAM. QFP52 V6118 Applications nBalances and scales nAutomotive displays nUtility meters nLarge displays (public information panels etc.) nPagers nPortable, battery operated products nTelephones 1 V6118 2/4/8 Absolute Maximum Ratings Handling Procedures VDD VLCD VLOGIC -0.3V to +8V -0.3V to +9V -0.3V to VDD+0.3V VDISP TSTO PMAX -0.3V to VLCD+0.3V - 65 to +150 oC 100 mW VSMAX TS 1000V 250 oC x 10 s This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Electrical Characteristics ILCD IDD IDD IDD ISS IIN CIN VIL 1) See note 1) See note at TA = + 25 oC 1) See note 2) See note 3) See note at TA = + 25 oC 0 < VIN < VDD o at TA = + 25 C VIH VIH 1) VOH VOL IH = 4 mA IL = 4 mA ROUT ROUT ROUT RBIAS RBIAS RBIAS ±VDC IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V IOUT = 10 µA, VLCD = 7 V IOUT = 10 µA, VLCD = 3 V IOUT = 10 µA, VLCD = 2 V See tables 4a and 4b, VLCD = 5 V 100 0.1 3 200 0.1 150 1 12 250 1 µA µA µA µA µA 1 8 100 0 0.8 nA pF V 2.0 3.0 VDD VDD V V 0.4 V V 2.4 0.5 1.2 9 16 18 30 1.5 2.5 30 50 All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD. 2) All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD. 3) All outputs open, all inputs at VDD. 4) This is the impedance between the voltage bias level pins (V1, V2, or V3) and the output pins S1 to S40 when a given voltage bias level is driving the outputs (S1 to S40). 5) This is the impedance seen at the segment pin. Outputs measured one at a time. 2 20 25 kΩ kΩ kΩ kΩ kΩ kΩ mV Table 3 V6118 2/4/8 Column Drivers S1 to S40 S1 to S40 logic 1 logic 0 logic 0 logic 0 logic 1 logic 1 | Sx* - VSS | | VLCD - Sx* | S1 to S40 S1 to S40 logic 1 logic 0 logic 0 logic 0 logic 0 logic 0 | VLCD - Sx* | | Sx* - VSS | | VLCD - Sx* | = | Sx* - VSS | ± 25mV | VLCD - Sx* | = | Sx* - VSS | ± 25 mV Row Drivers Timing Characteristics VDD = 5.0 V ± 10%, VLCD = 2 to 8 V, and TA = -40 to +85oC Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling tCH tCL tCR tCF tDS tDH tPD tSTR tP tD FR frequency (Vers. 2/4/8) FFR Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width CLK falling to STR rising STR falling to CLK falling FR frequency (Vers. 2/4/8) tCH tCL tCR tCF tDS tDH tPD tSTR tP tD FFR 120 120 200 200 1) 20 1) 30 CLOAD = 50 pF 100 100 10 200 2) 128/256/512 Hz 128/256/512 ns ns ns ns ns ns ns ns ns µs Hz 500 500 200 200 1) 100 1) 150 CLOAD = 50 pF 400 500 10 1 2) 3 ns ns ns ns ns ns ns ns ns ns V6118 2/4/8 V 6118 as a row and column driver (COL inactive) 40 bit load cycle, RAM address provided by address bit 1 to (n*) CLK DI 1) STR * n = the V6118 version number (i.e. 2,4, or 8) A set address bit corresponds to a write enabled RAM Address, the same data can be written to more than one RAM address by setting the required address bits. CLK DI Col39 STR 1) A set address bit corresponds to a write enabled RAM address,the same data can be written to more than one RAM address by setting the required address bits. 4 V6118 2/4/8 X 40 bit display latch 40 display driver outputs 5 V6118 2/4/8 Name S1...S40 V3 V2 V1 VLCD FR DI DO CLK STR COL VSS Function LCD outputs, see table 7 LCD voltage bias level 31)2) LCD voltage bias level 21) LCD voltage bias level 11) Power supply for the LCD AC input signal for LCD driver outputs Serial data input Serial data output Data clock input Data strobe, blank, synchronize input Power supply for logic Column only driver mode Supply GND 1) The V6118 has internal voltage bias level generation.When driving large pixels, an external resistor divider chain can be connected to the voltage bias level inputs to obtain enhanced display contrast (see Fig. 12, 13 and 14). The external resistor divider ratio should be in accordance with the internalresistor ratio (see table 8). 2) V3 is connected internally on the V6118 4. LCD Voltage Bias Levels VOP (*) VOFF (rms) VON (rms) VOFF 1+ = 1+ 6 = V6118 2/4/8 Row and Column Multiplexing Waveform V6118 2 VOP = VLCD - VSS, VSTATE = VCOL - VROW TFRAME =2/(FR frequency) VDD FR VSS State1 State2 VLCD Row1 Row2 V1 V2 V3 VSS VLCD V1 V2 V3 VSS Col1 Col2 VLCD V1 V2 V3 VSS VLCD V1 V2 V3 VSS 2.43VOP/2.86 VOP/2.86 0.43VOP/2.86 State1* 0 -0.43VOP/2.86 -VOP/2.86 -2.43VOP/2.86 2.43VOP/2.86 VOP/2.86 0.43VOP/2.86 State2* 0 -0.43VOP/2.86 -VOP/2.86 -2.43VOP/.86 Fig. 7 *See Table 8 7 V6118 2/4/8 Row and Column Multiplexing Waveform V6118 4 VOP = VLCD - VSS, VSTATE = VCOL - VROW 8 V6118 2/4/8 9 V6118 2/4/8 Functional Description The display RAM word length is 40 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When down loading data to the V 6118 any display RAM address can be chosen, there is no display RAM addressing sequence (see Fig. 4 and 5). The same data can be written to more than one display RAM address. If more than one address bit is set, then more than one display RAM address is write enabled, and so the same data is written to more than one address. This feature can be useful to flash the LCD on and off under software control. If the address bits are all zero then no display RAM is write enabled and no data is written to the display RAM on the falling edge of STR. Use address 0 to synchronize cascaded V 6118s without updating the display RAM. Supply Voltage VLCD, VDD, VSS The voltage between VDD and VSS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias levels. The internal LCD bias levels have a maximum impedance of 25 kΩ for a VLCD voltage from 3 to 8 V. Without external connections to the V1, V2, and V3 bias level inputs, the V 6118 can drive mostmedium sized LCD (pixel area 2 up to 4'000 mm ). For displays with a wide variation in pixel sizes the configuration shown in Fig. 13 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9 ) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. If for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V 6118. An external bias level generation circuit can lower the bias level impedance and hence improve the LCD contrast (see Fig. 12). The optimum values of R, Rx, and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. 2 For LCD with every large average pixel size up to 10'000 mm , the bias level configuration shown in Fig. 14 should be used. When V 6118s are cascaded connect the V1, V2, and V3 bias inputs are shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give enhanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V 6118 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 12.5 KΩ for a VLCD voltage from 3 to 8 V. Table 8 shows the relationship between V1, V2, and V3 for multiplex rates 2, 4 and 8. Note that VLCD>V1>V2>V3 for the V 6118 2 and V 6118 8, and for the V 6118 4, VLCD>V1>V2. CLK Input The CLK is used to clock the DI serial data into the shift register and to clock the DO serial data out. Loading and shifting of data occurs at the falling edge of this clock, outputting of the data at the rising edge (see Fig. 3). When cascading devices, all CLK lines should be tied together (see Fig. 10). STR Input The STR input is used to write to the display RAM, blank the LCD, and synchronize cascaded V 6118s. The STR input writes the data loaded into the shift register, on the DI input, to the display RAM on the falling edge of the STR signal. The display RAM address is given by the address bits (see Fig. 4 and 5). The STR input when high blanks the LCD by disconnecting the internal voltage bias generation from the VSS potential. Segment outputs S1 to S40 (rows and columns) are pulled up to VLCD. The delay to driving the LCD with VLCD on S1 to S40, is dependent on the capacitive load of the LCD and is typically 1 µs. An LCD pixel responds to RMS voltage and takes approximately 100 ms to turn on or off. The delay from putting STR high to the LCD being blank is dependent on the LCD off time and is typically 100 ms. In applications, which have a long STR pulse width (10 µs), the LCD is driven by VLCD on both the rows and columns during this time. As the time is short (1 µA), it will have zero measurable effect on the RMS "on" value (over 100 ms) of an LCD pixel and also zero measurable effect on the pixel DC component. Such STR pulses will not be visible to the human eye on an LCD. Data Input/ Output The data input pin, DI, is used to load serial data into the V 6118. The serial data word length is 40 bits when COL is inactive, and 48 bits when it is active. Data is loaded in inverse numerical order, the data for bit 40 (bit 48 when COL is active) is loaded first with the data for bit 1 last. The column data bits are loaded first and then the address bits (see Fig. 4 and 5). The data output pin, DO, is used in cascaded applications (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 40 clock periods, when COL is inactive and 48 clock periods when COL is active. In order to cascade V 6118s, DOofonechipmustbeconnected to DI of the following chip (see Fig. 10). In cascaded applications the data of the last V 6118 (the one that does not have DO connected) must be loaded first and the data for the first V6118 (its DI is connected to the processor) loaded last (see Fig. 10). Note if an external voltage bias generation circuit is used as shown in Fig. 12 and 14, the LCD blank function (STR high) will not blank the LCD. When STR is high the LCD will be driven by the parallel combination of the external voltage bias generation circuit and part of the internal voltage bias generation circuit. The STR input, when high, synchronizes cascaded V 6118s by forcing a new time frame to begin at the next falling edge of the FR input signal (see Fig.6). A time frame begins with row 1 and so the LCD picture is rebuilt from row 1 each time 10 V6118 2/4/8 to one relationship between the display RAM and the LCD driver outputs. Each pixel (segment) driven by the V 6118 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the segment "on" and clearing it turns it "off". cascaded V 6118s are synchronized.Whencascading devices, all STR lines must be tied together (see Fig. 10). FR input The FR signal controls the segment output frequency generation (see Fig. 7,8 and 9). To avoid having DC on the display, the FR signal must have a 50% duty cycle. The frequency of the FR signal must be n times the desired display refresh rate, where n is the V 6118 version no. (2,4 or 8). For example, if the desired refresh rate is 40 Hz, the FR signal frequency must be 320 Hz for the V6118 8. A selected row (on) is in phasewith the FR signal (see Fig. 7, 8 and 9). It is recommended that data transfer to the V 6118 should be synchronized to the FR signal to avoid a falling or rising edge on the FR signal while writing data to the V 6118. The LCD pixels change polarity with the FR signal. On the edges of the FR signal current spikes will appear on the VSS and VLCD supply lines. If the supply lines have high impedance then voltage spikes will appear. These voltage spikes could interfere with data loading on the DI and CLK pins. COL Input The V 6118 functions as a row and column driver while the COL is inactive. When active the COL input configures the V 6118 to function as a column driver only. The former row outputs function as column outputs. In cascaded applications one V6118 should be used in the row column configuration (COL inactive) and the rest as pure column drivers (COL active) (see Fig. 10). Note when cascading V 6118s never cascades one version with another. If a V6118 8 is used to drive the rows then only V 6118 8s can be cascaded with it.When COL is active the V 6118 needs 48 bits of data in a load cycle. 40 bits are used for the column data and 8 bits to address the display RAM regardless of V 6118 version (2, 4 or 8) (see Fig. 4, 5 and 10). Power Up On power up the data is shift registers, the display RAM and the 40-bit display latch are undefined. The STR input should be taken high on power up to blank the display, and then the display data written to the display RAM (see Fig. 11). When finished the initial write to the display RAM, take the STR input low to display the display RAM contents (see also section “STR Input"). Driver output S1 to S40 There are 40 LCD driver outputs on the V 6118. When COL is inactive the outputs S1 to Sn function as row drivers and the outputs S(n + 1) to S40 function as column drivers, where n is the V 6118 version no. (2,4 or 8). When COL is active, all 40 outputs function as column drivers (see table 6). There is a one 11 V6118 2/4/8 V6118 8 By connecting the V1, V2 and V3 bias inputs as shown, the pixel load is averaged across all the drivers. The sffective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V 6118 are cascaded as above, then the maximum bias level impedance becomes 12. 5 k . 1) When themicroprocessor is reset, the port pin will be configured as an input and so the STR line would float. The pullup resistor will ensure that the LCD is blank while the system reset line is active and after until the port pin is setup by software. 12 V6118 2/4/8 V6118 8 13 V6118 2/4/8 Package and Ordering Informatiion Ordering Information The V 6118 is available in the following packages: QFP52, pin plastic package V 6118 2 52F V 6118 4 52F V 6118 8 52F TAB, tape automated bonding V 6118 2 TAB V 6118 4 TAB V 6118 8 TAB Chip form V 6118 2Chip* V 6118 4 Chip* V 6118 8 Chip' * on request When ordering, please specify the complete part number and package. EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin product. EM Microelectronic-Marin reserves the right to change circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. 1997 EM Microelectronic-Marin SA, 09/97, Rev. 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