ETC VT8231

Z.4330.9
H
97
6RXWK%ULGJH
3&&203/,$17
,17(*5$7('683(5,2)'&/37&20$1'),5
,17(*5$7(')$67(7+(51(7/3&,6$/3&%,26520
,17(*5$7('6281'%/$67(535208/7,&+$11(/
',5(&76281'$&$8',2$1'0&02'(0,17(5)$&(
8/75$'0$0$67(502'((,'(&21752//(5
325786%&21752//(5.(<%2$5'&21752//(557&
6(5,$/,5460%866(5,$/((3520
3/8*$1'3/$<$&3,(1+$1&('32:(50$1$*(0(17
7(03(5$785(92/7$*($1')$163(('021,725,1*
3UHOLPLQDU\5HYLVLRQ
2FWREHU
9,$7(&+12/2*,(6,1&
&RS\ULJKW1RWLFH
&RS\ULJKW
‹ 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG
// 5,*+76 5(6(59('
3ULQWHG LQ WKH 8QLWHG 6WDWHV $
1R SDUW RI WKLV GRFXPHQW PD\ EH UHSURGXFHG WUDQVPLWWHG WUDQVFULEHG VWRUHG LQ D UHWULHYDO V\VWHP RU WUDQVODWHG LQWR
DQ\ ODQJXDJH LQ DQ\ IRUP RU E\ DQ\ PHDQV HOHFWURQLF PHFKDQLFDO PDJQHWLF RSWLFDO FKHPLFDO PDQXDO RU RWKHUZLVH
ZLWKRXW WKH SULRU ZULWWHQ SHUPLVVLRQ RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG
97 PD\ RQO\ EH XVHG WR LGHQWLI\ SURGXFWV RI 9,$ 7HFKQRORJLHV ,QF
LV D UHJLVWHUHG WUDGHPDUN RI 9,$ 7HFKQRORJLHV ,QFRUSRUDWHG
3670 LV D UHJLVWHUHG WUDGHPDUN RI ,QWHUQDWLRQDO %XVLQHVV 0DFKLQHV &RUS
3HQWLXP70 3HQWLXP3UR70 3HQWLXP,,70 3HQWLXP,,,70 &HOHURQ70DQG *7/70 DUH UHJLVWHUHG WUDGHPDUNV RI ,QWHO &RUS
:LQGRZV 70 :LQGRZV 70 :LQGRZV 1770 DQG 3OXJ DQG 3OD\70 DUH UHJLVWHUHG WUDGHPDUNV RI 0LFURVRIW &RUS
3&,70 LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS
$OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV
'LVFODLPHU1RWLFH
1R OLFHQVH LV JUDQWHG LPSOLHG RU RWKHUZLVH XQGHU DQ\ SDWHQW RU SDWHQW ULJKWV RI 9,$ 7HFKQRORJLHV
9,$ 7HFKQRORJLHV
PDNHV QR ZDUUDQWLHV LPSOLHG RU RWKHUZLVH LQ UHJDUG WR WKLV GRFXPHQW DQG WR WKH SURGXFWV GHVFULEHG LQ WKLV GRFXPHQW
7KH LQIRUPDWLRQ SURYLGHG E\ WKLV GRFXPHQW LV EHOLHYHG WR EH DFFXUDWH DQG UHOLDEOH WR WKH SXEOLFDWLRQ GDWH RI WKLV
GRFXPHQW
+RZHYHU 9,$ 7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU DQ\ HUURUV LQ WKLV GRFXPHQW
)XUWKHUPRUH 9,$
7HFKQRORJLHV DVVXPHV QR UHVSRQVLELOLW\ IRU WKH XVH RU PLVXVH RI WKH LQIRUPDWLRQ LQ WKLV GRFXPHQW DQG IRU DQ\ SDWHQW
LQIULQJHPHQWV WKDW PD\ DULVH IURP WKH XVH RI WKLV GRFXPHQW
7KH LQIRUPDWLRQ DQG SURGXFW VSHFLILFDWLRQV ZLWKLQ WKLV
GRFXPHQW DUH VXEMHFW WR FKDQJH DW DQ\ WLPH ZLWKRXW QRWLFH DQG ZLWKRXW REOLJDWLRQ WR QRWLI\ DQ\ SHUVRQ RI VXFK FKDQJH
2IILFHV
86$ 2IILFH
0LVVLRQ &RXUW
)UHPRQW &$
86$
7DLSHL 2IILFH
WK
)ORRU 1R &KXQJ&KHQJ 5RDG +VLQ7LHQ
7DLSHL 7DLZDQ
52&
7HO
7HO
)D[
)D[
2QOLQH6HUYLFHV
)73 6HUYHU
http://www.via.com.tw ¤RU http://www.viatech.com
ftp.via.com.tw
%%6
+RPH 3DJH
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
REVISION HISTORY
Document Release
Revision 0.4
Date
9/17/99
Revision 0.5
Revision 0.6
Revision 0.7
Revision 0.8
9/27/99
10/1/99
10/15/99
10/29/99
Revision
Initial release based on 82C686A “Super South” Data Sheet revision 1.42
Updated feature bullets, document title, and block diagram
Replaced pinout diagram with blank BGA352 template
Added LAN, LPC, and EEPROM pin descriptions, removed signals as req’d
Updated Functions 5 and 6 per engineering input
Added Preliminary Ballout & Mechanical Spec
Updated pin descriptions and pin lists
Updated pinouts to conform to engineering pinout revision 0.4 dated 10/6/99
Updated feature bullets and performed partial edit of Overview text
Updated pinouts per engineering pinout rev 0.6 / pinlist rev 0.2 dated 10/20/99
Updated Electrical Specs and added “output drive” and “input voltage” tables
Preliminary Revision 0.8 October 29, 1999
-i-
Initials
DH
DH
DH
DH
DH
Revision History
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
TABLE OF CONTENTS
REVISION HISTORY........................................................................................................................................................................I
TABLE OF CONTENTS.................................................................................................................................................................. II
LIST OF FIGURES..........................................................................................................................................................................IV
LIST OF TABLES ...........................................................................................................................................................................IV
OVERVIEW ....................................................................................................................................................................................... 5
PINOUTS ............................................................................................................................................................................................ 7
PIN DIAGRAM................................................................................................................................................................................. 7
PIN LISTS........................................................................................................................................................................................ 8
PIN DESCRIPTIONS....................................................................................................................................................................... 10
REGISTERS ..................................................................................................................................................................................... 29
REGISTER OVERVIEW ................................................................................................................................................................. 29
REGISTER DESCRIPTIONS............................................................................................................................................................ 41
Legacy I/O Ports ................................................................................................................................................................... 41
Keyboard Controller Registers.............................................................................................................................................................. 42
DMA Controller I/O Registers .............................................................................................................................................................. 44
Interrupt Controller Registers ............................................................................................................................................................... 45
Timer / Counter Registers ..................................................................................................................................................................... 45
CMOS / RTC Registers......................................................................................................................................................................... 46
Super-I/O Configuration Index / Data Registers ............................................................................................................... 47
Super-I/O Configuration Registers ..................................................................................................................................... 47
Super-I/O I/O Ports .............................................................................................................................................................. 50
Floppy Disk Controller Registers.......................................................................................................................................................... 50
Parallel Port Registers........................................................................................................................................................................... 51
Serial Port 1 Registers........................................................................................................................................................................... 52
Serial Port 2 Registers........................................................................................................................................................................... 53
SoundBlaster Pro Port Registers......................................................................................................................................... 54
FM Registers ......................................................................................................................................................................................... 54
Mixer Registers ..................................................................................................................................................................................... 54
Sound Processor Registers .................................................................................................................................................................... 54
Game Port Registers ............................................................................................................................................................. 55
PCI Configuration Space I/O............................................................................................................................................... 56
Function 0 Registers - PCI to ISA Bridge........................................................................................................................... 57
PCI Configuration Space Header .......................................................................................................................................................... 57
ISA Bus Control.................................................................................................................................................................................... 57
Plug and Play Control ........................................................................................................................................................................... 61
Distributed DMA / Serial IRQ Control ................................................................................................................................................. 63
Miscellaneous / General Purpose I/O.................................................................................................................................................... 64
Function 1 Registers - Enhanced IDE Controller .............................................................................................................. 69
PCI Configuration Space Header .......................................................................................................................................................... 69
IDE-Controller-Specific Confiiguration Registers ................................................................................................................................ 71
IDE I/O Registers.................................................................................................................................................................................. 76
Function 2 Registers - USB Controller Ports 0-1 ............................................................................................................... 77
PCI Configuration Space Header .......................................................................................................................................................... 77
USB-Specific Configuration Registers.................................................................................................................................................. 78
USB I/O Registers................................................................................................................................................................................. 79
Function 3 Registers - USB Controller Ports 2-3 ............................................................................................................... 80
PCI Configuration Space Header .......................................................................................................................................................... 80
USB-Specific Configuration Registers.................................................................................................................................................. 81
USB I/O Registers................................................................................................................................................................................. 82
Preliminary Revision 0.8 October 29, 1999
-ii-
Table of Contents
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 4 Regs - Power Management, SMBus and HWM.............................................................................................. 83
PCI Configuration Space Header .......................................................................................................................................................... 83
Power Management-Specific PCI Configuration Registers .................................................................................................................. 84
Hardware-Monitor-Specific Configuration Registers ........................................................................................................................... 91
System Management Bus-Specific Configuration Registers ................................................................................................................. 91
Power Management I/O-Space Registers .............................................................................................................................................. 92
System Management Bus I/O-Space Registers.................................................................................................................................... 101
Hardware Monitor I/O Space Registers .............................................................................................................................................. 104
Function 5 & 6 Registers - AC97 Audio & Modem Codecs ............................................................................................ 108
PCI Configuration Space Header – Function 5 Audio ........................................................................................................................ 108
PCI Configuration Space Header – Function 6 Modem...................................................................................................................... 109
Function 5 & 6 Codec-Specific Configuration Registers .................................................................................................................... 110
Function 5 I/O Base 0 Regs – DXSn Scatter/Gather DMA................................................................................................................. 112
Function 5 I/O Base 1 Registers –Audio FM NMI Status................................................................................................................... 117
Function 5 I/O Base 2 Registers –MIDI / Game Port.......................................................................................................................... 117
Function 6 I/O Base 0 Regs –Modem Scatter/Gather DMA ............................................................................................................... 118
FUNCTIONAL DESCRIPTIONS ................................................................................................................................................ 120
POWER MANAGEMENT .............................................................................................................................................................. 120
Power Management Subsystem Overview .......................................................................................................................................... 120
Processor Bus States ........................................................................................................................................................................... 120
System Suspend States and Power Plane Control ............................................................................................................................... 121
General Purpose I/O Ports................................................................................................................................................................... 121
Power Management Events ................................................................................................................................................................. 122
System and Processor Resume Events ................................................................................................................................................ 122
Legacy Power Management Timers .................................................................................................................................................... 123
System Primary and Secondary Events ............................................................................................................................................... 123
Peripheral Events ................................................................................................................................................................................ 123
ELECTRICAL SPECIFICATIONS............................................................................................................................................. 124
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................... 124
DC CHARACTERISTICS.............................................................................................................................................................. 124
OUTPUT DRIVE .......................................................................................................................................................................... 125
INPUT VOLTAGE ........................................................................................................................................................................ 125
PACKAGE MECHANICAL SPECIFICATIONS ...................................................................................................................... 126
Preliminary Revision 0.8 October 29, 1999
-iii-
Table of Contents
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
LIST OF FIGURES
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 8.
PC SYSTEM CONFIGURATION USING THE VT8231......................................................................................... 6
VT8231 BALL DIAGRAM (TOP VIEW) .................................................................................................................. 7
VT8231 PIN LIST (NUMERICAL ORDER) ............................................................................................................. 8
VT8231 PIN LIST (ALPHABETICAL ORDER) ...................................................................................................... 9
STRAP OPTION CIRCUIT....................................................................................................................................... 62
POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ......................................................................... 120
MECHANICAL SPECIFICATIONS – 376 PIN BALL GRID ARRAY PACKAGE......................................... 126
LIST OF TABLES
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
PIN DESCRIPTIONS................................................................................................................................................... 10
SYSTEM I/O MAP ....................................................................................................................................................... 29
REGISTERS.................................................................................................................................................................. 30
KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 43
CMOS REGISTER SUMMARY................................................................................................................................. 46
Preliminary Revision 0.8 October 29, 1999
-iv-
Table of Contents
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
VT8231
SOUTH BRIDGE
PC99 COMPLIANT
INTEGRATED SUPER-I/O (FDC, LPT, COM, AND FIR),
INTEGRATED FAST ETHERNET, LPC, ISA / LPC BIOS ROM,
INTEGRATED SOUNDBLASTER PRO / MULTICHANNEL
DIRECT SOUND AC97 AUDIO AND MC97 MODEM INTERFACE,
ULTRADMA-33/66/100 MASTER MODE EIDE CONTROLLER,
4 PORT USB CONTROLLER, KEYBOARD CONTROLLER, RTC,
SERIAL IRQ, SMBUS, SERIAL EEPROM,
PLUG AND PLAY, ACPI, ENHANCED POWER MANAGEMENT,
TEMPERATURE, VOLTAGE, AND FAN-SPEED MONITORING
•
Inter-operable with VIA and other Host-to-PCI Bridges
− Combine with VT82C598 for a complete Super-7 (66 / 75 / 83 / 100MHz) AGP 2x system (Apollo MVP3)
− Combine with VT8501 for a complete Super-7 system with integrated 2D / 3D graphics (Apollo MVP4)
− Combine with VT82C694X for a complete 66 / 100 / 133 MHz Socket370 / Slot1 AGP 4x system (Apollo Pro133A)
− Combine with VT8601 for a complete 66 / 100 / 133 MHz Socket370 / Slot1 system with integrated 2D / 3D
graphics (Apollo ProMedia)
− Inter-operable with Intel or other Host-to-PCI bridges for a complete PC99 compliant PCI / AGP / LPC system
•
Integrated Peripheral Controllers
− Integrated Fast Ethernet Controller with 1 / 10 / 100 Mbit capability
− Integrated USB Controller with two root hub and four function ports
− Dual channel UltraDMA-33 / 66 /100 master mode EIDE controller
− AC-link interface for AC-97 audio codec and modem codec
− HSP modem support
− Interface for optional external modem DSP
− Integrated SoundBlasterPro / DirectSound compatible digital audio controller
− LPC interface for Low Pin Count interface to Super-I/O or ROM
•
Integrated Legacy Functions
− Integrated Keyboard Controller with PS2 mouse support
− Integrated DS12885-style Real Time Clock with extended 256 byte CMOS RAM and Day/Month Alarm for ACPI
− Integrated Bus Controller including DMA, timer, and interrupt controller
− Serial IRQ for docking and non-docking applications
− Flash EPROM, 32Mbit (4Mbyte) EPROM and combined BIOS support
− Fast reset and Gate A20 operation
Preliminary Revision 0.8 October 29, 1999
-1-
Features
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
•
Fast Ethernet Controller
− High performance PCI master interface with scatter / gather and bursting capability
− Standard MII interface to PHYceiver
− 1 / 10 / 100 MHz full and half duplex operation
− Transmit data buffer byte alignment for low CPU utilization
− Separate 2K byte FIFOs for receive and transmit of full Ethernet packets
− Flexible dynamically loadable EEPROM algorithm
− Physical, Broadcast, and Multicast address filtering using hashing function
− Flexible wakeup events: link status change, magic packet, unicast physical address match, predefined pattern match
− Software controllable power down
•
UltraDMA-33 / 66 / 100 Master Mode PCI EIDE Controller
− Dual channel master mode PCI supporting four Enhanced IDE devices
− Transfer rate up to 100MB/sec to cover up to PIO mode 4, multi-word DMA mode 2, and UltraDMA mode 5
− Thirty-two levels (doublewords) of prefetch and write buffers per channel
− Dual DMA engine for concurrent dual channel operation
− Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 / 98 / 2000 compliant
− Full scatter gather capability
− Support ATAPI compliant devices including DVD devices
− Support PCI native and ATA compatibility modes
− Complete software driver support
•
Integrated Super IO Controller
− Supports 2 serial ports, IR port, parallel port, and floppy disk controller functions
− Two UARTs for Complete Serial Ports
−
−
−
Programmable character lengths (5,6,7,8)
Even, odd, stick or no parity bit generation and detection
Programmable baud rate generator
High speed baud rate (230Kbps, 460Kbps) support
Independent transmit/receiver FIFOs
Modem Control
Plug and play with 96 base IO address and 12 IRQ options
Fast IR (FIR) port
IrDA 1.0 SIR and IrDA 1.1 FIR compliant
IR function through the second serial port
Infrared-IrDA (HPSIR) and ASK (Amplitude Shift Keyed) IR
Multi-mode parallel port
Standard mode, ECP and EPP support
Dynamic and static switch between parallel port pinout and FDC pinout
Plug and play with 192 base IO address, 12 IRQ and 4 DMA options
Floppy Disk Controller
16 bytes of FIFO
Data rates up to 1Mbps
Perpendicular recording driver support
Two FDDs with drive swap support
Plug and play with 48 base IO address, 12 IRQ and 4 DMA options
Preliminary Revision 0.8 October 29, 1999
-2-
Features
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
•
SoundBlaster Pro Hardware and Direct Sound Ready AC97 Digital Audio Controller
− Up to six concurrent AC97 output channels for six-speaker surround sound experience
− Multiple Direct Sound channels between system memory and AC97 link
−
−
−
−
−
−
−
−
−
−
10 Direct Sound output channels
4 Direct Sound input channels
8-channel hardware sample-rate-converter / mixer
1 Surround Sound channel of up to six data streams
PCI bus master interface with scatter / gather and bursting capability
32 byte FIFO for each direct sound channel
Host based wave table synthesis
Standard v1.03 or v2.1 AC97 Codec interface with up to four AC97 codec’s from multiple vendors
Loopback capability for re-directing mixed audio streams into USB and 1394 speakers
Hardware SoundBlaster Pro for legacy compatibility
Plug and play with 4 IRQ, 4 DMA, and 4 I/O space options for SoundBlaster Pro and MIDI hardware
Hardware assisted FM synthesis for legacy compatibility
Direct two game ports and one MIDI port interface
Complete software driver support for Windows-95 / 98 / 2000 and Windows-NT
•
MC97 HSP Modem Controller
− PCI bus master interface with scatter / gather and burst capability
− Standard AC97 codec interface for MC or AMC codec
− Wake on ring in APM or ACPI mode through AC97 link
− Supported by most HSP modem vendors
•
Universal Serial Bus Controller
− USB v.1.1 and Intel Universal HCI v.1.1 compatible
− Eighteen level (doublewords) data FIFO with full scatter and gather capability
− Root hub and four function ports
− Integrated physical layer transceivers with optional over-current detection status on USB inputs
− Legacy keyboard and PS/2 mouse support
•
System Management Bus Interface
− One master / slave SMBus and one slave-only SMBus
− Host interface for processor communications
− Slave interface for external SMBus masters
Preliminary Revision 0.8 October 29, 1999
-3-
Features
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
•
Voltage, Temperature, Fan Speed Monitor and Controller
− Five universal input channels for voltage or temperature sensing
− Two fan-speed monitoring channels
− Input channel for thermal diode in Intel™ high speed Pentium II™ / Pentium III™ CPUs
− Programmable control, status, monitor and alarm for flexible desktop management
− External thermister or internal bandgap temperature sensing
− Automatic clock throttling with integrated temperature sensing
− Internal core VCC voltage sensing
− Flexible external voltage sensing arrangement (any positive supply and battery)
•
Sophisticated PC99-Compatible Mobile Power Management
− Supports both ACPI (Advanced Configuration and Power Interface) and legacy (APM) power management
− ACPI v1.0 Compliant
− APM v1.2 Compliant
− CPU clock throttling and clock stop control for complete ACPI C0 to C3 state support
− PCI bus clock run, Power Management Enable (PME) control, and PCI/CPU clock generator stop control
− Supports multiple system suspend types: power-on suspends with flexible CPU/PCI bus reset options,
−
−
−
−
−
−
−
−
−
−
−
−
−
•
suspend to DRAM, and suspend to disk (soft-off), all with hardware automatic wake-up
Multiple suspend power plane controls and suspend status indicators
One idle timer, one peripheral timer and one general purpose timer, plus 24/32-bit ACPI compliant timer
Normal, doze, sleep, suspend and conserve modes
Global and local device power control
System event monitoring with two event classes
Primary and secondary interrupt differentiation for individual channels
Dedicated input pins for power and sleep buttons, external modem ring indicator, and notebook lid open/close for
system wake-up
Multiple internal and external SMI sources for flexible power management models
One programmable chip select and one microcontroller chip select
Enhanced integrated real time clock (RTC) with date alarm, month alarm, and century field
Thermal alarm on either external or any combination of three internal temperature sensing circuits
Hot docking support
I/O pad leakage control
Plug and Play Controller
− PCI interrupts steerable to any interrupt channel
− Steerable interrupts for integrated peripheral controllers: USB, floppy, serial, parallel, audio, soundblaster, MIDI
− Steerable DMA channels for integrated floppy, parallel, and soundblaster pro controllers
− One additional steerable interrupt channel for on-board plug and play devices
− Microsoft Windows 2000TM, Windows 98SETM, Windows 98TM, Windows NTTM, Windows 95TM and plug and play
BIOS compliant
•
Built-in NAND-tree pin scan test capability
•
0.30um, 3.3V, low power CMOS process
•
Single chip 27x27 mm, 376 pin BGA
Preliminary Revision 0.8 October 29, 1999
-4-
Features
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
OVERVIEW
The VT8231 South Bridge is a high integration, high performance, power-efficient, and high compatibility device that supports
Intel, AMD, and VIA / Cyrix based processor to PCI bus bridge functionality to make a complete Microsoft PC99-compliant PCI /
LPC system. The VT8231 includes standard intelligent peripheral controllers:
a) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands. Dedicated
FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE
devices. In addition to standard PIO and DMA mode operation, the VT8231 also supports the UltraDMA-33, 66, and 100
standards to allow reliable data transfer rates up to 100 MB/sec throughput. The IDE controller is SFF-8038i v1.0 and
Microsoft Windows-family compliant.
b) Integrated LAN Fast Ethernet controller (MAC) with Media Independent Interface (MII) to external PHY. The LAN
controller operates at 1 / 10 / 100 Mbit/sec transfer rates using either full and half duplex operation and has separate 2Kbyte
FIFOs for receive and transmit of full ethernet packets. The internal high-performance PCI interface has scatter / gather and
bursting capability and can align bytes in the transmit data buffer to reduce CPU utilization. The LAN interface can perform
address filtering on physical, broadcast, and multicast packets. The interface can also be configured for system wake up on
link status change, receipt of magic packet, unicast physical address match on incoming packets, and predefined pattern
match in the incoming data.
c) LPC (Low Pin Count) interface for BIOS ROM plus optional conventional BIOS ROM support
d) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT8231 includes the root hub with
four function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous
peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and
mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.
e) Keyboard controller with PS2 mouse support
f) Real Time Clock with 256 byte extended CMOS. In addition to standard RTC functionality, the integrated RTC also includes
the date alarm, century field, and other enhancements for compatibility with the ACPI standard.
g) Notebook-class power management functionality compliant with ACPI and legacy APM requirements. Multiple sleep states
(power-on suspend, suspend-to-DRAM, and suspend-to-Disk) are supported with hardware automatic wake-up. Additional
functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control,
modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip
select and external SMI.
h) Hardware monitoring subsystem for managing system / motherboard voltage levels, temperatures, and fan speeds
i) Full System Management Bus (SMBus) interface with one master / slave port and one slave-only port
j) 16550-compatible serial I/O port with “Fast-IR” infrared communications port option.
k) Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system. Hardware soundblaster-pro and
hardware-assisted FM blocks are included for Windows DOS box and real-mode DOS compatibility. Loopback capability is
also implemented for directing mixed audio streams into USB and 1394 speakers for high quality digital audio.
l) Game port and MIDI port
m) Standard floppy disk drive interface
n) ECP/EPP-capable parallel port with floppy disk controller pinout option
o) Serial IRQ for docking and non-docking applications
p) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts to any interrupt channel.
One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of on-board peripherals for
Windows family compliance.
Preliminary Revision 0.8 October 29, 1999
-5-
Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
CA
CD
CPU / Cache
MA/Command
MD
North Bridge
DIMM Module ID
Sideband Signals:
Init / CPUreset
IRQ / NMI
SMI / StopClk
FERR / IGNNE
SLP# (Slot-1)
PCI
SMB
LPC
Boot ROM
System Memory
USB Ports 0-3
Keyboard / Mouse
Expansion
MIDI / Game Ports
Cards
Parallel Port
Serial Ports 1 and 2
Infrared Comm Port
IDE Primary and Secondary
Floppy Disk Interface
AC97 Link
Hardware Monitor Inputs
GPIO, Power Control, Reset
Fast Ethernet Interface
VT8231
376 BGA
Onboard
LPC I/O
RTC
Crystal
Figure 1. PC System Configuration Using the VT8231
Preliminary Revision 0.8 October 29, 1999
-6-
Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PINOUTS
Pin Diagram
Figure 2. VT8231 Ball Diagram (Top View)
Key
A
1
AD
30
2
AD
31
3
AD
26
4
AD
24
5
AD
21
6
AD
16
7
DEV
SEL#
8
CBE
1#
9
AD
9
10
AD
5
11
STR#
12
PD
2
13
PD
6
14
15
16
17
18
USB USB
BUSY RTS# DTR# OC0# P2-
B
PINT PINT
B#
A#
AD
28
AD
25
AD
23
AD
18
T
RDY#
AD
15
AD
10
AD
4
AD
1
P
INIT#
PD
5
ACK#
C
PREQ PINT
H#
D#
PINT
C#
AD
27
CBE
3#
AD
19
I
RDY# PAR
AD
12
AD
6
AD
0
PD
1
PD
4
PD
7
D
PGNT PREQ PGNT
L#
L#
H#
AD
29
AD
20
CBE
2#
STOP
#
AD
14
AD
7
AD
2
PD
0
SLCT
IN#
PE
DSR#
GND USB
USB OC1#
AD
22
AD
17
SERR
#
AD
13
AD
8
AD
3
AUTO
FD#
PD
3
SLCT
RXD
VCC
USB
RSM
RST# FRM# VCC
AD
11
VCC
CBE
0#
VCC VCC
E
RTC
X2
F
JB
B1
RTC
X1
PWR PCI
GD RST#
V
INTR
BAT UDR#
AC
AC
G SYNC RST
JA
B1
AC
AC
AC
H SDIN0 SDIN1 SDO
GPI
0
MSI
I2S
JA
X
VCC
GND
VCC
JB
B2
JA
Y
VCC
H7
8
JB
Y
VCC
J
JB
X
GND
PCS1# GPIO AC MSO
J SDIN2
C
BCLK SPDIF
K VREF
FAN FAN2
1 SLPB#
JA
B2
9
19
USB
P1-
20
USB
P0-
TXD CTS#
USB
P3-
USB
P2+
USB
P1+
USB
P0+
USB
CLK
USB
P3+
EE
CS#
EE
DI
EE
DO
MD
CK
MD
IO
RI#
MRX MRX
D3
D2
EE
CK
MRX MRX MRX MRX
CLK
D1
D0
DV
ERR# VCC VCC DCD# VCC
VCC
MII
MTX MRX MTX MTX
CLK ERR ENA
D0
GND
VCC
VCC RAM GND RAM
M
CRS
M
COL
GND
MTX MTX MTX
D1
D2
D3
H14
GND
TRK WRT DSK
HD
R
00# PRT# CHG# SEL# DATA#
GND GND
J
VCC
MTR
1#
GND
GND GND
K
VCC
VCC DRV MTR
MII DEN1 0#
10
11
GND GND
GND
GND
K
GND GND
GND
12
13
DS
0#
W
W
STEP# DATA# GATE#
DS
1#
DIR#
L
UIC
5
DTD
+
DTD
-
UIC
4
GND
HWM VCC
L
GND GND
GND
GND
GND GND
L
GND
IN
VCC DRV PDCS PDCS
1#
3#
DEX#
PLL DEN0
M
UIC
1
UIC
3
UIC
2
KB
CK
VCC
HWM VCC
M
GND GND
GND
GND
GND GND
M
VCC
GND
PLL
PCI
CLK
PD
A1
N
KB
DT
MS
CK
SUS
C#
MS
DT
SUS
ST#
10
11
N14
GND
PD
D10
PD
D5
PD
IOR#
PD
PD
RDY DACK#
SUSA SUS
#/strap B#
AOL
GPI
SUS
CLK
VCC VCC
SUS SUS
GND
GND
VCC
PD
D4
PD
D11
PD
D8
PD
PD
DRQ IOW#
SMB
CK1
GPO
0
CPU
MISS INTR
VCC
IR
TX
VCC VCC
SD
6
SD
0
VCC
VCC VCC
PD
D1
PD
D14
PD
D7
PD
D9
PD
D6
IGN
NE#
IO
W#
IR
RX2
ROM SD11
CS# HG2#
SD
7
OSC
SA17
/strap
IRQ
14
SA8
SDD8
PD
D0
PD
D15
PD
D13
PD
D3
PD
D12
CPU FERR
SLP#
RST
#
IO
R#
IR
RX
SPKR
SD12
SD
5
SD
4
SA
18
IRQ
15
SA7 SA6
SD SDCS SDCS
SDD7 SDD6 DRQ
1#
3#
L
AD3
L
AD0
SER
IRQ
P
R
SMB
CK2
SMB
DT2
T
SMB SMB BAT EXT
DT1 ALRT# LOW# SMI#
U
PWR RING
PME# BTN#
#
PCK GPIO
V RUN#
A
GPI
1
NMI
VCC
N7
8
9
VCC VCC
GND
LR1#
12
13
VCC VCC VCC
PD
A2
PD
D2
WSC#
ARQ#
STP
INIT CLK#
HR2#
SD
1
SA
19
SA5 SA11 SA2 SA14
SDD5 SDD11 SDD2 SDD14
APIC
D0
A20 MCCS
L
L
MEM SD14 SD9
LR2# HG1#
M# #/strap AD2 FRM# R#
SD
2
LA
20
SA9 SA4 SA12 SA1 SA15 SD
SD
SDD9 SDD4 SDD12 SDD1 SDD15 IOR# DACK#
APIC APIC
CLK D1
PCS0#
L
L
MEM SD13 SD8
SMI# /strap AD1 DRQ# W#
LG1# HR1#
SD
3
LA
21
SA16 SA10 SA3 SA13 SA0
SD
SD
/strap SDD10 SDD3 SDD13 SDD0 IOW# RDY
12
13
W
PCI CPU GPIO
STP# STP#
E
Y
GPIO
D
LID
1
2
3
4
5
6
7
8
9
SD15 SD10
PD
A0
LG2#
10
11
14
15
16
17
SD
A1
18
SD
A0
19
SD
A2
20
Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name (usually the most often used function), but
the pin lists and pin descriptions contain all names.
Preliminary Revision 0.8 October 29, 1999
-7-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Pin Lists
Figure 3. VT8231 Pin List (Numerical Order)
Pin
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
O
O
I
IO
IO
IO
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
O
I
IO
IO
IO
IO
O
I
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
IO
O
I
O
I
O
I
IO
IO
IO
IO
IO
IO
IO
IO
Pin Name
AD30
AD31
AD26
AD24
AD21
AD16
DEVSEL#
CBE1#
AD09
AD05
STROBE#
PD2 / WRTPRT#
PD6
BUSY / MTR1#
RTS#
DTR#
USBOC0#
USBP2USBP1USBP0PINTB#
PINTA#
AD28
AD25
AD23
AD18
TRDY#
AD15
AD10
AD04
AD01
PINIT# / DIR#
PD5
ACK# / DS1#
TXD
CTS#
USBP3USBP2+
USBP1+
USBP0+
PREQH#
PINTD#
PINTC#
AD27
CBE3#
AD19
IRDY#
PAR
AD12
AD06
AD00
PD1 / TRK00#
PD4 / DSKCHG#
PD7
USBCLK
RI#
USBP3+
EECS#
EEDI
EEDO
PGNTL#
PREQL#
PGNTH#
AD29
AD20
CBE2#
STOP#
AD14
AD07
AD02
PD0 / INDEX#
Pin
D12
D13
D14
D15
D16
D17
D18
D19
D20
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F16
F18
F19
F20
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H01
H02
IO
I
I
P
I
O
IO
I
I
O
I
I
O
IO
IO
I
IO
IO
IO
IO
IO
I
I
P
O
I
I
I
I
I
P
I
I
I
IO
P
IO
P
IO
I
P
P
I
P
I
P
I
O
O
O
O
I
I
I
P
P
P
P
P
P
P
P
P
P
I
I
O
O
O
I
I
Pin Name
SLCTIN#/STEP#
PE / WDATA#
DSR#
GNDUSB
USBOC1#
MDCK
MDIO
MRXD3
MRXD2
RTCX2
RTCX1
PWRGD
PCIRST#
AD22
AD17
SERR#
AD13
AD08
AD03
AUTOFD#/DRV0
PD3 / RDATA#
SLCT/WGATE#
RXD
VCCUSB
EECK
MRXCLK / AIRQ
MRXD1
MRXD0 / AIRQ
MRXDV / AIRQ
JBB1 / GAMED6
VBAT
INTRUDER#/GPI8
GPI0
RSMRST#
FRAME#
VCC
AD11
VCC
CBE0#
ERROR#/HDSEL#
VCC
VCC
DCD#
VCC
MTXCLK / AIRQ
VCCMII
MRXERR / AIRQ
MTXENA / AIRQ
MTXD0 / AIRQ
ACSYNC
ACRST
JAB1 / GAMED4
MSI / I2S
JAX / GAMED0
VCC
GND
VCC
VCC
VCC
GND
VCC
GNDRAM
GND
VCCRAM
MCRS / AIRQ
MCOL / AIRQ
MTXD1 / AIRQ
MTXD2 / AIRQ
MTXD3 / AIRQ
ACSDIN0
ACSDIN1
Pin
H03
H04
H05
H06
H15
H16
H17
H18
H19
H20
J01
J02
J03
J04
J05
J06
J15
J16
J17
J18
J19
J20
K01
K02
K03
K04
K05
K06
K15
K16
K17
K18
K19
K20
L01
L02
L03
L04
L05
L06
L15
L16
L17
L18
L19
L20
M01
M02
M03
M04
M05
M06
M15
M16
M17
M18
M19
M20
N01
N02
N03
N04
N05
N06
N15
N16
N17
N18
N19
N20
P01
O
I
I
P
P
I
I
I
OD
I
O
IO
I
O
I
P
P
OD
OD
OD
OD
OD
P
I
I
I
I
P
P
P
OD
OD
OD
OD
AI
AI
AI
AI
P
P
P
P
OD
O
O
I
AI
AI
AI
IO
P
P
P
P
I
O
O
O
IO
IO
O
IO
O
P
P
IO
IO
O
I
O
O
Pin Name
ACSDOUT
JBB2 / GAMED7
JAY / GAMED1
VCC
GND
TRK00#
WRTPRT#
DSKCHG#
HDSEL#
RDATA#
PCS1# / SDI2 / IO
GPIOC/IO25/ATST
ACBITCLK
MSO / SPDIF
JBY / GAMED3
VCC
VCC
MTR1#
DS0#
STEP#
WDATA#
WGATE#
VREF
FAN1
FAN2/SLPB#/IO18
JAB2 / GAMED5
JBX / GAMED2
GND
VCC
VCCMII
DRVDEN1
MTR0#
DS1#
DIR#
UIC5
DTD+
DTDUIC4
GNDHWM
VCC
GND
VCCPLL
DRVDEN0
PDCS1#
PDCS3#
INDEX#
UIC1
UIC3
UIC2
KBCK / A20G
VCCHWM
VCC
VCC
GNDPLL
PCICLK
PDA1
PDA0
PDA2
KBDT / KBRC
MSCK / IRQ1
SUSC# / GPO
MSDT / IRQ12
SUSST1# / GPO3
VCC
GND
PDD10
PDD05
PDIOR#
PDRDY
PDDACK#
SUSA#/GPO1/strap
Pin
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T01
T02
T03
T04
T05
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
O
I
O
P
P
P
P
P
P
P
P
P
P
P
IO
IO
IO
I
O
IO
IO
IO
O
I
OD
P
O
P
P
IO
IO
P
P
P
IO
IO
IO
IO
IO
IO
I
I
IOD
OD
OD
IO
I
O
O
IO
I
IO
I
IO
IO
IO
IO
IO
IO
I
I
I
OD
I
OD
IO
I
O
I
IO
IO
Pin Name
SUSB# / GPIO2
AOLGPI/THRM/I17
SUSCLK / GPO4
VCCSUS
VCCSUS
GND
VCC
VCC
GND
VCC
VCC
VCC
GND
VCC
PDD04
PDD11
PDD08
PDDRQ
PDIOW#
SMBCK2 / GPIO27
SMBDT2 / GPIO26
SMBCK1
SLOWCLK / O0
CPUMISS / GPI16
INTR
VCC
IRTX / GPO14
VCC
VCC
SD06
SD00
VCC
VCC
VCC
PDD01
PDD14
PDD07
PDD09
PDD06
SMBDT1
SMBALRT# / GPI7
BATLOW# / GPI5
EXTSMI# / GPI2
NMI
IGNNE#
IOW# / GPO23
IRRX2 / GPI
ROMCS#/KBCS#
HGNT2#/SD11/O9
SD07
OSC
SA17 / strap
IRQ14
SA08 / SDD08
PDD00
PDD15
PDD13
PDD03
PDD12
PME# / GPI6
PWRBTN#
RING# / GPI3
CPURST
FERR#
SLP# / GPO7
IOR# / GPO22
IRRX / GPO15
SPKR
LREQ1#/SD12/I12
SD05
SD04
Pin
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
IO
I
IO
IO
I
O
O
IO
IO
IO
I
I
OD
OD
IO
IO
I
O
I
IO
IO
IO
IO
IO
IO
O
O
O
O
O
IO
O
OD
O
IO
O
IO
I
O
IO
IO
IO
IO
IO
IO
IO
O
O
IO
I
I
O
OD
O
IO
I
IO
O
I
IO
IO
IO
IO
IO
IO
IO
O
I
Pin Name
SA18
IRQ15
SA07 / SDD07
SA06 / SDD06
SDDRQ
SDCS1#
SDCS3#
PDD02
PCKRUN#
GPIOA / GPIO24
GPI1 / IRQ8#
WSC#/ARQ#/I24
INIT
STPCLK#
LAD3
LAD0
SERIRQ#
LGT2#/SD15/O11
HRQ2#/SD10/I11
SD01
SA19
SA05 / SDD05
SA11 / SDD11
SA02 / SDD02
SA14 / SDD14
SDA1
SDA0
SDA2
PCISTP# / GPO6
CPUSTP# / GPO5
GPIOE / GPIO31
APD0/ACS#/IO28
A20M#
MCCS#/O17/strap
LAD2
LFRAME#
MEMR#
LRQ2#/SD14/I13
HGT1#/SD09/O8
SD02
LA20/OC2#/O20
SA09 / SDD09
SA04 / SDD04
SA12 / SDD12
SA01 / SDD01
SA15 / SDD15
SDIOR#
SDDACK#
IOD/30/SCO#/DT
LID / GPI4
APICCLK / GPI9
APD1/AK#/IO29
SMI#
PCS0#/O16/strap
LAD1
LDRQ#/SIN3/I15
MEMW#
LG1#/ SD13/O10
HRQ1#/SD08/I10
SD03
LA21/OC3#/O21
SA16 / strap
SA10 / SDD10
SA03 / SDD03
SA13 / SDD13
SA00 / SDD00
SDIOW#
SDRDY
Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13
Preliminary Revision 0.8 October 29, 1999
-8-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Figure 4. VT8231 Pin List (Alphabetical Order)
Pin
W05
J03
B14
G02
H01
H02
H03
G01
C11
B11
D10
E10
B10
A10
C10
D09
E09
A09
B09
F08
C09
E08
D08
B08
A06
E06
B06
C06
D05
A05
E05
B05
A04
B04
A03
C04
B03
D04
A01
A02
P03
Y03
Y04
W04
E11
T03
A14
F10
A08
D06
C05
R05
U04
W02
B16
F14
A07
K20
L17
K17
J17
K19
H18
D14
L02
L03
A16
E16
C18
C19
C20
OD
I
I
O
I
I
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
O
I
O
IO
I
I
IO
IO
IO
IO
I
OD
O
I
I
IO
OD
OD
OD
OD
OD
I
I
AI
AI
O
O
O
I
O
Pin Name
A20M#
ACBITCLK
ACK# / DS1#
ACRST
ACSDIN0
ACSDIN1
ACSDOUT
ACSYNC
AD00
AD01
AD02
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AOLGPI/THRM/I17
APICLK / GPI9
APICD1/AK#/IO29
APICD0/ACS#/IO28
AUTOFD# / DRV0
BATLOW# / GPI5
BUSY / MTR1#
CBE0#
CBE1#
CBE2#
CBE3#
CPUMISS / GPI16
CPURST
CPUSTP# / GPO5
CTS#
DCD#
DEVSEL#
DIR#
DRVDEN0
DRVDEN1
DS0#
DS1#
DSKCHG#
DSR#
DTD+
DTDDTR#
EECK
EECS#
EEDI
EEDO
Pin
F11
T04
K02
K03
U05
F06
G07
G11
G14
H15
K06
L15
N15
P07
P10
P14
L05
M16
G13
D15
F04
V03
V02
J02
Y01
W03
H19
W11
T10
Y11
V11
T06
L20
V05
R06
F03
U07
T07
C07
T14
U14
U08
T08
R08
G03
K04
G05
H05
F01
H04
K05
J05
M04
N01
W13
Y13
V08
Y07
W07
V07
Y08
W08
Y10
V10
Y02
U10
W10
W06
G17
G16
D17
I
IOD
I
I
I
IO
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
I
IO
IO
IO
IO
OD
O
O
I
I
OD
I
OD
OD
I
IO
IO
IO
I
I
I
I
O
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
I
O
O
O
I
I
I
O
I
I
O
Pin Name
ERROR#/HDSEL#
EXTSMI# / GPI2
FAN1
FAN2/SLPB#/IO18
FERR#
FRAME#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDHWM
GNDPLL
GNDRAM
GNDUSB
GPI0
GPI1 / IRQ8#
GPIOA/24
GPIOC/25/ATST
GPIOD/30/SCIOU#
GPIOE
HDSEL#
HGNT1#/SD09/O8
HGNT2#/SD11/O9
HREQ1#/SD08/I10
HREQ2#/SD10/I11
IGNNE#
INDEX#
INIT
INTR
INTRUDER#/GPI8
IOR# / GPO22
IOW# / GPO23
IRDY#
IRQ14
IRQ15
IRRX / GPO15
IRRX2 / GPI
IRTX / GPO14
JAB1 / GAMED4
JAB2 / GAMED5
JAX / GAMED0
JAY / GAMED1
JBB1 / GAMED6
JBB2 / GAMED7
JBX / GAMED2
JBY / GAMED3
KBCK / A20G
KBDT / KBRC
LA20/OC2#/O20
LA21/OC3#/O21
LAD0
LAD1
LAD2
LAD3
LDRQ#/SDIN3/I15
LFRAME#
LGNT1#/SD13/O10
LGNT2#/SD15/O11
LID / GPI4
LREQ1#/SD12/I12
LREQ2#/SD14/I13
MCCS#/O17/strap
MCOL / AIRQ
MCRS / AIRQ
MDCK
Pin
D18
W09
Y09
E17
E19
E18
D20
D19
E20
F18
N02
N04
G04
J04
K18
J16
F16
F20
G18
G19
G20
F19
T05
T12
C08
V01
M17
E04
W01
Y06
J01
D11
C12
A12
E12
C13
B13
A13
C14
M19
M18
M20
L18
L19
T16
R16
U20
T19
P16
N17
R20
R18
P18
R19
N16
P17
T20
T18
R17
T17
N20
P19
N18
P20
N19
D13
D03
D01
B12
B02
B01
IO
IO
IO
I
I
I
I
I
I
I
IO
IO
I
O
OD
OD
I
O
O
O
O
O
OD
I
IO
IO
I
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
I
O
O
I
I
I
I
IO
I
I
Pin Name
MDIO
MEMR#
MEMW#
MRXCLK / AIRQ
MRXD0 / AIRQ
MRXD1
MRXD2
MRXD3
MRXDV / AIRQ
MRXERR/AIRQ
MSCK / IRQ1
MSDT / IRQ12
MSI / I2S
MSO / SPDIF
MTR0#
MTR1#
MTXCLK/AIRQ
MTXD0/AIRQ
MTXD1/AIRQ
MTXD2/AIRQ
MTXD3/AIRQ
MTXENA/AIRQ
NMI
OSC
PAR
PCKRUN#
PCICLK
PCIRST#
PCISTP# / GPO6
PCS0#/O16/strap
PCS1#/SIN2/IO19
PD0/INDEX#
PD1/TRK00#
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6
PD7
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
PDD00
PDD01
PDD02
PDD03
PDD04
PDD05
PDD06
PDD07
PDD08
PDD09
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDACK#
PDDRQ
PDIOR#
PDIOW#
PDRDY
PE / WDATA#
PGNTH#
PGNTL#
PINIT# / DIR#
PINTA#
PINTB#
Pin
C03
C02
U01
C01
D02
U02
E03
H20
C16
U03
T09
F05
E02
E01
A15
E14
Y18
W17
V16
Y16
W15
V14
U16
U15
T15
W14
Y15
V15
W16
Y17
V17
W18
Y14
T13
U13
V13
R12
V12
W12
Y12
U12
U11
R11
T11
V19
V18
V20
U18
U19
W20
U17
W19
Y19
Y20
V09
E07
E13
D12
R04
U06
T02
R03
R01
T01
R02
Y05
U09
J18
D07
V06
A11
I
I
I
O
O
I
I
I
I
I
O
I
I
O
O
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
O
O
O
O
O
I
O
O
I
I
I
I
IO
O
OD
I
IO
IO
IO
IO
OD
O
OD
IO
OD
IO
Pin Name
PINTC#
PINTD#
PME# / GPI6
PREQH#
PREQL#
PWRBTN#
PWRGD
RDATA#
RI#
RING# / GPI3
ROMCS#/KBCS#
RSMRST#
RTCX1
RTCX2
RTS#
RXD
SA00 / SDD00
SA01 / SDD01
SA02 / SDD02
SA03 / SDD03
SA04 / SDD04
SA05 / SDD05
SA06 / SDD06
SA07 / SDD07
SA08 / SDD08
SA09 / SDD09
SA10 / SDD10
SA11 / SDD11
SA12 / SDD12
SA13 / SDD13
SA14 / SDD14
SA15 / SDD15
SA16 / strap
SA17 / strap
SA18
SA19
SD00
SD01
SD02
SD03
SD04
SD05
SD06
SD07
SDA0
SDA1
SDA2
SDCS1#
SDCS3#
SDDACK#
SDDRQ
SDIOR#
SDIOW#
SDRDY
SERIRQ#
SERR#
SLCT/WGATE#
SLCTIN#/STEP#
SLOWCLK / O0
SLP# / GPO7
SMBALRT# / I7
SMBCK1
SMBCK2 / IO27
SMBDT1
SMBDT2 / IO26
SMI#
SPKR
STEP#
STOP#
STPCLK#
STROBE#
Pin
P01
P02
N03
P04
N05
B07
H16
B15
M01
M03
M02
L04
L01
C15
A17
D16
A20
B20
A19
B19
A18
B18
B17
C17
F02
F07
F09
F12
F13
F15
G06
G08
G09
G10
G12
H06
J06
J15
K15
L06
M06
M15
N06
P08
P09
P11
P12
P13
P15
R07
R09
R10
R13
R14
R15
M05
F16
K16
L16
G15
P05
P06
E15
K01
J19
J20
H17
V04
O
O
O
O
O
IO
I
O
I
I
I
I
I
I
I
I
IO
IO
IO
IO
IO
IO
IO
IO
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
OD
OD
I
I
Pin Name
SUSA# / GPO1
SUSB# / GPO2
SUSC#
SUSCLK
SUSST1# / GPO3
TRDY#
TRK00#
TXD
UIC1
UIC2
UIC3
UIC4
UIC5
USBCLK
USBOC0#
USBOC1#
USBP0USBP0+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
VBAT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCHWM
VCCMII
VCCMII
VCCPLL
VCCRAM
VCCSUS
VCCSUS
VCCUSB
VREF
WDATA#
WGATE#
WRTPRT#
WSC#/ARQ#/I14
Center GND pins (24 pins): J8-J13, K8-K13, L8-L13, M8-M13
Preliminary Revision 0.8 October 29, 1999
-9-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Pin Descriptions
Table 1. Pin Descriptions
PCI Bus Interface
Signal Name
Pin #
I/O
Signal Description
IO
FRAME#
(see pin
list)
C5, D6,
A8, F10
F6
IRDY#
TRDY#
STOP#
DEVSEL#
C7
B7
D7
A7
IO
IO
IO
IO
PAR
SERR#
C8
E7
IO
I
B2, B1,
C3, C2
I
PREQH#
PGNTH#
C1
D3
O
I
PREQL#
PGNTL#
D2
D1
O
I
PCICLK
PCKRUN#
M17
V1
I
IO
PCIRST#
PCISTP# / GPO6
CPUSTP# / GPO5
E4
W1
W2
O
O
O
Address/Data Bus. The standard PCI address and data lines. The address is driven with
FRAME# assertion and data is driven or received in following cycles.
Command/Byte Enable. The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that
one more data transfer is desired by the cycle initiator.
Initiator Ready. Asserted when the initiator is ready for data transfer.
Target Ready. Asserted when the target is ready for data transfer.
Stop. Asserted by the target to request the master to stop the current transaction.
Device Select. The VT8231 asserts this signal to claim PCI transactions through positive
or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8231initiated transaction and is also sampled when decoding whether to subtractively decode
the cycle.
Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
System Error. SERR# can be pulsed active by any PCI device that detects a system
error condition. Upon sampling SERR# active, the VT8231 can be programmed to
generate an NMI to the CPU.
PCI Interrupt Request. These pins are typically connected to the PCI bus INTA#INTD# pins as follows:
PINTA#
PINTB#
PINTC#
PINTD#
PCI Slot 1
INTA#
INTB#
INTC#
INTD#
PCI Slot 2
INTB#
INTC#
INTD#
INTA#
PCI Slot 3
INTC#
INTD#
INTA#
INTB#
PCI Slot 4
INTD#
INTA#
INTB#
INTC#
PCI Slot 5
INTA#
INTB#
INTC#
INTD#
PCI Request. This signal goes to the North Bridge to request the PCI bus.
PCI Grant. This signal is driven by the North Bridge to grant PCI access to the
VT8231.
PCI Request. This signal goes to the North Bridge to request the PCI bus.
PCI Grant. This signal is driven by the North Bridge to grant PCI access to the
VT8231.
PCI Clock. PCLK provides timing for all transactions on the PCI Bus.
PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped
(high) or running (low). The VT8231 drives this signal low when the PCI clock is
running (default on reset) and releases it when it stops the PCI clock. External devices
may assert this signal low to request that the PCI clock be restarted or prevent it from
stopping. Connect this pin to ground using a 100 Ω resistor if the function is not used.
Refer to the “PCI Mobile Design Guide” and the VIA “Apollo MVP4 Design Guide” for
more details.
PCI Reset.
PCI Stop.
CPU Stop.
AD[31:0]
C/BE[3:0]#
PINTA-D#
IO
IO
Preliminary Revision 0.8 October 29, 1999
-10-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
CPU Interface
Signal Name
Pin #
I/O
U4
OD
Signal Description
CPU Reset. The VT8231 asserts CPURST to reset the CPU during
power-up.
R6
OD
INTR
CPU Interrupt. INTR is driven by the VT8231 to signal the CPU that
an interrupt request is pending and needs service.
T5
OD
NMI
Non-Maskable Interrupt. NMI is used to force a non-maskable
interrupt to the CPU. The VT8231 generates an NMI when either
SERR# or IOCHK# is asserted.
V5
OD
INIT
Initialization. The VT8231 asserts INIT if it detects a shut-down
special cycle on the PCI bus or if a soft reset is initiated by the register
V6
OD
STPCLK#
Stop Clock. STPCLK# is asserted by the VT8231 to the CPU to
throttle the processor clock.
Y5
OD
SMI#
System Management Interrupt. SMI# is asserted by the VT8231 to
the CPU in response to different Power-Management events.
U5
I
FERR#
Numerical Coprocessor Error. This signal is tied to the coprocessor
error signal on the CPU. Internally generates interrupt 13 if active.
T6
OD
IGNNE#
Ignore Numeric Error. This pin is connected to the “ignore error” pin
on the CPU.
U6
OD
SLP# / GPO7
Sleep (Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1
CPUs only. Not currently used with socket-7 CPUs.
W5
OD
A20M#
A20 Mask. Connect to A20 mask input of the CPU to control address
bit-20 generation. Logical combination of the A20GATE input (from
internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).
L2
Analog I CPU DTD (Thermal Diode) Channel Plus. Connect to cathode of first
DTD+
external temperature sensing diode.
L3
Analog
I
DTDCPU DTD (Thermal Diode) Channel Minus. Connect to anode of
first external temperature sensing diode.
Note: Connect each of the above signals to 4.7K Ω pullup resistors to VCC3.
CPURST
Strap Options
Signal Name
Pin #
I/O
Signal Description
Strap / SUSA#
P1
I/O
Strap / MCCS#
W6
I/O
Strap / PCS0#
Y6
I/O
Strap / SA16
Y14
I / IO
Strap / SA17
T13
I / IO
Strap / KBCS# / ROMCS#
T9
I/O/O
CPURST / INIT Polarity
H:
L:
CPU Frequency Strapping
H: Disable
L: Enable
SD Bus Width
H: 16-Bit
L: 8-Bit
BIO ROM Interface
H: LPC
L: Conventional
Auto Reboot
H: Disable
L: Enable
CPU Type
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
Preliminary Revision 0.8 October 29, 1999
-11-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Advanced Programmable Interrupt Controller (APIC) Interface
Signal Name
Pin #
I/O
WSC# / APICREQ# / GPI14
V4
I/I/I
APICD0 / APICCS# / GPIO28
W4
O / O / IO
APICD1 / APICACK# / GPIO29
Y4
O / O / IO
APICCLK / GPI9
SCIOUT# / GPIOD
/ GPIO30 / DTEST
Y3
Y1
I/I
O / IO
IO / O
AIRQ / MCOL
AIRQ / MCRS
AIRQ / MRXCLK
AIRQ / MRXD0
AIRQ / MRXDV
AIRQ / MRXERR
AIRQ / MTXCLK
AIRQ / MTXD0
AIRQ / MTXD1
AIRQ / MTXD2
AIRQ / MTXD3
AIRQ / MTXENA
G17
G16
E17
E19
E20
F18
F16
F20
G18
G19
G20
F19
O
O
O
O
O
O
O
O
O
O
O
O
Signal Description
Internal APIC Write Snoop Complete. Asserted by the north
bridge to indicate that all snoop activity on the CPU bus initiated
by the last PCI-to-DRAM write is complete and that it is safe to
perform an APIC interrupt.
External APIC Request. Asserted by external APIC synchronous
to PCICLK prior to sending an interrupt over the APIC serial bus.
This signals the VT8231 to flush its internal buffers.
Internal APIC Data 0.
External APIC Chip Select. The VT8231 drives this signal active
to select an external APIC (if used). This occurs if the external
APIC is enabled and a PCI cycle is detected within the
programmed APIC address range.
Internal APIC Data 1.
External APIC Acknowledge. Asserted by the VT8231 to indicate
that it internal buffers have been flushed (in response to
APICREQ#). This indicates to the external APIC that the
VT8231’s internal buffers have been flushed and that it is OK for
the APIC to send its interrupt.
APIC Clock.
SCI Out. Used to route internally generated SCI and SMBus
interrupts to external APIC (if used). Defined as SCIOUT# if
external APIC enabled (function 0 Rx74[7] = 1).
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
APIC IRQ. Internal condition for connection to external APIC.
Serial EEPROM Interface
Signal Name
Pin #
I/O
EECS#
EECK
EEDO
EEDI
C18
E16
C20
C19
O
O
O
I
Preliminary Revision 0.8 October 29, 1999
Signal Description
Serial EEPROM Chip Select.
Serial EEPROM Clock.
Serial EEPROM Data Output.
Serial EEPROM Data Input.
-12-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Low Pin Count (LPC) Interface
Signal Name
Pin #
I/O
Signal Description
W8
O
LFRAME#
LPC Frame.
Y8
I
/
I
/
I
LDRQ# / ACSDIN3 / GPI15
LPC Data Request.
V7, W7, Y7, V8 IO / IO LPC Address / Data.
LAD[3-0]
Y11
I / IO High Priority Request 1.
HREQ1# / SD8 / GPI10
W11
O / IO High Priority Grant 1.
HGNT1# / SD9 / GPO8
V11
I / IO High Priority Request 2.
HREQ2# / SD10 / GPI11
T10
O / IO High Priority Grant 2.
HGNT2# / SD11 / GPO9
U10
I / IO Low Priority Request 1.
LREQ1# / SD12 / GPI12
Y10
O / IO Low Priority Grant 1.
LGNT1# / SD13 / GPO10
W10
I / IO Low Priority Request 2.
LREQ2# / SD14 / GPI13
V10
O / IO Low Priority Grant 2.
LGNT2# / SD15 / GPO11
Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#
LAN Controller - Media Independent Interface (MII)
Signal Name
Pin #
I/O
Signal Description
MCOL / APICIRQ
MCRS / APICIRQ
G17
G16
I/I
I/I
MDCK
D17
O
MDIO
D18
IO
MRXCLK / APICIRQ
MRXD[3],
MRXD[2],
MRXD[1],
MRXD[0] / APICIRQ
MRXDV / APICIRQ
MRXERR / APICIRQ
E17
D19
D20
E18
E19
E20
F18
I/I
I
I
I
I/I
I/I
I/I
MII Collision Detect. From the external PHY.
MII Carrier Sense. Asserted by the external PHY when the
media is active.
MII Management Data Clock. Sent to the external PHY as a
timing reference for MDIO
MII Management Data I/O. Read from the MDI bit or written to
the MDO bit.
MII Receive Clock. 2.5 or 25 MHz clock recovered by the PHY.
MII Receive Data. Parallel receive data lines driven by the
external PHY synchronous with MRXCLK.
MTXCLK / APICIRQ
F16
I/I
MTXD[3] / APICIRQ,
MTXD[2] / APICIRQ,
MTXD[1] / APICIRQ,
MTXD[0] / APICIRQ
MTXENA / APICIRQ
G20
G19
G18
F20
F19
O/I
O/I
O/I
O/I
O/I
Preliminary Revision 0.8 October 29, 1999
MII Receive Data Valid.
MII Receive Error. Asserted by the PHY when it detects a data
decoding error.
MII Transmit Clock. Always active 2.5 or 25 MHz clock
supplied by the PHY.
MII Transmit Data. Parallel transmit data lines synchronized to
MTXCLK.
MII Transmit Enable. Indicates transmit active from the MII
port to the PHY.
-13-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Universal Serial Bus Interface
Signal Name
Pin #
I/O
USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBCLK
USBOC0#
USBOC1#
USBOC2# / LA20 / GPO20
USBOC3# / LA21 / GPO21
B20
A20
B19
A19
B18
A18
C17
B17
C15
A17
D16
W13
Y13
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I / IO / O
I / IO / O
Signal Description
USB Port 0 Data +
USB Port 0 Data USB Port 1 Data +
USB Port 1 Data USB Port 2 Data +
USB Port 2 Data USB Port 3 Data +
USB Port 3 Data USB Clock. 48MHz clock input for the USB interface
USB Port 0 Over Current Detect. Port 0 is disabled if this input is low.
USB Port 1 Over Current Detect. Port 1 is disabled if this input is low
USB Port 2 Over Current Detect. Port 2 is disabled if this input is low.
USB Port 3 Over Current Detect. Port 3 is disabled if this input is low.
System Management Bus (SMB) Interface (I2C Bus)
Signal Name
SMBCK1
SMBCK2 / GPIO27
SMBDT1
SMBDT2 / GPIO26
SMBALRT# / GPI7
Pin #
I/O
R3
R1
T1
R2
T2
IO
IO / IO
IO
IO / IO
I/I
Preliminary Revision 0.8 October 29, 1999
Signal Description
SMB / I2C Channel 1 Clock.
SMB / I2C Channel 2 Clock.
SMB / I2C Channel 1 Data.
SMB / I2C Channel 2 Data.
SMB Alert. (System Management Bus I/O space Rx08[3] = 1) When the
chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a
power management resume event. The same pin is used as General Purpose
Input 6 whose value is reflected in Rx48[6] of function 4 I/O space
-14-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
UltraDMA-33 / 66 Enhanced IDE Interface
Signal Name
Pin #
I/O
PDRDY /
PDDMARDY /
PDSTROBE
N19
I
SDRDY /
SDDMARDY /
SDSTROBE
Y20
I
PDIOR# /
PHDMARDY /
PHSTROBE
N18
O
SDIOR# /
SHDMARDY /
SHSTROBE
W19
O
PDIOW# /
PSTOP
P20
O
SDIOW# /
SSTOP
Y19
O
PDDRQ
SDDRQ
PDDACK#
SDDACK#
IRQ14
IRQ15
P19
U17
N20
W20
T14
U14
I
I
O
O
I
I
Preliminary Revision 0.8 October 29, 1999
Signal Description
EIDE Mode:
Primary I/O Channel Ready. Device ready indicator
UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device
may assert DDMARDY to pause output transfers
Primary Device Strobe. Input data strobe (both edges). The
device may stop DSTROBE to pause input data transfers
EIDE Mode:
Secondary I/O Channel Ready. Device ready indicator
UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The
device may assert DDMARDY to pause output transfers
Secondary Device Strobe. Input data strobe (both edges). The
device may stop DSTROBE to pause input data transfers
EIDE Mode:
Primary Device I/O Read. Device read strobe
UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control.
The host may assert HDMARDY to pause input transfers
Primary Host Strobe. Output data strobe (both edges). The host
may stop HSTROBE to pause output data transfers
EIDE Mode:
Secondary Device I/O Read. Device read strobe
UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host may
assert HDMARDY to pause input transfers
Host Strobe B. Output strobe (both edges). The host may stop
HSTROBE to pause output data transfers
EIDE Mode:
Primary Device I/O Write. Device write strobe
UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
EIDE Mode:
Secondary Device I/O Write. Device write strobe
UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to
initiation of an UltraDMA burst; negated by the host before data
is transferred in an UltraDMA burst. Assertion of STOP by the
host during or after data transfer in UltraDMA mode signals the
termination of the burst.
Primary Device DMA Request. Primary channel DMA request
Secondary Device DMA Request. Secondary channel DMA request
Primary Device DMA Acknowledge. Primary channel DMA acknowledge
Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge
Primary Channel Interrupt Request.
Secondary Channel Interrupt Request.
-15-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
UltraDMA-33 / 66 Enhanced IDE Interface (continued)
Signal Name
Pin #
I/O
PDCS1#
L18
O
PDCS3#
L19
O
SDCS1#
U18
O
SDCS3#
U19
O
PDA[2-0]
M20, M18, M19
O
SDA[2-0]
V20, V18, V19
O
PDD[15-0]
T17, R17, T18, T20,
P17, N16, R19, P18,
R18, R20, N17, P16,
T19, U20, R16, T16
W18, V17, Y17, W16,
V15, Y15, W14, T15,
U15, U16, V14, W15,
Y16, V16, W17, Y18
IO
SDD[15-0] / SA[15-0]
Preliminary Revision 0.8 October 29, 1999
IO
Signal Description
Primary Master Chip Select. This signal corresponds to CS1FX#
on the primary IDE connector.
Primary Slave Chip Select. This signal corresponds to CS3FX# on
the primary IDE connector.
Secondary Master Chip Select. This signal corresponds to
CS17X# on the secondary IDE connector.
Secondary Slave Chip Select. This signal corresponds to CS37X#
on the secondary IDE connector.
Primary Disk Address. PDA[2:0] are used to indicate which byte
in either the ATA command block or control block is being accessed.
Secondary Disk Address. SDA[2:0] are used to indicate which byte
in either the ATA command block or control block is being accessed.
Primary Disk Data
Secondary Disk Data (SPKR strap 4.7K ohms low) or
ISA Address (SPKR strap 4.7K ohms high)
-16-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
MIDI Interface
Signal Name
Pin #
I/O
MSI / I2S
MSO / SPDIF
G4
J4
I/I
O/O
Signal Description
MIDI Serial In
MIDI Serial Out
Serial Digital Audio Interface
Signal Name
Pin #
I/O
I2S / MSI
SPDIF / MSO
G4
J4
I/I
O/O
Signal Description
Serial Digital Audio In.
Serial Digital Audio Out.
AC97 Audio / Modem Interface
Signal Name
ACRST
ACSYNC
ACSDOUT
ACSDIN0
ACSDIN1
ACSDIN2 / PCS1# / GPIO19
ACSDIN3 / LDRQ# / GPI5
ACBITCLK
Pin #
I/O
G2
G1
H3
H1
H2
J1
Y8
J3
O
O
O
I
I
I / O / IO
I/I/I
I
Signal Description
AC97 Reset
AC97 Sync
AC97 Serial Data Out
AC97 Serial Data In 0
AC97 Serial Data In 1
AC97 Serial Data In 2
AC97 Serial Data In 3
AC97 Bit Clock
Game Port Interface
Signal Name
JAX / GAMED0
JAY / GAMED1
JBX / GAMED2
JBY / GAMED3
JAB1 / GAMED4
JAB2 / GAMED5
JBB1 / GAMED6
JBB2 / GAMED7
See Function 0 Rx77[6]
Pin #
I/O
G5
H5
K5
J5
G3
K4
F1
H4
I
I
I
I
I
I
I
I
Preliminary Revision 0.8 October 29, 1999
Signal Description
Joystick A X-axis
Joystick A Y-axis
Joystick B X-axis
Joystick B Y-axis
Joystick A Button 1
Joystick A Button 2
Joystick B Button 1
Joystick B Button 2
-17-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Floppy Disk Interface
Signal Name
Pin #
I/O
DRVDEN0
DRVDEN1
MTR0#
MTR1#
DS0#
DS1#
DIR#
STEP#
INDEX#
HDSEL#
TRK00#
RDATA#
WDATA#
WGATE#
DSKCHG#
L17
K17
K18
J16
J17
K19
K20
J18
L20
H19
H16
H20
J19
J20
H18
OD
OD
OD
OD
OD
OD
OD
OD
I
OD
I
I
OD
OD
I
Signal Description
Drive Density Select 0.
Drive Density Select 1.
Motor Control 0. Select motor on drive 0.
Motor Control 1. Select motor on drive 1
Drive Select 0. Select drive 0.
Drive Select 1. Select drive 1
Direction. Direction of head movement (0 = inward motion, 1 = outward motion)
Step. Low pulse for each track-to-track movement of the head.
Index. Sense to detect that the head is positioned over the beginning of a track
Head Select. Selects the side for R/W operations (0 = side 1, 1 = side 0)
Track 0. Sense to detect that the head is positioned over track 0.
Read Data. Raw serial bit stream from the drive for read operatrions.
Write Data. Encoded data to the drive for write operations.
Write Gate. Signal to the drive to enable current flow in the write head.
Disk Change. Sense that the drive door is open or the diskette has been changed
since the last drive selection.
H17
I
WRTPRT#
Write Protect. Sense for detection that the diskette is write protected (causes write
commands to be ignored)
See also Parallel Port pin descriptions for optional Floppy Disk interface functionality
Preliminary Revision 0.8 October 29, 1999
-18-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Parallel Port Interface
Signal Name
Pin #
I/O
PINIT# / DIR#
STROBE# / nc
AUTOFD# / DRVEN0
B12
A11
E11
IO / O
IO / IO / O
SLCTIN# / STEP#
SLCT / WGATE#
ACK# / DS1#
D12
E13
B14
IO / O
I/O
I/O
ERROR# / HDSEL#
F11
I/O
Signal Description
Initialize. Initialize printer. Output in standard mode, I/O in ECP/EPP mode.
Strobe. Output used to strobe data into the printer. I/O in ECP/EPP mode.
Auto Feed. Output used to cause the printer to automatically feed one line after
each line is printed. I/O pin in ECP/EPP mode.
Select In. Output used to select the printer. I/O pin in ECP/EPP mode.
Select. Status output from the printer. High indicates that it is powered on.
Acknowledge. Status output from the printer. Low indicates that it has received
the data and is ready to accept new data
Error. Status output from the printer. Low indicates an error condition in the
printer.
Busy. Status output from the printer. High indicates not ready to accept data.
Paper End. Status output from the printer. High indicates that it is out of paper.
Parallel Port Data.
A14
I/O
BUSY / MTR1#
D13
I/O
PE / WDATA#
IO / C14
PD7 / nc,
IO / A13
PD6 / nc,
IO / B13
PD5 / nc,
IO
/I
C13
/
DSKCHG#,
PD4
IO / I
E12
PD3 / RDATA#,
IO / I
A12
PD2 / WRTPRT#,
IO / I
C12
PD1 / TRK00#,
IO / I
D11
PD0 / INDEX#
As shown by the alternate functions above, in mobile applications the parallel port pins can optionally be selected to function as a
floppy disk interface for attachment of an external floppy drive using the parallel port connector (see Super I/O Configuration
Index F6[5]).
Preliminary Revision 0.8 October 29, 1999
-19-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Serial Port and Infrared Interface
Signal Name
TXD
RXD
IRTX / GPO14
Pin #
B15
E14
R8
I/O
O
I
O/O
IRRX / GPO15
U8
I/O
IRRX2 / GPI
RTS#
T8
A15
I/I
O
CTS#
B16
I
DTR#
A16
O
DSR#
D14
I
DCD#
F14
I
RI#
C16
I
Preliminary Revision 0.8 October 29, 1999
Signal Description
Transmit Data. Serial port transmit data out.
Receive Data. Serial port receive data in.
Infrared Transmit. IR transmit data out (Rx76[5] = 0) selectable from serial port
1, 2, or 3. General Purpose Output 14 if Rx76[5] = 1
Infrared Receive. IR receive data in (Rx76[5] = 0) selectable to serial port 1, 2,
or 3. General Purpose Output 15 if Rx76[5] = 1
Infrared Receive. IR receive data in (Rx76[5] = 0)
Request To Send. Indicator that the serial output port is ready to transmit data.
Typically used as hardware handshake with CTS# for low level flow control.
Designed for direct input to external RS-232C driver.
Clear To Send. Indicator to the serial port that an external communications
device is ready to receive data. Typically used as hardware handshake with RTS#
for low level flow control. Designed for input from external RS-232C receiver.
Data Terminal Ready. Indicator that serial port is powered, initialized, and
ready. Typically used as hardware handshake with DSR# for overall readiness to
communicate. Designed for direct input to external RS-232C driver.
Data Set Ready. Indicator to serial port that an external serial communications
device is powered, initialized, and ready. Typically used as hardware handshake
with DTR# for overall readiness to communicate. Designed for direct input from
external RS-232C receiver.
Data Carrier Detect. Indicator to serial port that an external modem is detecting
a carrier signal (i.e., a communications channel is currently open). In direct
connect environments, this input will typically be driven by DTR# as part of the
DTR/DSR handshake. Designed for direct input from external RS-232C receiver.
Ring Indicator. Indicator to serial port that an external modem is detecting a ring
condition. Used by software to initiate operations to answer and open the
communications channel. Designed for direct input from external RS-232C
receiver (whose input is typically not connected in direct connect environments).
-20-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Conventional BIOS ROM / ISA Bus Interface
Signal Name
Pin #
I/O
Y13
W13
V13, U13,
T13,
Y14,
W18, V17, Y17, W16,
V15, Y15, W14, T15,
U15, U16, V14, W15,
Y16, V16, W17, Y18
V10
W10
Y10
U10
T10
V11
W11
Y11
T11
R11
U11
U12
Y12
W12
V12
R12
O
IO / O / O
IO / I / I
IO / O / O
IO / I / I
IO / O / O
IO / I / I
IO / O / O
IO / I / I
IO
IO
IO
IO
IO
IO
IO
IO
System Data. SD[15:0] provide the data path for BIOS
ROMs and for devices residing on the ISA bus. SD0-7
also output general purpose output information when
GPOWE# is active.
U7
IO
IOW# / GPO23
T7
IO
MEMR#
W9
IO
MEMW#
Y9
IO
IRQ1 / MSCK
IRQ8# / GPI1
IRQ12 / MSDT
IRQ14
IRQ15
SPKR
N2
V3
N4
T14
U14
U9
I / IO
I/I
I / IO
I
I
O
I/O Read. IOR# is the command to an ISA I/O slave
device that the slave may drive data on to the ISA data bus.
I/O Write. IOW# is the command to an ISA I/O slave
device that the slave may latch data from the ISA data bus.
Memory Read. MEMR# is the command to a memory
slave that it may drive data onto the ISA data bus.
Memory Write. MEMW# is the command to a memory
slave that it may latch data from the ISA data bus.
Interrupt 1 (optional external Keyboard Controller).
Interrupt 8 (optional external RTC).
Interrupt 12 (optional external PS2 Mouse Controller).
Interrupt 14 (IDE Primary Channel).
Interrupt 15 (IDE Secondary Channel).
Speaker Drive. Output of internal timer/counter 2.
LA21 / USBOC3# / GPO21
LA20 / USBOC2# / GPO20
SA[19:18],
SA17 / strap,
SA16 / strap,
SA[15:0] / SDD[15:0]
SD15 / LGNT2# / GPO11,
SD14 / LREQ2# / GPI13,
SD13 / LGNT1# / GPO10,
SD12 / LREQ1# / GPI12,
SD11 / HGNT2# / GPO9,
SD10 / HREQ2# / GPI11,
SD9 / HGNT1# / GPO8,
SD8 / HREQ1# / GPI10,
SD7,
SD6,
SD5,
SD4,
SD3,
SD2,
SD1,
SD0
IOR# / GPO22
Signal Description
System Address Bus. Allows access to physical memory
devices (e.g., BIOS ROMs) up to 4 Mbytes.
System Address Bus. These address lines are used to
interface to BIOS ROMs but may also be used to
implement a subset of the ISA bus if required. SA[19-16]
are connected to ISA bus SA[19-16] directly. SA[19-17]
are also connected to LA[19-17] of the ISA bus.
IO
Serial IRQ
Signal Name
SERIRQ
Pin #
I/O
V9
I
Preliminary Revision 0.8 October 29, 1999
Signal Description
Serial IRQ (Rx68[3] = 1 and Rx74[6] = 0)
-21-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Internal Keyboard Controller
Signal Name
Pin #
I/O
MSCK / IRQ1
N2
IO / I
MSDT / IRQ12
N4
IO / I
KBCK / A20GATE
M4
IO / I
KBDT / KBRC
N1
IO / I
KBCS# / ROMCS# / strap
T9
O/O/I
Signal Description
MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Clock. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 1. Interrupt 1 (external KBC).
MultiFunction Pin (Internal mouse controller enabled by Rx5A[1])
Rx5A[1]=1 Mouse Data. From internal mouse controller.
Rx5A[1]=0 Interrupt Request 12. Interrupt 12 (ext PS2 mouse ctlr).
MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0])
Rx5A[0]=1 Keyboard Clock. From internal keyboard controller
Rx5A[0]=0 Gate A20. Input from external keyboard controller.
MultiFunction Pin (Internal keyboard controller enabled by Rx5A[0])
Rx5A[0]=1 Keyboard Data. From internal keyboard controller.
Rx5A[0]=0 Keyboard Reset. From external keyboard controller (KBC)
for CPURST# generation
Keyboard Chip Select (Rx5A[0]=0). To external keyboard controller chip.
Chip Selects
Signal Name
Pin #
I/O
ROMCS# / KBCS# / strap
MCCS# / GPO17 / strap
T9
W6
O/O/I
O / IO
PCS0# / GPO16 / strap
Y6
PCS1# / ACSDIN2 / GPIO19
J1
Signal Description
ROM Chip Select (Rx5A[0]=1). Chip Select to the BIOS ROM.
Microcontroller Chip Select (Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).
Asserted during read or write accesses to I/O ports 62h or 66h.
O / IO / IO Programmable Chip Select 0. (Rx76[1] = 1 and Rx8B[0] = 1). Asserted
during I/O cycles to programmable read or write ISA I/O port ranges. See
also Rx59[3] and Rx77[2].
O / I / IO Programmable Chip Select 1.
Preliminary Revision 0.8 October 29, 1999
-22-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
General Purpose Inputs
Signal Name
Pin #
I/O
GPI0
GPI1 / IRQ8#
GPI2 / EXTSMI#
GPI3 / RING#
GPI4 / LID
GPI5 / BATLOW#
GPI6 / PME#
GPI7 / SMBALRT#
GPI8 / INTRUDER#
GPI9 / APICCLK
GPI10 / SD8 / HREQ1#
GPI11 / SD10 / HREQ2#
GPI12 / SD12 / LREQ1#
GPI13 / SD14 / LREQ2#
GPI14 / WSC# / APICREQ#
GPI15 / LDRQ# / ACSDIN3
GPI16 / CPUMISS
GPI17 / AOLGPI / THRM
GPI18 / GPO18 / FAN2 / SLPBTN#
GPI19 / GPO19 / ACSDIN2 / PCS1#
GPI20
GPI21
GPI22
GPI23
GPI24 / GPO24 / GPIOA
GPI25 / GPO25 / GPIOC / ATEST
GPI26 / GPO26 / SMBDT2
GPI27 / GPO27 / SMBCK2
GPI28 / GPO28 / APICD0 / APICCS#
GPI29 / GPO29 / APICD1 / APICACK#
GPI30 / GPO30 / GPIOD / DTEST / SCIOUT#
GPI31 / GPO31 / GPIOE
F4
V3
T4
U3
Y2
T3
U1
T2
F3
Y3
Y11
W11
U10
W10
V4
Y8
R5
P3
K3
J1
I
I/I
I / IO
I/I
I/I
I/I
I/I
I/I
I/I
I/I
I / IO / I
I / IO / I
I / IO / I
I / IO / I
I/I/I
I/I/I
I/I
I/I/I
I/O/I/I
I/O/I/O
Preliminary Revision 0.8 October 29, 1999
V2
J2
R2
R1
W4
Y4
Y1
W3
Signal Description
General Purpose Input 0
General Purpose Input 1 (Rx5A[2] = 1)
General Purpose Input 2
General Purpose Input 3
General Purpose Input 4
General Purpose Input 5
General Purpose Input 6
General Purpose Input 7
General Purpose Input 8
General Purpose Input 9
General Purpose Input 10
General Purpose Input 11
General Purpose Input 12
General Purpose Input 13
General Purpose Input 14
General Purpose Input 15
General Purpose Input 16
General Purpose Input 17
General Purpose Input 18
General Purpose Input 19
General Purpose Input 20
General Purpose Input 21
General Purpose Input 22
General Purpose Input 23
I / O / IO
General Purpose Input 24
I / O / IO / O
General Purpose Input 25
I / O / IO
General Purpose Input 26
I / O / IO
General Purpose Input 27
I/O/O/O
General Purpose Input 28
I/O/O/O
General Purpose Input 29
I / O / IO / O / O General Purpose Input 30
I / O / IO
General Purpose Input 31
-23-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
General Purpose Outputs
Signal Name
GPO0 / SLOWCLK
GPO1 / SUSA#
GPO2 / SUSB#
GPO3 / SUSST1#
GPO4 / SUSCLK
GPO5 / CPUSTP#
GPO6 / PCISTP#
GPO7 / SLP#
GPO8 / SD9 / HGNT1#
GPO9 / SD11 / HGNT2#
GPO10 / SD13 / LGNT1#
GPO11 / SD15 / LGNT2#
GPO12
GPO13
GPO14 / IRTX
GPO15 / IRRX
GPO16 / PCS0#
GPO17 / MCCS#
GPO18 / GPI18 / FAN2 / SLPBTN#
GPO19 / GPI19 / PCS1# / ACSDIN2
GPO20 / LA20 / USBOC2#
GPO21 / LA21 / USBOC3#
GPO22 / IOR#
GPO23 / IOW#
GPO24 / GPI24 / GPIOA
GPO25 / GPI25 / GPIOC / ATEST
GPO26 / GPI26 / SMBDT2
GPO27 / GPI27 / SMBCK2
GPO28 / GPI28 / APICD0 / APICCS#
GPO29 / GPI29 / APICD1 / APICACK#
GPO30 / GPI30 / GPIOD / DTEST / SCIOUT#
GPO31 / GPI31 / GPIOE
Preliminary Revision 0.8 October 29, 1999
Pin #
I/O
R4
O/O
P1
P2
N5
P4
W2
W1
U6
W11
T10
Y10
V10
R8
U8
Y6
W6
K3
J1
W13
Y13
U7
T7
V2
J2
R2
R1
W4
Y4
Y1
W3
Signal Description
General Purpose Output 0. (Func 4 Rx54[1-0] =
00). Output value determined by PMU I/O Rx4C[0]
O/O
General Purpose Output 1.
O/O
General Purpose Output 2.
O/O
General Purpose Output 3.
O/O
General Purpose Output 4.
O/O
General Purpose Output 5.
O/O
General Purpose Output 6.
O/O
General Purpose Output 7.
O / IO / O
General Purpose Output 8.
O / IO / O
General Purpose Output 9.
O / IO / O
General Purpose Output 10.
O / IO / O
General Purpose Output 11.
General Purpose Output 12.
General Purpose Output 13.
O/O
General Purpose Output 14 (Rx76[5] = 1)
O/I
General Purpose Output 15 (Rx76[5] = 1)
O/O
General Purpose Output 16.
O/O
General Purpose Output 17.
O/I/I/I
General Purpose Output 18.
O/I/O/I
General Purpose Output 19.
O / IO / I
General Purpose Output 20.
O / IO / I
General Purpose Output 21.
O/O
General Purpose Output 22.
O/O
General Purpose Output 23.
O / I / IO
General Purpose Output 24.
O / I / IO / O
General Purpose Output 25.
O / I / IO
General Purpose Output 26.
O / I / IO
General Purpose Output 27.
O/I/O/O
General Purpose Output 28.
O/I/O/O
General Purpose Output 29.
O / I / IO / O / O General Purpose Output 30.
O / I / IO
General Purpose Output 31.
-24-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
General Purpose I/Os
Signal Name
GPIOA / GPI24 / GPO24
GPIOB
GPIOC / GPI25 / GPO25 / ATEST
GPIOD / GPI30 / GPO30 / DTEST
/ SCIOUT#
GPIOE / GPI31 / GPO31
Pin #
I/O
V2
IO / I / O
J2
Y1
W3
Signal Description
General Purpose I/O A / 24 (Rx76[0] = 0). GPOWE# if Rx76[0]
= 1. See also Rx74[2]
General Purpose I/O B
IO / I / O / O General Purpose I/O C / 25. (Rx76[2] = 0). See also Rx74[4]
IO / I / O / O General Purpose I/O D / 30. (Rx76[3] = 0). See also Rx74[5]
O
IO
General Purpose I/O E / 31.
Hardware Monitoring
Signal Name
UIC1
UIC2
UIC3
UIC4
UIC5
DTD+
DTDVREF
FAN1
FAN2 / SLPBTN# / GPI18 / GPO18
DTEST / GPIOD (30) / SCIOUT#
ATEST / GPIOC (25)
Pin #
I/O
M1
M3
M2
L4
L1
L2
L3
K1
K2
K3
Y1
J2
Analog I
Analog I
Analog I
Analog I
Analog I
Analog I
Analog I
P
I
I/I/I/O
O
O
Preliminary Revision 0.8 October 29, 1999
Signal Description
Universal Input Channel. For temperature / voltage monitoring.
Universal Input Channel. For temperature / voltage monitoring.
Universal Input Channel. For temperature / voltage monitoring.
Universal Input Channel. For temperature / voltage monitoring.
Universal Input Channel. For temperature / voltage monitoring.
CPU DTD (Thermal Diode) Channel Plus.
CPU DTD (Thermal Diode)Channel Minus.
Voltage Reference for Thermal Sensing (5V ±5%)
Fan Speed Monitor 1. (3.3V only)
Fan Speed Monitor 2. (3.3V only)
Hardware Monitor Digital Test Out
Hardware Monitor Analog Test Out
-25-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Power Management and External State Monitoring
Signal Name
Pin #
I/O
PME# / GPI6
EXTSMI# / GPI2
U1
T4
I/I
IOD / I
SMBALRT# / GPI7
T2
I/I
THRM / AOLGPI / GPI17
P3
I/I/I
LID / GPI4
Y2
I/I
RING# / GPI3
U3
I/I
BATLOW# / GPI5
CPUMISS / GPI16
T3
R5
I/I
I/I
AOLGPI / GPI17 / THRM
INTRUDER# / GPI8
RSMRST#
P3
F3
F5
I/I/I
I/I
I
SUSA# / GPO1 / strap
P1
O/O/I
SUSB# / GPO2
P2
O/O
SUSC# / GPO
N3
O/O
SUSST1# / GPO3
N5
O/O
SUSCLK / GPO4
P4
O/O
Preliminary Revision 0.8 October 29, 1999
Signal Description
Power Management Event. (Rx74[1]=0) (1K PU to VCCS if not used)
External System Management Interrupt. When enabled to allow it, a
falling edge on this input causes an SMI# to be generated to the CPU to
enter SMI mode. (10K PU to VCCS if not used) (3.3V only)
SMB Alert (System Management Bus I/O space Rx08[3] = 1). When the
chip is enabled to allow it, assertion generates an IRQ or SMI or power
management event. (10K PU to VCCS if not used)
Monitor Input - Thermal Alarm. (Rx74[1]=1) (1K PU to VCCS if not
used)
Monitor Input - Notebook Computer Display Lid Open / Closed.
Used by the Power Management subsystem to monitor the opening and
closing of the display lid of notebook computers. Can be used to detect
either low-to-high and/or high-to-low transitions to generate an SMI#. The
VT8231 performs a 200 usec debounce of this input if Function 4 Rx40[5]
is set to 1. (10K PU to VCCS if not used)
Monitor Input – Modem Ring. May be connected to external modem
circuitry to allow the system to be re-activated by a received phone call.
(10K PU to VCCS if not used)
Monitor Input - Battery Low. (10K PU to VCCS if not used)
Monitor Input - CPU Missing. Indicates whether the CPU is plugged in
correctly.
Monitor Input - Awake On LAN External Event.
Monitor Input – Chassis Intrusion.
Resume Reset. Resets the internal logic connected to the VCCS power
plane and also resets portions of the internal RTC logic.
Suspend Plane A Control (Rx74[7]=0 and Function 4 Rx54[2]=0).
Asserted during power management POS, STR, and STD suspend states.
Used to control the primary power plane. (10K PU to VCCS if not used)
Suspend Plane B Control (Rx74[7]=0 and Function 4 Rx54[3]=0).
Asserted during power management STR and STD suspend states. Used
to control the secondary power plane. (10K PU to VCCS if not used)
Suspend Plane C Control. Asserted during power management STD
suspend state. Used to control the tertiary power plane. Also connected to
ATX power-on circuitry.
Suspend Status 1 (Func4 Rx54[4] = 1 for GPO3). Typically connected to
the North Bridge to provide information on host clock status. Asserted
when the system may stop the host clock, such as Stop Clock or during
POS, STR, or STD suspend states. Connect 10K PU to VCCS.
Suspend Clock. 32.768 KHz output clock for use by the North Bridge
(e.g., Apollo MVP3 or MVP4) for DRAM refresh purposes. Stopped
during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VCCS.
-26-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Resets, Clocks, and Clock Control
Signal Name
Pin #
I/O
PWRGD
PWRBTN#
E3
U2
I
I
SLPBTN# /
FAN2 /
GPIO18
PCIRST#
K3
I/I
/ IO
E4
O
RTCX1
E2
I
RTCX2
OSC
SLOWCLK /
GPO0
CPUSTP# /
GPO5
E1
T12
R4
O
I
O
W2
O/
O
PCISTP# /
GPO6
W1
O/
O
Preliminary Revision 0.8 October 29, 1999
Signal Description
Power Good. Connected to the PWRGOOD signal on the Power Supply.
Power Button. Used by the Power Management subsystem to monitor an
external system on/off button or switch. The VT8231 performs a 200us
debounce of this input if Function 4 Rx40[5] is set to 1. (3.3V only)
Sleep Button. Used by the power management subsystem to monitor an
external system sleep button or switch (Function 4 Rx40[6] = 1). Connect to
VCC if not used.
PCI Reset. Active low reset signal for the PCI bus. The VT8231 will assert
this pin during power-up or from the control register.
RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is
used for the internal RTC and for power-well power management logic.
RTC Crystal Output: 32.768 KHz crystal output
Oscillator. 14.31818 MHz clock signal used by the internal Timer.
Slow Clock. Frequency selectable if PMU function 4 Rx54[1-0] is nonzero
(set to 01, 10, or 11).
CPU Clock Stop (Rx75[4] = 0). Signals the system clock generator to
disable the CPU clock outputs. Not connected if not used. See also PMU I/O
Rx2C[3].
PCI Clock Stop (Rx75[5] = 0). Signals the system clock generator to disable
the PCI clock outputs. Not connected if not used.
-27-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Power and Ground
Signal Name
Pin #
I/O
F7, F9, F12-F13, F15,
G6, G8-G10, G12,
H6, J6, J15, K15,
L6, M6, M15, N6,
P8-P9, P11-P13, P15,
R7, R9-R10, R13-R15
G7, G11, G14, H15,
J8-J13, K6, K8-K13,
L8-L13, L15, M8-M13,
N15, P7, P10, P14
P5, P6
P
Core Power. 3.3V nominal (3.15V to 3.45V). This supply is turned on only
when the mechanical switch on the power supply is turned on and the
PWRON signal is conditioned high. These pins should be connected to the
same voltage as the CPU I/O circuitry. Internally connected to hardware
monitoring system voltage detection circuitry for 3.3V monitoring.
P
Ground. Connect to primary motherboard ground plane.
P
VBAT
F2
P
VREF
VCCHWM
K1
M5
P
P
GNDHWM
VCCMII
L5
F16, K16
P
P
VCCRAM
G15
P
GNDRAM
VCCPLL
G13
L16
P
P
GNDPLL
VCCUSB
M16
E15
P
P
GNDUSB
D15
P
Suspend Power. Always available unless the mechanical switch of the power
supply is turned off. If the “soft-off” state is not implemented, then this pin
can be connected to VCC. Signals powered by or referenced to this plane are:
SMBCK1/DT1, KBCK/DT, MSCK/DT, PWRBTN#, SUSC#, GPO0 /
SLOWCLK, GPO1 / SUSA#, GPO2 / SUSB#, GPO3 / SUSST1#, GPO4 /
SUSCLK, GPI1 / IRQ8#, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID,
GPI5 / BATLOW#, GPI6 / PME#, GPI7 / SMBALRT#, GPI16 / CPUMISS,
GPI17 / AOLGPI / THRM, GPIO26 / SMBDT2, GPIO27 / SMBCK2
RTC Battery. Battery input for internal RTC. Signals powered by or
referenced to this plane are: RTCX1, RTCX2, PWRGD, RSMRST#, GPI0,
and INTRUDER#.
Voltage Reference (5V ±5%). For thermal sensing and 5V input tolerance.
Hardware Monitor Power. Power for hardware monitoring subsystem
(voltage monitoring, temperature monitoring, and fan speed monitoring).
Connect to VCC through a ferrite bead. Signals powered by or referenced to
this plane are: UIC[5:1], DTD+/-, FAN1, FAN2 / SLPBTN# / GPIO18
Hardware Monitor Ground. Connect to GND through a ferrite bead.
LAN MII Power. Power for LAN Media Independent Interface (interface to
external PHY). Connect to VCC through a ferrite bead. Signals powered by
or referenced to this plane are: MCRS, MCOL, MDCK, MDIO, MTXD[3:0],
MTXENA, MTXCLK, MRXERR, MRXCLK, MRXDV, and MRXD[3:0]
LAN RAM Power. Power for LAN internal RAM. Connect to VCC through
a ferrite bead.
LAN RAM Ground. Connect to GND through a ferrite bead.
PLL Power. Power for internal PLL. Connect to VCC through a ferrite
bead.
PLL Ground. Connect to GND through a ferrite bead.
USB Differential Output Power. Power for USB differential outputs
(USBP0+, P0-, P1+, P1-, P2+, P2-, P3+, P3-). Connect to VCC through a
ferrite bead.
USB Differential Output Ground. Connect to GND through a ferrite bead.
VCC (27 Pins)
GND (27 Pins)
VCCSUS
Preliminary Revision 0.8 October 29, 1999
Signal Description
-28-
Pinouts
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
REGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT8231. These tables also document the
power-on default value (“Default”) and access type (“Acc”)
for each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see
individual register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
Table 2. System I/O Map
Port
00-1F
20-3F
40-5F
60-6F
(60h)
(61h)
(64h)
70-77
78-7F
80
81-8F
90-91
92
93-9F
A0-BF
C0-DF
E0-FF
Function
Actual Port Decoding
Master DMA Controller
0000 0000 000x nnnn
Master Interrupt Controller 0000 0000 001x xxxn
Timer / Counter
0000 0000 010x xxnn
Keyboard Controller
0000 0000 0110 xnxn
KBC Data
0000 0000 0110 x0x0
Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1
KBC Command / Status
0000 0000 0110 x1x0
RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn
-available for system use- 0000 0000 0111 1xxx
-reserved- (debug port)
0000 0000 1000 0000
DMA Page Registers
0000 0000 1000 nnnn
-available for system use- 0000 0000 1001 000x
System Control
0000 0000 1001 0010
-available for system use- 0000 0000 1001 nnnn
Slave Interrupt Controller 0000 0000 101x xxxn
Slave DMA Controller
0000 0000 110n nnnx
-available for system use- 0000 0000 111x xxxx
100-CF7
-available for system use*
CF8-CFB PCI Configuration Address 0000 1100 1111 10xx
CFC-CFF PCI Configuration Data
0000 1100 1111 11xx
D00-FFFF -available for system use-
* On-Chip Super-I/O Functions – PC-Standard Port Addresses
200-20F
Game Port
2E8-2EF COM4
2F8-2FF COM2
378-37F
Parallel Port (Standard & EPP)
3E8-3EF COM3
3F0-3F1
Configuration Index / Data
3F0-3F7
Floppy Controller
3F8-3FF COM1
400-402
Parallel Port (ECP Extensions)
Preliminary Revision 0.8 October 29, 1999
-29-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Table 3. Registers
Legacy I/O Registers (continued)
Legacy I/O Registers
Port
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Master DMA Controller Registers
Channel 0 Base & Current Address
Channel 0 Base & Current Count
Channel 1 Base & Current Address
Channel 1 Base & Current Count
Channel 2 Base & Current Address
Channel 2 Base & Current Count
Channel 3 Base & Current Address
Channel 3 Base & Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer FF
Master Clear
Clear Mask
Read / Write Mask
Default Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
Port Master Interrupt Controller Regs
20 Master Interrupt Control
21 Master Interrupt Mask
20 Master Interrupt Control Shadow
21 Master Interrupt Mask Shadow
* RW if shadow registers are disabled
Default Acc
—
*
—
*
—
RW
—
RW
Port
40
41
42
43
Timer/Counter Registers
Timer / Counter 0 Count
Timer / Counter 1 Count
Timer / Counter 2 Count
Timer / Counter Control
Default Acc
RW
RW
RW
WO
Port
60
61
64
Keyboard Controller Registers
Keyboard Controller Data
Misc Functions & Speaker Control
Keyboard Ctrlr Command / Status
Default Acc
RW
RW
RW
DMA Page Registers
DMA Page – DMA Channel 0
DMA Page – DMA Channel 1
DMA Page – DMA Channel 2
DMA Page – DMA Channel 3
DMA Page – DMA Channel 4
DMA Page – DMA Channel 5
DMA Page – DMA Channel 6
DMA Page – DMA Channel 7
Default Acc
RW
RW
RW
RW
RW
RW
RW
RW
Port
92
System Control Registers
System Control
Default Acc
RW
Port Slave Interrupt Controller Regs
Default Acc
A0 Slave Interrupt Control
—
*
A1 Slave Interrupt Mask
—
*
A0 Slave Interrupt Control Shadow
—
RW
A1 Slave Interrupt Mask Shadow
—
RW
* RW accessible if shadow registers are disabled
Port
C0
C2
C4
C6
C8
CA
CC
CE
D0
D2
D4
D6
D8
DA
DC
DE
Port CMOS / RTC / NMI Registers
Default Acc
70 CMOS Memory Address & NMI Disa
WO
71 CMOS Memory Data (128 bytes)
RW
72 CMOS Memory Address
RW
73 CMOS Memory Data (256 bytes)
RW
74 CMOS Memory Address
RW
75 CMOS Memory Data (256 bytes)
RW
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC
is disabled.
Preliminary Revision 0.8 October 29, 1999
Port
87
83
81
82
8F
8B
89
8A
-30-
Slave DMA Controller Registers
Channel 0 Base & Current Address
Channel 0 Base & Current Count
Channel 1 Base & Current Address
Channel 1 Base & Current Count
Channel 2 Base & Current Address
Channel 2 Base & Current Count
Channel 3 Base & Current Address
Channel 3 Base & Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer FF
Master Clear
Clear Mask
Read / Write Mask
Default Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Super-I/O Configuration Registers (I/O Space)
Port
3F0
3F1
Super-I/O Configuration Registers
Super-I/O Config Index (Rx85[1]=1)
Super-I/O Config Data (Rx85[1]=1)
Super-I/O I/O Ports
Default Acc
00
RW
00
RW
Super-I/O Config Registers (Indexed via Port 3F0/1)
Offset
00-DF
E0
E1
E2
E3
E4-E5
E6
E7
E8
E9-ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9-FB
FC
FD-FF
Super-I/O Control
-reservedSuper-I/O Device ID
Super-I/O Device Revision
Function Select
Floppy Ctrlr Base Addr (def = 3F0-7)
-reservedParallel Port Base Addr (def = 378-F)
Serial Port 1 Base Addr (def = 3F8-F)
Serial Port 2 Base Addr (def = 2F8-F)
-reservedSerial Port Configuration
Power Down Control
Parallel Port Control
Serial Port Control
Test Mode (Do Not Program)
-reservedTest Mode (Do Not Program) 2
-reservedFloppy Controller Configuration
-reservedFloppy Controller Drive Select
-reservedGeneral Purpose I/O
-reserved-
Preliminary Revision 0.8 October 29, 1999
Default
00
3C
00
00
FC
00
DE
FE
BE
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Acc
RO
RW
RW
RW
RW
RO
RW
RW
RW
RO
RW
RW
RW
RW
RW
RO
RW
RO
RW
RO
RW
RO
RW
RO
-31-
Offset
00-01
02
03
04
04
05
06
07
07
Floppy Disk Controller (3F0-3F7)
-reservedFDC Command
-reservedFDC Main Status
FDC Data Rate Select
FDC Data
-reservedDiskchange Status
FDC Configuration Control
Default
00
-00
-00
-00
-00
Acc
-RW
-RO
WO
RW
-RO
WO
Offset
00
01
02
03
04
05
06
07
400h
401h
402h
Parallel Port (378-37F typical)
Parallel Port Data
Parallel Port Status
Parallel Port Control
EPP Address
EPP Data Port 0
EPP Data Port 1
EPP Data Port 2
EPP Data Port 3
ECP Data / Configuration A
ECP Configuration B
ECP Extended Control
Default
--E0
Acc
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
Offset
0
1
2
2
3
4
5
6
7
9-8
A-F
Serial Port 1 (COM1=3F8, 3=3E8)
Transmit (Wr) / Receive (Rd) Buffer
Interrupt Enable
FIFO Control
Interrupt Status
UART Control
Handshake Control
UART Status
Handshake Status
Scratchpad
Baud Rate Generator Divisor
-undefined-
Default Acc
RW
RW
WO
RO
RW
RW
RW
RW
RW
RW
--
Offset
0
1
2
2
3
4
5
6
7
9-8
A-F
Serial Port 2 (COM2=2F8, 4=2E8)
Transmit (Wr) / Receive (Rd) Buffer
Interrupt Enable
FIFO Control
Interrupt Status
UART Control
Handshake Control
UART Status
Handshake Status
Scratchpad
Baud Rate Generator Divisor
-undefined-
Default Acc
RW
RW
WO
RO
RW
RW
RW
RW
RW
RW
--
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Function 0 Registers – PCI-to-ISA Bridge
Configuration Space PCI-to-ISA Bridge Header Registers
Offset
1-0
3-2
5-4
7-6
8
9
A
B
C
D
E
F
10-27
28-2B
2F-2C
30-33
34-3B
3C
3D
3E
3F
PCI Configuration Space Header
Vendor ID
Device ID
Command
Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
-reserved- (cache line size)
-reserved- (latency timer)
Header Type
Built In Self Test (BIST)
-reserved- (base address registers)
-reserved- (unassigned)
Subsystem ID Read
-reserved- (expan. ROM base addr)
-reserved- (unassigned)
-reserved- (interrupt line)
-reserved- (interrupt pin)
-reserved- (min gnt)
-reserved- (max lat)
Default
1106
8231
0087
0200
nn
00
01
06
00
00
80
00
00
00
00
00
00
00
00
00
00
Acc
RO
RO
RW
WC
RO
RO
RO
RO
—
—
RO
RO
—
—
RO
—
—
—
—
—
—
Configuration Space PCI-to-ISA Bridge-Specific Registers
Offset
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4F-4E
ISA Bus Control
ISA Bus Control
ISA Test Mode
ISA Clock Control
ROM Decode Control
Keyboard Controller Control
Type F DMA Control
Miscellaneous Control 1
Miscellaneous Control 2
Miscellaneous Control 3
-reservedIDE Interrupt Routing
-reservedDMA / Master Mem Access Control 1
DMA / Master Mem Access Control 2
DMA / Master Mem Access Control 3
Preliminary Revision 0.8 October 29, 1999
Default
00
00
00
00
00
00
00
00
01
00
04
00
00
00
0300
Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
—
RW
RW
RW
Offset Plug and Play Control
Default
50 PnP DMA Request Control
2D
51 PnP Routing for LPT / FDC IRQ
00
52 PnP Routing for COM2 / COM1 IRQ
00
53 -reserved00
54 PCI IRQ Edge / Level Select
00
55 PnP Routing for PCI INTA
00
56 PnP Routing for PCI INTB-C
00
57 PnP Routing for PCI INTD
00
58 -reserved00
59 -reserved04
5A KBC / RTC Control
x4†
5B Internal RTC Test Mode
00
5C DMA Control
00
5D-5E -reserved00
5F -reserved- (do not program)
04
† Bit 7-4 power-up default depends on external strapping
Acc
RW
RW
RW
—
RW
RW
RW
RW
—
—
RW
RW
RW
—
RW
Offset
61-60
63-62
65-64
67-66
69-68
6B-6A
6D-6C
6F-6E
Distributed DMA
Channel 0 Base Address / Enable
Channel 1 Base Address / Enable
Channel 2 Base Address / Enable
Channel 3 Base Address / Enable
Serial IRQ Control
Channel 5 Base Address / Enable
Channel 6 Base Address / Enable
Channel 7 Base Address / Enable
Acc
RW
RW
RW
RW
RW
RW
RW
RW
Offset
70
71-73
74
75
76
77
79-78
7B-7A
7D-7C
7F-7E
80
81
82
83
84
85
86-87
88
89
8A
8B
8D-8C
8F-8E
90-FF
Miscellaneous
Default Acc
Subsystem ID Write
00
WO
-reserved00
—
GPIO Control 1
00
RW
GPIO Control 2
00
RW
GPIO Control 3
00
RW
GPIO Control 4
00
RW
PCS0# I/O Port Address
0000 0000 RW
PCS1# I/O Port Address
0000 0000 RW
PCI DMA Channel Enable
0000
RW
32-Bit DMA Control
0000
RW
Programmable Chip Select Mask
00
RW
ISA Positive Decoding Control 1
00
RW
ISA Positive Decoding Control 2
00
RW
ISA Positive Decoding Control 3
00
RW
ISA Positive Decoding Control 4
00
RW
Extended Function Enable
00
RW
PnP IRQ/DRQ Test (do not program)
00
RW
PLL Test
00
RW
PLL Control
00
RW
PCS2/3 I/O Port Address Mask
00
RW
PCS Control
00
RW
PCS2# I/O Port Address
0000
RW
PCS3# I/O Port Address
0000
RW
-reserved00
—
-32-
Default
0000
0000
0000
0000
0000
0000
0000
0000
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Function 1 Registers – IDE Controller
Configuration Space IDE Header Registers
Offset PCI Configuration Space Header
1-0 Vendor ID
3-2 Device ID
5-4 Command
7-6 Status
8 Revision ID
9 Programming Interface
A Sub Class Code
B Base Class Code
C -reserved- (cache line size)
D Latency Timer
E Header Type
F Built In Self Test (BIST)
13-10 Base Address – Pri Data / Command
17-14 Base Address – Pri Control / Status
1B-18 Base Address – Sec Data / Command
1F-1C Base Address – Sec Control / Status
23-20 Base Address – Bus Master Control
24-2F -reserved- (unassigned)
30-33 -reserved- (expan ROM base addr)
34 Capability Pointer
35-3B -reserved- (unassigned)
3C Interrupt Line
3D Interrupt Pin
3E Minimum Grant
3F Maximum Latency
Default
1106
0571
0080
0280
nn
85
01
01
00
00
00
00
000001F0
000003F4
00000170
00000374
0000CC01
00
00
C0
00
0E
00
00
00
Acc
RO
RO
RO
RW
RO
RW
RO
RO
—
RW
RO
RO
RO
RO
RO
RO
RW
—
—
RO
—
RW
RO
RO
RO
Configuration Space IDE-Specific Registers
Offset Configuration Space IDE Registers Default
40 IDE Chip Enable
08
41 IDE Configuration
02
42 -reserved- (do not program)
09
43 IDE FIFO Configuration
3A
44 IDE Miscellaneous Control 1
68
45 IDE Miscellaneous Control 2
03
46 IDE Miscellaneous Control 3
C0
A8A8A8A8
4B-48 IDE Drive Timing Control
4C IDE Address Setup Time
FF
4D -reserved- (do not program)
00
4E Sec Non-1F0 IDE Port Access Timing
FF
4F Pri Non-1F0 IDE Port Access Timing
FF
Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Preliminary Revision 0.8 October 29, 1999
Configuration Space IDE-Specific Registers (continued)
Offset Configuration Space IDE Registers Default Acc
53-50 UltraDMA Extended Timing Control 03030303 RW
54 UltraDMA FIFO Control
RW
06
55-5F -reserved00
—
61-60 IDE Primary Sector Size
RW
0200
62-67 -reserved00
—
69-68 IDE Secondary Sector Size
RW
0200
69-6F -reserved00
—
70 IDE Primary Status
00
RW
71 IDE Primary Interrupt Control
00
RW
72-77 -reserved00
—
78 IDE Secondary Status
00
RW
79 IDE Secondary Interrupt Control
00
RW
7A-7F -reserved00
—
83-80 IDE Primary S/G Descriptor Address 0000 0000 RW
84-87 -reserved00
—
8B-88 IDE Secondary S/G Descriptor Addr 0000 0000 RW
8C-BF -reserved00
—
C3-C0 PCI PM Block 1
0201
RO
C7-C4 PCI PM Block 2
0000
RW
C8-FF -reserved00
—
I/O Registers – IDE Controller (SFF 8038 v1.0 Compliant
Offset IDE I/O Registers
Default Acc
0 Primary Channel Command
00
RW
1 -reserved00
—
2 Primary Channel Status
00
WC
3 -reserved00
—
4-7 Primary Channel PRD Table Addr
00
RW
8 Secondary Channel Command
00
RW
9 -reserved00
—
A Secondary Channel Status
00
WC
B -reserved00
—
C-F Secondary Channel PRD Table Addr
00
RW
-33-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Function 2 Registers – USB Controller Ports 0-1
PCI Function 3 Registers – USB Controller Ports 2-3
Configuration Space USB Header Registers
Configuration Space USB Header Registers
Offset
1-0
3-2
5-4
7-6
8
9
A
B
C
D
E
F
10-1F
23-20
24-3B
3C
3D
3E-3F
PCI Configuration Space Header
Vendor ID
Device ID
Command
Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Latency Timer
Header Type
BIST
-reservedUSB I/O Register Base Address
-reservedInterrupt Line
Interrupt Pin
-reserved-
Default
1106
3038
0000
0200
nn
00
03
0C
00
16
00
00
00
00000301
00
00
04
00
Acc
RO
RO
RW
WC
RO
RO
RO
RO
RO
RW
RO
RO
—
RW
—
RW
RO
—
Configuration Space USB-Specific Registers
Offset
40
41
42
43
44-45
46-47
48-5F
60
61-7F
83-80
84
85-BF
C1-C0
C2-FF
USB Control
USB Miscellaneous Control 1
USB Miscellaneous Control 2
USB FIFO Control
-reserved-reserved- (test, do not program)
-reserved- (test)
-reservedUSB Serial Bus Release Number
-reservedPM Capability
PM Capability Status
-reservedUSB Legacy Support
-reserved-
USB I/O Registers
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start Of Frame Modify
Port 0 Status / Control
Port 1 Status / Control
-reserved-
Preliminary Revision 0.8 October 29, 1999
PCI Configuration Space Header
Vendor ID
Device ID
Command
Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Latency Timer
Header Type
BIST
-reservedUSB I/O Register Base Address
-reservedInterrupt Line
Interrupt Pin
-reserved-
Default
1106
3038
0000
0200
nn
00
03
0C
00
16
00
00
00
00000301
00
00
04
00
Acc
RO
RO
RW
WC
RO
RO
RO
RO
RO
RW
RO
RO
—
RW
—
RW
RO
—
USB Control
Default
USB Miscellaneous Control 1
00
USB Miscellaneous Control 2
10
USB FIFO Control
00
-reserved00
-reserved- (test only, do not program)
-reserved- (test)
-reserved00
USB Serial Bus Release Number
10
-reserved00
PM Capability
0002 0001
PM Capability Status
00
-reserved00
USB Legacy Support
2000
-reserved00
Acc
RW
RW
RW
RO
RW
RO
—
RO
—
RO
RW
—
RW
—
Configuration Space USB-Specific Registers
Default
00
10
00
00
Acc
RW
RW
RW
RO
RW
RO
00
—
RO
10
00
—
0002 0001 RO
00
RW
00
—
2000
RW
00
—
I/O Registers – USB Controller
Offset
1-0
3-2
5-4
7-6
B-8
C
11-10
13-12
14-1F
Offset
1-0
3-2
5-4
7-6
8
9
A
B
C
D
E
F
10-1F
23-20
24-3B
3C
3D
3E-3F
Offset
40
41
42
43
44-45
46-47
48-5F
60
61-7F
83-80
84
85-BF
C1-C0
C2-FF
I/O Registers - USB Controller
Default
0000
0000
0000
0000
00000000
40
0080
0080
00
Acc
RW
WC
RW
RW
RW
RW
WC
WC
—
Offset
1-0
3-2
5-4
7-6
B-8
C
11-10
13-12
14-1F
-34-
USB I/O Registers
USB Command
USB Status
USB Interrupt Enable
Frame Number
Frame List Base Address
Start Of Frame Modify
Port 2 Status / Control
Port 3 Status / Control
-reserved-
Default
0000
0000
0000
0000
00000000
40
0080
0080
00
Acc
RW
WC
RW
RW
RW
RW
WC
WC
—
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Function 4 Registers - Power Management
Configuration Space Power Management Header
Registers
Offset PCI Configuration Space Header
Default Acc
1-0 Vendor ID
RO
1106
3-2 Device ID
RO
3068
5-4 Command
0000
RO
7-6 Status
0280
WC
8 Revision ID
RO
nn
9 Programming Interface
RO
00†
A Sub Class Code
RO
00†
B Base Class Code
RO
00†
C Cache Line Size
00
RO
D Latency Timer
00
RO
E Header Type
00
RO
F BIST
00
RO
10-3F -reserved00
—
† The default values for these registers may be changed by
writing to offsets 61-63h (see below).
Configuration Space Hardware Monitor Registers
Offset
71-70
72-73
74
75-8F
System Management Bus
Hardware Mon IO Base (128 Bytes)
-reservedHardware Monitor Control
-reserved-
Default
0001
00
00
00
Acc
RW
—
RW
—
Configuration Space SMBus Registers
Offset
93-90
94-D1
D2
D3
D4
D5
D6
D7-FF
System Management Bus
Default
SMBus I/O Base (16 Bytes)
0000 0001
-reserved00
SMBus Host Configuration
00
SMBus Host Slave Command
00
SMBus Slave Address Shadow Port 1
00
SMBus Slave Address Shadow Port 2
00
SMBus Revision ID
nn
-reserved00
Acc
RW
—
RW
RW
RW
RW
RO
—
Configuration Space Power Management Registers
Offset
40
41
42
43
45-44
47-46
4B-48
4C
4D
4E-4F
53-50
54
55
56-57
58
59
5A
5B-60
61
62
63
64-7F
Power Management
Default Acc
General Configuration 0
00
RW
General Configuration 1
00
RW
ACPI Interrupt Select
00
RW
Internal Timer Read Test
—
RO
Primary Interrupt Channel
0000
RW
Secondary Interrupt Channel
0000
RW
Power Mgmt I/O Base (256 Bytes)
0000 0001 RW
Host Bus Power Management Control
00
RW
Throttle / Clock Stop Control
00
RW
-reserved00
—
GP Timer Control
0000 0000 RW
Power Well Control
00
RW
USB Wakeup Control
00
RW
-reserved00
—
GP2 / GP3 Timer Control
00
RW
GP2 Timer
00
RW
GP3 Timer
00
RW
-reserved00
—
Write value for Offset 9 (Prog Intfc)
00
WO
Write value for Offset A (Sub Class)
00
WO
Write value for Offset B (Base Class)
00
WO
-reserved00
—
Preliminary Revision 0.8 October 29, 1999
-35-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Space Power Management- Registers
I/O Space System Management Bus Registers
Offset
1-0
3-2
5-4
6-7
B-8
C-F
Basic Control / Status Registers
Power Management Status
Power Management Enable
Power Management Control
-reservedPower Management Timer
-reserved-
Default
0000
0000
0000
00
0000 0000
00
Acc
WC
RW
RW
—
RW
—
Offset
13-10
14
15
16-1F
Processor Registers
Processor and PCI Bus Control
Processor LVL2
Processor LVL3
-reserved-
Default
0000 0000
00
00
00
Acc
RW
RO
RO
—
Offset
21-20
23-22
25-24
26-27
General Purpose Registers
General Purpose Status
General Purpose SCI Enable
General Purpose SMI Enable
-reserved-
Default
0000
0000
0000
00
Acc
WC
RW
RW
—
Offset
29-28
2B-2A
2D-2C
2E
2F
33-30
37-34
3B-38
3C-3F
Generic Registers
Global Status
Global Enable
Global Control
-reservedSMI Command
Primary Activity Detect Status
Primary Activity Detect Enable
GP Timer Reload Enable
-reserved-
Default
0000
0000
0010
00
00
0000 0000
0000 0000
0000 0000
00
Acc
WC
RW
RW
—
RW
WC
RW
RW
—
Offset
40
41
42
43
44
45
46-47
4B-48
4F-4C
50-FF
General Purpose I/O Registers
Extended I/O Trap Status
-reservedExtended I/O Trap Enable
-reservedExternal SMI / GPI Input Value
SMI / IRQ / Resume Status
-reservedGPI Port Input Value
GPO Port Output Value
-reserved-
Default
00
00
00
00
input
00
00
input
Preliminary Revision 0.8 October 29, 1999
Offset
0
1
2
3
4
5
6
7
8
9
A-B
C-D
E-F
System Management Bus
SMBus Host Status
SMBus Slave Status
SMBus Host Control
SMBus Host Command
SMBus Host Address
SMBus Host Data 0
SMBus Host Data 1
SMBus Block Data
SMBus Slave Control
SMBus Shadow Command
SMBus Slave Event
SMBus Slave Data
-reserved-
Default
00
00
00
00
00
00
00
00
00
00
0000
0000
00
Acc
WC
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RO
—
Acc
WC
—
RW
—
RO
RO
—
RO
03FF FFFF RW
00
—
-36-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Space Hardware Monitor Registers
Offset
00-3F
00-12
13
14
15
16
17
18-1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Hardware Monitor
Value RAM
-reservedAnalog Data 15-8
Analog Data 7-0
Digital Data 7-0
Channel Counter
Data Valid & Channel Indicators
-reservedTSENS3 Hot Hi Limit
TSENS3 Hot Hysteresis Lo Lim
TSENS3 (Int) Temp Reading
TSENS1 (W13) Temp Reading
TSENS2 (Y13) Temp Reading
VSENS1 (U13) Voltage Reading
VSENS2 (V13) Voltage Reading
Internal Core VCC Voltage Reading
VSENS3 (W14) Voltage Reading
VSENS4 (Y14) Voltage Reading
-reserved- (-12V Voltage Reading)
-reserved- (-5V Voltage Reading)
FAN1 (T12) Count Reading
FAN2 (U12) Count Reading
VSENS1 (CPU) Voltage High Limit
VSENS1 (CPU) Voltage Low Limit
VSENS2 (NB) Voltage High Limit
VSENS2 (NB) Voltage Low Limit
Internal Core VCC High Limit
Internal Core VCC Low Limit
VSENS3 (5V) Voltage High Limit
VSENS3 (5V) Voltage Low Limit
VSENS4 (12V) Voltage High Limit
VSENS4 (12V) Voltage Low Limit
-reserved- (-12V Sense High Limit)
-reserved- (-12V Sense Low Limit)
-reserved- (-5V Sense High Limit)
-reserved- (-5V Sense Low Limit)
TSENS1 Hot High Limit
TSENS1 Hot Hysteresis Lo Lim
FAN1 Fan Count Limit
FAN2 Fan Count Limit
TSENS2 Hot High Limit
TSENS2 Hot Hysteresis Lo Lim
Stepping ID Number
Preliminary Revision 0.8 October 29, 1999
Default
Acc
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
—
RW
RW
RW
RW
RW
—
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
—
—
—
RW
RW
RW
RW
RW
RW
RW
Offset
40
41
42
43
44
45-46
47
48
49
4A
4B
4C-FF
-37-
Hardware Monitor (continued)
Hardware Monitor Configuration
Hardware Monitor Interrupt Status 1
Hardware Monitor Interrupt Status 2
Hardware Monitor Interrupt Mask 1
Hardware Monitor Interrupt Mask 2
-reservedHardware Monitor Fan Configuration
-reservedHW Mon Temp Value Lo-Order Bits
-reservedTemperature Interrupt Configuration
-reserved-
Default
08
00
00
00
00
00
50
00
00
00
15
00
Acc
RW
RO
RO
RW
RW
—
RW
—
RW
—
RW
—
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Function 5 & 6 Registers – AC97 / MC97 Codecs
Function 5 Configuration Space AC97 Header Registers
Function 6 Configuration Space MC97 Header Registers
Offset
1-0
3-2
5-4
7-6
8
9
A
B
C
D
E
F
13-10
17-14
1B-18
1F-1C
23-20
27-24
28-29
2F-2C
33-30
34
35-3B
3C
3D
3E
3F
Offset
1-0
3-2
5-4
7-6
8
9
A
B
C
D
E
F
13-10
17-14
1B-18
1F-1C
23-20
27-24
28-29
2F-2C
33-30
34
35-3B
3C
3D
3E
3F
PCI Configuration Space Header
Vendor ID
Device ID
Command
Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Latency Timer
Header Type
BIST
Base Address 0 - SGD Control/Status
Base Address 1 - FM NMI Status
Base Address 2 - MIDI Port
Base Address 3 (reserved)
Base Address 4 (reserved)
Base Address 5 (reserved)
-reservedSubsystem ID / SubVendor ID
Expansion ROM (reserved)
Capture Pointer
-reservedInterrupt Line
Interrupt Pin
Minimum Grant
Maximum Latency
Default
1106
3058
0000
0210
40
00
01
04
00
00
00
00
0000 0001
0000 0001
0000 0331
0000 0000
0000 0000
0000 0000
00
0000 0000
0000 0000
00
00
00
03
00
00
Acc
RO
RO
RW
WC
RO
RO
RO
RO
RO
RW
RO
RO
RW
RW
RW
—
—
—
—
RW
—
RW
—
RW
RO
RO
RO
Configuration Space Audio Codec-Specific Registers
Offset
40
41
42
43
44
45-47
48
49
4B-4A
4C-FF
Audio Codec Link Control
AC-Link Interface Status
AC-Link Interface Control
Function Enable
Plug and Play Control
MC97 Interface Control
-reservedFM NMI Control
-reservedGame Port Base Address
-reserved-
Preliminary Revision 0.8 October 29, 1999
Default
00
00
00
1C
00
00
00
00
0000
00
PCI Configuration Space Header
Vendor ID
Device ID
Command
Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Latency Timer
Header Type
BIST
Base Address 0 - SGD Control/Status
Base Address 1 - (reserved)
Base Address 2 - (reserved)
Base Address 3 – Codec Reg Shadow
Base Address 4 (reserved)
Base Address 5 (reserved)
-reservedSubsystem ID / SubVendor ID
Expansion ROM (reserved)
Capture Pointer
-reservedInterrupt Line
Interrupt Pin
Minimum Grant
Maximum Latency
Default
1106
3068
0000
0200
40
00
80
07
00
00
00
00
0000 0001
0000 0000
0000 0000
0000 0001
0000 0000
0000 0000
00
0000 0000
0000 0000
00
00
00
03
00
00
Acc
RO
RO
RW
WC
RO
RO
RO
RO
RO
RW
RO
RO
RW
RW
RW
—
—
—
—
RW
—
RW
—
RW
RO
RO
RO
Configuration Space Modem Codec-Specific Registers
Acc
RO
RW
RW
RW
RO
—
RW
—
RW
—
Offset
40
41
42
43
44
45-47
48
49
4B-4A
4C-FF
-38-
Modem Codec Link Control
AC-Link Interface Status
AC-Link Interface Control
Function Enable
Plug and Play Control
MC97 Interface Control
-reservedFM NMI Control
-reservedGame Port Base Address
-reserved-
Default
00
00
00
1C
00
00
00
00
0000
00
Acc
RO
RW
RO
RO
RW
—
RO
—
RO
—
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Func 5 I/O Base 0 Regs – Audio Scatter-Gather DMA
Offset
n0
n1
n2
n3
n7-n4
nB-n8
nF-nC
40
41
42
43
47-44
4B-48
4F-4C
50
51
52
53
57-54
58-5B
5F-5C
60
61
62
63
67-64
68-6B
6F-6C
70
71
72
73
77-74
78-7B
7F-7C
SGD I/O Registers (DSXn: n=1-3)
SGD DXSn Read Channel Status
SGD DXSn Read Channel Control
SGD DXSn Read Chan Left Volume
SGD DXSn Read Chan Right Volume
SGD DXSn Read Ch Table Ptr Base
SGD DXSn Read Ch Current Address
SGD DXSn Read Channel Format
SGD DXSn Read Chan Index / Count
SGD 3D Channel Status
SGD 3D Channel Control
SGD 3D Channel Format
SGD 3D Channel Scratch
SGD 3D Channel Table Ptr Base
SGD 3D Channel Current Address
SGD 3D Channel Slot Select
SGD 3D Channel Index / Count
SGD FM Channel Status
SGD FM Channel Control
SGD FM Channel Type
-reservedSGD FM Channel Table Pointer Base
SGD FM Channel Current Address
-reservedSGD FM Channel Current Count
SGD Write Channel 0 Status
SGD Write Channel 0 Control
SGD Write Channel 0 Format
-reservedSGD Write Channel 0 Table Ptr Base
SGD Write Channel 0 Current Addr
-reservedSGD Write Channel 0 Current Count
SGD Write Channel 1 Status
SGD Write Channel 1 Control
SGD Write Channel 1 Format
-reservedSGD Write Channel 1 Table Ptr Base
SGD Write Channel 1 Current Addr
-reservedSGD Write Channel 1 Current Count
Default
00
00
00
00
0000 0000
0000 0000
0000 0000
00
00
00
00
0000 0000
0000 0000
0000 0000
00
00
00
00
0000 0000
00
0000 0000
00
00
00
00
0000 0000
00
0000 0000
00
00
00
00
0000 0000
00
0000 0000
Function 5 I/O Base 1 Registers – FM NMI Status
Acc
WC
RW
RW
RW
WR
RD
RO
RO
WC
RW
RW
RW
WR
RD
RW
RO
WC
RW
RW
—
WR
RD
—
RO
WC
RW
RW
—
WR
RD
—
RO
WC
RW
RW
—
WR
RD
—
RO
Offset AC97 Controller I/O Registers
Default Acc
80-DF -reserved00
—
E3-E0 AC97 Controller Command / Status
0000 0000 RW
E4-EF -reserved00
—
F3-F0 SGD Status Shadow
0000 0000 RO
F4-FF -reserved00
—
The above registers are accessable through function 5 only.
Preliminary Revision 0.8 October 29, 1999
Offset FM NMI Status Registers
Default Acc
0 FM NMI Status
00
RO
1 FM NMI Data
00
RO
2 FM NMI Index
00
RO
3 Reserved
00
—
The above registers are accessable through function 5 only.
Function 5 I/O Base 2 Registers – MIDI / Game Port
Offset FM NMI Status Registers
Default Acc
1-0 MIDI Port Base
0330
RW
3-2 Game Port Base
0200
RW
The above registers are accessable through function 5 only.
Func 6 I/O Base 0 Regs – Modem Scatter Gather DMA
Offset
0
1
2
3
7-4
8-B
F-C
10
11
12
13
17-14
18-1B
1F-1C
MC97 SGD I/O Registers
SGD Modem Read Channel Status
SGD Modem Read Channel Control
SGD Modem Read Channel Type
-reservedSGD Modem Read Ch Table Ptr Base
SGD Modem Read Ch Current Addr
-reservedSGD Modem Read Ch Current Count
SGD Modem Write Channel Status
SGD Modem Write Channel Control
SGD Modem Write Channel Type
-reservedSGD Modem Wr Ch Table Ptr Base
SGD Modem Wr Ch Current Address
-reservedSGD Modem Write Ch Current Count
Default
00
00
00
00
0000 0000
Acc
WC
RW
RW
—
WR
RD
00
—
0000 0000 RO
00
WC
00
RW
00
RW
00
—
0000 0000 WR
RD
00
—
0000 0000 RO
Offset Modem Codec I/O Registers
Default Acc
23-20 Modem Codec Command / Status
0000 0000 RW
24-2F -reserved00
—
33-30 Codec GPI Interrupt Status / GPIO
0000 0000 WC
37-34 Codec GPI Interrupt Enable
0000 0000 RW
38-FF Reserved
00
—
The above registers are accessable through function 6 only.
-39-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Registers – Game Port
I/O Registers – SoundBlaster Pro
Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
SB Pro Registers (220 or 240h typ)
FM Left Channel Index / Status
FM Left Channel Data
FM Right Channel Index / Status
FM Right Channel Data
Mixer Index
Mixer Data
Sound Processor Reset
-reservedFM Index / Status (Both Channels)
FM Data (Both Channels)
Sound Processor Data
-reservedSound Processor Command / Data
Sound Processor Buffer Status
-reservedSnd Processor Data Available Status
-reserved-
Default Acc
RW
WO
RW
WO
WO
RW
WO
00
-RW
WO
RO
00
-WR
RD
00
-RO
00
--
Offset
0
1
1
2-F
Game Port (200-20F typical)
-reservedGame Port Status
Start One-Shot
-reserved-
Default Acc
00
-RO
WO
00
--
Port SB Pro Regs (same as offsets 8 & 9) Default Acc
388h FM Index / Status
RW
389h FM Data
WO
The above group of registers emulates the “FM”, “Mixer”, and
“Sound Processor” functions of the SoundBlaster Pro.
Preliminary Revision 0.8 October 29, 1999
-40-
Register Overview
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Register Descriptions
Legacy I/O Ports
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All of
these registers reside in I/O space.
Port 61 - Misc Functions & Speaker Control ................. RW
........................................always reads 0
7
Reserved
6
IOCHCK# Active .................................................RO
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register. Bit-3 should be cleared to
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
5
Timer/Counter 2 Output......................................RO
This bit reflects the output of Timer/Counter 2
without any synchronization.
4
Refresh Detected...................................................RO
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
3
IOCHCK# Disable...............................................RW
0 Enable IOCHCK# assertions ................. default
1 Force IOCHCK# inactive and clear any
“IOCHCK# Active” condition in bit-6
........................................RW, default=0
2
Reserved
1
Speaker Enable ....................................................RW
0 Disable................................................... default
1 Enable Timer/Ctr 2 output to drive SPKR pin
0
Timer/Counter 2 Enable .....................................RW
0 Disable................................................... default
1 Enable Timer/Counter 2
Port 92h - System Control ................................................ RW
7-6 Hard Disk Activity LED Status
0 Off
.................................................... default
1-3 On
........................................always reads 0
5-4 Reserved
3
Power-On Password Bytes Inaccessable ..default=0
........................................always reads 0
2
Reserved
1
A20 Address Line Enable
0 A20 disabled / forced 0 (real mode) ...... default
1 A20 address line enabled
0
High Speed Reset
0 Normal
1 Briefly pulse system reset to switch from
protected mode to real mode
Preliminary Revision 0.8 October 29, 1999
-41-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Keyboard Controller Registers
The keyboard controller handles the keyboard and mouse
interfaces. Two ports are used: port 60 and port 64. Reads
from port 64 return a status byte. Writes to port 64h are
command codes (see command code list following the register
descriptions). Input and output data is transferred via port 60.
A “Control” register is also available. It is accessable by
writing commands 20h / 60h to the command port (port 64h);
The control byte is written by first sending 60h to the
command port, then sending the control byte value.
The
control register may be read by sending a command of 20h to
port 64h, waiting for “Output Buffer Full” status = 1, then
reading the control byte value from port 60h.
Traditional (non-integrated) keyboard controllers have an
“Input Port” and an “Output Port” with specific pins dedicated
to certain functions and other pins available for general
purpose I/O. Specific commands are provided to set these pins
high and low. All outputs are “open-collector” so to allow
input on one of these pins, the output value for that pin would
be set high (non-driving) and the desired input value read on
the input port. These ports are defined as follows:
Bit Input Port
Lo Code Hi Code
0
P10 - Keyboard Data In
B0
B8
1
P11 - Mouse Data In
B1
B9
2
P12 - Turbo Pin (PS/2 mode only)
B2
BA
3
P13 - user-defined
B3
BB
4
P14 - user-defined
B6
BE
5
P15 - user-defined
B7
BF
6
P16 - user-defined
–
–
7
P17 - undefined
–
–
Bit Output Port
Lo Code Hi Code
0
P20 - SYSRST (1=execute reset)
–
–
1
P21 - GATEA20 (1=A20 enabled)
–
–
2
P22 - Mouse Data Out
B4
BC
3
P23 - Mouse Clock Out
B5
BD
4
P24 - Keyboard OBF Interrupt (IRQ1) –
–
5
P25 - Mouse OBF Interrupt (IRQ 12) –
–
6
P26 - Keyboard Clock Out
–
–
7
P27 - Keyboard Data Out
–
–
Bit Test Port
Lo Code Hi Code
0
T0 - Keyboard Clock In
–
–
1
T1 - Mouse Clock In
–
–
Note: Command code C0h transfers input port data to the
output buffer. Command code D0h copies output port values
to the output buffer. Command code E0h transfers test input
port data to the output buffer.
Port 60 - Keyboard Controller Input Buffer ................. WO
Only write to port 60h if port 64h bit-1 = 0 (1=full).
Port 60 - Keyboard Controller Output Buffer ................RO
Only read from port 60h if port 64h bit-0 = 1 (0=empty).
Preliminary Revision 0.8 October 29, 1999
Port 64 - Keyboard / Mouse Status .................................. RO
7
Parity Error
0 No parity error (odd parity received)..... default
1 Even parity occurred on last byte received
from keyboard / mouse
6
General Receive / Transmit Timeout
0 No error ................................................. default
1 Error
5
Mouse Output Buffer Full
0 Mouse output buffer empty.................... default
1 Mouse output buffer holds mouse data
4
Keylock Status
0 Locked
1 Free
3
Command / Data
0 Last write was data write ....................... default
1 Last write was command write
2
System Flag
0 Power-On Default .................................. default
1 Self Test Successful
1
Input Buffer Full
0 Input Buffer Empty................................ default
1 Input Buffer Full
0
Keyboard Output Buffer Full
0 Keyboard Output Buffer Empty............. default
1 Keyboard Output Buffer Full
KBC Control Register .......... (R/W via Commands 20h/60h)
........................................always reads 0
7
Reserved
6
PC Compatibility
0 Disable scan conversion
1 Convert scan codes to PC format; convert 2byte break sequences to 1-byte PC-compatible
break codes ............................................ default
5
Mouse Disable
0 Enable Mouse Interface ......................... default
1 Disable Mouse Interface
4
Keyboard Disable
0 Enable Keyboard Interface .................... default
1 Disable Keyboard Interface
3
Keyboard Lock Disable
0 Enable Keyboard Inhibit Function......... default
1 Disable Keyboard Inhibit Function
2
System Flag ................................................default=0
This bit may be read back as status register bit-2
1
Mouse Interrupt Enable
0 Disable mouse interrupts ....................... default
1 Generate interrupt on IRQ12 when mouse data
comes in output bufer
0
Keyboard Interrupt Enable
0 Disable Keyboard Interrupts.................. default
1 Generate interrupt on IRQ1 when output buffer
has been written.
-42-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Port 64 - Keyboard / Mouse Command .......................... WO
This port is used to send commands to the keyboard / mouse
controller. The command codes recognized by the VT8231
are listed n the table below.
Note: The VT8231 Keyboard Controller is compatible with
the VIA VT82C42 Industry-Standard Keyboard Controller
except that due to its integrated nature, many of the input and
output port pins are not available externally for use as general
purpose I/O pins (even though P13-P16 are set on power-up as
strapping options). In other words, many of the commands
below are provided and “work”, but otherwise perform no
useful function (e.g., commands that set P12-P17 high or low).
Also note that setting P10-11, P22-23, P26-27, and T0-1 high
or low directly serves no useful purpose, since these bits are
used to implement the keyboard and mouse ports and are
directly controlled by keyboard controller logic.
Table 4. Keyboard Controller Command Codes
Code
20h
21-3Fh
60h
61-7Fh
Keyboard Command Code Description
Read Control Byte (next byte is Control Byte)
Read SRAM Data (next byte is Data Byte)
Write Control Byte (next byte is Control Byte)
Write SRAM Data (next byte is Data Byte)
Code
C0h
9xh
A1h
A4h
C2h
AAh
ABh
ADh
AEh
AFh
Write low nibble (bits 0-3) to P10-P13
Output Keyboard Controller Version #
Test if Password is installed
(always returns F1h to indicate not installed)
Disable Mouse Interface
Enable Mouse Interface
Mouse Interface Test (puts test results in port 60h)
(value: 0=OK, 1=clk stuck low, 2=clk stuck high,
3=data stuck lo, 4=data stuck hi, FF=general error)
KBC self test (returns 55h if OK, FCh if not)
Keyboard Interface Test (see A9h Mouse Test)
Disable Keyboard Interface
Enable Keyboard Interface
Return Version #
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
Set P10 low
Set P11 low
Set P12 low
Set P13 low
Set P22 low
Set P23 low
Set P14 low
Set P15 low
Set P10 high
Set P11 high
Set P12 high
Set P13 high
Set P22 high
Set P23 high
Set P14 high
Set P15 high
A7h
A8h
A9h
Preliminary Revision 0.8 October 29, 1999
C1h
C8h
C9h
Keyboard Command Code Description
Read input port (read P10-17 input data to
the output buffer)
Poll input port low (read input data on P11-13
repeatably & put in bits 5-7 of status
Poll input port high (same except P15-17)
Unblock P22-23 (use before D1 to change
active mode)
Reblock P22-23 (protection mechanism for D1)
CAh
Read mode (output KBC mode info to port 60
output buffer (bit-0=0 if ISA, 1 if PS/2)
D0h
D4h
Read Output Port (copy P10-17 output port values
to port 60)
Write Output Port (data byte following is written to
keyboard output port as if it came from keyboard)
Write Keyboard Output Buffer & clear status bit-5
(write following byte to keyboard)
Write Mouse Output Buffer & set status bit-5 (write
following byte to mouse; put value in mouse input
buffer so it appears to have come from the mouse)
Write Mouse (write following byte to mouse)
E0h
Exh
Fxh
Read test inputs (T0-1 read to bits 0-1 of resp byte)
Set P23-P21 per command bits 3-1
Pulse P23-P20 low for 6usec per command bits 3-0
D1h
D2h
D3h
All other codes not listed are undefined.
-43-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
DMA Controller I/O Registers
Ports 00-0F - Master DMA Controller
Channels 0-3 of the Master DMA Controller control System
DMA Channels 0-3. There are 16 Master DMA Controller
registers:
I/O Address Bits 15-0
0000 0000 000x 0000
0000 0000 000x 0001
0000 0000 000x 0010
0000 0000 000x 0011
0000 0000 000x 0100
0000 0000 000x 0101
0000 0000 000x 0110
0000 0000 000x 0111
0000 0000 000x 1000
0000 0000 000x 1001
0000 0000 000x 1010
0000 0000 000x 1011
0000 0000 000x 1100
0000 0000 000x 1101
0000 0000 000x 1110
0000 0000 000x 1111
Register Name
Ch 0 Base / Current Address
Ch 0 Base / Current Count
Ch 1 Base / Current Address
Ch 1 Base / Current Count
Ch 2 Base / Current Address
Ch 2 Base / Current Count
Ch 3 Base / Current Address
Ch 3 Base / Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer F/F
Master Clear
Clear Mask
R/W All Mask Bits
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
Ports C0-DF - Slave DMA Controller
Channels 0-3 of the Slave DMA Controller control System
DMA Channels 4-7. There are 16 Slave DMA Controller
registers:
I/O Address Bits 15-0
0000 0000 1100 000x
0000 0000 1100 001x
0000 0000 1100 010x
0000 0000 1100 011x
0000 0000 1100 100x
0000 0000 1100 101x
0000 0000 1100 110x
0000 0000 1100 111x
0000 0000 1101 000x
0000 0000 1101 001x
0000 0000 1101 010x
0000 0000 1101 011x
0000 0000 1101 100x
0000 0000 1101 101x
0000 0000 1101 110x
0000 0000 1101 111x
Register Name
Ch 4 Base / Current Address
Ch 4 Base / Current Count
Ch 5 Base / Current Address
Ch 5 Base / Current Count
Ch 6 Base / Current Address
Ch 6 Base / Current Count
Ch 7 Base / Current Address
Ch 7 Base / Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer F/F
Master Clear
Clear Mask
Read/Write All Mask Bits
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
WO
Note that not all bits of the address are decoded.
The Master and Slave DMA Controllers are compatible with
the Intel 8237 DMA Controller chip. Detailed description of
8237 DMA controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports 80-8F - DMA Page Registers
There are eight DMA Page Registers, one for each DMA
channel. These registers provide bits 16-23 of the 24-bit
address for each DMA channel (bits 0-15 are stored in
registers in the Master and Slave DMA Controllers). They are
located at the following I/O Port addresses:
I/O Address Bits 15-0
0000 0000 1000 0111
0000 0000 1000 0011
0000 0000 1000 0001
0000 0000 1000 0010
Register Name
Channel 0 DMA Page (M-0).........RW
Channel 1 DMA Page (M-1).........RW
Channel 2 DMA Page (M-2).........RW
Channel 3 DMA Page (M-3).........RW
0000 0000 1000 1111
0000 0000 1000 1011
0000 0000 1000 1001
0000 0000 1000 1010
Channel 4 DMA Page (S-0) ..........RW
Channel 5 DMA Page (S-1) ..........RW
Channel 6 DMA Page (S-2) ..........RW
Channel 7 DMA Page (S-3) .........RW
DMA Controller Shadow Registers
The DMA Controller shadow registers are enabled by setting
function 0 Rx77 bit 0. If the shadow registers are enabled,
they are read back at the indicated I/O port instead of the
standard DMA controller registers (writes are unchanged).
Port 0 –Channel 0 Base Address ...................................... RO
Port 1 –Channel 0 Byte Count .......................................... RO
Port 2 –Channel 1 Base Address ...................................... RO
Port 3 –Channel 1 Byte Count .......................................... RO
Port 4 –Channel 2 Base Address ...................................... RO
Port 5 –Channel 2 Byte Count .......................................... RO
Port 6 –Channel 3 Base Address ...................................... RO
Port 7 –Channel 3 Byte Count .......................................... RO
Port 8 –1st Read Channel 0-3 Command Register .......... RO
Port 8 –2nd Read Channel 0-3 Request Register.............. RO
Port 8 –3rd Read Channel 0 Mode Register ..................... RO
Port 8 –4th Read Channel 1 Mode Register ..................... RO
Port 8 –5th Read Channel 2 Mode Register ..................... RO
Port 8 –6th Read Channel 3 Mode Register ..................... RO
Port F –Channel 0-3 Read All Mask ................................ RO
Port C4 –Channel 5 Base Address.................................... RO
Port C6 –Channel 5 Byte Count ....................................... RO
Port C8 –Channel 6 Base Address.................................... RO
Port CA –Channel 6 Byte Count ...................................... RO
Port CC –Channel 7 Base Address ................................... RO
Port CE –Channel 7 Byte Count ...................................... RO
Port D0 –1st Read Channel 4-7 Command Register........ RO
Port D0 –2nd Read Channel 4-7 Request Register ........... RO
Port D0 –3rd Read Channel 4 Mode Register .................. RO
Port D0 –4th Read Channel 5 Mode Register .................. RO
Port D0 –5th Read Channel 6 Mode Register .................. RO
Port D0 –6th Read Channel 7 Mode Register .................. RO
Port DE –Channel 4-7 Read All Mask ............................. RO
Preliminary Revision 0.8 October 29, 1999
-44-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Interrupt Controller Shadow Registers
Interrupt Controller Registers
Ports 20-21 - Master Interrupt Controller
The Master Interrupt Controller controls system interrupt
channels 0-7. Two registers control the Master Interrupt
Controller. They are:
I/O Address Bits 15-0
0000 0000 001x xxx0
0000 0000 001x xxx1
Register Name
Master Interrupt Control
Master Interrupt Mask
RW
RW
Note that not all bits of the address are decoded.
The Master Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
Ports A0-A1 - Slave Interrupt Controller
The Slave Interrupt Controller controls system interrupt
channels 8-15. The slave system interrupt controller also
occupies two register locations:
I/O Address Bits 15-0
0000 0000 101x xxx0
0000 0000 101x xxx1
Register Name
Slave Interrupt Control
Slave Interrupt Mask
RW
RW
Note that not all address bits are decoded.
The Slave Interrupt Controller is compatible with the Intel
8259 Interrupt Controller chip. Detailed descriptions of 8259
Interrupt Controller operation can be obtained from the Intel
Peripheral Components Data Book and numerous other
industry publications.
The following shadow registers are enabled by setting function
0 Rx47[4]. If the shadow registers are enabled, they are read
back at the indicated I/O port instead of the standard interrupt
controller registers (writes are unchanged).
Port 20 - Master Interrupt Control Shadow ................... RO
Port A0 - Slave Interrupt Control Shadow ..................... RO
........................................always reads 0
7
Reserved
6
OCW3 bit 2 (POLL)
5
OCW3 bit 0 (RIS)
4
OCW3 bit 5 (SMM)
3
OCW2 bit 7 (R)
2
ICW4 bit 4 (SFNM)
1
ICW4 bit 1 (AEOI)
0
ICW1 bit 3 (LTIM)
Port 21 - Master Interrupt Mask Shadow ....................... RO
Port A1 - Slave Interrupt Mask Shadow ........................ RO
........................................always reads 0
7-5 Reserved
4-0 T7-T3 of Interrupt Vector Address
Timer / Counter Registers
Ports 40-43 - Timer / Counter Registers
There are 4 Timer / Counter registers:
I/O Address Bits 15-0
0000 0000 010x xx00
0000 0000 010x xx01
0000 0000 010x xx10
0000 0000 010x xx11
Register Name
Timer / Counter 0 Count
Timer / Counter 1 Count
Timer / Counter 2 Count
Timer / Counter Cmd Mode
RW
RW
RW
WO
Note that not all bits of the address are decoded.
The Timer / Counters are compatible with the Intel 8254
Timer / Counter chip. Detailed descriptions of 8254 Timer /
Counter operation can be obtained from the Intel Peripheral
Components Data Book and numerous other industry
publications.
Timer / Counter Shadow Registers
The following shadow registers are enabled for readback by
setting function 0 Rx47[4]. If the shadow registers are
enabled, they are read back at the indicated I/O port instead of
the standard timer / counter registers (writes are unchanged).
Port 40 – Counter 0 Base Count Value (LSB 1st MSB 2nd)RO
Port 41 – Counter 1 Base Count Value (LSB 1st MSB 2nd)RO
Port 42 – Counter 2 Base Count Value (LSB 1st MSB 2nd)RO
Preliminary Revision 0.8 October 29, 1999
-45-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
CMOS / RTC Registers
Offset
00
01
02
03
04
Port 70 - CMOS Address .................................................. RW
7
NMI Disable......................................................... RW
0 Enable NMI Generation. NMI is asserted on
encountering IOCHCK# on the ISA bus or
SERR# on the PCI bus.
1 Disable NMI Generation ........................default
6-0 CMOS Address (lower 128 bytes)....................... RW
05
Port 71 - CMOS Data........................................................ RW
7-0 CMOS Data (128 bytes)
Description
Binary Range BCD Range
00-3Bh
00-59h
Seconds
00-3Bh
00-59h
Seconds Alarm
00-3Bh
00-59h
Minutes
00-3Bh
00-59h
Minutes Alarm
am 12hr: 01-1Ch
01-12h
Hours
pm 12hr: 81-8Ch
81-92h
24hr: 00-17h
00-23h
01-12h
Hours Alarm am 12hr: 01-1Ch
pm 12hr: 81-8Ch
81-92h
24hr: 00-17h
00-23h
01-07h
Day of the Week Sun=1: 01-07h
01-1Fh
01-31h
Day of the Month
01-0Ch
01-12h
Month
00-63h
00-99h
Year
Ports 70-71 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 70-71 will be directed to an
external RTC.
06
07
08
09
Port 72 - CMOS Address .................................................. RW
7-0 CMOS Address (256 bytes)................................. RW
0A
Register A
7
UIP Update In Progress
6-4 DV2-0 Divide (010=ena osc & keep time)
3-0 RS3-0 Rate Select for Periodic Interrupt
0B
Register B
7
SET
6
PIE
5
AIE
4
UIE
3 SQWE
2
DM
1
24/12
0
DSE
Inhibit Update Transfers
Periodic Interrupt Enable
Alarm Interrupt Enable
Update Ended Interrupt Enable
No function (read/write bit)
Data Mode (0=BCD, 1=binary)
Hours Byte Format (0=12, 1=24)
Daylight Savings Enable
Register C
7
IRQF
6
PF
5
AF
4
UF
3-0
0
Interrupt Request Flag
Periodic Interrupt Flag
Alarm Interrupt Flag
Update Ended Flag
Unused (always read 0)
Register D
7
VRT
6-0
0
Reads 1 if VBAT voltage is OK
Unused (always read 0)
Note:
Port 73 - CMOS Data........................................................ RW
7-0 CMOS Data (256 bytes)
Note:
Ports 72-73 may be accessed if Rx5A bit-2 is set to
one to select the internal RTC. If Rx5A bit-2 is set to
zero, accesses to ports 72-73 will be directed to an
external RTC.
Port 74 - CMOS Address .................................................. RW
7-0 CMOS Address (256 bytes)................................. RW
Port 75 - CMOS Data........................................................ RW
7-0 CMOS Data (256 bytes)
Note:
Ports 74-75 may be accessed only if Function 0 Rx5B
bit-1 is set to one to enable the internal RTC SRAM
and if Rx48 bit-3 (Port 74/75 Access Enable) is set to
one to enable port 74/75 access.
Note:
Ports 70-71 are compatible with PC industrystandards and may be used to access the lower 128
bytes of the 256-byte on-chip CMOS RAM. Ports
72-73 may be used to access the full extended 256byte space. Ports 74-75 may be used to access the
full on-chip extended 256-byte space in cases where
the on-chip RTC is disabled.
Note:
The system Real Time Clock (RTC) is part of the
“CMOS” block. The RTC control registers are
located at specific offsets in the CMOS data area (00Dh and 7D-7Fh). Detailed descriptions of CMOS /
RTC operation and programming can be obtained
from the VIA VT82887 Data Book or numerous
other industry publications.
For reference, the
definition of the RTC register locations and bits are
summarized in the following table:
Preliminary Revision 0.8 October 29, 1999
0C
0D
0E-7C Software-Defined Storage Registers (111 Bytes)
Offset
7D
7E
7F
Extended Functions
Date Alarm
Month Alarm
Century Field
Binary Range BCD Range
01-1Fh
01-31h
01-0Ch
01-12h
13-14h
19-20h
80-FF Software-Defined Storage Registers (128 Bytes)
Table 5. CMOS Register Summary
-46-
Register Descriptions - Legacy I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Super-I/O Configuration Index / Data Registers
Super-I/O Configuration Registers
Super-I/O configuration registers are accessed by performing
I/O operations to / from an index / data pair of registers in
system I/O space at port addresses 3F0h and 3F1h. The
configuration registers accessed using this mechanism are used
to configure the Super-I/O registers (parallel port, serial ports,
IR port, and floppy controller).
These registers are accessed via the port 3F0 / 3F1 index / data
register pair using the indicated index values below
Index E0 – Super-I/O Device ID ....................................... RO
7-0 Super-I/O ID ........................................ default = 3Ch
Super I/O configuration is accomplished in three steps:
1) Enter configuration mode (set Function 0 Rx85[1] = 1)
2) Configure the chip
a) Write index to port 3F0
b) Read / write data from / to port 3F1
c) Repeat a and b for all desired registers
3) Exit configuration mode (set Function 0 Rx85[1] = 0)
Port 3F0h – Super-I/O Configuration Index................... RW
7-0 Index value
Function 0 PCI configuration space register Rx85[1] must be
set to 1 to enable access to the Super-I/O configuration
registers.
Port 3F1h – Super-I/O Configuration Data .................... RW
7-0 Data value
This register shares a port with the Floppy Status Port (which
is read only). This port is accessible only when Rx85[1] is set
to 1 (the floppy status port is accessed if Rx85[1] = 0).
Index E1 – Super-I/O Device Revision ............................. RO
7-0 Super-I/O Revision Code .........................default = 0
Index E2 – Super-I/O Function Select ............................ RW
........................................always reads 0
7-5 Reserved
4
Floppy Controller Enable
0 Disable................................................... default
1 Enable
3
Serial Port 2 Enable
0 Disable................................................... default
1 Enable
2
Serial Port 1 Enable
0 Disable................................................... default
1 Enable
1-0 Parallel Port Mode / Enable
00 Unidirectional mode .............................. default
01 ECP
10 EPP
11 Parallel Port Disabled
Index E3 – Floppy Controller I/O Base Address ........... RW
7-2 I/O Address 9-4.........................................default = 0
1-0 Must be 0 ..............................................default = 0
Index E6 – Parallel Port I/O Base Address .................... RW
7-0 I/O Address 9-2.........................................default = 0
If EPP is not enabled, the parallel port can be set to 192
locations on 4-byte boundaries from 100h to 3FCh. If EPP is
enabled, the parallel port can be set to 96 locations on 8-byte
boundaries from 100h to 3F8h.
Index E7 – Serial Port 1 I/O Base Address ..................... RW
7-1 I/O Address 9-3.........................................default = 0
0
Must be 0 ..............................................default = 0
Index E8 – Serial Port 2 I/O Base Address ..................... RW
7-1 I/O Address 9-3.........................................default = 0
0
Must be 0 ..............................................default = 0
Preliminary Revision 0.8 October 29, 1999
-47-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Index EE – Serial Port Configuration ............................. RW
7
Serial Port 2 High Speed Enable
0 Disable ...................................................default
1 Enable
6
Serial Port 1 High Speed Enable
0 Disable ...................................................default
1 Enable
5-3 Serial Port 2 Mode
000 Standard
001 IrDA (HIPSIR)
010 Amplitude shift keyed IR @ 500KHz
011 -reserved1xx -reserved2
Serial Port 2 Half Duplex
0 Disable ...................................................default
1 Enable
1
Serial Port 2 TX Output Inversion
0 Disable ...................................................default
1 Enable
0
Serial Port 2 RX Input Inversion
0 Disable ...................................................default
1 Enable
Index EF – Power Down Control ..................................... RW
........................................ always reads 0
7-6 Reserved
5
Clock Power Down
0 Normal operation ...................................default
1 Power Down
4
Parallel Port Power Down
0 Normal operation ...................................default
1 Power Down
3
Serial Port 2 Power Down
0 Normal operation ...................................default
1 Power Down
2
Serial Port 1 Power Down
0 Normal operation ...................................default
1 Power Down
1
FDC Power Down
0 Normal operation ...................................default
1 Power Down
0
All Power Down
0 Normal operation ...................................default
1 Power Down All
Preliminary Revision 0.8 October 29, 1999
Index F0 – Parallel Port Control ..................................... RW
7
PS2 Type BiDirectionl Parallel Port
0 Disable................................................... default
1 Enable
6
EPP Direction by Register not by IOW
0 Disable................................................... default
1 Enable
5
EPP+ECP
0 Disable................................................... default
1 Enable
4
EPP Version
0 Version 1.9 ............................................ default
1 Version 1.7
........................................always reads 0
3-0 Reserved
Index F1 – Serial Port Control ........................................ RW
........................................always reads 0
7-6 Reserved
5
IR Loop Back
0 Disable................................................... default
1 Enable
4
Serial Port 2 Power-Down State
0 Normal................................................... default
1 Tristate output in power down mode
3
Serial Port 1 Power-Down State
0 Normal................................................... default
1 Tristate output in power down mode
2
IR Dedicated Pin (IRTX/IRRX) Select
0 IRTX / IRRX Output from Serial Port 2...... def
1 Function 0 Rx76[5] = 0:
IRRX output from dedicated pin D12
IRTX output from dedicated pin E12
........................................always reads 0
1-0 Reserved
Index F2 – Test Mode (Do Not Program) ....................... RW
Index F4 – Test Mode (Do Not Program) ....................... RW
-48-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Index F6 – Floppy Controller Configuration .................. RW
........................................ always reads 0
7-6 Reserved
5
Floppy Drive On Parallel Port
0 Parallel Port (SPP) Mode .......................default
1 FDC Mode
This bit is used in notebook applications to allow
attachment of an external floppy drive using the
parallel port I/O connector:
SPP Mode
STROBE#
4
3
2
1
0
Pin Type
I/O
Index F8 – Floppy Drive Control .................................... RW
7-6 Floppy Drive 3 (see table below)
5-4 Floppy Drive 2 (see table below)
3-2 Floppy Drive 1 (see table below)
1-0 Floppy Drive 0 (see table below)
00
01
10
11
FDC Mode Pin Type
n/a
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INDEX#
TRK00#
WRTPRT#
RDATA#
DSKCHG#
-
I
I
I
I
I
n/a
n/a
n/a
ACK#
BUSY
PE
SLCT
AUTOFD#
ERROR#
PINIT#
SLCTIN#
I
I
I
I
I/O
I
I/O
I/O
DS1#
MTR1#
WDATA#
WGATE#
DRVEN0
HDSEL#
DIR#
STEP#
O
O
O
O
O
O
O
O
DRVEN1
DRATE0
DRATE0
DRATE0
DRATE1
DRVEN0
DENSEL
DRATE1
DENSEL#
DRATE0
3-Mode FDD
0 Disable ...................................................default
1 Enable
........................................ always reads 0
Reserved
Four Floppy Drive Option
0 Internal 2-Drive Decoder .......................default
1 External 4-Drive Decoder
FDC DMA Non-Burst
0 Burst .....................................................default
1 Non-Burst
FDC Swap
0 Disable ...................................................default
1 Enable
Preliminary Revision 0.8 October 29, 1999
-49-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Super-I/O I/O Ports
Floppy Disk Controller Registers
These registers are located at I/O ports which are offsets from
“FDCBase” (index C3h of the Super-I/O configuration
registers). FDCBase is typically set to allow these ports to be
accessed at the standard floppy disk controller address range
of 3F0-3F7h.
Port FDCBase+2 – FDC Command ................................. RW
7
Motor 3 (unused in VT8231: no MTR3# pin)
6
Motor 2 (unused in VT8231: no MTR2# pin)
5
Motor 1
0 Motor Off
1 Motor On
4
Motor 0
0 Motor Off
1 Motor On
3
DMA and IRQ Channels
0 Disabled
1 Enabled
2
FDC Reset
0 Execute FDC Reset
1 FDC Enabled
1-0 Drive Select
00 Select Drive 0
01 Select Drive 1
1x -reservedPort FDCBase+4 – FDC Main Status ...............................RO
7
Main Request
0 Data register not ready
1 Data register ready
6
Data Input / Output
0 CPU => FDC
1 FDC => CPU
5
Non-DMA Mode
0 FDC in DMA mode
1 FDC not in DMA mode
4
FDC Busy
0 FDC inactive
1 FDC active
........................................ always reads 0
3-2 Reserved
1
Drive 1 Active
0 Drive inactive
1 Drive performing a positioning change
0
Drive 0 Active
0 Drive inactive
1 Drive performing a positioning change
Preliminary Revision 0.8 October 29, 1999
Port FDCBase+4 – FDC Data Rate Select ...................... WO
Port FDCBase+5 – FDC Data .......................................... RW
Port FDCBase+7 – FDC Disk Change Status .................. RO
7
Disk Change
0 Floppy not changed
1 Floppy changed since last instruction
6-3 Undefined ......................................... always read 1
2-1 Data Rate
00 500 Kbit/sec (1.2MB 5” or 1.44 MB 3” drive)
01 300 Kbit/sec (360KB 5” drive)
10 250 Kbit/sec (720KB 3” drive)
11 1 Mbit/sec
0
High Density Rate
0 500 Kbit/sec or 1 Mbit/sec selected
1 250 Kbit/set or 300 Kbit/sec selected
Port FDCBase+7 – FDC Configuration Control ............ WO
7-2 Undefined ......................................... always read 1
1-0 Data Rate
00 500 Kbit/sec (1.2MB 5” or 1.44 MB 3” drive)
01 300 Kbit/sec (360KB 5” drive)
10 250 Kbit/sec (720KB 3” drive)
11 1 Mbit/sec
-50-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Parallel Port Registers
These registers are located at I/O ports which are offsets from
“LPTBase” (index C6h of the Super-I/O configuration
registers). LPTBase is typically set to allow these ports to be
accessed at the standard parallel port address range of 37837Fh.
Port LPTBase+0 – Parallel Port Data ............................. RW
7-0 Parallel Port Data
Port LPTBase+1 – Parallel Port Status ............................RO
7
BUSY#
0 Printer busy, offline, or error
1 Printer not busy
6
ACK#
0 Data transfer to printer complete
1 Data transfer to printer in progress
5
PE
0 Paper available
1 No paper available
4
SLCT
0 Printer offline
1 Printer online
3
ERROR#
0 Printer error
1 Printer OK
................................... always read 1 bits
2-0 Reserved
Port LPTBase+3 – Parallel Port EPP Address............... RW
Port LPTBase+4 – Parallel Port EPP Data Port 0......... RW
Port LPTBase+5 – Parallel Port EPP Data Port 1......... RW
Port LPTBase+6 – Parallel Port EPP Data Port 2......... RW
Port LPTBase+7 – Parallel Port EPP Data Port 3......... RW
Port LPTBase+400h – Parallel Port ECP Data / Cfg A RW
Port LPTBase+401h – Parallel Port ECP Config B....... RW
Port LPTBase+401h – Parallel Port ECP Extd Ctrl...... RW
Port LPTBase+2 – Parallel Port Control ........................ RW
7-5 Undefined ................................. always read back 1
4
Hardware Interrupt
0 Disable ...................................................default
1 Enable
3
Printer Select
0 Deselect printer ......................................default
1 Select printer
2
Printer Initialize
0 Initialize Printer......................................default
1 Allow printer to operate normally
1
Automatic Line Feed
0 Host handles line feeds...........................default
1 Printer does automatic line feeds
0
Strobe
0 No data transfer ......................................default
1 Transfer data to printer
Preliminary Revision 0.8 October 29, 1999
-51-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Serial Port 1 Registers
These registers are located at I/O ports which are offsets from
“COM1Base” (index C7h of the Super-I/O configuration
registers). COM1Base is typically set to allow these ports to
be accessed at the standard serial port 1 address range of 3F83FFh.
Port COM1Base+0 – Transmit / Receive Buffer ............ RW
7-0 Serial Data
Port COM1Base+1 – Interrupt Enable ........................... RW
7-4 Undefined ..........................................always read 0
3
Interrupt on Hnadshake Input State Change
2
Intr on Parity, Overrun, Framing Error or Break
1
Interrupt on Transmit Buffer Empty
0
Interrupt on Receive Data Ready
Port COM1Base+2 – Interrupt Status .............................RO
7-3 Undefined ..........................................always read 0
2-1 Interrupt ID (0=highest priority)
00 Priority 3 (Handshake Input Changed State)
01 Priority 2 (Transmit Buffer Empty)
10 Priority 1 (Data Received)
11 Priority 0 (Serialization Error or Break)
0
Interrupt Pending
0 Interrupt Pending
1 No Interrupt Pending
Port COM1Base+2 – FIFO Control ............................... WO
Port COM1Base+3 – UART Control............................... RW
7
Divisor Latch Access
0 Select transmit / receive registers
1 Select divisor latch
6
Break
0 Break condition off
1 Break condition on
5-3 Parity
000 None
001 Odd
011 Even
101 Mark
111 Space
2
Stop Bits
0 1
1 2
1-0 Data Bits
00 5
01 6
10 7
11 8
Preliminary Revision 0.8 October 29, 1999
Port COM1Base+4 – Handshake Control ...................... RW
7-5 Undefined ......................................... always read 0
4
Loopback Check
0 Normal operation
1 Loopback enabled
3
General Purpose Output 2 (unused in VT8231)
2
General Purpose Output 1 (unused in VT8231)
1
Request To Send
0 Disabled
1 Enabled
0
Data Terminal Ready
0 Disabled
1 Enabled
Port COM1Base+5 – UART Status ................................. RW
7
Undefined ......................................... always read 0
6
Transmitter Empty
0 1 byte in transmit hold or transmit shift register
1 0 bytes transmit hold and transmit shift regs
5
Transmit Buffer Empty
0 1 byte in transmit hold register
1 Transmit hold register empty
4
Break Detected
0 No break detected
1 Break detected
3
Framing Error Detected
0 No error
1 Error
2
Parity Error Detected
0 No error
1 Error
1
Overrun Error Detected
0 No error
1 Error
0
Received Data Ready
0 No received data available
1 Received data in receiver buffer register
Port COM1Base+6 – Handshake Status ......................... RW
7
DCD Status (1=Active, 0=Inactive)
6
RI Status (1=Active, 0=Inactive)
5
DSR Status (1=Active, 0=Inactive)
4
CTS Status (1=Active, 0=Inactive)
3
DCD Changed (1=Changed Since Last Read)
2
RI Changed (1=Changed Since Last Read)
1
DSR Changed (1=Changed Since Last Read)
0
CTS Changed (1=Changed Since Last Read)
Port COM1Base+7 – Scratchpad .................................... RW
7
Scratchpad Data
Port COM1Base+9-8 – Baud Rate Generator Divisor .. RW
15-0 Divisor Value for Basud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
-52-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Serial Port 2 Registers
These registers are located at I/O ports which are offsets from
“COM2Base” (index C8h of the Super-I/O configuration
registers). COM2Base is typically set to allow these ports to
be accessed at the standard serial port 2 address range of 2F82FFh.
Port COM1Base+0 – Transmit / Receive Buffer ............ RW
7-0 Serial Data
Port COM1Base+1 – Interrupt Enable ........................... RW
7-4 Undefined ..........................................always read 0
3
Interrupt on Hnadshake Input State Change
2
Intr on Parity, Overrun, Framing Error or Break
1
Interrupt on Transmit Buffer Empty
0
Interrupt on Receive Data Ready
Port COM1Base+2 – Interrupt Status .............................RO
7-3 Undefined ..........................................always read 0
2-1 Interrupt ID (0=highest priority)
00 Priority 3 (Handshake Input Changed State)
01 Priority 2 (Transmit Buffer Empty)
10 Priority 1 (Data Received)
11 Priority 0 (Serialization Error or Break)
0
Interrupt Pending
0 Interrupt Pending
1 No Interrupt Pending
Port COM1Base+2 – FIFO Control ............................... WO
Port COM1Base+3 – UART Control............................... RW
7
Divisor Latch Access
0 Select transmit / receive registers
1 Select divisor latch
6
Break
0 Break condition off
1 Break condition on
5-3 Parity
000 None
001 Odd
011 Even
101 Mark
111 Space
2
Stop Bits
0 1
1 2
1-0 Data Bits
00 5
01 6
10 7
11 8
Preliminary Revision 0.8 October 29, 1999
Port COM1Base+4 – Handshake Control ...................... RW
7-5 Undefined ......................................... always read 0
4
Loopback Check
0 Normal operation
1 Loopback enabled
3
General Purpose Output 2 (unused in VT8231)
2
General Purpose Output 1 (unused in VT8231)
1
Request To Send
0 Disabled
1 Enabled
0
Data Terminal Ready
0 Disabled
1 Enabled
Port COM1Base+5 – UART Status ................................. RW
7
Undefined ......................................... always read 0
6
Transmitter Empty
0 1 byte in transmit hold or transmit shift register
1 0 bytes transmit hold and transmit shift regs
5
Transmit Buffer Empty
0 1 byte in transmit hold register
1 Transmit hold register empty
4
Break Detected
0 No break detected
1 Break detected
3
Framing Error Detected
0 No error
1 Error
2
Parity Error Detected
0 No error
1 Error
1
Overrun Error Detected
0 No error
1 Error
0
Received Data Ready
0 No received data available
1 Received data in receiver buffer register
Port COM1Base+6 – Handshake Status ......................... RW
7
DCD Status (1=Active, 0=Inactive)
6
RI Status (1=Active, 0=Inactive)
5
DSR Status (1=Active, 0=Inactive)
4
CTS Status (1=Active, 0=Inactive)
3
DCD Changed (1=Changed Since Last Read)
2
RI Changed (1=Changed Since Last Read)
1
DSR Changed (1=Changed Since Last Read)
0
CTS Changed (1=Changed Since Last Read)
Port COM1Base+7 – Scratchpad .................................... RW
7
Scratchpad Data
Port COM1Base+9-8 – Baud Rate Generator Divisor .. RW
15-0 Divisor Value for Basud Rate Generator
Baud Rate = 115,200 / Divisor
(e.g., setting this register to 1 selects 115.2 Kbaud)
-53-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
SoundBlaster Pro Port Registers
Register Summary - FM
These registers are located at offsets from “SBPBase” (defined
in Rx43 of Audio Function 5 PCI configuration space).
SBPBase is typically set to allow these ports to be accessed at
the standard SoundBlaster Pro port address of 220h or 240h.
Index Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
01
Test
02
Fast Counter (80 usec)
03
Slow Counter (320 usec)
04
IRQ MFC MSC
SSSC SSFC
08
CSM SEL
20-35 AM VIB EGT KSR
Multi
40-55
KSL
Total Level (TL)
60-75
Attack Rate (AR)
Decay Rate (DR)
80-95
Sustain Level (SL)
Release Rate (RR)
A0-A8
F-Number
B0-B8
Key
Block
F-Number
BD Int AM VIB Ryth Bass Snare Tom Cym HiHat
C0-C8
Feedback
FM
E0-F5
WS
MFC=Mask Fast Counter SSFC=Start / Stop Fast Counter
MSC=Mask Slow Counter SSSC=Start / Stop Slow Counter
FM Registers
Port SBPBase+0 – FM Left Channel Index / Status ....... RW
7-0 FM Right Channel Index / Status
Port SBPBase+1 – FM Left Channel Data ..................... WO
7-0 Right Channel FM Data
Port SBPBase+2 – FM Right Channel Index / Status .... RW
7-0 FM Right Channel Index / Status
Port SBPBase+3 – FM Right Channel Data .................. WO
7-0 Right Channel FM Data
Register Summary – Mixer
Port 388h or SBPBase+8 – FM Index / Status ................ RW
7-0 FM Index / Status (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 0 and 2 as well)
Port 389h or SBPBase+9 – FM Data .............................. WO
7-0 FM Data (Both Channels)
Writing to this port programs both the left and right channels
(the write programms port offsets 1 and 3 as well)
Mixer Registers
Port SBPBase+4 – Mixer Index....................................... WO
7-0 Mixer Index
Port SBPBase+5 – Mixer Data ......................................... RW
7-0 Mixer Data
Index Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
00
Data Reset
02
SP Volume L
SP Volume R
0A
Mic Vol
0C
Finp
TFIL
Select
0E
Fout
ST
22
General Volume
General Volume
26
FM Volume L
FM Volume R
28
CD Volume L
CD Volume R
2E
Line Volume L
Line Volume R
Finp = Input Filter
Fout = Output Filter
TFIL = Input Filter Type
ST = Stereo / Mono Mode
Select = Input Choices (0=Microphone, 1=CD, 3=Line)
Command Summary – Sound Processor (see next page)
Sound Processor Registers
Port SBPBase+6 – Sound Processor Reset ..................... WO
0
1 = Sound Processor Reset
Port SBPBase+A – Sound Processor Read Data .............RO
7-0 Sound Processor Read Data
Port SBPBase+C – Sound Processor Command / Data WO
7-0 Sound Processor Command / Write Data
Port SBPBase+C – Sound Processor Buffer Status .........RO
7
1 = Sound Processor Command / Data Port Busy
Port SBPBase+E – Sound Processor Data Avail Status ..RO
7
1 = Sound Processor Data Available
Preliminary Revision 0.8 October 29, 1999
-54-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Command Summary – Sound Processor
Game Port Registers
#
10
14
91
16
17
74
75
76
77
These registers are fixed at the standard game port address of
201h.
Type
Play
Play
Play
Play
Play
Play
Play
Play
Play
Command
8 bits directly
8 bits via DMA
High-speed 8 bits via DMA
2-bit compressed via DMA
2-bit compressed via DMA with reference
4-bit compressed via DMA
4-bit compressed via DMA with reference
2.6-bit compressed via DMA
2.6-bit compressed via DMA with reference
20 Record Direct
24 Record Via DMA
99 Record High-speed 8 bits via DMA
I/O Port 201h – Game Port Status ................................... RO
7
Joystick B Button 2 Status
6
Joystick B Button 1 Status
5
Joystick A Button 2 Status
4
Joystick A Button 1 Status
3
Joystick B One-Shot Status for Y-Potentiometer
2
Joystick B One-Shot Status for X-Potentiometer
1
Joystick A One-Shot Status for Y-Potentiometer
0
Joystick A One-Shot Status for X-Potentiometer
I/O Port 201h – Start One-Shot ....................................... WO
7-0 (Value Written is Ignored)
D1 Speaker Turn on speaker connection
D3 Speaker Turn off speaker connection
D8 Speaker Get speaker setting
40
48
80
D0
D4
E1
Misc
Misc
Misc
Misc
Misc
Misc
Set sample rate
Set block length
Set silence block
Stop DMA
Continue DMA
Get version
30
31
32
33
34
35
36
37
38
MIDI
MIDI
MIDI
MIDI
MIDI
MIDI
MIDI
MIDI
MIDI
Direct MIDI input
MIDI input via interrupt
Direct MIDI input with time stamp
MIDI input via interrupt with time stamp
Direct MIDI UART mode
MIDI UART mode via interrupt
Direct MIDI UART mode with time stamp
MIDI UART mode via interrupt with time stamp
Send MIDI code
Preliminary Revision 0.8 October 29, 1999
-55-
Register Descriptions - Super-I/O I/O Ports
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Configuration Space I/O
PCI configuration space accesses for functions 0-6 use PCI
configuration mechanism 1 (see PCI specification revision 2.2
for more details). The ports respond only to double-word
accesses. Byte or word accesses will be passed on unchanged.
Port CFB-CF8 - Configuration Address ......................... RW
31 Configuration Space Enable
0 Disabled .................................................default
1 Convert configuration data port writes to
configuration cycles on the PCI bus
........................................ always reads 0
30-24 Reserved
23-16 PCI Bus Number
Used to choose a specific PCI bus in the system
15-11 Device Number
Used to choose a specific device in the system
10-8 Function Number
Used to choose a specific function if the selected
device supports multiple functions
7-2 Register Number
Used to select a specific DWORD in the device’s
configuration space
........................................ always reads 0
1-0 Fixed
There are 7 “functions” implemented in the VT8231:
Function #
Function
0
PCI to ISA Bridge
1
IDE Controller
2
USB Controller Ports 0-1
3
USB Controller Ports 2-3
4
Power Management, SMBus & Hardware
Monitor
5
AC97 Audio Codec Controller
6
MC97 Modem Codec Controller
The following sections describe the registers and register bits
of these functions.
Port CFF-CFC - Configuration Data .............................. RW
Preliminary Revision 0.8 October 29, 1999
-56-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 0 Registers - PCI to ISA Bridge
All registers are located in the function 0 PCI configuration
space of the VT8231. These registers are accessed through
PCI configuration mechanism #1 via I/O address CF8/CFC.
PCI Configuration Space Header
Offset 1-0 - Vendor ID = 1106h .........................................RO
Offset 3-2 - Device ID = 8231h ..........................................RO
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-8 Reserved
7
Address / Data Stepping
0 Disable
1 Enable ....................................................default
........................................ always reads 0
6-4 Reserved
3
Special Cycle Enable .....Normally RW†, default = 0
2
Bus Master ........................................ always reads 1
1
Memory Space.................. Normally RO†, reads as 1
0
I/O Space ...................... Normally RO†, reads as 1
† If the test bit at offset 46 bit-4 is set, access to the above
indicated bits is reversed: bit-3 above becomes read only
(reading back 1) and bits 0-1 above become read / write (with
a default of 1).
Offset 7-6 - Status ........................................................... RWC
15 Detected Parity Error .................... write one to clear
14 Signalled System Error...................... always reads 0
13 Signalled Master Abort ................. write one to clear
12 Received Target Abort .................. write one to clear
11 Signalled Target Abort .................. write one to clear
10-9 DEVSEL# Timing .................... fixed at 01 (medium)
8
Data Parity Detected.......................... always reads 0
7
Fast Back-to-Back.............................. always reads 0
........................................ always reads 0
6-0 Reserved
Offset 8 - Revision ID = nn ................................................RO
7-0 Revision ID
Offset 9 - Program Interface = 00h ...................................RO
Offset A - Sub Class Code = 01h .......................................RO
ISA Bus Control
Offset 40 - ISA Bus Control ............................................. RW
7
ISA Command Delay
0 Normal................................................... default
1 Extra
6
Extended ISA Bus Ready
0 Disable................................................... default
1 Enable
5
ISA Slave Wait States
0 4 Wait States.......................................... default
1 5 Wait States
4
Chipset I/O Wait States
0 2 Wait States.......................................... default
1 4 Wait States
3
I/O Recovery Time
0 Disable................................................... default
1 Enable
2
Extend-ALE
0 Disable................................................... default
1 Enable
1
ROM Wait States
0 1 Wait State ........................................... default
1 0 Wait States
0
ROM Write
0 Disable................................................... default
1 Enable
Offset 41 - ISA Test Mode ................................................ RW
7
Bus Refresh Arbitration (do not program) default=0
6
XRDY Test Mode (do not program) ...........default=0
5
Port 92 Fast Reset
0 Disable................................................... default
1 Enable
4
A20G Emulation (do not program) .............default=0
3
Double DMA Clock
0 Disable (DMA Clock = ½ ISA Clock)... default
1 Enable (DMA Clock = ISA Clock)
2
SHOLD Lock During INTA (do not program) def=0
1
Refresh Request Test Mode (do not program).def=0
0
ISA Refresh
0 Disable................................................... default
1 Enable
This bit should be set to 1 for ISA compatibility.
Offset B - Class Code = 06h ...............................................RO
Offset E - Header Type = 80h............................................RO
7-0 Header Type Code .........80h (Multifunction Device)
Offset F - BIST = 00h .........................................................RO
Offset 2F-2C - Subsystem ID .............................................RO
Use offset 70-73 to change the value returned.
Preliminary Revision 0.8 October 29, 1999
-57-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 42 - ISA Clock Control. ......................................... RW
7
Latch IO16#
0 Enable (recommended setting) ...............default
1 Disable
6
MCS16# Output
0 Disable ...................................................default
1 Enable
5
Master Request Test Mode (do not program)
0 Disable ...................................................default
1 Enable
4
Reserved (Do Not Program) ................... default = 0
3
ISA Clock (BCLK) Select Enable
0 BCLK = PCICLK/4................................default
1 BCLK selected per bits 2-0
2-0 ISA Bus Clock Select (if bit-3 = 1)
000 BCLK = PCICLK/3................................default
001 BCLK = PCICLK/2
010 BCLK = PCICLK/4
011 BCLK = PCICLK/6
100 BCLK = PCICLK/5
101 BCLK = PCICLK/10
110 BCLK = PCICLK/12
111 BCLK = OSC
Note: Procedure for ISA Clock switching:
1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1
Preliminary Revision 0.8 October 29, 1999
Offset 43 - ROM Decode Control .................................... RW
Setting these bits enables the indicated address range to be
included in the ROMCS# decode:
7
6
5
4
3
2
1
0
FFFE0000h-FFFEFFFFh ..........................default=0
FFF80000h-FFFDFFFFh ..........................default=0
FFF00000h-FFF7FFFFh............................default=0
000E0000h-000EFFFFh .............................default=0
000D8000h-000DFFFFh ............................default=0
000D0000h-000D7FFFh ............................default=0
000C8000h-000CFFFFh ............................default=0
000C0000h-000C7FFFh .............................default=0
Offset 44 - Keyboard Controller Control ....................... RW
7
KBC Timeout Test (do not program)........default = 0
6-4 Reserved (do not program) ........................default = 0
3
Mouse Lock Enable
0 Disable................................................... default
1 Enable
2-1 Reserved (do not program) ........................default = 0
0
Reserved (no function) ..............................default = 0
Offset 45 - Type F DMA Control .................................... RW
7
ISA Master / DMA to PCI Line Buffer
0 Disable................................................... default
1 Enable
6
DMA type F Timing on Channel 7............default=0
5
DMA type F Timing on Channel 6............default=0
4
DMA type F Timing on Channel 5............default=0
3
DMA type F Timing on Channel 3............default=0
2
DMA type F Timing on Channel 2............default=0
1
DMA type F Timing on Channel 1............default=0
0
DMA type F Timing on Channel 0............default=0
-58-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 46 - Miscellaneous Control 1 ................................. RW
7
PCI Master Write Wait States
0 0 Wait States ..........................................default
1 1 Wait State
6
Gate INTR
0 Disable ...................................................default
1 Enable
5
Flush Line Buffer for Int or DMA IOR Cycle
0 Disable ...................................................default
1 Enable
4
Config Command Reg Rx04 Access (Test Only)
0 Normal: Bits 0-1=RO, Bit 3=RW..........default
1 Test Mode: Bits 0-1=RW, Bit-3=RO
3
Reserved (do not program)........................ default = 0
2
Reserved (no function) .............................. default = 0
1
PCI Burst Read Interruptability
0 Allow burst reads to be interrupted by ISA
master or DMA.......................................default
1 Don’t allow PCI burst reads to be interrupted
0
Posted Memory Write Enable
0 Disable ...................................................default
1 Enable
The Posted Memory Write function is automatically
enabled when Delay Transaction (see Rx47 bit-6) is
enabled, independent of the state of this bit.
Preliminary Revision 0.8 October 29, 1999
Offset 47 - Miscellaneous Control 2 ................................ RW
7
CPU Reset Source
0 Use CPURST as CPU Reset .................. default
1 Use INIT as CPU Reset
6
PCI Delay Transaction Enable
0 Disable................................................... default
1 Enable
The "Posted Memory Write" function is
automatically enabled when this bit is enabled,
independent of the state of Rx46 bit-0.
5
EISA 4D0/4D1 Port Enable
0 Disable (ignore ports 4D0-1) ................. default
1 Enable (ports 4D0-1 per EISA specification)
4
Interrupt Controller Shadow Register Enable
0 Disable................................................... default
1 Enable (for test purposes, enable readback of
interrupt controller internal functions on I/O
reads from ports 20-21, A0-A1, A8-A9, and
C8-C9) (Contact VIA Test Engineering
department)
3
Reserved (always program to 0)..............default = 0
Note: Always mask this bit. This bit may read back
as either 0 or 1 but must always be
programmed with 0.
2
Write Delay Transaction Time-Out Timer
0 Disable................................................... default
1 Enable
1
Read Delay Transaction Time-Out Timer
0 Disable................................................... default
1 Enable
0
Software PCI Reset ......write 1 to generate PCI reset
-59-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 48 - Miscellaneous Control 3 ................................. RW
........................................ always reads 0
7-4 Reserved
3
Extra RTC Port 74/75 Enable
0 Disable ...................................................default
1 Enable
2
Integrated USB Controller Disable
0 Enable.....................................................default
1 Disable
1
Integrated IDE Controller Disable
0 Enable.....................................................default
1 Disable
0
512K PCI Memory Decode
0 Use Rx4E[15-12] to select top of PCI memory
1 Use contents of Rx4E[15-12] plus 512K as top
of PCI memory .......................................default
Offset 4A - IDE Interrupt Routing .................................. RW
7
Wait for PGNT Before Grant to ISA Master /
DMA
0 Disable ...................................................default
1 Enable
6
Bus Select for Access to I/O Devices Below 100h
0 Access ports 00-FFh via XD bus............default
1 Access ports 00-FFh via SD bus (applies to
external devices only; internal devices such as
the mouse controller are not effected)
5-4 Reserved (do not program) ..................... default = 0
3-2 IDE Second Channel IRQ Routing
00 IRQ14
01 IRQ15.....................................................default
10 IRQ10
11 IRQ11
1-0 IDE Primary Channel IRQ Routing
00 IRQ14.....................................................default
01 IRQ15
10 IRQ10
11 IRQ11
Preliminary Revision 0.8 October 29, 1999
4C - ISA DMA/Master Memory Access Control 1 ........ RW
7-0 PCI Memory Hole Bottom Address
These bits correspond to HA[23:16] ............default=0
4D - ISA DMA/Master Memory Access Control 2 ........ RW
7-0 PCI Memory Hole Top Address (HA[23:16])
These bits correspond to HA[23:16] ............default=0
Note:
Access to the memory defined in the PCI memory
hole will not be forwarded to PCI. This function is
disabled if the top address is less than or equal to the
bottom address.
4F-4E - ISA DMA/Master Memory Access Control 3 ... RW
15-12 Top of PCI Memory for ISA DMA/Master accesses
0000 1M .................................................... default
0001 2M
... ...
1111 16M
Note: All ISA DMA / Masters that access addresses higher
than the top of PCI memory will not be directed to the
PCI bus.
11 Forward E0000-EFFFF Accesses to PCI........def=0
10 Forward A0000-BFFFF Accesses to PCI .......def=0
9
Forward 80000-9FFFF Accesses to PCI ........def=1
8
Forward 00000-7FFFF Accesses to PCI ........def=1
7
Forward DC000-DFFFF Accesses to PCI ......def=0
6
Forward D8000-DBFFF Accesses to PCI ......def=0
5
Forward D4000-D7FFF Accesses to PCI .......def=0
4
Forward D0000-D3FFF Accesses to PCI .......def=0
3
Forward CC000-CFFFF Accesses to PCI .....def=0
2
Forward C8000-CBFFF Accesses to PCI ......def=0
1
Forward C4000-C7FFF Accesses to PCI .......def=0
0
Forward C0000-C3FFF Accesses to PCI .......def=0
-60-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Plug and Play Control
PnP IRQ Routing Table
0000 Disabled................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 Reserved
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 Reserved
1110 IRQ14
1111 IRQ15
Offset 50 – PNP DMA Request Control .......................... RW
.............................................. default = 0
7-4 Reserved
3-2 PnP Routing for Parallel Port DRQ.....def = DRQ3
1-0 PnP Routing for Floppy DRQ...............def = DRQ2
DRQ Mapping: 00=DRQ0, 01=DRQ1, 10=DRQ2, 11=DRQ3
Offset 51 - PNP IRQ Routing 1 ........................................ RW
7-4 PnP Routing for Parallel Port IRQ (see PnP IRQ
routing table)
3-0 PnP Routing for Floppy IRQ (see PnP IRQ routing
table)
Offset 52 - PNP IRQ Routing 2 ........................................ RW
7-4 PnP Routing for Serial Port 2 IRQ (see PnP IRQ
routing table)
3-0 PnP Routing for Serial Port 1 IRQ (see PnP IRQ
routing table)
Offset 54 - PCI IRQ Edge / Level Select .......................... RW
........................................ always reads 0
7-4 Reserved
The following bits all default to “level” triggered (0)
3
PIRQA# Invert (edge) / Non-invert (level).......(1/0)
2
PIRQB# Invert (edge) / Non-invert (level).......(1/0)
1
PIRQC# Invert (edge) / Non-invert (level).......(1/0)
0
PIRQD# Invert (edge) / Non-invert (level).......(1/0)
Note:
PIRQA-D# normally connect to PCI interrupt pins
INTA-D# (see pin definitions for more information).
Offset 55 - PNP IRQ Routing 4 ........................................ RW
7-4 PIRQA# Routing (see PnP IRQ routing table)
........................................ always reads 0
3-0 Reserved
Offset 56 - PNP IRQ Routing 5 ........................................ RW
7-4 PIRQC# Routing (see PnP IRQ routing table)
3-0 PIRQB# Routing (see PnP IRQ routing table)
Offset 57 - PNP IRQ Routing 6 ........................................ RW
7-4 PIRQD# Routing (see PnP IRQ routing table)
........................................ always reads 0
3-0 Reserved
Preliminary Revision 0.8 October 29, 1999
-61-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 59 – PCS0# Control ............................................... RW
........................................ always reads 0
7-4 Reserved
3
PCS0# Pin Function (Pin T5)
0 Pin is defined as PCS0# ........................default
1 Pin is defined as Internal Trap I/O
........................................ always reads 0
2-0 Reserved
Offset 5A – KBC / RTC Control ...................................... RW
Bits 7-4 of this register are latched from pins SD7-4 at powerup but are read/write accessible so may be changed after
power-up to change the default strap setting:
7
6
5
4
3
2
1
0
Note:
Keyboard RP16 ............................. latched from SD7
Keyboard RP15 ............................ latched from SD6
Keyboard RP14 ............................ latched from SD5
Keyboard RP13 ............................ latched from SD4
Audio Function Enable
....... RO, strapped from SPKR pin V5
0 Disable (SDD pins function as SDD)
1 Enable (SDD pins function as Audio / Game)
Internal RTC Enable
0 Disable
1 Enable ....................................................default
Internal PS2 Mouse Enable
0 Disable ..................................................default
1 Enable
Internal KBC Enable
0 Disable ..................................................default
1 Enable
External strap option values may be set by connecting
the indicated external pin to a 4.7K ohm pullup (for
1) or driving it low during reset with a 7407 TTL
open collector buffer (for 0) as shown in the
suggested circuit below:
9&&
9&&
.
5(6(7
6'Q
Offset 5B - Internal RTC Test Mode .............................. RW
........................................always reads 0
7-4 Reserved
3
Map RTC Rx32 to Rx3F
0 Disable................................................... default
1 Enable
2
RTC Reset Enable (do not program)
0 Disable................................................... default
1 Enable
1
RTC SRAM Access Enable
0 Disable................................................... default
1 Enable
This bit is set if the internal RTC is disabled but it is
desired to still be able to access the internal RTC
SRAM via ports 74-75. If the internal RTC is
enabled, setting this bit does nothing (the internal
RTC SRAM should be accessed at either ports 70/71
or 72/73.
0
RTC Test Mode Enable (do not program) .default=0
Offset 5C - DMA Control................................................. RW
7
PCS0# & PCS1# 16-Bit I/O
0 Disable................................................... default
1 Enable
6
Passive Release
0 Disable................................................... default
1 Enable
5
Internal Passive Release
0 Disable................................................... default
1 Enable
4
Dummy PREQ
0 Disable................................................... default
1 Enable
........................................always reads 0
3
Reserved
2
APIC Connection
0 APIC on SD Bus.................................... default
1 APIC on XD Bus
1
Reserved (Do Not Program) ....................default = 0
0
DMA Line Buffer Disable
0 DMA cycles can be to/from line buffer ....... def
1 Disable DMA Line Buffer
Figure 5. Strap Option Circuit
Preliminary Revision 0.8 October 29, 1999
-62-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Distributed DMA / Serial IRQ Control
Offset 61-60 - Distributed DMA Ch 0 Base / Enable ...... RW
15-4 Channel 0 Base Address Bits 15-4 .......... default = 0
3
Channel 0 Enable
0 Disable ...................................................default
1 Enable
........................................ always reads 0
2-0 Reserved
Offset 6B-6A - Distributed DMA Ch 5 Base / Enable.... RW
15-4 Channel 5 Base Address Bits 15-4...........default = 0
3
Channel 5 Enable
0 Disable................................................... default
1 Enable
........................................always reads 0
2-0 Reserved
Offset 63-62 - Distributed DMA Ch 1 Base / Enable ...... RW
15-4 Channel 1 Base Address Bits 15-4 .......... default = 0
3
Channel 1 Enable
0 Disable ...................................................default
1 Enable
........................................ always reads 0
2-0 Reserved
Offset 6D-6C - Distributed DMA Ch 6 Base / Enable ... RW
15-4 Channel 6 Base Address Bits 15-4...........default = 0
3
Channel 6 Enable
0 Disable................................................... default
1 Enable
........................................always reads 0
2-0 Reserved
Offset 65-64 - Distributed DMA Ch 2 Base / Enable ...... RW
15-4 Channel 2 Base Address Bits 15-4 .......... default = 0
3
Channel 2 Enable
0 Disable ...................................................default
1 Enable
........................................ always reads 0
2-0 Reserved
Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW
15-4 Channel 7 Base Address Bits 15-4...........default = 0
3
Channel 7 Enable
0 Disable................................................... default
1 Enable
........................................always reads 0
2-0 Reserved
Offset 67-66 - Distributed DMA Ch 3 Base / Enable ...... RW
15-4 Channel 3 Base Address Bits 15-4 .......... default = 0
3
Channel 3 Enable
0 Disable ...................................................default
1 Enable
........................................ always reads 0
2-0 Reserved
Offset 69-68 – Serial IRQ Control ................................... RW
........................................ always reads 0
15-4 Reserved
3
ISA IRQ Asserted Via Serial IRQ (Pin H3 or L4)
0 Disable ...................................................default
1 Enable
2
Serial IRQ Mode
0 Continuous Mode ...................................default
1 Quiet Mode
1-0 Serial IRQ Start-Frame Width
00 4 PCI Clocks ..........................................default
01 6 PCI Clocks
10 8 PCI Clocks
11 10 PCI Clocks
The frame size is fixed at 21 PCI clocks.
Preliminary Revision 0.8 October 29, 1999
-63-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Miscellaneous / General Purpose I/O
Offset 73-70 - Subsystem ID ............................................ WO
31-0 Subsystem ID / Vendor ID................. always reads 0
Contents may be read at offset 2C.
Offset 74 – GPIO Control 1 .............................................. RW
7
APIC Enable
0 Disable (Pin U8 is GPIOD / MCCS#)....default
1 Enable (Pin U8 is SCIOUT#)
6
SERIRQ Pin
0 SERIRQ input from DRQ2 (Pin H3)......default
1 SERIRQ input from DACK5# (Pin L4)
5
GPIOD Direction (Pin U8)
0 Input .....................................................default
1 Output (GPO11)
4
GPIOC Direction (Pin V14)
0 Input .....................................................default
1 Output
3
GPIOB Direction (Pin U12)
0 Input .....................................................default
1 Output
2
GPIOA Direction (Pin T14)
0 Input .....................................................default
1 Output
1
THRM Enable (Pin T11)
0 PME# / GPI5 (see Func 4 Rx48[5]) .......default
1 THRM
0
GPI0 / IOCHCK# Select
0 GPI0 .....................................................default
1 IOCHCK#
Preliminary Revision 0.8 October 29, 1999
Offset 75 – GPIO Control 2 ............................................. RW
7
GPO7 Enable (Pin T7)
0 Pin defined as SLP#............................... default
1 Pin defined as GPO7
........................................always reads 0
6
Reserved
5
GPO5 Enable (Pin V12)
0 Pin defined as PCISTP# ........................ default
1 Pin defined as GPO5
4
GPO4 Enable (Pin Y12)
0 Pin defined as CPUSTP# ....................... default
1 Pin defined as GPO4
3
FDC External IRQ / DRQ Via DACK2# / DRQ2
0 Pin G5 is FDCIRQ, pin H3 is FDCDRQ ..... def
1 Pin G5 is DACK2# or other alternate function
Pin H3 is DRQ2 or other alternate function
2
GPO25 Enable (Pin G5)
0 Rx75[3]=0: Pin G5 defined as DACK2# .... def
1 Pin G5 defined as GPO25
1
GPO24 Enable (Pin H3)
0 Rx75[3]=0: ............................................ default
Rx68[3]=0: Pin H3 defined as DRQ2
Rx68[3]=1: Pin H3 defined as SERIRQ
1 Pin H3 defined as GPO24
0
Positive Decode
0 Subtractive Decode................................ default
1 Positive Decode
-64-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 76 – GPIO Control 3 .............................................. RW
7
Over-Current (OC) Input
0 Disable ...................................................default
1 Enable
6
OC[3:0] From SD[3:0] By Scan
0 Disable ...................................................default
1 Enable
5
GPO14 / GPO15 Enable (Pins E12 / D12)
0 Pins used for IRTX and IRRX ...............default
1 Pins used for GPO14 and GPO15
4
MCCS# Pin Select
0 MCCS# is on Pin U5..............................default
1 MCCS# is on Pin U8
3
MCCS# Function
0 Disable MCCS# function on U5/U8.......default
1 Enable MCCS# function on U5/U8
(see bit-4 for select of U5 or U8 for MCCS#)
2
CHAS Enable (Pin V14)
0 Pin is defined as GPIOC.........................default
1 Pin is defined as CHAS
1
GPO12 Enable (Pin T5)
0 Pin is defined as XDIR...........................default
1 Pin is defined as GPO12
0
GPOWE# (GPO[23-16]) Enable (Pin T14)
0 Pin is defined as GPIOA ........................default
1 Pin is defined as GPOWE# (Rx74[2] also must
be set to 1)
Offset 77 – GPIO Control 4 Control................................ RW
7
DRQ / DACK# Pins are GPI / GPO
0 Disable ...................................................default
1 Enable
6
Game Port XY Pins are GPI / GPO
0 Disable ...................................................default
1 Enable
........................................ always reads 0
5-4 Reserved
3
SERIRQ SMI Slot
0 Disable ...................................................default
1 Enable
2
RTC Rx32 Write Protect
0 Disable ...................................................default
1 Enable
1
RTC Rx0D Write Protect
0 Disable ...................................................default
1 Enable
0
GPO13 Enable (Pin U5)
0 Pin defined as SOE#...............................default
1 Pin defined as GPO13
Preliminary Revision 0.8 October 29, 1999
Offset 79-78 – PCS0# I/O Port Address .......................... RW
15-0 PCS0# I/O Port Address [15-0]
Offset 7B-7A – PCS1# I/O Port Address ........................ RW
15-0 PCS1# I/O Port Address [15-0]
Offset 7D-7C – PCI DMA Channel Enable .................... RW
........................................always reads 0
15-9 Reserved
8
PCI DMA Pair A
0 Disable................................................... default
1 Enable
7
PCI DMA Channel 7
0 Disable................................................... default
1 Enable
6
PCI DMA Channel 6
0 Disable................................................... default
1 Enable
5
PCI DMA Channel 5
0 Disable................................................... default
1 Enable
........................................always reads 0
4
Reserved
3
PCI DMA Channel 3
0 Disable................................................... default
1 Enable
2
PCI DMA Channel 2
0 Disable................................................... default
1 Enable
1
PCI DMA Channel 1
0 Disable................................................... default
1 Enable
0
PCI DMA Channel 0
0 Disable................................................... default
1 Enable
Offset 7F-7E – 32-Bit DMA Control ............................... RW
15-3 32-Bit DMA High Page (A31-24) Registers IOBase
........................................always reads 0
2-1 Reserved
0
32-Bit DMA
0 Disable................................................... default
1 Enable
Offset 80 – Programmable Chip Select Mask ................ RW
7-4 PCS1# I/O Port Address Mask [3-0]
3-0 PCS0# I/O Port Address Mask [3-0]
-65-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 81 – ISA Positive Decoding Control 1 .................. RW
7
On-Board I/O Port Positive Decoding
0 Disable ...................................................default
1 Enable
6
Microsoft-Sound System I/O Port Positive
Decoding
0 Disable ...................................................default
1 Enable
5-4 Microsoft-Sound System I/O Decode Range
00 0530h-0537h ..........................................default
01 0604h-060Bh
10 0E80-0E87h
11 0F40h-0F47h
3
APIC Positive Decoding
0 Disable ...................................................default
1 Enable
2
BIOS ROM Positive Decoding
0 Disable ...................................................default
1 Enable
........................................ always reads 0
1
Reserved
0
PCS0 Positive Decoding
0 Disable ...................................................default
1 Enable
Offset 82 – ISA Positive Decoding Control 2 .................. RW
7
FDC Positive Decoding
0 Disable ...................................................default
1 Enable
6
LPT Positive Decoding
0 Disable ...................................................default
1 Enable
5-4 LPT Decode Range
00 3BCh-3BFh, 7BCh-7BEh.......................default
01 378h-37Fh, 778h-77Ah
10 278h-27Fh, 678h-67Ah
11 -reserved3
Game Port Positive Decoding
0 Disable ...................................................default
1 Enable
2
MIDI Positive Decoding
0 Disable ...................................................default
1 Enable
1-0 MIDI Decode Range
00 300h-303h ..............................................default
01 310h-313h
10 320h-323h
11 330h-333h
Preliminary Revision 0.8 October 29, 1999
Offset 83 – ISA Positive Decoding Control 3 .................. RW
7
COM Port B Positive Decoding
0 Disable................................................... default
1 Enable
6-4 COM-Port B Decode Range
000 3F8h-3FFh (COM1)............................ default
001 2F8h-2FFh (COM2)
010 220h-227h
011 228h-22Fh
100 238h-23Fh
101 2E8h-2EFh (COM4)
110 338h-33Fh
111 3E8h-3EFh (COM3)
3
COM Port A Positive Decoding
0 Disable................................................... default
1 Enable
2-0 COM-Port A Decode Range
000 3F8h-3FFh (COM1)............................ default
001 2F8h-2FFh (COM2)
010 220h-227h
011 228h-22Fh
100 238h-23Fh
101 2E8h-2EFh (COM4)
110 338h-33Fh
111 3E8h-3EFh (COM3)
Offset 84 – ISA Positive Decoding Control 4 .................. RW
........................................always reads 0
7-4 Reserved
3
FDC Decoding Range
0 Primary .................................................. default
1 Secondary
2
Sound Blaster Positive Decoding
0 Disable................................................... default
1 Enable
1-0 Sound Blaster Decode Range
00 220h-22Fh, 230h-233h .......................... default
01 240h-24Fh, 250h-253h
10 260h-26Fh, 270h-273h
11 280h-28Fh, 290h-293h
-66-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 85 – Extended Function Enable ............................ RW
........................................ always reads 0
7-5 Reserved
4
Function 3 USB Ports 2-3
0 Enable.....................................................default
1 Disable
3
Function 6 Modem / Audio
0 Enable.....................................................default
1 Disable
2
Function 5 Audio
0 Enable.....................................................default
1 Disable
1
Super-I/O Configuration
0 Disable ...................................................default
1 Enable
0
Super-I/O
0 Disable ...................................................default
1 Enable
Preliminary Revision 0.8 October 29, 1999
Offset 86 – PNP IRQ/DRQ Test 1 (Do Not Program) ... RW
Offset 87 – PNP IRQ/DRQ Test 2 (Do Not Program) ... RW
-67-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 88 – PLL Test ......................................................... RW
7
PCS0# Access Status
6
RTC Rx32 / Rx7F Write Protect
0 Disable ...................................................default
1 Enable
5
MC IRQ Test (Do Not Program)
0 Disable ...................................................default
1 Enable
4
PLL PU (Do Not Program)
0 Disable ...................................................default
1 Enable
3
PLL Test Mode (Do Not Program)
0 Disable ...................................................default
1 Enable
2-0 PLL Test Mode Select
Offset 89 – PLL Control ................................................... RW
........................................ always reads 0
7-4 Reserved
3-2 PLL PCLK Input Delay Select
1-0 PLL CLK66 Feedback Delay Select
Offset 8A – PCS2/3 I/O Port Address Mask................... RW
7-4 PCS3# I/O Port Address Mask 3-0
3-0 PCS2# I/O Port Address Mask 3-0
Offset 8B – PCS Control .................................................. RW
7
PCS3# For Internal I/O
0 Disable................................................... default
1 Enable
6
PCS2# For Internal I/O
0 Disable................................................... default
1 Enable
5
PCS1# For Internal I/O
0 Disable................................................... default
1 Enable
4
PCS0# For Internal I/O
0 Disable................................................... default
1 Enable
3
PCS3#
0 Disable................................................... default
1 Enable
2
PCS2#
0 Disable................................................... default
1 Enable
1
PCS1#
0 Disable................................................... default
1 Enable
0
PCS0#
0 Disable................................................... default
1 Enable
Offset 8D-8C – PCS2# I/O Port Address ........................ RW
15-0 PCS2# I/O Port Address
Offset 8F-8E – PCS3# I/O Port Address ......................... RW
15-0 PCS3# I/O Port Address
Preliminary Revision 0.8 October 29, 1999
-68-
Function 0 Registers - PCI to ISA Bridge
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 1 Registers - Enhanced IDE Controller
This Enhanced IDE controller interface is fully compatible
with the SFF 8038i v.1.0 specification. There are two sets of
software accessible registers -- PCI configuration registers and
Bus Master IDE I/O registers. The PCI configuration registers
are located in the function 1 PCI configuration space of the
VT8231. The Bus Master IDE I/O registers are defined in the
SFF8038i v1.0 specification.
PCI Configuration Space Header
Offset 1-0 - Vendor ID (1106h=VIA) ................................RO
Offset 3-2 - Device ID (0571h=IDE Controller) ...............RO
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-10 Reserved
9
Fast Back to Back Cycles ....... default = 0 (disabled)
8
SERR# Enable......................... default = 0 (disabled)
7
Address Stepping ...................... fixed at 1 (enabled)
A value of 1 provides additional address decode time
to IDE devices.
6
Parity Error Response............ default = 0 (disabled)
5
VGA Palette Snoop ....................fixed at 0 (disabled)
4
Memory Write & Invalidate .....fixed at 0 (disabled)
3
Special Cycles .............................fixed at 0 (disabled)
2
Bus Master ............................. default = 0 (disabled)
S/G operation can be issued only when the “Bus
Master” bit is enabled.
1
Memory Space............................fixed at 0 (disabled)
0
I/O Space ............................. default = 0 (disabled)
When the “I/O Space” bit is disabled, the device will
not respond to any I/O addresses for both compatible
and native mode.
Offset 7-6 - Status ...............................................................RO
15 Detected Parity Error .................................fixed at 0
14 Signalled System Error...............................fixed at 0
13 Received Master Abort...............................fixed at 0
12 Received Target Abort ...............................fixed at 0
11 Signalled Target Abort ...............................fixed at 0
10-9 DEVSEL# Timing ..................default = 01 (medium)
8
Data Parity Detected...................................fixed at 0
7
Fast Back to Back .......................................fixed at 1
........................................ always reads 0
6-0 Reserved
Offset 9 - Programming Interface ................................... RW
7
Master IDE Capability........... fixed at 1 (Supported)
........................................always reads 0
6-4 Reserved
3
Programmable Indicator - Secondary ...... fixed at 1
Supports both modes (may be set to either mode by
writing bit-2)
........................................always reads 0
2
Reserved
1
Programmable Indicator - Primary.......... fixed at 1
Supports both modes (may be set to either mode by
writing bit-0)
........................................always reads 0
0
Reserved
Compatibility Mode (fixed IRQs and I/O addresses):
Command Block
Control Block
Channel
Registers
Registers
IRQ
Pri
1F0-1F7
3F6
14
Sec
170-177
376
15
Native PCI Mode (registers are programmable in I/O space)
Command Block
Control Block
Channel
Registers
Registers
Pri
BA @offset 10h
BA @offset 14h
Sec
BA @offset 18h BA @offset 1Ch
Command register blocks are 8 bytes of I/O space
Control registers are 4 bytes of I/O space (only byte 2 is used)
Offset A - Sub Class Code (01h=IDE Controller) ........... RO
Offset B - Base Class Code (01h=Mass Storage Ctrlr) ... RO
Offset C – Cache Line Size (00h) ...................................... RO
Offset D - Latency Timer (Default=0) ............................. RW
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h) ......................................................... RO
Offset 8 - Revision ID (06) .................................................RO
0-7 Revision Code for IDE Controller Logic Block
Preliminary Revision 0.8 October 29, 1999
-69-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 13-10 - Pri Data / Command Base Address.......... RW
Specifies an 8 byte I/O address space.
..........................................always read 0
31-16 Reserved
15-3 Port Address....................................... default=01F0h
2-0 Fixed at 001b ..................................................... fixed
Offset 17-14 - Pri Control / Status Base Address............ RW
Specifies a 4 byte I/O address space of which only the third
byte is active (i.e., 3F6h for the default base address of 3F4h).
..........................................always read 0
31-16 Reserved
15-2 Port Address....................................... default=03F4h
1-0 Fixed at 01b ....................................................... fixed
Offset 34 - Capability Pointer (C0h) ................................ RO
Offset 3C - Interrupt Line (0Eh) ...................................... RO
Offset 3D - Interrupt Pin (00h) ......................................... RO
7-0 Interrupt Routing Mode
00h Legacy mode interrupt routing............... default
01h Native mode interrupt routing
Offset 3E - Min Gnt (00h) ................................................. RO
Offset 3F - Max Latency (00h).......................................... RO
Offset 1B-18 - Sec Data / Command Base Address ........ RW
Specifies an 8 byte I/O address space.
..........................................always read 0
31-16 Reserved
15-3 Port Address ...................................... default=0170h
2-0 Fixed at 001b ..................................................... fixed
Offset 1F-1C - Sec Control / Status Base Address .......... RW
Specifies a 4 byte I/O address space of which only the third
byte is active (i.e., 376h for the default base address of 374h).
..........................................always read 0
31-16 Reserved
15-2 Port Address ...................................... default=0374h
1-0 Fixed at 01b ....................................................... fixed
Offset 23-20 - Bus Master Control Regs Base Address .. RW
Specifies a 16 byte I/O address space compliant with the SFF8038i rev 1.0 specification.
..........................................always read 0
31-16 Reserved
15-4 Port Address ....................................... default=CC0h
3-0 Fixed at 0001b .................................................. fixed
Preliminary Revision 0.8 October 29, 1999
-70-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
IDE-Controller-Specific Confiiguration Registers
Offset 40 - Chip Enable..................................................... RW
........................................ always reads 0
7-4 Reserved
3-2 Reserved (Do Not Program)...........R/W, default = 0
1
Primary Channel Enable........ default = 0 (disabled)
0
Secondary Channel Enable .... default = 0 (disabled)
Offset 41 - IDE Configuration .......................................... RW
7
Primary IDE Read Prefetch Buffer
0 Disable ...................................................default
1 Enable
6
Primary IDE Post Write Buffer
0 Disable ...................................................default
1 Enable
5
Secondary IDE Read Prefetch Buffer
0 Disable ...................................................default
1 Enable
4
Secondary IDE Post Write Buffer
0 Disable ...................................................default
1 Enable
Offset 43 - FIFO Configuration ....................................... RW
........................................always reads 0
7-4 Reserved
3-2 Threshold for Primary Channel
00 0
01 1/4
10 1/2
.................................................... default
11 3/4
1-0 Threshold for Secondary Channel
00 0
01 1/4
10 1/2
.................................................... default
11 3/4
........................................ always reads 0
3
Reserved
2
1
Reserved (Do Not Change)........................ default=1
Reserved (Do Not Change)........................ default=1
0
Reserved
........................................ always reads 0
Offset 42 - Reserved (Do Not Program) .......................... RW
Preliminary Revision 0.8 October 29, 1999
-71-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 44 - Miscellaneous Control 1 ................................. RW
........................................ always reads 0
7
Reserved
6
Master Read Cycle IRDY# Wait States
0 0 wait states
1 1 wait state..............................................default
5
Master Write Cycle IRDY# Wait States
0 0 wait states
1 1 wait state..............................................default
........................................ always reads 0
4
Reserved
3
Bus Master IDE Status Register Read Retry
Retry bus master IDE status register read when
master write operation for DMA read is not complete
0 Disabled
1 Enabled...................................................default
........................................ always reads 0
2-1 Reserved
0
UltraDMA Host Must Wait for First Strobe
Before Termination
0 Enabled...................................................default
1 Disabled
Offset 45 - Miscellaneous Control 2 ................................. RW
........................................ always reads 0
7
Reserved
6
Interrupt Steering Swap
0 Don’t swap channel interrupts................default
1 Swap interrupts between the two channels
........................................ always reads 0
5-4 Reserved
3
Memory Read Multiple Command
0 Disable ...................................................default
1 Enable
2
Memory Read and Invalidate Command
0 Disable ...................................................default
1 Enable
1
Secondary Channel Threshold Enable
0 Disable (data transfer starts immediately if
FIFO is not empty)
1 Enable (data transfer will not start until the
FIFO is filled to the threshold set in bits 1-0 of
Rx43) .....................................................default
0
Primary Channel Threshold Enable
0 Disable (data transfer starts immediately if
FIFO is not empty)
1 Enable (data transfer will not start until the
FIFO is filled to the threshold set in bits 3-2 of
Rx43) .....................................................default
Preliminary Revision 0.8 October 29, 1999
Offset 46 - Miscellaneous Control 3 ................................ RW
7
Primary Channel Read DMA FIFO Flush
1 = Enable FIFO flush for read DMA when interrupt
asserts primary channel. ...............default=1 (enabled)
6
Secondary Channel Read DMA FIFO Flush
1 = Enable FIFO flush for Read DMA when interrupt
asserts secondary channel. ........... Default=1 (enabled)
5
Primary Channel End-of-Sector FIFO Flush
1 = Enable FIFO flush at the end of each sector for
the primary channel. ................... Default=0 (disabled)
4
Secondary Channel End-of-Sector FIFO Flush
1 = Enable FIFO flush at the end of each sector for
the secondary channel................. Default=0 (disabled)
........................................always reads 0
3-2 Reserved
1-0 Max DRDY Pulse Width
Maximum DRDY# pulse width after the cycle count.
Command will deassert in spite of DRDY# status to
avoid system ready hang.
00 No limitation.......................................... default
01 64 PCI clocks
10 128 PCI clocks
11 192 PCI clocks
-72-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 4B-48 - Drive Timing Control ............................... RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
31-28
27-24
23-20
19-16
15-12
11-8
7-4
3-0
Primary Drive 0 Active Pulse Width ...... def=1010b
Primary Drive 0 Recovery Time ............. def=1000b
Primary Drive 1 Active Pulse Width ...... def=1010b
Primary Drive 1 Recovery Time ............. def=1000b
Secondary Drive 0 Active Pulse Width .. def=1010b
Secondary Drive 0 Recovery Time ......... def=1000b
Secondary Drive 1 Active Pulse Width .. def=1010b
Secondary Drive 1 Recovery Time ......... def=1000b
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
Offset 4C - Address Setup Time ....................................... RW
7-6 Primary Drive 0 Address Setup Time
5-4 Primary Drive 1 Address Setup Time
3-2 Secondary Drive 0 Address Setup Time
1-0 Secondary Drive 1 Address Setup Time
Offset 53-50 - UltraDMA Extended Timing Control ..... RW
31 Pri Drive 0 UltraDMA-Mode Enable Method
0 Enable by using “Set Feature” command..... def
1 Enable by setting bit-30 of this register
30 Pri Drive 0 UltraDMA-Mode Enable
0 Disable................................................... default
1 Enable UltraDMA-Mode Operation
29 Pri Drive 0 Transfer Mode
0 DMA or PIO Mode ............................... default
1 UltraDMA Mode
........................................always reads 0
28-27 Reserved
26-24 Pri Drive 0 Cycle Time (T = 30nsec @33MHz)
000 2T
001 3T
010 4T
011 5T
100 6T
101 7T
110 8T
111 9T
.................................................... default
For each field above:
00 1T
01 2T
10 3T
11 4T
.....................................................default
23
22
21
20
19
Pri Drive 1 UltraDMA-Mode Enable Method
Pri Drive 1 UltraDMA-Mode Enable
Pri Drive 1 Transfer Mode
........................................always reads 0
Reserved
Pri Clock Source
0 33 MHz.................................................. default
1 66 MHz
18-16 Pri Drive 1 Cycle Time
Offset 4E - Secondary Non-1F0 Port Access Timing...... RW
7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b
3-0 DIOR#/DIOW# Recovery Time.............. def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW
7-4 DIOR#/DIOW# Active Pulse Width....... def=1111b
3-0 DIOR#/DIOW# Recovery Time.............. def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
15
14
13
12-11
10-8
Sec Drive 0 UltraDMA-Mode Enable Method
Sec Drive 0 UltraDMA-Mode Enable
Sec Drive 0 Transfer Mode
........................................always reads 0
Reserved
Sec Drive 0 Cycle Time
7
6
5
4
3
Sec Drive 1 UltraDMA-Mode Enable Method
Sec Drive 1 UltraDMA-Mode Enable
Sec Drive 1 Transfer Mode
........................................always reads 0
Reserved
Sec Clock Source
0 33 MHz.................................................. default
1 66 MHz
Sec Drive 1 Cycle Time
2-0
Each byte defines UltraDMA operation for the indicated drive.
The bit definitions are the same within each byte.
Preliminary Revision 0.8 October 29, 1999
-73-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 54 – UltraDMA FIFO Control .............................. RW
........................................ always reads 0
7-5 Reserved
4
One Frame For Each PCI Request For IDE PCI
Master Cycles
0 Disabled ................................................default
1 Enabled
3
Grant ISA While Sharing Bus with SA & IDE in
IDLE State
0 Enable.....................................................default
1 Disable
2
Change Drive to Clear All FIFO & Internal States
0 Disabled
1 Enabled...................................................default
1
Add Dummy FIFO Push After End of Transfer
0 Enabled
1 Disabled .................................................default
This bit is normally set to 0 for effective handling of
transfer lengths that are not doubleword multiples
0
Complete DMA Cycle with Transfer Size Less
Than FIFO Size
0 Enabled...................................................default
1 Disabled
Preliminary Revision 0.8 October 29, 1999
Offset 61-60 - Primary Sector Size .................................. RW
........................................always reads 0
15-12 Reserved
11-0 Number of Bytes Per Sector ...def=200h (512 bytes)
Offset 69-68 - Secondary Sector Size .............................. RW
........................................always reads 0
15-12 Reserved
11-0 Number of Bytes Per Sector ...def=200h (512 bytes)
-74-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 70 – Primary IDE Status ....................................... RW
7
Interrupt Status
6
Prefetch Buffer Status
5
Post Write Buffer Status
4
DMA Read Prefetch Status
3
DMA Write Prefetch Status
2
S/G Operation Complete
........................................ always reads 0
1-0 Reserved
Offset 78 – Secondary IDE Status ................................... RW
7
Interrupt Status
6
Prefetch Buffer Status
5
Post Write Buffer Status
4
DMA Read Prefetch Status
3
DMA Write Prefetch Status
2
S/G Operation Complete
........................................always reads 0
1-0 Reserved
Offset 71 – Primary Interrupt Control............................ RW
........................................ always reads 0
7-1 Reserved
0
Flush FIFO Before Generating IDE Interrupt
0 Disable ...................................................default
1 Enable
Offset 79 - Secondary Interrupt Control ........................ RW
........................................always reads 0
7-1 Reserved
0
Flush FIFO Before Generating IDE Interrupt
0 Disable................................................... default
1 Enable
Preliminary Revision 0.8 October 29, 1999
-75-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 83-80 – Primary S/G Descriptor Address ............ RW
Offset 8B-88 – Secondary S/G Descriptor Address ........ RW
Offset C3-C0 – PCI PM Block 1 .......................................RO
31-0 PCI PM Block 1.......................... always reads 0201h
Offset C7-C4 – PCI PM Block 2 .......................................RO
........................................ always reads 0
31-2 Reserved
1-0 Power State
00 On
.....................................................default
01 Off
1x -reserved-
IDE I/O Registers
These registers are compliant with the SFF 8038I v1.0
standard. Refer to the SFF 8038I v1.0 specification for further
details.
I/O Offset 0 - Primary Channel Command
I/O Offset 2 - Primary Channel Status
I/O Offset 4-7 - Primary Channel PRD Table Address
I/O Offset 8 - Secondary Channel Command
I/O Offset A - Secondary Channel Status
I/O Offset C-F - Secondary Channel PRD Table Address
Preliminary Revision 0.8 October 29, 1999
-76-
Function 1 Registers - Enhanced IDE Controller
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 2 Registers - USB Controller Ports 0-1
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 2 PCI configuration space of the
VT8231. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 0-1 (see function 3 for ports 2-3).
Offset 8 - Revision ID (nnh) .............................................. RO
7-0 Silicon Revision Code (0 indicates first silicon)
06h Corresponds to Chip Revision D
Offset 9 - Programming Interface (00h) .......................... RO
Offset A - Sub Class Code (03h=USB Controller) .......... RO
Offset B - Base Class Code (0Ch=Serial Bus Controller)RO
Offset C – Cache Line Size (00h) ...................................... RO
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
0-7 Vendor ID ................. (1106h = VIA Technologies)
Offset 3-2 - Device ID .........................................................RO
0-7 Device ID (3038h = VT8231 USB Controller)
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-8 Reserved
7
Address Stepping ...................... default=0 (disabled)
6
Reserved (parity error response) ..................fixed at 0
5
Reserved (VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate . default=0 (disabled)
3
Reserved (special cycle monitoring) ............fixed at 0
2
Bus Master ............................... default=0 (disabled)
1
Memory Space........................... default=0 (disabled)
0
I/O Space ............................... default=0 (disabled)
Offset 7-6 - Status ........................................................... RWC
15 Reserved (detected parity error).......... always reads 0
14 Signalled System Error.............................. default=0
13 Received Master Abort.............................. default=0
12 Received Target Abort .............................. default=0
11 Signalled Target Abort .............................. default=0
10-9 DEVSEL# Timing
00 Fast
01 Medium ......................................default (fixed)
10 Slow
11 Reserved
........................................ always reads 0
8-0 Reserved
Offset D - Latency Timer ................................................. RW
7-0 Timer Value .......................................... default = 16h
Offset E - Header Type (00h)............................................ RO
Offset F - BIST (00h) ......................................................... RO
Offset 23-20 - USB I/O Register Base Address............... RW
........................................always reads 0
31-16 Reserved
15-5 USB I/O Register Base Address. Port Address for
the base of the 32-byte USB I/O Register block,
corresponding to AD[15:5]
4-0 00001b
Offset 3C - Interrupt Line (00h) ...................................... RW
........................................always reads 0
7-4 Reserved
3-0 USB Interrupt Routing ........................ default = 16h
0000 Disabled................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
Offset 3D - Interrupt Pin (04h) ......................................... RO
Preliminary Revision 0.8 October 29, 1999
-77-
Function 2 Registers - USB Controller Ports 0-1
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
USB-Specific Configuration Registers
Offset 40 - Miscellaneous Control 1 ................................. RW
7
PCI Memory Command Option
0 Support Memory-Read-Line, Memory-ReadMultiple, & Memory-Write-&-Invalidate.... def
1 Only support Mem Read, Mem Write Cmds
6
Babble Option
0 Automatically disable babbled port when EOF
babble occurs..........................................default
1 Don’t disable babbled port
5
PCI Parity Check Option
0 Disable PERR# generation.....................default
1 Enable parity check and PERR# generation
4
Frame Interval Select
0 1 ms frame..............................................default
1 0.1 ms frame
3
USB Data Length Option
0 Support TD length up to 1280................default
1 Support TD length up to 1023
2
USB Power Management
0 Disable USB power management...........default
1 Enable USB power management
1
DMA Option
0 8 DW burst access with better FIFO latency def
1 16 DW burst access (original performance)
0
PCI Wait States
0 Zero wait ................................................default
1 One wait
Preliminary Revision 0.8 October 29, 1999
Offset 41 - Miscellaneous Control 2 ................................ RW
7
USB 1.1 Improvement for EOP
0 USB Specification 1.1 Compliant.......... default
If a bit stuffing error occurs before EOP, the
receiver will accept the packet
1 USB Specification 1.0 Compliant
If a bit stuffing error occurs before EOP, the
receiver will ignore the packet
6-5 Reserved (Do Not Program) ....................default = 0
4
Hold PCI Request for Successive Accesses
0 Disable
1 Enable .................................................... default
Setting this bit to “enable” causes the system to treat
the USB request as higher priority
3
Frame Counter Test Mode
0 Disable................................................... default
1 Enable
2
Trap Option
0 Set trap 60/64 status bits only when trap 60/64
enable bits are set. ................................. default
1 Set trap 60/64 status bits without checking
enable bits
1
A20gate Pass Through Option
0 Pass through A20GATE command sequence
defined in UHCI .................................... default
1 Don’t pass through Write I/O port 64 (ff)
0
USB IRQ Test Mode
0 Normal Operation .................................. default
1 Generate USB IRQ
-78-
Function 2 Registers - USB Controller Ports 0-1
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 42 - FIFO Control .................................................. RW
........................................ always reads 0
7-4 Reserved
3-2 Reserved (Do Not Program).................... default = 0
1-0 Release Continuous REQ After “N” PCICLKs
00 Do Not Release ........................................... def
01 N = 32 PCICLKs
10 N = 64 PCICLKs
11 N = 96 PCICLKs
USB I/O Registers
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
I/O Offset 1-0 - USB Command
I/O Offset 3-2 - USB Status
I/O Offset 5-4 - USB Interrupt Enable
Offset 60 - Serial Bus Release Number .............................RO
7-0 Release Number.............................. always reads 10h
I/O Offset 7-6 - Frame Number
I/O Offset B-8 - Frame List Base Address
I/O Offset 0C - Start Of Frame Modify
Offset 83-80 – PM Capability ............................................RO
31-0 PM Capability .................... always reads 00020001h
Offset 84 – PM Capability Status .................................... RW
7-0 PM Capability Status........................... default = 00h
Supports 00h (Off) and 11h (On) only
I/O Offset 11-10 - Port 0 Status / Control
I/O Offset 13-12 - Port 1 Status / Control
Offset C1-C0 - Legacy Support .........................................RO
15-0 UHCI v1.1 Compliant ................ always reads 2000h
Preliminary Revision 0.8 October 29, 1999
-79-
Function 2 Registers - USB Controller Ports 0-1
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 3 Registers - USB Controller Ports 2-3
Offset 8 - Revision ID (nnh) .............................................. RO
7-0 Silicon Revision Code (0 indicates first silicon)
This Universal Serial Bus host controller interface is fully
compatible with UHCI specification v1.1. There are two sets
of software accessible registers: PCI configuration registers
and USB I/O registers. The PCI configuration registers are
located in the function 3 PCI configuration space of the
VT8231. The USB I/O registers are defined in UHCI
specification v1.1. The registers in this function control USB
ports 2-3 (see function 2 for ports 0-1).
Offset A - Sub Class Code (03h=USB Controller) .......... RO
PCI Configuration Space Header
Offset D - Latency Timer ................................................. RW
7-0 Timer Value .......................................... default = 16h
Offset 1-0 - Vendor ID .......................................................RO
0-7 Vendor ID ................. (1106h = VIA Technologies)
Offset E - Header Type (00h)............................................ RO
Offset 3-2 - Device ID .........................................................RO
0-7 Device ID (3038h = VT8231 USB Controller)
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-8 Reserved
7
Address Stepping ...................... default=0 (disabled)
6
Reserved (parity error response) ..................fixed at 0
5
Reserved (VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate . default=0 (disabled)
3
Reserved (special cycle monitoring) ............fixed at 0
2
Bus Master ............................... default=0 (disabled)
1
Memory Space........................... default=0 (disabled)
0
I/O Space ............................... default=0 (disabled)
Offset 7-6 - Status ........................................................... RWC
15 Reserved (detected parity error).......... always reads 0
14 Signalled System Error.............................. default=0
13 Received Master Abort.............................. default=0
12 Received Target Abort .............................. default=0
11 Signalled Target Abort .............................. default=0
10-9 DEVSEL# Timing
00 Fast
01 Medium ......................................default (fixed)
10 Slow
11 Reserved
........................................ always reads 0
8-0 Reserved
Offset 9 - Programming Interface (00h) .......................... RO
Offset B - Base Class Code (0Ch=Serial Bus Controller)RO
Offset C – Cache Line Size (00h) ...................................... RO
Offset F - BIST (00h) ......................................................... RO
Offset 23-20 - USB I/O Register Base Address............... RW
........................................always reads 0
31-16 Reserved
15-5 USB I/O Register Base Address. Port Address for
the base of the 32-byte USB I/O Register block,
corresponding to AD[15:5]
4-0 00001b
Offset 3C - Interrupt Line (00h) ...................................... RW
........................................always reads 0
7-4 Reserved
3-0 USB Interrupt Routing ........................ default = 16h
0000 Disabled................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
Offset 3D - Interrupt Pin (04h) ......................................... RO
Preliminary Revision 0.8 October 29, 1999
-80-
Function 3 Registers - USB Controller Ports 2-3
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
USB-Specific Configuration Registers
Offset 40 - Miscellaneous Control 1 ................................. RW
7
PCI Memory Command Option
0 Support Memory-Read-Line, Memory-ReadMultiple, & Memory-Write-&-Invalidate.... def
1 Only support Mem Read, Mem Write Cmds
6
Babble Option
0 Automatically disable babbled port when EOF
babble occurs..........................................default
1 Don’t disable babbled port
5
PCI Parity Check Option
0 Disable PERR# generation.....................default
1 Enable parity check and PERR# generation
4
Frame Interval Select
0 1 ms frame..............................................default
1 0.1 ms frame
3
USB Data Length Option
0 Support TD length up to 1280................default
1 Support TD length up to 1023
2
USB Power Management
0 Disable USB power management...........default
1 Enable USB power management
1
DMA Option
0 8 DW burst access with better FIFO latency def
1 16 DW burst access (original performance)
0
PCI Wait States
0 Zero wait ................................................default
1 One wait
Preliminary Revision 0.8 October 29, 1999
Offset 41 - Miscellaneous Control 2 ................................ RW
7
USB 1.1 Improvement for EOP
0 USB Specification 1.1 Compliant.......... default
If a bit stuffing error occurs before EOP, the
receiver will accept the packet
1 USB Specification 1.0 Compliant
If a bit stuffing error occurs before EOP, the
receiver will ignore the packet
6-5 Reserved (Do Not Program) ....................default = 0
4
Hold PCI Request for Successive Accesses
0 Disable
1 Enable .................................................... default
Setting this bit to “enable” causes the system to treat
the USB request as higher priority
3
Frame Counter Test Mode
0 Disable................................................... default
1 Enable
2
Trap Option
0 Set trap 60/64 status bits only when trap 60/64
enable bits are set. ................................. default
1 Set trap 60/64 status bits without checking
enable bits
1
A20gate Pass Through Option
0 Pass through A20GATE command sequence
defined in UHCI .................................... default
1 Don’t pass through Write I/O port 64 (ff)
0
USB IRQ Test Mode
0 Normal Operation .................................. default
1 Generate USB IRQ
-81-
Function 3 Registers - USB Controller Ports 2-3
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 42 - FIFO Control .................................................. RW
........................................ always reads 0
7-4 Reserved
3-2 Reserved (Do Not Program).................... default = 0
1-0 Release Continuous REQ After “N” PCICLKs
00 Do Not Release ........................................... def
01 N = 32 PCICLKs
10 N = 64 PCICLKs
11 N = 96 PCICLKs
USB I/O Registers
These registers are compliant with the UHCI v1.1 standard.
Refer to the UHCI v1.1 specification for further details.
I/O Offset 1-0 - USB Command
I/O Offset 3-2 - USB Status
I/O Offset 5-4 - USB Interrupt Enable
Offset 60 - Serial Bus Release Number .............................RO
7-0 Release Number.............................. always reads 10h
I/O Offset 7-6 - Frame Number
I/O Offset B-8 - Frame List Base Address
I/O Offset 0C - Start Of Frame Modify
Offset 83-80 – PM Capability ............................................RO
31-0 PM Capability .................... always reads 00020001h
Offset 84 – PM Capability Status .................................... RW
7-0 PM Capability Status.......supports 00h and 11h only
I/O Offset 11-10 - Port 0 Status / Control
I/O Offset 13-12 - Port 1 Status / Control
Offset C1-C0 - Legacy Support .........................................RO
15-0 UHCI v1.1 Compliant ................ always reads 2000h
Preliminary Revision 0.8 October 29, 1999
-82-
Function 3 Registers - USB Controller Ports 2-3
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 4 Regs - Power Management, SMBus and HWM
This section describes the ACPI (Advanced Configuration and
Power Interface) Power Management system of the VT8231
which includes a System Management Bus (SMBus) interface
controller and Hardware Monitoring (HWM) subsystem. The
power management system of the VT8231 supports both ACPI
and legacy power management functions and is compatible
with the APM v1.2 and ACPI v1.0 specifications.
PCI Configuration Space Header
Offset 1-0 - Vendor ID .......................................................RO
0-7 Vendor ID ................. (1106h = VIA Technologies)
Offset 3-2 - Device ID .........................................................RO
0-7 Device ID ................ (3057h = ACPI Power Mgmt)
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-8 Reserved
7
Address Stepping ........................................fixed at 0
6
Reserved (parity error response) ..................fixed at 0
5
Reserved (VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate ...................fixed at 0
3
Reserved (special cycle monitoring) ............fixed at 0
2
Bus Master .................................................fixed at 0
1
Memory Space.............................................fixed at 0
0
I/O Space .................................................fixed at 0
Offset 7-6 - Status ........................................................... RWC
15 Detected Parity Error ........................ always reads 0
14 Signalled System Error...................... always reads 0
13 Received Master Abort...................... always reads 0
12 Received Target Abort ...................... always reads 0
11 Signalled Target Abort ...................... always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .....................................default (fixed)
10 Slow
11 Reserved
8
Data Parity Detected.......................... always reads 0
7
Fast Back to Back Capable ............... always reads 1
........................................ always reads 0
6-0 Reserved
Preliminary Revision 0.8 October 29, 1999
Offset 8 - Revision ID (nnh) .............................................. RO
7-0 Silicon Revision Code
Offset 9 - Programming Interface (00h) .......................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 61h.
Offset A - Sub Class Code (00h) ....................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 62h.
Offset B - Base Class Code (00h) ...................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 4 offset 63h.
Offset 0D - Latency Timer ............................................... RW
7-0 Timer Value ..............................................default = 0
Offset 0E - Header Type (00h).......................................... RO
-83-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Power Management-Specific PCI Configuration Registers
Offset 40 – General Configuration 0 ............................... RW
7
Thermal Alarm Source Select
0 From pin T11 (Function 0 Rx74[1] must be set
to define the pin as THRM#)..................default
1 From any of the three internal temperature
sensing circuits (see Rx43 and Rx44 of
Hardware Monitoring configuration space)
6
Sleep Button
0 Disable ...................................................default
1 Sleep Button is on IRQ6 pin (pin G1)
5
Debounce LID and PWRBTN# Inputs for 200us
0 Disable ...................................................default
1 Enable
........................................ always reads 0
4
Reserved
3
Microsoft Sound Monitor in Audio Access
0 Disable ...................................................default
1 Enable
2
Game Port Monitor in Audio Access
0 Disable ...................................................default
1 Enable
1
SoundBlaster Monitor in Audio Access
0 Disable ...................................................default
1 Enable
0
MIDI Monitor in Audio Access
0 Disable ...................................................default
1 Enable
Preliminary Revision 0.8 October 29, 1999
Offset 41 - General Configuration 1................................ RW
7
I/O Enable for ACPI I/O Base
0 Disable access to ACPI I/O block.......... default
1 Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block). The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
6
ACPI Timer Reset
0 Normal Timer Operation ....................... default
1 Reset Timer
5-4 PMU Timer Test Mode (Do Not Program) ....def = 0
3
ACPI Timer Count Select
0 24-bit Timer........................................... default
1 32-bit Timer
2
RTC Enable Signal Gated with PSON (SUSC#) in
Soft-Off Mode
0 Disable................................................... default
1 Enable
1
Clock Throttling Clock Selection
0 32 usec (512 usec cycle time) ................ default
1 1 msec (16 msec cycle time)
0
DEVSEL# Test Mode (Do Not Program).......def = 0
-84-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 42 - ACPI Interrupt Select .................................... RW
7
ATX / AT Power Indicator.................................. RO
0 ATX
1 AT
6
SUSC# State.......................................................... RO
........................................ always reads 0
5
Reserved
4
SUSC# AC-Power-On Default Value ................. RO
This bit is written at RTC Index 0A bit-7.
3-0 SCI Interrupt Assignment
0000 Disabled .................................................default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 IRQ15
Offset 43 – Internal Timer Read Test ...............................RO
7-0 Internal Timer Read Test
Preliminary Revision 0.8 October 29, 1999
Offset 45-44 - Primary Interrupt Channel (0000h) ....... RW
15 1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel
14 1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel
13 1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel
12 1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel
11 1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel
10 1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel
9
1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel
8
1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel
7
1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel
6
1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel
5
1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel
4
1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel
3
1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel
........................................always reads 0
2
Reserved
1
1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel
0
1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel
Offset 47-46 - Secondary Interrupt Channel (0000h) .... RW
15 1/0 = Ena/Disa IRQ15 as Secondary Intr Channel
14 1/0 = Ena/Disa IRQ14 as Secondary Intr Channel
13 1/0 = Ena/Disa IRQ13 as Secondary Intr Channel
12 1/0 = Ena/Disa IRQ12 as Secondary Intr Channel
11 1/0 = Ena/Disa IRQ11 as Secondary Intr Channel
10 1/0 = Ena/Disa IRQ10 as Secondary Intr Channel
9
1/0 = Ena/Disa IRQ9 as Secondary Intr Channel
8
1/0 = Ena/Disa IRQ8 as Secondary Intr Channel
7
1/0 = Ena/Disa IRQ7 as Secondary Intr Channel
6
1/0 = Ena/Disa IRQ6 as Secondary Intr Channel
5
1/0 = Ena/Disa IRQ5 as Secondary Intr Channel
4
1/0 = Ena/Disa IRQ4 as Secondary Intr Channel
3
1/0 = Ena/Disa IRQ3 as Secondary Intr Channel
........................................always reads 0
2
Reserved
1
1/0 = Ena/Disa IRQ1 as Secondary Intr Channel
0
1/0 = Ena/Disa IRQ0 as Secondary Intr Channel
-85-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 4B-48 – Power Management I/O Base ................. RW
........................................ always reads 0
31-16 Reserved
15-7 Power Management I/O Register Base Address.
Port Address for the base of the 128-byte Power
Management I/O Register block, corresponding to
AD[15:7]. The "I/O Space" bit at offset 41 bit-7
enables access to this register block. The definitions
of the registers in the Power Management I/O
Register Block are included later in this document,
following the Power-Management-Specific PCI
Configuration register descriptions and the Power
Management Subsystem overview.
6-0 0000001b
Offset 4C – Host Bus Power Management Control........ RW
7-4 Thermal Duty Cycle (THM_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the THRM# pin is asserted
low. The field is decoded as follows:
0000 Reserved.................................................default
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%
3
THRM Enable
0 Disable ...................................................default
1 Enable
2
Frame Input as Resume Event in C3
0 Disable ...................................................default
1 Enable
........................................ always reads 0
1
Reserved
0
CPU Stop Grant Cycle Select
0 From Halt and Stop Grant Cycle ............default
1 From Stop Grant Cycle
This bit is combined with I/O space Rx2C[3] for
controlling the start of CPUSTP# assertion during
system suspend mode:
Rx2C[3]
Rx4C[0]
Function 4 Function 4
I/O Space Cfg Space
CPUSTP# Assertion
0
x
Immediate
1
0
Wait for CPU Halt
/ Stop Grant cycle
1
1
Wait for CPU
Stop Grant cycle
Preliminary Revision 0.8 October 29, 1999
Offset 4D – Throttle / Clock Stop Control ...................... RW
7
Throttle Timer Reset ......................................def = 0
6-5 Throttle Timer
0x 4-Bit .................................................... default
10 3-Bit
11 2-Bit
4
Fast Clock (7.5us) as Throttle Timer Tick
0 Disable................................................... default
1 Enable
........................................always reads 0
3
Reserved
2
Internal Clock Stop for PCI Idle
0 Disable................................................... default
1 Enable
1
Internal Clock Stop During C3
0 Disable................................................... default
1 Enable
0
Internal Clock Stop During Suspend
0 Disable................................................... default
1 Enable
-86-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
3
Offset 53-50 - GP Timer Control (0000 0000h) .............. RW
31-30 Conserve Mode Timer Count Value
00 1/16 second ............................................default
01 1/8 second
10 1 second
11 1 minute
29 Conserve Mode Status
This bit reads 1 when in Conserve Mode
28 Conserve Mode Enable
0 Disable ...................................................default
1 Enable
27-26 Secondary Event Timer Count Value
00 2 milliseconds.........................................default
01 64 milliseconds
10 ½ second
11 by EOI + 0.25 milliseconds
25 Secondary Event Occurred Status
This bit reads 1 to indicate that a secondary event has
occurred (to resume the system from suspend) and the
secondary event timer is counting down.
24 Secondary Event Timer Enable
0 Disable ...................................................default
1 Enable
2
1-0
GP0 Timer Start
On setting this bit to 1, the GP0 timer loads the value
defined by bits 15-8 of this register and starts
counting down. The GP0 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP Timer Reload Enable Register (Power
Management I/O Space Offset 38h). If no such event
occurs and the GP0 timer counts down to zero, then
the GP0 Timer Timeout Status bit is set to one (bit-2
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP0 Timer Timeout Enable bit is set (bit-2 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
GP0 Timer Automatic Reload
0 GP0 Timer stops at 0 ............................ default
1 Reload GP0 timer automatically after counting
down to 0
GP0 Timer Base
00 Disable................................................... default
01 1/16 second
10 1 second
11 1 minute
23-16 GP1 Timer Count Value (base defined by bits 5-4)
Write to load count value; Read to get current count
15-8 GP0 Timer Count Value (base defined by bits 1-0)
Write to load count value; Read to get current count
7
6
5-4
GP1 Timer Start
On setting this bit to 1, the GP1 timer loads the value
defined by bits 23-16 of this register and starts
counting down. The GP1 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP Timer Reload Enable Register (Power
Management I/O Space Offset 38h). If no such event
occurs and the GP1 timer counts down to zero, then
the GP1 Timer Timeout Status bit is set to one (bit-3
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP1 Timer Timeout Enable bit is set (bit-3 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
GP1 Timer Automatic Reload
0 GP1 Timer stops at 0 .............................default
1 Reload GP1 timer automatically after counting
down to 0
GP1 Timer Base
00 Disable ...................................................default
01 1/4 msec
10 1 second
11 1 minute
Preliminary Revision 0.8 October 29, 1999
-87-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 54 – Power Well Control ...................................... WO
7
SMBus Clock Select
0 SMBus Clock from 14.31818 MHz Divider def
1 SMBus Clock from RTC 32.768 KHz
6
STR Power Well Output Gating
0 Disable ...................................................default
1 Enable
5
SUSC# = 0 for STR
0 Disable ...................................................default
1 Enable
4
SUSST1# / GPO3 Select (Pin V10)
0 SUSST1#................................................default
1 GPO3
3
GPO2 / SUSB# Select (Pin W9)
0 SUSB#....................................................default
1 GPO2
Before chip rev C, these definitions were reversed
2
GPO1 / SUSA# Select (Pin V9)
0 SUSA# ...................................................default
1 GPO1
Before chip rev C, these definitions were reversed
1-0 GPO0 (SLOWCLK) Output Selection (Pin T8)
00 From GPO0 (PMU I/O Rx4C[0])...........default
01 1 Hz
10 4 Hz
11 16 Hz
Preliminary Revision 0.8 October 29, 1999
Offset 55 – USB Wakeup.................................................. RW
........................................always reads 0
7-1 Reserved
0
USB Wakeup for STR/STD/Soff
0 Disable................................................... default
1 Enable
-88-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 58 – GP2 / GP3 Timer Control ............................. RW
7
GP3 Timer Start
On setting this bit to 1, the GP3 timer loads the value
defined by Rx5A and starts counting down. The GP3
timer is reloaded at the occurrence of certain events
enabled in the GP Timer Reload Enable Register
(Power Management I/O Space Offset 38h). If no
such event occurs and the GP3 timer counts down to
zero, then the GP3 Timer Timeout Status bit is set to
one (bit-13 of the Global Status register at Power
Management Register I/O Space Offset 28h).
Additionally, if the GP3 Timer Timeout Enable bit is
set (bit-13 of the Global Enable register at Power
Management Register I/O Space Offset 2Ah), then an
SMI is generated.
6
GP3 Timer Automatic Reload
0 GP3 Timer stops at 0 .............................default
1 Reload GP3 timer automatically after counting
down to 0
5-4 GP3 Timer Tick Select
00 Disable ...................................................default
01 1/4 millisecond
10 1 second
11 1 minute
3
2
1-0
Offset 59 – GP2 Timer ...................................................... RW
7
Write: GP2 Timer Load Value...............default = 0
Read: GP2 Timer Current Count
Offset 5A – GP3 Timer ..................................................... RW
7
Write: GP3 Timer Load Value...............default = 0
Read: GP3 Timer Current Count
GP2 Timer Start
On setting this bit to 1, the GP2 timer loads the value
defined by Rx59 and starts counting down. The GP2
timer is reloaded at the occurrence of certain events
enabled in the GP Timer Reload Enable Register
(Power Management I/O Space Offset 38h). If no
such event occurs and the GP2 timer counts down to
zero, then the GP2 Timer Timeout Status bit is set to
one (bit-12 of the Global Status register at Power
Management Register I/O Space Offset 28h).
Additionally, if the GP2 Timer Timeout Enable bit is
set (bit-12 of the Global Enable register at Power
Management Register I/O Space Offset 2Ah), then an
SMI is generated.
GP2 Timer Automatic Reload
0 GP2 Timer stops at 0 .............................default
1 Reload GP2 timer automatically after counting
down to 0
GP2 Timer Tick Select
00 Disable ...................................................default
01 1/16 second
10 1 second
11 1 minute
Preliminary Revision 0.8 October 29, 1999
-89-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 61 – Program Interface Read Value .................... WO
7-0 Rx09 Read Value
The value returned by the register at offset 9h (Programming
Interface) may be changed by writing the desired value to this
location.
Offset 62 - Sub Class Read Value.................................... WO
7-0 Rx0A Read Value
The value returned by the register at offset 0Ah (Sub Class
Code) may be changed by writing the desired value to this
location.
Offset 63 - Base Class Read Value .................................. WO
7-0 Rx0B Read Value
The value returned by the register at offset 0Bh (Base Class
Code) may be changed by writing the desired value to this
location.
Preliminary Revision 0.8 October 29, 1999
-90-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Hardware-Monitor-Specific Configuration Registers
System Management Bus-Specific Configuration Registers
Offset 71-70 – Hardware Monitor I/O Base ................... RW
15-7 I/O Base (128-byte I/O space) ................. default = 0
.......................... always reads 0000001b
6-0 Fixed
Offset 93-90 – SMBus I/O Base ....................................... RW
........................................always reads 0
31-16 Reserved
15-4 I/O Base (16-byte I/O space)................ default = 00h
................................ always reads 0001b
3-0 Fixed
Offset 74 –Hardware Monitor Control ........................... RW
........................................ always reads 0
7-4 Reserved
3
Hardware Monitoring Interrupt
0 SMI .....................................................default
1 SCI
........................................ always reads 0
2-1 Reserved
0
Hardware Monitoring I/O Enable
0 Disable hardware monitor functions.......default
1 Enable hardware monitor functions
Offset D2 – SMBus Host Configuration ......................... RW
........................................always reads 0
7-4 Reserved
3
SMBus Interrupt Select
0 SMI .................................................... default
1 SCI
........................................always reads 0
2
Reserved
1
SMBus IRQ
0 Disable................................................... default
1 Enable
0
SMBus Host Controller Enable
0 Disable SMB controller functions ......... default
1 Enable SMB controller functions
Offset D3 – SMBus Host Slave Command ...................... RW
7-0 SMBus Host Slave Command Code..........default=0
Offset D4 – SMBus Slave Address for Port 1 ................. RW
7-0 SMBus Slave Address for Port 1...............default=0
Bit-0 must be set to 0 for proper operation
Offset D5 – SMBus Slave Address for Port 2 ................. RW
7-0 SMBus Slave Address for Port 2...............default=0
Bit-0 must be set to 0 for proper operation
Offset D6 – SMBus Revision ID ....................................... RO
7-0 SMBus Revision Code
Preliminary Revision 0.8 October 29, 1999
-91-
Function 4 Regs - Power Management, SMBus and HWM
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Power Management I/O-Space Registers
Basic Power Management Control and Status
I/O Offset 1-0 - Power Management Status ................. RWC
The bits in this register are set only by hardware and can be
reset by software by writing a one to the desired bit position.
I/O Offset 3-2 - Power Management Enable .................. RW
The bits in this register correspond to the bits in the Power
Management Status Register at offset 1-0.
Wakeup Status (WAK_STS) ................... default = 0
This bit is set when the system is in the suspend state
and an enabled resume event occurs. Upon setting
this bit, the system automatically transitions from the
suspend state to the normal working state (from C3 to
C0 for the processor).
........................................ always reads 0
14-12 Reserved
11 Abnormal Power-Off (APO_STS)........... default = 0
10 RTC Status (RTC_STS) ........................... default = 0
This bit is set when the RTC generates an alarm (on
assertion of the RTC IRQ signal).
15
9
8
7-6
5
4
3-1
0
15
........................................always reads 0
........................................always reads 0
14-12 Reserved
........................................always reads 0
11 Reserved
10 RTC Enable (RTC_EN)............................default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the RTC_STS bit is set.
9
Sleep Button Enable (SB_EN) .................default = 0
This bit may be set to trigger either an SCI or SMI
when the SB_STS bit is set.
8
Power Button Enable (PB_EN) ...............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the PB_STS bit is set.
Sleep Button Status (SB_STS)................. default = 0
This bit is set when the sleep button (SLPBTN# /
IRQ6 / GPI4) is pressed.
Power Button Status (PB_STS)............... default = 0
This bit is set when the PWRBTN# signal is asserted
LOW. If the PWRBTN# signal is held LOW for
more than four seconds, this bit is cleared, the
PBOR_STS bit is set, and the system will transition
into the soft off state.
........................................ always reads 0
Reserved
Global Status (GBL_STS)........................ default = 0
This bit is set by hardware when BIOS_RLS is set
(typically by an SMI routine to release control of the
SCI/SMI lock). When this bit is cleared by software
(by writing a one to this bit position) the BIOS_RLS
bit is also cleared at the same time by hardware.
Bus Master Status (BM_STS) ................. default = 0
This bit is set when a system bus master requests the
system bus. All PCI master, ISA master and ISA
DMA devices are included.
........................................ always reads 0
Reserved
ACPI Timer Carry Status (TMR_STS) .. default = 0
The bit is set when the 23rd (31st) bit of the 24 (32)
bit ACPI power management timer changes.
Preliminary Revision 0.8 October 29, 1999
Reserved
7-6
5
4
3-1
0
-92-
........................................always reads 0
Reserved
Global Enable (GBL_EN).........................default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the GBL_STS bit is set.
Reserved
........................................always reads 0
........................................always reads 0
Reserved
ACPI Timer Enable (TMR_EN) ..............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the TMR_STS bit is set.
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 5-4 - Power Management Control ................. RW
15 Soft Resume
........................................ always reads 0
14 Reserved
13 Sleep Enable (SLP_EN)...................... always reads 0
This is a write-only bit; reads from this bit always
return zero. Writing a one to this bit causes the
system to sequence into the sleep (suspend) state
defined by the SLP_TYP field.
12-10 Sleep Type (SLP_TYP)
000 Normal On
001 Suspend to RAM (STR)
010 Suspend to Disk (STD) (also called Soft Off).
The VCC power plane is turned off while the
VCCS and VBAT planes remain on.
011 Reserved
100 Power On Suspend without Reset
101 Power On Suspend with CPU Reset
110 Power On Suspend with CPU/PCI Reset
111 Reserved
In any sleep state, there is minimal interface between
powered and non-powered planes so that the effort
for hardware design may be well managed.
........................................ always reads 0
9-3 Reserved
2
Global Release (GBL_RLS) ............ WO, default = 0
This bit is set by ACPI software to indicate the
release of the SCI / SMI lock. Upon setting of this
bit, the hardware automatically sets the BIOS_STS
bit. The bit is cleared by hardware when the
BIOS_STS bit is cleared by software. Note that the
setting of this bit will cause an SMI to be generated if
the BIOS_EN bit is set (bit-5 of the Global Enable
register at offset 2Ah).
1
Bus Master Reload (BMS_RLD)
0 Bus master requests are ignored by power
management logic...................................default
1 Bus master requests transition the processor
from the C3 state to the C0 state
0
SCI Enable (SCI_EN)
Selects the power management event to generate
either an SCI or SMI:
0 Generate SCI ..........................................default
1 Generate SMI
Note that certain power management events can be
programmed individually to generate an SCI or SMI
independent of the setting of this bit (refer to the
General Purpose SCI Enable and General Purpose
SMI Enable registers at offsets 22 and 24). Also,
TMR_STS & GBL_STS always generate SCI and
BIOS_STS always generates SMI.
Preliminary Revision 0.8 October 29, 1999
I/O Offset 0B-08 - Power Management Timer ............... RW
31-24 Extended Timer Value (ETM_VAL)
This field reads back 0 if the 24-bit timer option is
selected (Rx41 bit-3).
23-0 Timer Value (TMR_VAL)
This read-only field returns the running count of the
power management timer. This is a 24/32-bit counter
that runs off a 3.579545 MHz clock, and counts while
in the S0 (working) system state. The timer is reset to
an initial value of zero during a reset, and then
continues counting until the 14.31818 MHz input to
the chip is stopped. If the clock is restarted without a
reset, then the counter will continue counting from
where it stopped.
-93-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Processor Power Management Registers
I/O Offset 13-10 - Processor & PCI Bus Control............ RW
........................................ always reads 0
31-12 Reserved
11 PCI Stop (PCISTP# asserted) when PCKRUN# is
Deasserted (PCI_STP)
0 Enable.....................................................default
1 Disable
10 PCI Bus Clock Run Without Stop (PCI_RUN)
0 PCKRUN# will be de-activated after the PCI
bus is idle for 26 clocks..........................default
1 PCKRUN# is always asserted
9
Host Clock Stop Enable (HOST_STP)
0 STPCLK# will be asserted in the C3 state, but
the CPU clock is not stopped .................default
1 CPU clock is stopped in the C3 state
8
Assert SLP# for Processor Level 3 Read
0 Disable ...................................................default
1 Enable
Used in Slot-1 systems only.
........................................ always reads 0
7-5 Reserved
4
Throttling Enable (THT_EN)
Setting this bit starts clock throttling (modulating the
STPCLK# signal) regardless of the CPU state. The
throttling duty cycle is determined by bits 3-0 of this
register.
3-0 Throttling Duty Cycle (THT_DTY)
This 4-bit field determines the duty cycle of the
STPCLK# signal when the system is in throttling
mode (the "Throttling Enable" bit is set to one). The
duty cycle indicates the percentage of time the
STPCLK# signal is asserted while the Throttling
Enable bit is set. The field is decoded as follows:
0000 Reserved
0001 0-6.25%
0010 6.25-12.50%
0011 18.75-25.00%
0100 31.25-37.50%
0101 37.50-43.75%
0110 43.75-50.00%
0111 50.00-56.25%
1000 56.25-62.50%
1001 62.50-68.75%
1010 68.75-75.00%
1011 75.00-87.50%
1100 75.00-81.25%
1101 81.25-87.50%
1110 87.50-93.75%
1111 93.75-100%
Preliminary Revision 0.8 October 29, 1999
I/O Offset 14 - Processor Level 2 ...................................... RO
........................................always reads 0
7-0 Level 2
Reads from this register put the processor into the
Stop Grant state (the VT8231 asserts STPCLK# to
suspend the processor). Wake up from Stop Grant
state is by interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.
I/O Offset 15 - Processor Level 3 ...................................... RO
........................................always reads 0
7-0 Level 3
Reads from this register put the processor in the C3
clock state with the STPCLK# signal asserted. If
Rx10[9] = 1 then the CPU clock is also stopped by
asserting CPUSTP#. Wakeup from the C3 state is by
interrupt (INTR, SMI, and SCI).
Reads from this register return all zeros; writes to this register
have no effect.
-94-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
General Purpose Power Management Registers
I/O Offset 21-20 - General Purpose Status (GP_STS). RWC
........................................ always reads 0
15 Reserved
14 USB Wake-Up Status (UWAK_STS)
For STR / STD / Soff
13 AC97 Wake-Up Status (AWAK_STS)
Can be set only in suspend mode
12 Battery Low Status (BL_STS)
This bit is set when the BATLOW# input is asserted
low.
11 Notebook Lid Status (LID_STS)
This bit is set when the LID input detects the edge
selected by Rx2C bit-7 (0=rising, 1=falling).
10 Thermal Detect Status (THRM_STS)
This bit is set when the THRM input detects the edge
selected by Rx2C bit-6 (0=rising, 1=falling).
9
USB Resume Status (USB_STS)
This bit is set when a USB peripheral generates a
resume event.
8
Ring Status (RING_STS)
This bit is set when the RING# input is asserted low.
7
GPI18 Toggle Status (GPI18_STS)
This bit is set when the GPI18 pin is toggled.
6
GPI6 / EXTSMI6 Toggle Status (GPI6_STS)
This bit is set when the GPI6 pin is toggled.
5
GPI5 Toggle Status (GPI5_STS)
This bit is set when the GPI5 pin is toggled.
4
GPI4 / EXTSMI4 Toggle Status (GPI4_STS)
This bit is set when the GPI4 pin is toggled.
3
GPI17 Toggle Status (GPI17_STS)
This bit is set when the GPI17 pin is toggled.
2
GPI16 Toggle Status (GPI16_STS)
This bit is set when the GPI16 pin is toggled.
1
GPI1 Toggle Status (GPI1_STS)
This bit is set when the GPI1 pin is toggled.
0
EXTSMI# Status (EXT_STS)
This bit is set when the EXTSMI# pin is asserted low.
Note that the above bits correspond one for one with the bits
of the General Purpose SCI Enable and General Purpose SMI
Enable registers at offsets 22 and 24: an SCI or SMI is
generated if the corresponding bit of the General Purpose SCI
or SMI Enable registers, respectively, is set to one.
I/O Offset 23-22 - General Purpose SCI Enable ............ RW
........................................always reads 0
15 Reserved
14 Enable SCI on setting of the UWAK_STS bit def=0
13 Enable SCI on setting of the AWAK_STS bit def=0
12 Enable SCI on setting of the BL_STS bit ......def=0
11 Enable SCI on setting of the LID_STS bit .....def=0
10 Enable SCI on setting of the THRM_STS bit def=0
9
Enable SCI on setting of the USB_STS bit ....def=0
8
Enable SCI on setting of the RING_STS bit .def=0
7
Enable SCI on setting of the GPI18_STS bit..def=0
6
Enable SCI on setting of the GPI6_STS bit....def=0
5
Enable SCI on setting of the GPI5_STS bit....def=0
4
Enable SCI on setting of the GPI4_STS bit....def=0
3
Enable SCI on setting of the GPI17_STS bit..def=0
2
Enable SCI on setting of the GPI16_STS bit..def=0
1
Enable SCI on setting of the GPI1_STS bit....def=0
0
Enable SCI on setting of the EXT_STS bit ....def=0
These bits allow generation of an SCI using a separate set of
conditions from those used for generating an SMI.
I/O Offset 25-24 - General Purpose SMI Enable ........... RW
........................................always reads 0
15-14 Reserved
13 Enable SMI on setting of the AWAK_STS bit def=0
12 Enable SMI on setting of the BL_STS bit .....def=0
11 Enable SMI on setting of the LID_STS bit ....def=0
10 Enable SMI on setting of the THRM_STS bit def=0
9
Enable SMI on setting of the USB_STS bit ...def=0
8
Enable SMI on setting of the RING_STS bit def=0
7
Enable SMI on setting of the GPI18_STS bit.def=0
6
Enable SMI on setting of the GPI6_STS bit...def=0
5
Enable SMI on setting of the GPI5_STS bit...def=0
4
Enable SMI on setting of the GPI4_STS bit...def=0
3
Enable SMI on setting of the GPI17_STS bit.def=0
2
Enable SMI on setting of the GPI16_STS bit.def=0
1
Enable SMI on setting of the GPI1_STS bit...def=0
0
Enable SMI on setting of the EXT_STS bit....def=0
These bits allow generation of an SMI using a separate set of
conditions from those used for generating an SCI.
The above bits are set by hardware only and can only be
cleared by writing a one to the desired bit.
Preliminary Revision 0.8 October 29, 1999
-95-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Generic Power Management Registers
I/O Offset 29-28 - Global Status .................................... RWC
15 GPIO Range 1 Access Status (GR1_STS) ...... def=0
14 GPIO Range 0 Access Status (GR0_STS) ...... def=0
13 GP3 Timer Timeout Status (G3TO_STS) ...... def=0
12 GP2 Timer Timeout Status (G2TO_STS) ...... def=0
11 SERIRQ SMI Status (SSMI_STS).................. def=0
........................................ always reads 0
10-9 Reserved
8
PCKRUN# Resume Status (PRRSM_STS).... def=0
This bit is set when PCI bus peripherals wake up the
system by asserting PCKRUN#
7
Primary IRQ Resume Status (PIRSM_STS) . def=0
This bit is set at the occurrence of primary IRQs as
defined in Rx45-44 of PCI configuration space
6
Software SMI Status (SW_SMI_STS)............ def=0
This bit is set when the SMI_CMD port (offset 2F) is
written.
5
BIOS Status (BIOS_STS) ................................ def=0
This bit is set when the GBL_RLS bit is set to one
(typically by the ACPI software to release control of
the SCI/SMI lock). When this bit is reset (by writing
a one to this bit position) the GBL_RLS bit is reset at
the same time by hardware.
4
Legacy USB Status (LEG_USB_STS) ............ def=0
This bit is set when a legacy USB event occurs.
I/O Offset 2B-2A - Global Enable ................................... RW
15 GPIO Range 1 SMI Enable (GR1_EN) ..........def=0
14 GPIO Range 0 SMI Enable (GR0_EN) ..........def=0
13 GP3 Timer Timeout SMI Enable (G3TO_EN)def=0
12 GP2 Timer Timeout SMI Enable (G2TO_EN)def=0
11 SERIRQ SMI Enable (SSMI_EN) ..................def=0
........................................always reads 0
10-9 Reserved
8
PCKRUN# Resume Enable (PRRSM_EN) ....def=0
This bit may be set to trigger an SMI to be generated
when the PRRSM_STS bit is set.
7
Primary IRQ Resume Enable (PIRSM_EN)..def=0
This bit may be set to trigger an SMI to be generated
when the PIRSM_STS bit is set.
6
SMI on Software SMI (SW_SMI_EN) ...........def=0
This bit may be set to trigger an SMI to be generated
when the SW_SMI_STS bit is set.
5
SMI on BIOS Status (BIOS_EN) ....................def=0
This bit may be set to trigger an SMI to be generated
when the BIOS_STS bit is set.
4
3
GP1 Timer Time Out Status (GP1TO_STS).. def=0
This bit is set when the GP1 timer times out.
3
2
GP0 Timer Time Out Status (GP0TO_STS).. def=0
This bit is set when the GP0 timer times out.
2
1
Secondary Event Timer Time Out Status
(STTO_STS) ..................................................... def=0
This bit is set when the secondary event timer times
out.
Primary Activity Status (PACT_STS)............ def=0
This bit is set at the occurrence of any enabled
primary system activity (see the Primary Activity
Detect Status register at offset 30h and the Primary
Activity Detect Enable register at offset 34h). After
checking this bit, software can check the status bits in
the Primary Activity Detect Status register at offset
30h to identify the specific source of the primary
event. Note that setting this bit can be enabled to
reload the GP0 timer (see bit-0 of the GP Timer
Reload Enable register at offset 38).
1
0
0
SMI on Legacy USB (LEG_USB_EN) ............def=0
This bit may be set to trigger an SMI to be generated
when the LEG_USB_STS bit is set.
SMI on GP1 Timer Time Out (GP1TO_EN) .def=0
This bit may be set to trigger an SMI to be generated
when the GP1TO_STS bit is set.
SMI on GP0 Timer Time Out (GP0TO_EN) .def=0
This bit may be set to trigger an SMI to be generated
when the GP0TO_STS bit is set.
SMI on Secondary Event Timer Time Out
(STTO_EN) ......................................................def=0
This bit may be set to trigger an SMI to be generated
when the STTO_STS bit is set.
SMI on Primary Activity (PACT_EN) ...........def=0
This bit may be set to trigger an SMI to be generated
when the PACT_STS bit is set.
Note that SMI can be generated based on the setting of any of
the above bits (see the offset 2Ah Global Enable register bit
descriptions in the right hand column of this page).
The bits in this register are set by hardware only and can only
be cleared by writing a one to the desired bit position.
Preliminary Revision 0.8 October 29, 1999
-96-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 2D-2C - Global Control (GBL_CTL) ............ RW
........................................ always reads 0
15-12 Reserved
11 IDE Secondary Bus Power-Off
0 Disable ...................................................default
1 Enable
10 IDE Primary Bus Power-Off
0 Disable ...................................................default
1 Enable
........................................ always reads 0
9
Reserved
8
SMI Active (INSMI)
0 SMI Inactive...........................................default
1 SMI Active. If the SMIIG bit is set, this bit
needs to be written with a 1 to clear it before
the next SMI can be generated.
7
LID Triggering Polarity
0 Rising Edge ............................................default
1 Falling Edge
6
THRM# Triggering Polarity
0 Rising Edge ............................................default
1 Falling Edge
5
Battery Low Resume Disable
0 Enable resume ........................................default
1 Disable resume from suspend when
BATLOW# is asserted
4
SMI Lock (SMIIG)
0 Disable SMI Lock
1 Enable SMI Lock (SMI low to gate for the
next SMI) ...............................................default
3
Wait for Halt / Stop Grant Cycle for CPUSTP#
Assertion
0 Don’t wait...............................................default
1 Wait
This bit works with Rx4C[7] of PCI configuration
space to control the start of CPUSTP# assertion.
2
Power Button Triggering Select
0 SCI/SMI generated by PWRBTN# rising edge
.....................................................default
1 SCI/SMI generated by PWRBTN# low level
Set to zero to avoid the situation where PB_STS is set
to wake up the system then reset again by
PBOR_STS to switch the system into the soft-off
state.
1
BIOS Release (BIOS_RLS)
This bit is set by legacy software to indicate release
of the SCI/SMI lock. Upon setting of this bit,
hardware automatically sets the GBL_STS bit. This
bit is cleared by hardware when the GBL_STS bit
cleared by software.
Note that if the GBL_EN bit is set (bit-5 of the Power
Management Enable register at offset 2), then setting
this bit causes an SCI to be generated (because setting
this bit causes the GBL_STS bit to be set).
0
SMI Enable (SMI_EN)
0 Disable all SMI generation.....................default
1 Enable SMI generation
Preliminary Revision 0.8 October 29, 1999
I/O Offset 2F - SMI Command (SMI_CMD) ................. RW
7-0 SMI Command
Writing to this port sets the SW_SMI_STS bit. Note
that if the SW_SMI_EN bit is set (see bit-6 of the
Global Enable register at offset 2Ah), then an SMI is
generated.
-97-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 33-30 - Primary Activity Detect Status ....... RWC
These bits correspond to the Primary Activity Detect Enable
bits in offset 37-34. All bits default to 0, are set by hardware
only, and may only be cleared by writing 1s to the desired bit.
I/O Offset 37-34 - Primary Activity Detect Enable ........ RW
These bits correspond to the Primary Activity Detect Status
bits in offset 33-30. Setting of any of these bits also sets the
PACT_STS bit (bit-0 of offset 28) which causes the GP0 timer
to be reloaded (if PACT_GP0_EN is set) or generates an SMI
(if PACT_EN is set).
..........................................always read 0
31-11 Reserved
10 Audio Access Status .............................. (AUD_STS)
Set if Audio is accessed.
......................................... always read 0
31-11 Reserved
10 SMI on Audio Status .............................. (KBC_EN)
0 Don't set PACT_STS if AUD_STS is set .... def
1 Set PACT_STS if AUD_STS is set
9
SMI on Keyboard Controller Status..... (KBC_EN)
0 Don't set PACT_STS if KBC_STS is set..... def
1 Set PACT_STS if KBC_STS is set
8
SMI on VGA Status................................ (VGA_EN)
0 Don't set PACT_STS if VGA_STS is set .... def
1 Set PACT_STS if VGA_STS is set
7
SMI on Parallel Port Status.................... (LPT_EN)
0 Don't set PACT_STS if LPT_STS is set...... def
1 Set PACT_STS if LPT_STS is set
6
SMI on Serial Port B Status ...............(COMB_EN)
0 Don't set PACT_STS if COMB_STS is set . def
1 Set PACT_STS if COMB_STS is set
5
SMI on Serial Port A Status .............. (COMA_EN)
0 Don't set PACT_STS if COMA_STS is set . def
1 Set PACT_STS if COMA_STS is set
4
SMI on Floppy Status .............................(FDC_EN)
0 Don't set PACT_STS if FDC_STS is set ..... def
1 Set PACT_STS if FDC_STS is set
3
SMI on Secondary IDE Status...............(SIDE_EN)
0 Don't set PACT_STS if SIDE_STS is set .... def
1 Set PACT_STS if SIDE_STS is set
2
SMI on PrimaryIDE Status ...................(PIDE_EN)
0 Don't set PACT_STS if PIDE_STS is set.... def
1 Set PACT_STS if PIDE_STS is set
1
SMI on Primary INTR Status .............. (PIRQ_EN)
0 Don't set PACT_STS if PIRQ_STS is set.... def
1 Set PACT_STS if PIRQ_STS is set
9
Keyboard Controller Access Status..... (KBC_STS)
Set if the KBC is accessed via I/O port 60h.
8
VGA Access Status................................ (VGA_STS)
Set if the VGA port is accessed via I/O ports 3B03DFh or memory space A0000-BFFFFh.
Parallel Port Access Status.................... (LPT_STS)
Set if the parallel port is accessed via I/O ports 27827Fh or 378-37Fh (LPT2 or LPT1).
Serial Port B Access Status .............. (COMB_STS)
Set if the serial port is accessed via I/O ports 2F82FFh or 2E8-2Efh (COM2 and COM4 respectively).
Serial Port A Access Status .............. (COMA_STS)
Set if the serial port is accessed via I/O ports 3F83FFh or 3E8-3EFh (COM1 and COM3, respectively).
Floppy Access Status..............................(FDC_STS)
Set if the floppy controller is accessed via I/O ports
3F0-3F5h or 3F7h.
Secondary IDE Access Status...............(SIDE_STS)
Set if the IDE controller is accessed via I/O ports
170-177h or 376h.
Primary IDE Access Status ................. (PIDE_STS)
Set if the IDE controller is accessed via I/O ports
1F0-1F7h or 3F6h.
Primary Interrupt Activity Status...... (PIRQ_STS)
Set on the occurrence of a primary interrupt (enabled
via the "Primary Interrupt Channel" register at
Function 4 PCI configuration register offset 44h).
PCI Master Access Status .................... (DRQ_STS)
Set on the occurrence of PCI master activity.
7
6
5
4
3
2
1
0
0
SMI on PCI Master Status .................... (DRQ_EN)
0 Don't set PACT_STS if DRQ_STS is set .... def
1 Set PACT_STS if DRQ_STS is set
Note: The bits above correspond to the bits of the Primary
Activity Detect Enable register at offset 34 (see right hand
column of this page): if the corresponding bit is set in that
register, setting of the above bits will cause the PACT_STS bit
to be set (bit-0 of the Global Status register at offset 28).
Setting of PACT_STS may be set up to enable a "Primary
Activity Event": an SMI will be generated if PACT_EN is set
(bit-0 of the Global Enable register at offset 2Ah) and/or the
GP0 timer will be reloaded if the "GP0 Timer Reload on
Primary Activity" bit is set (bit-0 of the GP Timer Reload
Enable register at offset 38 on this page).
Note: Bits 2-9 above also correspond to bits of the GP Timer
Reload Enable register (see offset 38 on next page): If bits are
set in that register, setting a corresponding bit in this register
will cause the GP1 timer to be reloaded.
Preliminary Revision 0.8 October 29, 1999
-98-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 3B-38 - GP Timer Reload Enable .................. RW
All bits in this register default to 0 on power up.
..........................................always read 0
31-8 Reserved
7
GP1 Timer Reload on KBC Access
0 Normal GP1 Timer Operation................default
1 Setting of KBC_STS causes the GP1 timer to
reload.
6
GP1 Timer Reload on Serial Port Access
0 Normal GP1 Timer Operation ...............default
1 Setting of COMA_STS or COMB_STS causes
the GP1 timer to reload.
..........................................always read 0
5
Reserved
4
GP1 Timer Reload on VGA Access
0 Normal GP1 Timer Operation ...............default
1 Setting of VGA_STS causes the GP1 timer to
reload.
GP1 Timer Reload on IDE/Floppy Access
0 Normal GP1 Timer Operation ...............default
1 Setting of FDC_STS, SIDE_STS, or
PIDE_STS causes the GP1 timer to reload.
3
2
1
0
I/O Offset 40 – Extended I/O Trap Status ................... RWC
......................................... always read 0
7-2 Reserved
1
GPIO Ramge 3 Access Status ............. (GPR3_STS)
0
GPIO Ramge 2 Access Status ............. (GPR2_STS)
I/O Offset 42 – Extended I/O Trap Enable ..................... RW
......................................... always read 0
7-2 Reserved
1
SMI on GPIO Ramge 3 Access.............(GPR3_EN)
0 Disable................................................... default
1 Enable
0
SMI on GPIO Ramge 2 Access.............(GPR2_EN)
0 Disable................................................... default
1 Enable
GP3 Timer Reload on GPIO Range 1 Access
0 Normal GP3 Timer Operation ...............default
1 Setting of GR1_STS causes the GP3 timer to
reload.
GP2 Timer Reload on GPIO Range 0 Access
0 Normal GP2 Timer Operation ...............default
1 Setting of GR0_STS causes the GP2 timer to
reload.
GP0 Timer Reload on Primary Activity
0 Normal GP0 Timer Operation ...............default
1 Setting of PACT_STS causes the GP0 timer to
reload. Primary activities are enabled via the
Primary Activity Detect Enable register (offset
37-34) with status recorded in the Primary
Activity Detect Status register (offset 33-30).
Preliminary Revision 0.8 October 29, 1999
-99-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
General Purpose I/O Registers
I/O Offset 44 – External SMI / GPI Input Value .............RO
Depending on the configuration, up to 8 external SCI/SMI
ports are available as indicated below. The state of these
inputs may be read in this register.
7
6
5
4
3
2
1
0
RING# Input Value................................. (GPI7 pin)
SMBALRT# Input Value ....................... (GPI6 pin)
PME# Input Value .................................. (GPI5 pin)
SLPBTN# Input Value............................ (GPI4 pin)
General Purpose Input 17 Value ......... (GPI17 pin)
General Purpose Input 16 Value ......... (GPI16 pin)
General Purpose Input 1 Value ............. (GPI1 pin)
EXTSMI# Input Value
I/O Offset 4B-48 - GPI Port Input Value (GPIVAL) ...... RO
......................................... always read 0
31-24 Reserved
23-16 GPI[23-16] by Refresh Scan .................... Read Only
......................................... always read 0
15-12 Reserved
11-0 GPI[11-0] Input Value ............................. Read Only
I/O Offset 4F-4C - GPO Port Output Value (GPOVAL)RW
Reads from this register return the last value written (held on
chip)
........................................always reads 0
31-26 Reserved
25-0 GPO[25-0] Output Value................def = 3FFFFFFh
I/O Offset 45 – SMI / IRQ / Resume Status .....................RO
........................................ always reads 0
7-5 Reserved
4
Latest PCSn Status
0 Latest PCSn was an I/O Read
1 Latest PCSn was an I/O Write
3
FM SMI or Serial SMI Status
2
Hardware Monitor IRQ Status
1
SMBus IRQ Status
0
SMBus Resume Status
Preliminary Revision 0.8 October 29, 1999
-100-
Power Management I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
System Management Bus I/O-Space Registers
The base address for these registers is defined in Rx93-90 of
the Function 4 PCI configuration registers. The System
Management Bus I/O space is enabled for access by the system
if RxD2[0] = 1.
I/O Offset 00 – SMBus Host Status............................... RWC
........................................ always reads 0
7-5 Reserved
4
Failed Bus Transaction....................................RWC
0 SMBus interrupt not caused by failed bus
transaction ..............................................default
1 SMBus interrupt caused by failed bus
transaction. This bit may be set when the
KILL bit (I/O Rx02[1]) is set and can be
cleared by writing a 1 to this bit position.
3
Bus Collision.....................................................RWC
0 SMBus interrupt not caused by transaction
collision..................................................default
1 SMBus interrupt caused by transaction
collision. This bit is only set by hardware and
can be cleared by writing a 1 to this bit
position.
2
Device Error .....................................................RWC
0 SMBus interrupt not caused by generation of
an SMBus transaction error....................default
1 SMBus interrupt caused by generation of an
SMBus transaction error (illegal command
field, unclaimed host-initiated cycle, or host
device timeout). This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
1
SMBus Interrupt..............................................RWC
0 SMBus interrupt not caused by host command
completion..............................................default
1 SMBus interrupt caused by host command
completion. This bit is only set by hardware
and can be cleared by writing a 1 to this bit
position.
0
Host Busy ..........................................................RO
0 SMBus controller host interface is not
processing a command ...........................default
1 SMBus host controller is busy processing a
command. None of the other SMBus registers
should be accessed if this bit is set.
Preliminary Revision 0.8 October 29, 1999
I/O Offset 01h – SMBus Slave Status ........................... RWC
........................................always reads 0
7-6 Reserved
5
Alert Status ..................................................... RWC
0 SMBus interrupt not caused by SMBALERT#
signal .................................................... default
1 SMBus interrupt caused by SMBALERT#
signal. This bit will be set only if the Alert
Enable bit is set in the SMBus Slave Control
Register at I/O Offset R08[3]. This bit is only
set by hardware and can be cleared by writing
a 1 to this bit position.
4
Shadow 2 Status............................................... RWC
0 SMBus interrupt not caused by address match
to SMBus Shadow Address Port 2......... default
1 SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 2. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
3
Shadow 1 Status............................................... RWC
0 SMBus interrupt not caused by address match
to SMBus Shadow Address Port 1......... default
1 SMBus interrupt or resume event caused by
slave cycle address match to SMBus Shadow
Address Port 1. This bit is only set by
hardware and can be cleared by writing a 1 to
this bit position.
2
Slave Status ..................................................... RWC
0 SMBus interrupt not caused by slave event
match .................................................... default
1 SMBus interrupt or resume event caused by
slave cycle event match of the SMBus Slave
Command Register at PCI Function 4
Configuration Offset D3h (command match)
and the SMBus Slave Event Register at
SMBus Base + Offset 0Ah (data event match).
This bit is only set by hardware and can be
cleared by writing a 1 to this bit position.
........................................always reads 0
1
Reserved
0
Slave Busy ......................................................... RO
0 SMBus controller slave interface is not
processing data ...................................... default
1 SMBus controller slave interface is busy
receiving data. None of the other SMBus
registers should be accessed if this bit is set.
-101-
System Management Bus I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 02h – SMBus Host Control ............................. RW
........................................ always reads 0
7
Reserved
........................................ always reads 0
6
Start
0 Writing 0 has no effect ...........................default
1 Start Execution of Command
Writing a 1 to this bit causes the SMBus
controller host interface to initiate execution of
the command programmed in the SMBus
Command Protocol field (bits 4-2).
All
necessary registers should be programmed
prior to writing a 1 to this bit. The Host Busy
bit (SMBus Host Status Register bit-0) can be
used to identify when the SMBus controller
has completed command execution.
........................................ always reads 0
5
Reserved
4-2 SMBus Command Protocol
000 Quick Read or Write ..............................default
001 Byte Read or Write
010 Byte Data Read or Write
011 Word Data Read or Write
100 Reserved
101 Block Read or Write
110 Reserved
111 Reserved
1
Kill Transaction in Progress
0 Normal host controller operation ...........default
1 Stop host transaction currently in progress.
Setting this bit also sets the FAILED status bit
(Host Status bit-4) and asserts the interrupt
selected by the SMB Interrupt Select bit
(Function 4 SMBus Host Configuration
Register RxD2[3]).
0
Interrupt Enable
0 Disable interrupt generation ...................default
1 Enable generation of interrupts on completion
of the current host transaction.
Preliminary Revision 0.8 October 29, 1999
I/O Offset 03h – SMBus Host Command ........................ RW
7-0 SMBUS Host Command ..........................default = 0
This field contains the data transmitted in the
command field of the SMBus host transaction.
I/O Offset 04h – SMBus Host Address............................ RW
The contents of this register are transmitted in the address field
of the SMBus host transaction.
7-1 SMBUS Address .......................................default = 0
This field contains the 7-bit address of the targeted
slave device.
0
SMBUS Read or Write
0 Execute a WRITE command ................. default
1 Execute a READ command
I/O Offset 05h – SMBus Host Data 0 .............................. RW
The contents of this register are transmitted in the Data 0 field
of SMBus host transaction writes. On reads, Data 0 bytes are
stored here.
7-0 SMBUS Data 0..........................................default = 0
For Block Write commands, this field is programmed
with the block transfer count (a value between 1 and
32). Counts of 0 or greater than 32 are undefined.
For Block Read commands, the count received from
the SMBus device is stored here.
I/O Offset 06h – SMBus Host Data 1 .............................. RW
The contents of this register are transmitted in the Data 1 field
of SMBus host transaction writes. On reads, Data 1 bytes are
stored here.
7-0 SMBUS Data 1..........................................default = 0
I/O Offset 07h – SMBus Block Data ............................... RW
Reads and writes to this register are used to access the 32-byte
block data storage array. An internal index pointer is used to
address the array. It is reset to 0 by reads of the SMBus Host
Control register (I/O Offset 2) and incremented automatically
by each access to this register. The transfer of block data into
(read) or out of (write) this storage array during an SMBus
transaction always starts at index address 0.
7-0 SMBUS Block Data ..................................default = 0
-102-
System Management Bus I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 08h – SMBus Slave Control............................ RW
........................................ always reads 0
7-4 Reserved
3
SMBus Alert Enable
0 Disable ...................................................default
1 Enable generation of an interrupt or resume
event on the assertion of the SMBALERT#
signal
2
SMBus Shadow Port 2 Enable
0 Disable ...................................................default
1 Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus Slave Shadow Port 2 register (PCI
function 4 configuration register RxD5).
1
SMBus Shadow Port 1 Enable
0 Disable ...................................................default
1 Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus Slave Shadow Port 1 register (PCI
function 4 configuration register RxD4).
0
SMBus Slave Enable
0 Disable ...................................................default
1 Enable generation of an interrupt or resume
event on external SMBus master generation of
a transaction with an address that matches the
SMBus host controller slave port of 10h, a
command field which matches the SMBus
Slave Command register (PCI function 4
configuration register RxD3), and a match of
one of the corresponding enabled events in the
SMBus Slave Event Register (I/O Offset 0Ah).
Preliminary Revision 0.8 October 29, 1999
I/O Offset 09h – SMBus Shadow Command ................... RO
This register is used to store command values for external
SMBus master accesses to the host slave and slave shadow
ports.
7-0 Shadow Command....................................default = 0
This field contains the command value which was
received during an external SMBus master access
whose address field matched the host slave address
(10h) or one of the slave shadow port addresses.
I/O Offset 0Ah – SMBus Slave Event ............................. RW
This register is used to enable generation of interrupt or
resume events for accesses to the host controller’s slave port.
15-0 SMBus Slave Event ..................................default = 0
This field contains data bits used to compare against
incoming data to the SMBus Slave Data Register (I/O
Offset 0Ch). When a bit in this register is set and the
corresponding bit the Slave Data register is also set,
an interrupt or resume event will be generated if the
command value matches the value in the SMBus
Slave Command register and the access was to
SMBus host address 10h.
I/O Offset 0Ch – SMBus Slave Data ................................ RO
This register is used to store data values for external SMBus
master accesses to the shadow ports or the SMBus host
controller’s slave port.
15-0 SMBus Slave Data ....................................default = 0
This field contains the data value which was
transmitted during an external SMBus master access
whose address field matched one of the slave shadow
port addresses or the SMBus host controller slave
port address of 10h.
-103-
System Management Bus I/O-Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Hardware Monitor I/O Space Registers
The I/O base address for access to the Hardware Monitor
registers is defined in Rx71-70 of function 4 PCI configuration
space. The hardware monitor I/O space is enabled for I/O
access by the system if Rx74[0] = 1.
Offset 13 – Analog Data 15-8 ........................................... RW
Offset 14 – Analog Data 7-0 ............................................. RW
Offset 15 – Digital Data 7-0 .............................................. RW
Offset 16 – Channel Counter ............................................ RW
Offset 17 – Data Valid & Channel Indicators ................. RW
Offset 29 – FAN1 (Pin T12) Count Reading ................... RW
Offset 2A – FAN2 (Pin U12) Count Reading .................. RW
The above two locations store the number of counts of the
internal clock per fan revolution.
Offset 2B – VSENS1 Voltage High Limit (CPU 2.0V) ... RW
Offset 2C – VSENS1 Voltage Low Limit (CPU 2.0V) ... RW
Offset 2D – VSENS2 Voltage High Limit (NB 2.5V) ..... RW
Offset 2E – VSENS2 Voltage Low Limit (NB 2.5V) ...... RW
Offset 2F – Internal Core Voltage High Limit (3.3V).... RW
Offset 30 – Internal Core Voltage Low Limit (3.3V) ..... RW
Offset 1D – TSENS3 Hot Temperature High Limit ....... RW
Offset 31 – VSENS3 Voltage High Limit (5V)................ RW
Offset 1E – TSENS3 Hot Temp Hysteresis Lo Limit...... RW
Offset 32 – VSENS3 Voltage Low Limit (5V) ................ RW
Offset 1F – TSENS3 Temperature Reading .................... RW
Temperature sensor 3 is an internal bandgap-type sensor which
has 10-bit resolution. The high order 8 bits are stored here and
the low order 2 bits are stored in Rx49[7-6]. Only the high
order 8 bits are used for comparison with the limit values in
offsets 1D and 1E.
Offset 33 – VSENS4 Voltage High Limit (12V).............. RW
Offset 34 – VSENS4 Voltage Low Limit (12V) .............. RW
Offset 35 – Reserved (-12V Sense High Limit) ............... RW
Offset 36 – Reserved (-12V Sense Low Limit) ................ RW
Offset 37 – Reserved (-5V Sense High Limit) ................. RW
Offset 20 – TSENS1 Temperature Reading .................... RW
Temperature sensor 1 is an external sensor input on pin W13
which has 10-bit resolution. The high order 8 bits are stored
here and the low order 2 bits are stored in Rx4B[7-6]. Only
the high order 8 bits are used for comparison with the limit
values in offsets 39 and 3A.
Offset 38 – Reserved (-5V Sense Low Limit) .................. RW
Offset 39 – TSENS1 Hot Temperature High Limit........ RW
Offset 3A – TSENS1Hot Temp Hysteresis Lo Limit ...... RW
Offset 3B – FAN1 Fan Count Limit ................................ RW
Offset 21 – TSENS2 Temperature Reading .................... RW
Temperature sensor 2 is an external sensor input on pin Y13
which has 10-bit resolution. The high order 8 bits are stored
here and the low order 2 bits are stored in Rx49[5-4]. Only
the high order 8 bits are used for comparison with the limit
values in offsets 3D and 3E.
Offset 22 – VSENS1 (Pin U13) Voltage Reading (2.0V). RW
Offset 23 – VSENS2 (Pin V13) Voltage Reading (2.5V). RW
Offset 3C – FAN2 Fan Count Limit ................................ RW
The above two locations store the number of counts of the
internal clock per fan revolution for the low limit of the fan
speed.
Offset 3D – TSENS2 Hot Temperature High Limit ....... RW
Offset 3E – TSENS2 Hot Temp Hysteresis Lo Limit ..... RW
Offset 3F – Stepping ID Number ..................................... RW
Offset 24 – Internal Core Voltage Reading (3.3V) ......... RW
Offset 25 – VSENS3 (Pin W14) Voltage Reading (5V) .. RW
Offset 26 – VSENS4 (Pin Y14) Voltage Reading (12V).. RW
Offset 27 – Reserved (-12V Sense Voltage Reading) ...... RW
Offset 28 – Reserved (-5V Sense Voltage Reading) ........ RW
Preliminary Revision 0.8 October 29, 1999
Note: For high limits, comparisons are “greater than”
comparisons. For low limits, comparisons are “less than or
equal” comparisons.
One consequence of the above is that if high limits are set to
all ones (FFh or 11111111b), interrupts are disabled for high
limits (i.e., interrupts will only be generated for cases when
voltages are equal to or below the low limits).
-104-
Hardware Monitor I/O Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 40 –Hardware Monitor Configuration ................ RW
7
Initialization
0 Normal operation ...................................default
1 Restore power-up default values to this
register, the interrupt status and mask registers,
the FAN/RST#/OS# register, and the OS#
Configuration / Temperature Resolution
register. This bit automatically clears itself
since the power-on default is 0.
6
Chassis Intrusion Reset
0 Normal operation ...................................default
1 Reset the Chassis Intrusion pin
5-4 Reserved (R/W) ........................................ default = 0
3
Hardware Monitor Interrupt Clear
0 Normal operation
1 Clear the hardware monitor interrupt output
(does not effect the contents of the interrupt
status register). Normally set during interrupt
service ....................................................default
........................................ always reads 0
2
Reserved
1
Hardware Monitor Interrupt Enable
0 Disable hardware monitor interrupt output.. def
1 Enable hardware monitor interrupt output
0
Start
0 Place hardware monitor in standby mode.... def
1 Enable startup of hardware monitor logic.
At startup, limit checking functions and
scanning begins. All high and low limits
should be set prior to turning on this bit. Note:
the hardware monitor interrupt output will not
be cleared if the user writes a zero to this bit
after an interrupt has occurred (the hardware
monitor interrupt clear bit must be used for this
purpose).
Preliminary Revision 0.8 October 29, 1999
-105-
Hardware Monitor I/O Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
TSENS1 Temperature Error
0 No error ..................................................default
1 High or low hot temperature limit exceeded.
The interrupt mode is determined by
Temperature Resolution register Rx4B[1-0].
VSENS3 Voltage Error (5V)
0 No error ..................................................default
1 High or low limit exceeded
Internal Core VCC Voltage Error (3.3V)
0 No error ..................................................default
1 High or low limit exceeded
VSENS2 Voltage Error (2.5V NB Core Voltage)
0 No error ..................................................default
1 High or low limit exceeded
VSENS1 Voltage Error (2.0V CPU Core Voltage)
0 No error ..................................................default
1 High or low limit exceeded
Offset 43 –Hardware Monitor Interrupt Mask 1 .......... RW
7
Fan 2 Count Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
6
Fan 1 Count Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
5
TSENS1 Thermal Alarm Control Mask
0 Enable TSENS1 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set )def
1 Disable
4
TSENS1 Temperature Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
3
VSENS3 Voltage Error Mask (5V)
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
2
Internal Core VCC Voltage Error Mask (3.3V)
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
1
VSENS2 Voltage Error Mask (2.5V NB Core)
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
0
VSENS1 Voltage Error Mask (2.0V CPU Core)
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
Offset 42 –Hardware Monitor Interrupt Status 2 ...........RO
7
TSENS3 (Internal Bandgap) Temp Error
0 No error ..................................................default
1 High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[5-4].
........................................ always reads 0
6-5 Reserved
4
Chassis Error
0 No error ..................................................default
1 Chassis Intrusion has gone high
3
TSENS2 Temperature Error
0 No error ..................................................default
1 High or low hot temperature limit exceeded.
Interrupt mode is determined by Rx4B[3-2].
........................................ always reads 0
2-1 Reserved
0
VSENS4 Voltage Error (12V)
0 No error ..................................................default
1 High or low limit exceeded
Note: When either status register is read, status conditions in
that register are reset. In the case of voltage priority
indications, if two or more voltages were out of limits, then
another indication would automatically be generated if it was
not handled during interrupt service. Errant voltages may be
disabled in the control register until the operator has time to
clear the errant condition or set the limit higher or lower.
Offset 44 –Hardware Monitor Interrupt Mask 2 .......... RW
7
TSENS3 Temperature Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
6
TSENS3 Thermal Alarm Control Mask
0 Enable TSENS3 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set) def
1 Disable
5
TSENS2 Thermal Alarm Control Mask
0 Enable TSENS2 over-temp condition to
control the thermal alarm (function 4 Rx40[7]
automatic CPU clock throttling must be set) def
1 Disable
4
Chassis Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
3
TSENS2 Temperature Error Mask
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
........................................always reads 0
2-1 Reserved
0
VSENS4 Voltage Error Mask (12V)
0 Enable interrupt on error status bit set ......... def
1 Disable interrupt on error status bit set
Offset 41 –Hardware Monitor Interrupt Status 1 ...........RO
7
Fan 2 Error
0 No error ..................................................default
1 Fan 2 count limit exceeded
6
Fan 1 Error
0 No error ..................................................default
1 Fan 1 count limit exceeded
........................................ always reads 0
5
Reserved
4
3
2
1
0
Preliminary Revision 0.8 October 29, 1999
-106-
Hardware Monitor I/O Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 47 –Hardware Monitor Fan Configuration ......... RW
7-6 Fan 2 RPM Control
00 Divide by 1
01 Divide by 2 ............................................default
10 Divide by 4
11 Divide by 8
5-4 Fan 1 RPM Control
00 Divide by 1
01 Divide by 2 ............................................default
10 Divide by 4
11 Divide by 8
........................................ always reads 0
3-0 Reserved
Offset 49 –Hardware Monitor Temp Low Order Value RW
7-6 TSENS3 Value Low-Order Bits
Upper 8 bits are stored in offset 1Fh
5-4 TSENS2 Value Low-Order Bits
Upper 8 bits are stored in offset 21h
3
Over Temperature Active Low for PMU to
Control Stop Clock
0 Disable ...................................................default
1 Enable
2
Chassis Active Low Output 20 msec
0 Disable ...................................................default
1 Enable
1
Interrupt Active High Output
0 Disable ...................................................default
1 Enable
........................................ always reads 0
0
Reserved
Preliminary Revision 0.8 October 29, 1999
Offset 4B –Temperature Interrupt Configuration ........ RW
7-6 TSENS1 Value Low-Order Bits ..................def = 00
Upper 8 bits are stored in offset 20h
5-4 TSENS3 Hot Temp Interrupt Mode ...........def = 01
3-2 TSENS2 Hot Temp Interrupt Mode ...........def = 01
1-0 TSENS1 Hot Temp Interrupt Mode ...........def = 01
The following applies to each of the above 3 fields
00 Default Interrupt Mode. An interrupt occurs if
the temperature goes above the hot limit. The
interrupt will be cleared once the status register
is read, but will be generated again when the
next conversion is completed. Interrupts will
continue to be generated until the temperature
goes below the hysteresis limit.
01 One-Time Interrupt Mode. An interrupt is
generated if the temperrature goes above the
hot limit. The interrupt will be cleared when
the status register is read. Another interrupt
will not be generated until the temperature first
drops below the hysteresis limit............. default
10 Comparator mode. An interrupt occurs if the
temperature goes above the hot limit. This
interrupt remains active until the temperature
goes below the hot limit (i.e., no hysteresis).
11 Default Interrupt Mode (same as 00)
-107-
Hardware Monitor I/O Space Registers
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
The codec interface is hardware compatible with AC97 and
SoundBlaster Pro. There are two sets of software accessible
registers: PCI configuration registers and I/O registers. The
PCI configuration registers for the Audio Codec are located in
the function 5 PCI configuration space of the VT8231. The
PCI configuration registers for the Modem Codec are located
in the function 6 PCI configuration space. The I/O registers
are located in the system I/O space.
Offset 9 - Programming Interface (00h)........................... RO
Offset A - Sub Class Code (01h=Audio Device) ............... RO
Offset B - Base Class Code (04h=Multimedia Device) ..... RO
Offset D - Latency Timer (00h) ......................................... RO
Offset E - Header Type (00h) ............................................ RO
Offset F - BIST (00h) ......................................................... RO
PCI Configuration Space Header – Function 5 Audio
Offset 1-0 - Vendor ID .......................................................RO
0-7 Vendor ID ................. (1106h = VIA Technologies)
Offset 3-2 - Device ID .........................................................RO
0-7 Device ID (3058h = VT8231 Audio Codec)
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-10 Reserved
9
Fast Back-to-Back.......................................fixed at 0
8
SERR# Enable.............................................fixed at 0
7
Address Stepping ........................................fixed at 0
6
Parity Error Response................................fixed at 0
5
VGA Palette Snoop .....................................fixed at 0
4
Memory Write and Invalidate ...................fixed at 0
3
Special Cycle Monitoring ...........................fixed at 0
2
Bus Master .................................................fixed at 0
1
Memory Space.............................................fixed at 0
0
I/O Space ............................... default=0 (disabled)
Offset 7-6 - Status ........................................................... RWC
15 Detected Parity Error .................................fixed at 0
14 Signalled System Error...............................fixed at 0
13 Received Master Abort...............................fixed at 0
12 Received Target Abort ...............................fixed at 0
11 Signalled Target Abort ...............................fixed at 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .................................................... fixed
10 Slow
11 Reserved
8
Data Parity Error........................................fixed at 0
7
Fast Back-to-Back Capable........................fixed at 0
........................................ always reads 0
6-5 Reserved
.................................................fixed at 1
4
PM 1.1
........................................ always reads 0
3-0 Reserved
Offset 8 - Revision ID (40h) ...............................................RO
7-0 Silicon Revision Code
Offset 13-10 - Base Address 0 – SGD Control / Status .. RW
........................................always reads 0
31-16 Reserved
15-8 Base Address......................................... default = 00h
7-0 00000001b (256 bytes)
Offset 17-14 - Base Address 1 – FM NMI Status ........... RW
........................................always reads 0
31-16 Reserved
15-2 Base Address..................................... default = 0000h
1-0 01b (4 bytes)
Offset 1B-18 - Base Address 2 – MIDI Port ................... RW
........................................always reads 0
31-16 Reserved
15-2 Base Address..................................... default = 0330h
1-0 01b (4 bytes)
Offset 2F-2C – Subsystem ID / Sub Vendor ID ............. RO*
*This register is RW if function 5-6 Rx42[5] = 1
Offset 34 – Capture Pointer (Default = C0h) .................. RO
Offset 3C - Interrupt Line ................................................ RW
........................................always reads 0
7-4 Reserved
3-0 Audio Interrupt Routing
0000 Disabled................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
Offset 3D - Interrupt Pin (03h) ......................................... RO
Offset 3E - Minimum Grant (00h) .................................... RO
Offset 3F - Maximum Latency (00h) ................................ RO
Preliminary Revision 0.8 October 29, 1999
-108-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PCI Configuration Space Header – Function 6 Modem
Offset 1-0 - Vendor ID .......................................................RO
0-7 Vendor ID ................. (1106h = VIA Technologies)
Offset 3-2 - Device ID .........................................................RO
0-7 Device ID (3068h = 8231 Modem Codec)
Offset 5-4 - Command ....................................................... RW
........................................ always reads 0
15-10 Reserved
9
Fast Back-to-Back.......................................fixed at 0
8
SERR# Enable.............................................fixed at 0
7
Address Stepping ........................................fixed at 0
6
Parity Error Response................................fixed at 0
5
VGA Palette Snoop .....................................fixed at 0
4
Memory Write and Invalidate ...................fixed at 0
3
Special Cycle Monitoring ...........................fixed at 0
2
Bus Master .................................................fixed at 0
1
Memory Space.............................................fixed at 0
0
I/O Space ............................... default=0 (disabled)
Offset 7-6 - Status ........................................................... RWC
15 Detected Parity Error .................................fixed at 0
14 Signalled System Error...............................fixed at 0
13 Received Master Abort...............................fixed at 0
12 Received Target Abort ...............................fixed at 0
11 Signalled Target Abort ...............................fixed at 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .................................................... fixed
10 Slow
11 Reserved
8
Data Parity Error........................................fixed at 0
7
Fast Back-to-Back Capable........................fixed at 0
........................................ always reads 0
6-0 Reserved
Offset 8 - Revision ID (nnh) ...............................................RO
7-0 Silicon Revision Code (0 indicates first silicon)
Offset 13-10 - Base Address 0 – SGD Control / Status .. RW
........................................always reads 0
31-16 Reserved
15-8 Base Address......................................... default = 00h
7-0 00000001b (256 bytes)
Offset 1F-1C - Base Address 3 – Codec Reg Shadow .... RW
........................................always reads 0
31-16 Reserved
15-8 Base Address......................................... default = 00h
7-0 00000001b (256 bytes)
Offset 3C - Interrupt Line ................................................ RW
........................................always reads 0
7-4 Reserved
3-0 Audio Interrupt Routing
0000 Disabled................................................. default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 Disabled
Offset 3D - Interrupt Pin (03h) ......................................... RO
Offset 3E - Minimum Grant (00h) .................................... RO
Offset 3F - Maximum Latency (00h) ................................ RO
Offset 9 - Programming Interface (00h) .........................*RO
Offset A - Sub Class Code (80h) ......................................*RO
Offset B - Base Class Code (07h) .....................................*RO
*Registers 9-B are RW if function 5-6 Rx44[5] = 1
Offset D - Latency Timer (00h) .........................................RO
Offset E - Header Type (00h) ............................................RO
Offset F - BIST (00h) ..........................................................RO
Preliminary Revision 0.8 October 29, 1999
-109-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 5 & 6 Codec-Specific Configuration Registers
Offset 40 – AC97 Interface Status ....................................RO
........................................ always reads 0
7-5 Reserved
4
AC97 Codec Low-Power Status..........................RO
0 AC97 Codec not in low-power mode
1 AC97 Codec in low-power mode
........................................ always reads 0
3
Reserved
2
Secondary Codec 2 (CID=10b) Ready Status ....RO
0 Codec Not Ready
1 Codec Ready (AC97 ctrlr can access codec)
1
Secondary Codec 1 (CID=01b) Ready Status ....RO
0 Codec Not Ready
1 Codec Ready (AC97 ctrlr can access codec)
0
Primary Codec Ready Status ..............................RO
0 Codec Not Ready
1 Codec Ready (AC97 ctrlr can access codec)
Preliminary Revision 0.8 October 29, 1999
Offset 41 – AC Link Interface Control ........................... RW
7
AC-Link Interface Enable (ENAC97)
0 Disable................................................... default
1 Enable
6
AC-Link Reset (ACRST#)
0 Assert AC-Link Reset ............................ default
1 De-assert AC-Link Reset
5
AC-Link Sync (RSYNCHI)
0 Release SYNC ....................................... default
1 Force SYNC High
4
AC-Link Serial Data Out
0 Release SDO.......................................... default
1 Force SDO High
Function 5 Only (Reserved in Function 6):
3
Variable-Sample-Rate On-Demand Mode
0 Disable................................................... default
1 Enable
Bit valid in function 5 only (reserved in function 6)
2
AC Link SGD Read Channel PCM Data Output
0 Disable................................................... default
1 Enable
Bit valid in function 5 only (reserved in function 6)
1
AC Link FM Channel PCM Data Out (SELFM)
0 Disable................................................... default
1 Enable
Bit valid in function 5 only (reserved in function 6)
0
AC Link SB PCM Data Output (SELSB)
0 Disable................................................... default
1 Enable
Bit valid in function 5 only (reserved in function 6)
-110-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 42 – Function Enable ....................... RW (Function 5)
Offset 42 – Function Enable ........................ RO (Function 6)
7
MIDI PnP
0 MIDI Port Address Selected by Rx43[3-2] . def
1 MIDI Port Address Selected by IOBase2
6
Mask MIDI IRQ
0 Disable ...................................................default
1 Enable
5
Function 5 Config Reg Rx2C Writable
0 F5Rx2C-2F RO ......................................default
1 F5Rx2C-2F RW
4
Gate SoundBlaster PCM When FIFO Empty
0 Disable ...................................................default
1 Enable
3
Game Port Enable (ENGAME)
0 Disable ...................................................default
1 Enable (200-207h)
2
FM Enable (ENFM)
0 Disable ...................................................default
1 Enable (388-38B)
1
MIDI Enable (ENMIDI)
0 Disable ...................................................default
1 Enable
0
SoundBlaster Enable (ENSB)
0 Disable ...................................................default
1 Enable
Offset 43 – Plug and Play Control ............. RW (Function 5)
Offset 43 – Plug and Play Control .............. RO (Function 6)
7-6 SoundBlaster IRQ Select (SBIRQS[1:0])
00 IRQ5 .....................................................default
01 IRQ7
10 IRQ9
11 IRQ10
5-4 SoundBlaster DRQ Select (SBDRQS[1:0])
00 DMA Channel 0
01 DMA Channel 1 .....................................default
10 DMA Channel 2
11 DMA Channel 3
3-2 MIDI Decode Select (MIDIBASE)
00 300-303h
01 310-313h
10 320-323h
11 330-333h ................................................default
1-0 SoundBlaster Decode Select (SBBASE)
00 220-22Fh ................................................default
01 240-24Fh
10 260-26Fh
11 280-28Fh
Preliminary Revision 0.8 October 29, 1999
Offset 44 – MC97 Interface Control .......... RO (Function 5)
Offset 44 – MC97 Interface Control ......... RW (Function 6)
7
Function 5 AC-Link Interface Access
0 Disable................................................... default
1 Enable
6
Secondary Codec Support
0 Disable................................................... default
1 Enable
5
Function 6 Config Reg Rx9-B Writable
0 F6Rx9-B RO.......................................... default
1 F6Rx9-B RW
4
Function 6 Config Reg 2Ch Writable
0 F6Rx2C-2F RO...................................... default
1 F6Rx2C-2F RW
........................................always reads 0
3-0 Reserved
Offset 48 – FM NMI Control ..................... RW (Function 5)
Offset 48 – FM NMI Control ...................... RO (Function 6)
........................................always reads 0
7-3 Reserved
2
FM IRQ Select
0 Route FM Trap interrupt to NMI........... default
1 Route FM Trap interrupt to SMI
1
FM SGD Data for SoundBlaster Mixing
0 Disable................................................... default
1 Enable
0
FM Trap Interrupt
0 Enable .................................................... default
1 Disable
Offset 4B-4A – Game Port Base Address . RW (Function 5)
Offset 4B-4A – Game Port Base Address .. RO (Function 6)
15-0 Game Port Base Address .........................default = 0
-111-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 5 I/O Base 0 Regs – DXSn Scatter/Gather DMA
“n” is 0-3 for DXS channels 0-3
I/O Offset n0 – DXSn SGD Read Channel Status ....... RWC
7
SGD Active (0 = completed or terminated)........RO
........................................ always reads 0
6-3 Reserved
2
SGD Stopped ........................................................RO
1
SGD EOL ......................................................RWC
0
SGD Flag ......................................................RWC
I/O Offset n1 – DXSn SGD Read Channel Control ........ RW
7
SGD Trigger ........................... WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate ...................... WO (always reads 0)
0 No effect
1 Terminate SGD Operation
5
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
4
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
........................................ always reads 0
3-2 Reserved
1
Interrupt on EOL @ End of Block
0 Disable ...................................................default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable ...................................................default
1 Enable
I/O Offset n2 – DXSn Read Channel Left Volume ......... RW
........................................ always reads 0
7-6 Reserved
5-0 Left Volume Control
000000 0 db ...................................................default
000111 -10.5 db
011111 -46.5 db.............................................default
111111 muted (instead of –94.5 db)
I/O Offset n3 – DXSn Read Channel Right Volume ...... RW
........................................ always reads 0
7-6 Reserved
5-0 Right Volume Control
000000 0 db ...................................................default
000111 -10.5 db
011111 -46.5 db.............................................default
111111 muted (instead of –94.5 db)
Preliminary Revision 0.8 October 29, 1999
I/O Offset n7-n4 – DXSn SGD Table Pointer Base ........ RW
31-0 SGD Table Pointer Base Address (even addr) .... W
Current Pointer Address ....................................... R
I/O Offset nB-n8 – DXSn Read Channel Format............ RO
31-24 Stop Index (SGD operation will stop at end of entry)
........................................always reads 0
23-22 Reserved
21-20 PCM Format
00 8-Bit Mono Format ................................ default
01 8-Bit Stereo Format
10 16-bit Mono Format............................... default
11 16-bit Stereo Format
19-0 DXSx Channel Sample Rate
I/O Offset nF-nC – DXSn SGD Count Pointer................ RO
31-24 Current SGD Index
23-0 Current SGD Count
SGD Table Format
63
62
61
60-56
55-32
EOL FLAG STOP -reserved- Base
(FM
Count
Chan
[23:0]
Only)
31-0
Base
Address
[31:0]
End Of Link. 1 indicates this block is the last of the
link. If the channel “Interrupt on EOL” bit is set, then
an interrupt is generated at the end of the transfer.
FLAG Block Flag. If set, transfer pauses at the end of this
block. If the channel “Interrupt on FLAG” bit is set,
then an interrupt is generated at the end of this block.
STOP Block Stop. If set, transfer pauses at the end of this
block. To resume the transfer, write 1 to Rx?0[2].
EOL
-112-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 40 – 3D Channel SGD Status....................... RWC
7
SGD Active (0 = completed or terminated)........RO
........................................ always reads 0
6-3 Reserved
2
SGD Stopped ........................................................RO
1
SGD EOL ......................................................RWC
0
SGD Flag ......................................................RWC
I/O Offset 41 – 3D Channel SGD Control ....................... RW
7
SGD Trigger ........................... WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate ...................... WO (always reads 0)
0 No effect
1 Terminate SGD Operation
5
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
4
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
........................................ always reads 0
3-2 Reserved
1
Interrupt on EOL @ End of Block
0 Disable ...................................................default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable ...................................................default
1 Enable
I/O Offset 47-44 – 3D Channel SGD Table Pointer ....... RW
31-0 SGD Table Pointer Base Address (even addr) .... W
Current Pointer Address ....................................... R
I/O Offset 4B-48 – 3D Channel SGD Slot-Select ............ RW
31-24 Stop Index (SGD operation will stop at end of entry)
23-20 Slot 9 Data Select
0000 No data assigned to slot 9
0001 1st data in the sample is assigned to slot9
0010 2nd data in the sample is assigned to slot9
0011 3rd data in the sample is assigned to slot9
0100 4th data in the sample is assigned to slot9
0101 5th data in the sample is assigned to slot9
0110 6th data in the sample is assigned to slot9
0111 -invalid1xxx -invalid19-16 Slot 6 Data Select
15-12 Slot 8 Data Select
11-8 Slot 7 Data Select
7-4 Slot 4 Data Select
3-0 Slot 3 Data Select
I/O Offset 4F-4C – 3D Channel SGD Current Count..... RO
31-24 Current SGD Index
23-0 Current SGD Count
I/O Offset 42 – 3D Channel SGD Format ....................... RW
7
PCM Format
0 8-bit .....................................................default
1 16-bit
6-4 # of Channels
000 -invalid- ..................................................default
001 One channel
010 Two channels
011 Three channels
100 Four channels
101 Five channels
110 Six channels
111 -invalid........................................ always reads 0
3-0 Reserved
I/O Offset 43 – Scratch ..................................................... RW
7-0 No Assigned Hardware Function
Preliminary Revision 0.8 October 29, 1999
-113-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 50 – FM Channel SGD Status ..................... RWC
7
SGD Active (0 = completed or terminated)........RO
........................................ always reads 0
6-3 Reserved
2
SGD Stopped ........................................................RO
1
SGD EOL ......................................................RWC
0
SGD Flag ......................................................RWC
I/O Offset 51 – FM Channel SGD Control...................... RW
7
SGD Trigger ........................... WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate ...................... WO (always reads 0)
0 No effect
1 Terminate SGD Operation
5-4 Reserved (Do Not Program)............always write 0’s
3
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
2-0 Reserved (No Function)...................................... RW
I/O Offset 52 – FM Channel SGD Type .......................... RW
7
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
........................................ always reads 0
6-4 Reserved
3-2 Interrupt Select
00 Interrupt at last line PCI read
01 Interrupt at last sample sent
10 Interrupt at less than one line to send
11 -reserved1
Interrupt on EOL @ End of Block
0 Disable ...................................................default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable ...................................................default
1 Enable
I/O Offset 57-54 – FM Channel SGD Table Pointer ...... RW
31-0 SGD Table Pointer Base Address (even addr).....W
Current Pointer Address ........................................R
I/O Offset 5F-5C – FM Channel SGD Current Count ....RO
31-24 Current SGD Index
23-0 Current SGD Count
Preliminary Revision 0.8 October 29, 1999
-114-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
I/O Offset 60 – Wr Channel 0 SGD Status ................... RWC
7
SGD Active (0 = completed or terminated)...........RO
6
SGD Paused ..........................................................RO
........................................ always reads 0
5-4 Reserved
3
SGD Trigger Queued (transaction will restart after
EOL)
..........................................................RO
2
SGD Stopped ........................................................RO
1
SGD EOL (clear interrupt if Rx62[1] is set) .....RWC
0
SGD Flag (clear interrupt if Rx62[0] is set) ......RWC
I/O Offset 70 – Wr Channel 1 SGD Status .................. RWC
7
SGD Active (0 = completed or terminated) .......... RO
6
SGD Paused ......................................................... RO
........................................always reads 0
5-4 Reserved
3
SGD Trigger Queued (transaction will restart after
EOL)
......................................................... RO
2
SGD Stopped........................................................ RO
1
SGD EOL (clear interrupt if Rx62[1] is set)..... RWC
0
SGD Flag (clear interrupt if Rx62[0] is set) ..... RWC
I/O Offset 61 – Wr Channel 0 SGD Control ................... RW
7
SGD Trigger ........................... WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate ...................... WO (always reads 0)
0 No effect
1 Terminate SGD Operation
........................................ always reads 0
5-4 Reserved
3
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
........................................ always reads 0
3-2 Reserved
I/O Offset 71 – Wr Channel 1 SGD Control................... RW
7
SGD Trigger............................WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate.......................WO (always reads 0)
0 No effect
1 Terminate SGD Operation
........................................always reads 0
5-4 Reserved
3
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
........................................always reads 0
3-2 Reserved
I/O Offset 62 – Wr Channel 0 SGD Format.................... RW
7
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
6
Recording FIFO
0 Disable ...................................................default
1 Enable
5
PCM 8/16 Format (0=8bit, 1=16bit)
4
PCM Mono/Stereo Format (0=Mono, Stereo)
3-2 Recording Source
00 Primary Codec
01 Secondary Codec 01
10 Secondary Codec 10
11 -reserved1
Interrupt on EOL @ End of Block
0 Disable ...................................................default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable ...................................................default
1 Enable
I/O Offset 72 – Wr Channel 1 SGD Format ................... RW
7
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
6
Recording FIFO
0 Disable................................................... default
1 Enable
5
PCM 8/16 Format (0=8bit, 1=16bit)
4
PCM Mono/Stereo Format (0=Mono, Stereo)
3-2 Recording Source
00 Primary Codec
01 Secondary Codec 01
10 Secondary Codec 10
11 -reserved1
Interrupt on EOL @ End of Block
0 Disable................................................... default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable................................................... default
1 Enable
I/O Offset 67-64 – Wr Channel 0 SGD Table Pointer .... RW
31-0 SGD Table Pointer Base Address (even addr).....W
Current Pointer Address ........................................R
I/O Offset 77-74 – Wr Channel 1 SGD Table Pointer ... RW
31-0 SGD Table Pointer Base Address (even addr) .... W
Current Pointer Address ....................................... R
I/O Offset 6F-6C – Wr Channel 0 SGD Current Count .RO
31-24 Current SGD Index
23-0 Current SGD Count
I/O Offset 7F-7C – Wr Channel 1 SGD Current Count . RO
31-24 Current SGD Index
23-0 Current SGD Count
Preliminary Revision 0.8 October 29, 1999
-115-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset E3-E0 – AC97 Controller Command / Status ...... RW
31-30 Codec ID ......................................................... RW
00 Select Primary Codec
01 Select Secondary Codec 01
10 Select Secondary Codec 10
11 -reserved........................................ always reads 0
29 Reserved
28 AC97 Controller Busy ......................................... RO
0 Primary Codec is ready for a register access
command
1 AC97 Controller is sending a command to the
primary codec (commands are not accepted)
........................................ always reads 0
27 Reserved
26 Secondary Codec 2 Data / Status Valid...........RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
25 Secondary Codec 1 Data / Status Valid...........RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
24 Primary Codec Data / Status Valid .................RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
23 Codec Command Register Read/Write Mode .. RW
0 Select Codec command register write mode
1 Select Codec command register read mode
22-16 Codec Command Register Index [7:1] .............. RW
Index of the AC97 codec command register to access
(in the attached codec). Data must be written before
or at the same time as Index as writing to the index
triggers the AC97 controller to access the addressed
codec register over the AC-link interface.
15-0 Codec Command Register Data / Status ........... RW
W Codec Command Register Data
R Codec Status Register Data
Preliminary Revision 0.8 October 29, 1999
Offset F3-F0 – SGD Status Shadow ................................. RO
........................................always reads 0
31 Reserved
30 Write Chan 1 SGD STOP Shadow........... (Rx70[2])
29 Write Chan 1 SGD EOL Shadow............. (Rx70[1])
28 Write Chan 1 SGD FLAG Shadow .......... (Rx70[0])
........................................always reads 0
27 Reserved
26 Write Chan 0 SGD STOP Shadow........... (Rx60[2])
25 Write Chan 0 SGD EOL Shadow............. (Rx60[1])
24 Write Chan 0 SGD FLAG Shadow .......... (Rx60[0])
-116-
23
22
21
20
19
18
17
16
........................................always reads 0
Reserved
FM Read Chan SGD STOP Shadow ....... (Rx50[2])
FM Read Chan SGD EOL Shadow ......... (Rx50[1])
FM Read Chan SGD FLAG Shadow....... (Rx50[0])
........................................always reads 0
Reserved
3D Read Chan SGD STOP Shadow......... (Rx40[2])
3D Read Chan SGD EOL Shadow........... (Rx40[1])
3D Read Chan SGD FLAG Shadow ........ (Rx40[0])
15
14
13
12
11
10
9
8
........................................always reads 0
Reserved
DX3 Read Chan SGD STOP Shadow ...... (Rx30[2])
DX3 Read Chan SGD EOL Shadow ........ (Rx30[1])
DX3 Read Chan SGD FLAG Shadow ..... (Rx30[0])
........................................always reads 0
Reserved
DX2 Read Chan SGD STOP Shadow ...... (Rx20[2])
DX2 Read Chan SGD EOL Shadow ........ (Rx20[1])
DX2 Read Chan SGD FLAG Shadow ..... (Rx20[0])
7
6
5
4
3
2
1
0
........................................always reads 0
Reserved
DX1 Read Chan SGD STOP Shadow ...... (Rx10[2])
DX1 Read Chan SGD EOL Shadow ........ (Rx10[1])
DX1 Read Chan SGD FLAG Shadow ..... (Rx10[0])
........................................always reads 0
Reserved
DX0 Read Chan SGD STOP Shadow ...... (Rx00[2])
DX0 Read Chan SGD EOL Shadow ........ (Rx00[1])
DX0 Read Chan SGD FLAG Shadow ..... (Rx00[0])
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 5 I/O Base 1 Registers –Audio FM NMI Status
Function 5 I/O Base 2 Registers –MIDI / Game Port
I/O Offset 0 – FM NMI Status ..........................................RO
........................................ always reads 0
7-2 Reserved
1-0 FM NMI Status
00 Undefined
01 OPL3 Bank 0
10 OPL3 Bank 1
11 Undefined
I/O Offset 1-0 – MIDI Port Base ..................................... RW
15-0 MIDI Port Base Address.................. default = 0330h
This register is functional only if Rx42[7] = 1
I/O Offset 3-2 – Game Port Base ..................................... RW
15-0 Game Port Base Address ................. default = 0200h
I/O Offset 1 – FM NMI Data .............................................RO
7-0 FM NMI Data
This register allows readback of the data written to
the FM data port
I/O Offset 2 – FM NMI Index ...........................................RO
7-0 FM NMI Index
This register allows readback of the data written to
the FM index port
Preliminary Revision 0.8 October 29, 1999
-117-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Function 6 I/O Base 0 Regs –Modem Scatter/Gather DMA
I/O Offset 0 – Modem Read Channel SGD Status ....... RWC
7
SGD Active (0 = completed or terminated)........RO
6
SGD Paused ..........................................................RO
........................................ always reads 0
5-4 Reserved
3
SGD Trigger Queued (transaction will restart after
EOL)
..........................................................RO
2
SGD Stopped ........................................................RO
1
SGD EOL ......................................................RWC
0
SGD Flag ......................................................RWC
I/O Offset 10 – Modem Write Channel SGD Status ... RWC
7
SGD Active (0 = completed or terminated) .......... RO
6
SGD Paused ......................................................... RO
........................................always reads 0
5-4 Reserved
3
SGD Trigger Queued (transaction will restart after
EOL)
......................................................... RO
........................................always reads 0
2
Reserved
1
SGD EOL (clear interrupt if Rx62[1] is set)..... RWC
0
SGD Flag (clear interrupt if Rx62[0] is set) ..... RWC
I/O Offset 1 – Modem Read Channel SGD Control ....... RW
7
SGD Trigger ........................... WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate ...................... WO (always reads 0)
0 No effect
1 Terminate SGD Operation
5-4 Reserved (Do Not Program)............always write 0’s
3
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
2-0 Reserved (No Function)...................................... RW
I/O Offset 11 – Modem Write Channel SGD Control ... RW
7
SGD Trigger............................WO (always reads 0)
0 No effect
1 Trigger SGD Operation
6
SGD Terminate.......................WO (always reads 0)
0 No effect
1 Terminate SGD Operation
........................................always reads 0
5-4 Reserved
3
SGD Pause
0 Release SGD pause and resume the transfer
from the paused line
1 Pause SGD read operation (SGD pointer stays
at the current address)
........................................always reads 0
3-2 Reserved
I/O Offset 2 – Modem Read Channel SGD Type ............ RW
7
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
........................................ always reads 0
6-4 Reserved
3-2 Interrupt Select
00 Interrupt at last line PCI read
01 Interrupt at last sample sent
10 Interrupt at less than one line to send
11 -reserved1
Interrupt on EOL @ End of Block
0 Disable ...................................................default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable ...................................................default
1 Enable
I/O Offset 12 – Modem Write Channel SGD Format .... RW
7
Auto Restart
0 Stop SGD Operation at EOL
1 Restart SGD Operation at EOL
........................................always reads 0
6-2 Reserved
1
Interrupt on EOL @ End of Block
0 Disable................................................... default
1 Enable
0
Interrupt on FLAG @ End-of-Blk
0 Disable................................................... default
1 Enable
I/O Offset 7-4 – Modem SGD Read Table Pointer ......... RW
31-0 SGD Table Pointer Base Address (even addr).....W
Current Pointer Address ........................................R
I/O Offset 17-14 – Modem Wr Chan SGD Table Ptr .... RW
31-0 SGD Table Pointer Base Address (even addr) .... W
Current Pointer Address ....................................... R
I/O Offset 1F-1C – Modem Wr Chan SGD Current CntRO
31-24 Current SGD Index
23-0 Current SGD Count
I/O Offset F-C – Modem SGD Current Read Count.......RO
........................................ always reads 0
31-24 Reserved
23-0 Current SGD Read Count
Preliminary Revision 0.8 October 29, 1999
-118-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Offset 23-20 –Modem Codec Command / Status ............ RW
31-30 Codec ID ......................................................... RW
00 Select Primary Codec
01 Select Secondary Codec 01
10 Select Secondary Codec 10
11 -reserved........................................ always reads 0
29-24 Reserved
28 AC97 Controller Busy ......................................... RO
0 Primary Codec is ready for a register access
command
1 AC97 Controller is sending a command to the
primary codec (commands are not accepted)
........................................ always reads 0
27 Reserved
26 Secondary Codec 2 Data / Status Valid...........RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
25 Secondary Codec 1 Data / Status Valid...........RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
24 Primary Codec Data / Status Valid .................RWC
0 Not Valid
1 Valid (OK to Read bits 0-23)
23 Codec Command Register Read/Write Mode .. RW
0 Select Codec command register write mode
1 Select Codec command register read mode
22-16 Codec Command Register Index [7:1] .............. RW
Index of the AC97 codec command register to access
(in the attached codec). Data must be written before
or at the same time as Index as writing to the index
triggers the AC97 controller to access the addressed
codec register over the AC-link interface.
15-0 Codec Command Register Data / Status ........... RW
W Codec Command Register Data
R Codec Status Register Data
Preliminary Revision 0.8 October 29, 1999
Offset 33-30 – Codec GPI Interrupt Status / GPIO .... RWC
31-16 GPI Interrupt Status ........................................ RWC
R GPI[15-0] Interrupt Status
W 1 to clear
15-0 Codec GPIO .........................................................RW
R Reflect status of Codec GPI[15-0]
W GPO[15-0]; triggers AC-Link slot-12 output to
codec
Offset 37-34 – Codec GPI Interrupt Enable ................... RW
31-16 Interrupt on GPI[15-0] Change of Status..........RW
0 Disable
1 Enable
........................................always reads 0
15-0 Reserved
-119-
Function 5 & 6 Registers - AC97 Audio & Modem Codecs
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Processor Bus States
FUNCTIONAL DESCRIPTIONS
The VT8231 supports the complete set of C0 to C3 processor
states as specified in the Advanced Configuration and Power
Interface (ACPI) specification (and defined in ACPI I/O space
Registers 10-15):
Power Management
Power Management Subsystem Overview
C0:
C1:
C2:
The power management function of the VT8231 is indicated in
the following block diagram:
*3
'HYLFH
,GOH
7LPHU
60, (YHQWV
6&,60, (YHQWV
:DNHXS (YHQWV
3ULPDU\
(YHQWV
*3
*OREDO
6WDQGE\
7LPHU
3:5%71
6/3%71
+DUGZDUH
0RQLWRULQJ
/,'
7+50
5,
86% UHVXPH
*3,2
8VHU
,QWHUIDFH
C3:
6&,B(1
'HF
60, $UELWHU
60,
6&, $UELWHU
6&,
%XV
0DVWHU
6OHHS:DNH
6WDWH
0DFKLQH
+DUGZDUH
(YHQWV
&38
673&/.
DQG &ON*HQ
&RQWURO
57&
30 7LPHU
3RZHU
3ODQH DQG
6\VWHP
&RQWURO
Normal Operation
CPU Halt (controlled by software).
Stop Clock. Entered when the P_LVL2 register is
read. The STPCLK# signal is asserted to put the
processor in the Stop Grant State. The CPUSTP#
signal is not asserted so that host clocks remain
running.
To exit this state, the chip negates
STPCLK#.
Suspend. Entered when the P_LVL3 register is read.
In addition to STPCLK# assertion as in the C2 state,
the SUSST1# (suspend status 1) signal is asserted to
tell the north bridge to switch to “Suspend DRAM
Refresh” mode based on the 32KHz suspend clock
(SUSCLK) provided by the VT8231.
If the
HOST_STP bit is enabled, then CPUSTP# is also
asserted to stop clock generation and put the CPU
into Stop Clock State. To exit this state, the chip
negates CPUSTP# and allows time for the processor
PLL to lock. Then the SUSST1# and STPCLK#
signals are negated to resume to normal operation.
During normal operation, two mechanisms are provided to
modulate CPU execution and control power consumption by
throttling the duty cycle of STPCLK#:
a.
b.
/HJDF\ 2QO\ (YHQW /RJLF
$&3, /HJDF\ (YHQW /RJLF
$&3, /HJDF\ *HQHULF &RQWURO )HDWXUHV
$&3, /HJDF\ )L[HG &RQWURO )HDWXUHV
$&3, 2QO\ (YHQW /RJLF
Setting the THT_EN bit to 1, the duty cycle
defined in THT_DTY (IO space Rx10) is used.
THRM# pin assertion enables automatic clock
throttling with duty cycle pre-configured in
THM_DTY (PCI configuration Rx4C).
Figure 6. Power Management Subsystem Block Diagram
Refer to ACPI Specification v1.0 and APM specification v1.2
for additional information.
Preliminary Revision 0.8 October 29, 1999
-120-
Functional Descriptions
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
System Suspend States and Power Plane Control
There are three power planes inside the VT8231. The first
power plane (VCCS) is always on unless turned off by the
mechanical switch. The second power plane (VCC) is
controlled by chip output SUSC# (also called “PSON”). The
third plane (VCCRTC) is powered by the combination of the
VCCS and the external battery (VBAT) for the integrated real
time clock. Most of the circuitry inside the VT8231 is
powered by VCC. The amount of logic powered by VCCS is
very small; its main function is to control the supply of VCC
and other power planes. VCCRTC is always on unless both the
mechanical switch and VBAT are removed.
The VT8231 supports multiple system suspend states by
configuring the SLP_TYP field of ACPI I/O space register
Rx4-5:
a)
b)
c)
d)
POS (Power On Suspend): Most devices in the
system remain powered. The host bus is put into an
equivalent of the C3 state. In particular, the CPU is
put into the Stop Grant State or Stop Clock State
depending on the setting of the HOST_STP bit.
SUSST1# is asserted to tell the north bridge to switch
to “Suspend DRAM Refresh” mode based on the
32KHz SUSCLK provided by the VT8231. As to the
PCI bus, setting the PCLK_RUN bit to 0 enables the
CLKRUN protocol defined in the PCI Mobile Design
Guide. That is, the PCKRUN# pin will be deactivated after the PCI bus is idle for 26 clocks. Any
PCI bus masters including the north bridge may
resume PCI clock operation by pulling the
PCKRUN# pin low. During the PCKRUN# deactivation period, the PCISTP# pin may be activated
to disable the output of the PCI clock generator if the
PCI_STP bit is enabled. When the system resumes
from POS, the VT8231 can optionally resume
without resetting the system, can reset the processor
only, or can reset the entire system. When no reset is
performed, the chip only needs to wait for the clock
synthesizer and processor PLL to lock before the
system is resumed, which typically takes 20ms.
STR (Suspend to RAM): Power is removed from
most of the system except the system DRAM. Power
is supplied to the suspend refresh logic in the north
bridge (VTT of VT82C598) and the suspend logic of
the VT8231 (VCCS). The VT8231 provides a
32KHz suspend clock to the north bridge for it to use
to continue DRAM refresh.
STD (Suspend to Disk, also called Soft-off): Power
is removed from most of the system except the
suspend logic of VT8231 (VCCS).
Mechanical Off: This is not a suspend state. All
power in the system is removed except the RTC
battery.
SUSC#) are provided to turn off more system power planes as
the system moves to deeper power-down states, i.e., from
normal operation to POS (only SUSA# asserted), to STR (both
SUSA# and SUSB# asserted), and to STD (all three SUS#
signals asserted). In particular, the assertion of SUSC# can be
used to turn off the VCC supply to the VT8231.
One additional suspend status indicator (SUSST1#) is
provided to inform the north bridge and the rest of the system
of the processor and system suspend states. SUSST1# is
asserted when the system enters the suspend state or the
processor enters the C3 state. SUSST1# is connected to the
north bridge to switch between normal and suspend-DRAMrefresh modes.
General Purpose I/O Ports
As ACPI compliant hardware, the VT8231 includes
PWRBTN#, SLPBTN#, and RI# pins to implement power
button, sleep button, and ring indicator functionality,
respectively. Furthermore, the VT8231 offers many generalpurpose I/O ports with the following capabilities:
I2C/SMB Support
Thermal Detect
Notebook Lid Open/Close Detect
Battery Low Detect
Twelve General Purpose Input Ports (multiplexed with
other functions).
• Nineteen General Purpose Output Ports (1 dedicated
and 18 multiplexed with other functions)
• Four General Purpose Input / Output Ports
(multiplexed with other functions)
In addition, the VT8231 provides an external dedicated SMI
pin (EXTSMI#). The external SMI input can be programmed
to trigger an SCI or SMI at both the rising and falling edges of
the corresponding input signal. Software can check the status
of the input pin and take appropriate actions.
•
•
•
•
•
The suspend state is entered by setting the SLP_EN bit to 1.
Three power plane control signals (SUSA#, SUSB# and
Preliminary Revision 0.8 October 29, 1999
-121-
Functional Descriptions
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
3) Generic Global Events defined in the GBL_STS and
GBL_EN registers. These registers are mainly used for
SMI:
Power Management Events
Three types of power management events are supported:
1) ACPI-required Fixed Events defined in the PM1a_STS
and PM1a_EN registers. These events can trigger either
SCI or SMI depending on the SCI_EN bit:
•
•
•
•
•
•
•
•
•
•
PCI Bus Clock Run Resume
Primary Interrupt Occurance
GP0 and GP1 Timer Time Out
Secondary Event Timer Time Out
Occurrence of Primary Events
(defined in register PACT_STS and PACT_EN)
• Legacy USB accesses (keyboard and mouse)
- Software SMI
PWRBTN# Triggering
RTC Alarm
Sleep Button
ACPI Power Management Timer Carry (always SCI)
BIOS Release (always SCI)
2) ACPI-aware General Purpose Function Events defined
in the GP_STS and GP_SCI_EN, and GP_SMI_EN
registers. These events can trigger either SCI or SMI
depending on the setting of individual SMI and SCI
enable bits:
•
•
•
•
•
•
System and Processor Resume Events
Depending on the system suspend state, different features can
be enabled to resume the system. There are two classes of
resume events:
a)
External SMI triggering
USB Resume
Ring Indicator (RI#)
Battery Low Detect (BATLOW#)
Notebook Lid Open/Close Detect (LID)
Thermal Detect (THRM#)
b)
Host CPU
VCCS-based events. Event logic resides in the
VCCS plane and thus can resume the system from
any suspend state. Such events include PWRBTN#,
RI#, BATLOW#, LID, SMBus resume event, RTC
alarm, EXTSMI#, and GP1 (EXTSMI1#).
VCC-Based Events. Event logic resides in the VCC
plane and thus can only resume the system from the
POS state. Such events include the ACPI PM timer,
USB resume, and EXTSMIn#.
HCLK
SMI# / STPCLK#
CPU Bus
L2 Cache
(Socket-7 Only)
Memory Bus
FPG, EDO, or
SDRAM
(SDR or DDR)
SMIACT#
3D
Graphics
Controller
GCLK
AGP Bus
GCKRUN#
PCKRUN#
PCLK
PCI Bus
ISA
IDE
BIOS ROM
USB
Keyboard / Mouse
VT82C598
(Apollo MVP3)
or
VT82C693
(Apollo ProPlus)
CKE#
HCLK
GCLK
PCLK
Module ID
SUSCLK,
SUSST1#
VT82C686A
Super South
MCLK
CPUSTP#
PCISTP#
SMBus
Clock
Generator
GPIO and ACPI Events
Power Plane & Peripheral Control
Figure 7. System Block Diagram Using the VT8231 Super South Bridge
Preliminary Revision 0.8 October 29, 1999
-122-
Functional Descriptions
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Legacy Power Management Timers
In addition to the ACPI power management timer, the VT8231
includes the following four legacy power management timers:
GP0 Timer: general purpose timer with primary event
GP1 Timer: general purpose timer with peripheral event
reload
Secondary Event Timer: to monitor secondary events
Conserve Mode Timer: Hardware-controlled return to
standby
The normal sequence of operations for a general purpose timer
(GP0 or GP1) is to
1) First program the time base and timer value of the initial
count (register GP_TIM_CNT).
2) Then activate counting by setting the GP0_START or
GP1_START bit to one: the timer will start with the
initial count and count down towards 0.
3) When the timer counts down to zero, an SMI will be
generated if enabled (GP0TO_EN and GP1TO_EN in the
GBL_EN register) with status recorded (GP0TO_STS and
GP1TO_STS in the GBL_STS register).
4) Each timer can also be programmed to reload the initial
count and restart counting automatically after counting
down to 0. This feature is not used in standard VIA
BIOS.
The GP0 and GP1 timers can be used just as the general
purpose timers described above. However, they can also be
programmed to reload the initial count by system primary
events or peripheral events thus used as primary event (global
standby) timer and peripheral timer, respectively.
The
secondary event timer is solely used to monitor secondary
events.
System Primary and Secondary Events
Primary system events are distinguished in the PRI_ACT_STS
and PRI_ACT_EN registers:
Bit Event
7 Keyboard Access
6 Serial Port Access
Trigger
I/O port 60h
I/O ports 3F8h-3FFh, 2F8h-2FFh,
3E8h-3EFh, or 2E8h-2EFh
5 Parallel Port Access I/O ports 378h-37Fh or 278h-27Fh
4 Video Access
I/O ports 3B0h-3DFh or memory
A/B segments
3 IDE/Floppy Access I/O ports 1F0h-1F7h, 170h-177h,
or 3F5h
2 Reserved
1 Primary Interrupts Each channel of the interrupt
controller can be programmed to
be a primary or secondary
interrupt
0 ISA Master/DMA Activity
Each category can be enabled as a primary event by setting the
corresponding bit of the PRI_ACT_EN register to 1. If
enabled, the occurrence of the primary event reloads the GP0
Preliminary Revision 0.8 October 29, 1999
timer if the PACT_GP0_EN bit is also set to 1. The cause of
the timer reload is recorded in the corresponding bit of
PRI_ACT_STS register while the timer is reloaded. If no
enabled primary event occurs during the count down, the GP0
timer will time out (count down to 0) and the system can be
programmed (setting the GP0TO_EN bit in the GBL_EN
register to one) to trigger an SMI to switch the system to a
power down mode.
The VT8231 distinguishes two kinds of interrupt requests as
far as power management is concerned: the primary and
secondary interrupts.
Like other primary events, the
occurrence of a primary interrupt demands that the system be
restored to full processing capability. Secondary interrupts,
however, are typically used for housekeeping tasks in the
background unnoticeable to the user. The VT8231 allows
each channel of interrupt request to be declared as either
primary, secondary, or ignorable in the PIRQ_CH and
SIRQ_CH registers. Secondary interrupts are the only system
secondary events defined in the VT8231.
Like primary events, primary interrupts can be made to reload
the GP0 timer by setting the PIRQ_EN bit to 1. Secondary
interrupts do not reload the GP0 timer. Therefore the GP0
timer will time out and the SMI routine can put the system into
power down mode if no events other than secondary interrupts
are happening periodically in the background.
Primary events can be programmed to trigger an SMI (setting
of the PACT_EN bit). Typically, this SMI triggering is turned
off during normal system operation to avoid degrading system
performance. Triggering is turned on by the SMI routine
before entering the power down mode so that the system may
be returned to normal operation at the occurrence of primary
events. At the same time, the GP0 timer is reloaded and the
count down process is restarted.
Peripheral Events
Primary and secondary events define system events in general
and the response is typically expressed in terms of system
events. Individual peripheral events can also be monitored by
the VT8231 through the GP1 timer. The following four
categories of peripheral events are distinguished (via register
GP_RLD_EN):
Bit-7 Keyboard Access
Bit-6 Serial Port Access
Bit-4 Video Access
Bit-3 IDE/Floppy Access
The four categories are subsets of the primary events as
defined in PRI_ACT_EN and the occurrence of these events
can be checked through a common register PRI_ACT_STS.
As a peripheral timer, GP1 can be used to monitor one (or
more than one) of the above four device types by programming
the corresponding bit to one and the other bits to zero. Time
out of the GP1 timer indicates no activity of the corresponding
device type and appropriate action can be taken as a result.
-123-
Functional Descriptions
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Min
Max
Unit
-55
125
oC
TS
Operating temperature - Case
0
85
oC
TC
Operating temperature - Ambient
0
70
oC
TA
Reference Voltage
0
5.5
Volts
VREF
Core Voltage
0
3.6
Volts
VCC
Suspend Voltage
-0.5
VCC + 0.3
Volts
VSUS
USB Voltage
-0.5
VCC + 0.3
Volts
VUSB
Hardware Monitor Voltage
-0.5
VCC + 0.3
Volts
VHWM
LAN MII Voltage
-0.5
VCC + 0.3
Volts
VMII
LAN RAM Voltage
-0.5
VCC + 0.3
Volts
VRAM
PLL Voltage
-0.5
VCC + 0.3
Volts
VPLL
Battery Voltage
-0.5
VCC + 0.3
Volts
VBAT
Input voltage (3.3V only inputs)
-0.5
VCC + 0.3
Volts
FERR#, USBCLK, PWRBTN#,
EXTSMI#, BATLOW#, FAN1,
FAN2, SMBCLK, SMBDATA
Input voltage (5V tolerant inputs)
-0.5
VREF + 0.5
Volts
All other inputs
Storage temperature
Comment
Note: Stress above the conditions listed may cause permanent damage to the device. Functional
operation of this device should be restricted to the conditions described under operating
conditions.
DC Characteristics
TA -0-70oC, VREF=5V ±5%,, VBAT=3.3V +0.3/-1.3V, GND=0V
VCC=VCCSUS=VCCHWM=VCCUSB=VCCMII=VCCRAM=VCCPLL=3.3V ±0.3V
Symbol
Parameter
Min
Max
Unit
VIL
Input low voltage
-0.5
0.8
V
VIH
Input high voltage
2.0
VCC+0.3
V
VOL
Output low voltage
-
0.45
V
IOL = 4.0mA
VOH
Output high voltage
2.4
-
V
IOH = -1.0mA
IIL
Input leakage current
-
±10
uA
0 < VIN < VCC
IOZ
Tristate leakage current
-
±20
uA
0.45 < VOUT < VCC
ICC
Power supply current
-
80
mA
Preliminary Revision 0.8 October 29, 1999
-124-
Condition
Electrical Specifications
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
Output Drive
TA -0-70oC, VREF=5V ±5%,, VBAT=3.3V +0.3/-1.3V, GND=0V
VCC=VCCSUS=VCCHWM=VCCUSB=VCCMII=VCCRAM=VCCPLL=3.3V ±0.3V
Drive
4 mA
8 mA
12 mA
16 mA
PCI
Signal
Load
Delay
GPO0, GPIOA, GPIOC, GPIOD, GPIOE, EECS#, EECK, EEDO, APICD[1:0],
SMBCK1, SMBCK2, SMBDT1, SMBDT2,
SUSA#, SUSB#, SUSC#, SUSCLK, SUSST1#,
A20M#, INIT, INTR, NMI, ROMCS#, STPCLK#, CPURST, SMI#, IGNNE#, SLP#,
TXD, RTS#, DTR#, IRTX
KBDT, KBCK, MSDT, MSCK,
PCISTP#, CPUSTP#,
SD[15:0], PDD[15:0], SDD[15:0],
MDCK, MDIO, MTXENA, MTXD[3:0],
PREQL#, PREQH#
PDCS1#, PDCS3#, SDCS1#, SDCS3#, PDA[2:0], SDA[2:0],
PDDACK#, SDDACK#, PDIOR#, PDIOW#, SDIOR#, SDIOW#
LA[21:20], SA[19:0], MEMR#, MEMW#, IOR#, IOW#, PCIRST#
AD[31:0],
CBE[3:0]#, FRAME#, DEVSEL#, IRDY#, TRDY#, STOP#, PAR, PCKRUN#
LFRAME#, LAD[3:0], USBP[3:0]+/ACRST, ACSYNC, ACSDOUT, MSO
PCS0#, PCS1#, MCCS#, SPKR
DRVDEN[1:0], MTR[1:0]#, DS[1:0]#, DIR#, STEP#, HDSEL#, WDATA#, WGATE#
PINIT#, STROBE#, AUTOFD#, SLCTIN#, PD[7:0]
RTCX2
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
30 pF
40 pF
40 pF
85 pF
50 pF
50 pF
15 ns
15 ns
15 ns
15 ns
15 ns
10 ns
8 ns
8 ns
8 ns
6 nS
8 ns
8 ns
10 ns
6 ns
5 ns
Input Voltage
TA -0-70oC, VREF=5V ±5%,, VBAT=3.3V +0.3/-1.3V, GND=0V
VCC=VCCSUS=VCCHWM=VCCUSB=VCCMII=VCCRAM=VCCPLL=3.3V ±0.3V
Input Voltage
Analog
1.5 – 3.3V Programmable Threshold
5V
3.3V (5V Tolerant)
3.3 V
Signal
DTD+/-, UIC[5:1]
FERR#
AD[31:0], CBE[3:0]#, FRAME#, DEVSEL#, IRDY#, TRDY#, STOP#, SERR#,
PAR, SERIRQ, PCKRUN#
PGNTH#, PGNTL#, PINT[A:D]#,
SA[19:0], SD[15:0], MEMR#, MEMW#, IOR#, IOW#, OSC,
PDD[15:0], SDD[15:0], PDDRQ, SDDRQ, PDRDY, SDRDY, IRQ14, IRQ15,
KBCK, KBDT, MSCK, MSDT, GAMED[7:0],
INDEX#, TRK00#, RDATA#, DSKCHG#, WRTPRT#, PD[7:0],
PINIT#, STROBE#, AUTOFD#, SLCTIN#, SLCT, ACK#, ERROR#, BUSY, PE,
RXD, CTS#, DSR#, DCD#, RI#, IRRX, IRRX2,
SMBCK1, SMBCK2, SMBDT1, SMBDT2, SMBALRT#,
MCOL, MCRS, MDIO, MRXCLK, MRXD[3:0], MRXDV, MRXERR, MTXCLK,
MSI, ACSDIN[2:0], ACBITCLK,
GPIOA, GPIOC, GPIOD, GPIOE, GPI0, GPI1, PWRGD, BATLOW#, THRM
USBP[3:0]+/-, USBCLK, USBOC[1:0]#, LDRQ#, LAD[3:0], EEDI,
PCICLK, APICCLK, WSC#, FAN1, FAN2 / SLPBTN#, PWRBTN#, RTCX1,
EXTSMI#, RSMRST#, PME#, LID, RING#, CPUMISS, INTRUDER#
Preliminary Revision 0.8 October 29, 1999
-125-
Electrical Specifications
VT8231
:H &RQQHFW
7HFKQRORJLHV ,QF
PACKAGE MECHANICAL SPECIFICATIONS
Pin #1 Corner
Y
W
V
R
L
= Date Code Year
= Date Code Week
= Chip Version
= Revision Code
= Lot Code
<<::997$,:$1
//5//////‹0
24.00 Ref.
97
4.00*45°(4X)
Ø 1.00 (3X) Ref.
24.00 Ref.
Ø 0.75±0.15 (376X)
Reference Document: JEDEC Spec MO-151
Figure 8. Mechanical Specifications – 376 Pin Ball Grid Array Package
Preliminary Revision 0.8 October 29, 1999
-126-
Package Mechanical Specifications