TI UCD9240RGCT

UCD9240
SLUS766 – APRIL 2007
UCD9240 Digital Point of Load
System Controller
FEATURES
• Controls up to 8 power stages and up to 4
voltage feedback control loops.
• Supports PMBus version 1.1.
• Flexible configuration, device can control:
o Four single or dual power stages,
o Two 4-phase power stages, or
o One 2,4,6, or 8-phase power stage.
• Supports switching frequencies up to 2MHz.
• Supports conversion ratio of 12 to 1 at 2MHz
with 250 psec duty-cycle resolution.
• +/-1mV feed-back resolution.
• Hardware accelerated digital 3-pole/3-zero
compensator.
• Internal regulator drives an external pass
element, giving a wide supply voltage range.
• 12-bit digital monitoring of power supply
parameters, including:
o Vin,
o Vout, each rail,
o Iout, each power stage (phase),
o External Temperature, each stage.
• Multiple levels of current fault protection:
o External current fault inputs,
o Fast analog comparators monitor
current sense voltage,
o Digital current sense monitor of
average current.
• Eight Synchronous Rectifier Enable (SRE)
outputs.
• Able to synchronize PWM clocks between
multiple UCD9240 devices.
• Enhanced non-volatile memory with ECC
• Programmable soft start and soft stop ramps
under closed loop control.
• Supports multiple soft-start and soft-stop
configuration including pre-bias start-up.
• Supports voltage tracking.
• Supports current sharing on multi-phase
power stages.
• Supports phase shedding on multi-phase
power stages based on average current.
• Programmable fan control outputs.
• Programmable margining and sequencing.
• Power+ Designer, a full featured PC based
design tool to simulate, configure, and
monitor power supply performance.
APPLICATIONS
•
•
•
•
•
Industrial / ATE
Networking Equipment
Servers
Storage Systems
Telecommunications Equipment
DESCRIPTION
The UCD9240 is a digital synchronous buck PWM
controller that can control up to 8 power stages in
multi-phase configuration or up to 4 feedback
outputs with two phases per output. This device
provides enhanced configurability and control for
point of load (POL) applications. The device is
configured via PMBus with the Power+ Designer
GUI.
The switching frequency, output configuration and
feedback compensation are programmed through
the Power+ Designer. This allows the UCD9240 to
support multiple converter arrangements and to meet
dynamic converter performance for a broad range of
POL applications.
Each high speed digital control loop has a dedicated
3-pole/3-zero compensator and 250ps PWMs. This
architecture enables wide input to output voltage
conversion ratio’s at switching frequency of up to
2MHz.
Additionally, the UCD9240 is able to monitor and
manage power supply operating conditions and
report the status to the host system through the
PMBus. The management parameters are
configurable through the Power+ Designer. The
design tool allows the power supply designer to
easily configure the control loop characteristics and
generate the expected performance by displaying
Bode plots for each controlled power stage.
On multi-phase power stage outputs, the UCD9240
incorporates current balancing. The average current
in each phase is monitored and the duty cycle for
each phase adjusted to balance the average current.
In addition, the UCD9240 supports "shedding" one or
more phases (ganged power stages) commanded
through PMBus or by average current demand.
When a phase is dropped or added the UCD9240
automatically adjusts the phase of each PWM output
to minimize output ripple as well as any needed
change in loop compensation.
Copyright © 2007, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
1
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
FUNCTIONAL BLOCK DIAGRAM
Fusion Power Peripherals
16
EAP4
EAP4
EAN4
EAN4
EAP3
EAP3
EAN3
EAN3
EAP2
EAP2
EAN2
EAN2
Error ADC
EAP1
EAP1
EAN1
EAN1
Diff
Amp
Digital
High Res
PWM
DPWMDPWM-4A
DPWM--4B
DPWM
FAULTFAULT-4A
FAULT--4B
FAULT
DPWMDPWM-3A
DPWM--3B
DPWM
FAULT--3A
FAULT
FAULTFAULT-3B
DPWMDPWM-2A
DPWM--2B
DPWM
FAULTFAULT-2A
FAULT--2B
FAULT
Compensator
EA
Ref
Digital
High Res
PWM
16
Compensator
3P/3Z IIR
6
Error ADC
16
Compensator
3P/3Z IIR
6
Error ADC
Digital
High Res
PWM
Compensator
3P/3Z IIR
6
Error ADC
6
ADC
6 bit
IIR
3P/3Z
16
Coeff.
Coeff.
Regs
Digital
High Res
PWM
DPWMDPWM-1A
DPWM--1B
DPWM
FAULT--1A
FAULT
FAULTFAULT-1B
SYNCSYNC-IN
SYNC -OUT
5
PWR
6
GND
BPCAP
ADDRADDR-00
ADDRADDR-01
CSCS-1A
CSCS-1B
CS2
CS2A
CSCS-2B
CSCS-3A
CSCS-3B
CSCS-4A
CSCS-4B
VIN
Vtrack
Temperature
ADC
Analog Comparators
TRIP1
Ref 1
12 bit
200 ksps
Flash
memory
with ECC
ARMARM-7
core
TRIP2
Ref 2
TRIP3
Ref 3
Vreg
Osc
TRIP4
ADCREFIN
2
SRE
control
SRESRE-4B
SRESRE-4A
SRESRE-3B
SRESRE-3A
SRESRE-2B
SRESRE-2A
SRESRE-1B
SRESRE-1A
Ref 4
POR/BOR
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PMBus
PMBusPMBus-Clk
PMBus--Data
PMBus
PMBus--Alert
PMBus
PMBusPMBus-Cntl
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
64-PIN AND 80-PIN I/O ASSIGNMENTS
UCD9240-64pin
50
51
52
53
54
55
56
57
61
60
59
3
2
1
63
62
4
5
6
EAp1
EAn1
EAp2
EAn2
EAp3
EAn3
EAp4
EAn4
AddrSens0
AddrSens1
CS-1A (COMP1)
CS-2A (COMP2)
CS-3A (COMP3)
CS-4A (COMP4)
CS-1B
CS-2B
Vin
Vtrack
Temp
DPWM-1A
DPWM-1B
DPWM-2A
DPWM-2B
DPWM-3A
DPWM-4A
FAULT-1A
FAULT-1B
FAULT-2A
FAULT-2B
FAULT-3A
FAULT-4A
SRE-1A
SRE-1B
SRE-2A
SRE-2B
SRE-3A
SRE-4A
17
18
19
20
21
23
UCD9240-80pin
62
63
64
65
66
67
68
69
11
12
13
14
25
34
77
76
75
4
3
2
79
78
74
73
5
6
7
72
71
1
22
24
33
35
29
30
31
TMUX-0
32
TMUX-1
42
PMBus-Clk
TMUX-2
PMBus-Data
41
FAN-PWM
PMBus-Alert
36
(TCLK) FAN-TACH
PMBus-Ctrl
38
PowerGood (TMS)
(TDI) SYNC-IN
37
(TDO) SYNC-OUT
9 -RESET
40
-TRST
10
RCK
15
16
27
28
39
EAp1
EAn1
EAp2
EAn2
EAp3
EAn3
EAp4
EAn4
AddrSen0
AddrSen1
CS-1A (COMP1)
CS-2A (COMP2)
CS-3A (COMP3)
CS-4A (COMP4)
CS-1B
CS-2B
CS-3B
CS-4B
Vin
Vtrack
Temp
n/a
n/a
ADCref
39
TMUX-1
40
TMUX-2
54
TMUX-3
19
20
35
36
32
PMBus-Clk
PMBus-Data
PMBus-Alert
PMBus-Ctrl
PowerGood
13 -RESET
DPWM-1A
DPWM-1B
DPWM-2A
DPWM-2B
DPWM-3A
DPWM-3B
DPWM-4A
DPWM-4B
FAULT-1A
FAULT-1B
FAULT-2A
FAULT-2B
FAULT-3A
FAULT-3B
FAULT-4A
FAULT-4B
SRE-1A
SRE-1B
SRE-2A
SRE-2B
SRE-3A
SRE-3B
SRE-4A
SRE-4B
SYNC-IN
SYNC-OUT
FAN-PWM
FAN-TACH
Diag LED
-TRST
TMS
TDI
TDO
TCK
RCK
21
22
23
24
25
26
27
28
15
16
17
18
29
41
42
43
12
11
10
37
38
52
33
50
31
30
53
49
51
48
47
46
45
44
14
The UCD9240 is available in a plastic 64-pin QFN package (RGC) and an 80-pin TQFP package (PFC).
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3
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
TYPICAL APPLICATION SCHEMATIC
The diagram above shows the UCD9240 Power Supply Controller working in a system which requires the
regulation of four independent power supplies. The loop for each power supply is created by the respective
voltage outputs feeding into the Error ADC differential inputs, and completed by DPWM outputs feeding into the
UCD7230 drivers which are on the PTD08A0x0 modules in the above diagram.
4
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
PIN DESCRIPTIONS
64-Pin Package
Pin
#
signal
80-Pin Package
Pin
#
signal
50
51
52
53
54
55
56
57
EAp1
EAn1
EAp2
EAn2
EAp3
EAn3
EAp4
EAn4
62
63
64
65
66
67
68
69
EAp1
EAn1
EAp2
EAn2
EAp3
EAn3
EAp4
EAn4
I
I
I
I
I
I
I
I
Error Analog, differential voltage, Positive channel #1 input.
Error Analog, differential voltage, Negative channel #1 input.
Error Analog, differential voltage, Positive channel #2 input.
Error Analog, differential voltage, Negative channel #2 input.
Error Analog, differential voltage, Positive channel #3 input.
Error Analog, differential voltage, Negative channel #3 input.
Error Analog, differential voltage, Positive channel #4 input.
Error Analog, differential voltage, Negative channel #4 input.
61
60
59
3
2
1
63
62
4
5
6
AddrSens0
AddrSens1
CS-1A
CS-2A
CS-3A
CS-4A
CS-1B
CS-2B
Vin
Vtrack
Temp
77
76
75
4
3
2
79
78
5
6
7
74
73
72
71
1
AddrSens0
AddrSens1
CS-1A
CS-2A
CS-3A
CS-4A
CS-1B
CS-2B
Vin
Vtrack
Temp
CS-3B
CS-4B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PMBus address sense. Least significant address bits
PMBus address sense. Most significant address bits.
Power stage 1A current sense input, Analog comparator 1.
Power stage 2A current sense input, Analog comparator 2.
Power stage 3A current sense input, Analog comparator 3.
Power stage 4A current sense input, Analog comparator 4.
Power stage 1B current sense input.
Power stage 2B current sense input.
Vin sense input.
Voltage Tracking
Temperature sense input
Power stage 3B current sense input.
Power stage 4B current sense input.
NA analog input
NA analog input
ADC Decoupling Cap Ground reference.
21
22
23
24
25
26
27
28
dPWM-1A
dPWM-1B
dPWM-2A
dPWM-2B
dPWM-3A
dPWM-3B
dPWM-4A
dPWM-4B
O
O
O
O
O
O
O
O
DPWM 1A output.
DPWM 1B output.
DPWM 2A output.
DPWM 2B output.
DPWM 3A output.
DPWM 3B output.
DPWM 4A output.
DPWM 4B output.
15
16
17
18
29
41
42
43
FAULT-1A
FAULT-1B
FAULT-2A
FAULT-2B
FAULT-3A
FAULT-3B
FAULT-4A
FAULT-4B
I
I
I
I
I
I
I
I
External Fault input 1A
External Fault input 1B
External Fault input 2A
External Fault input 2B
External Fault input 3A
External Fault input 3B
External Fault input 4A
External Fault input 4B
12
11
10
37
38
52
33
50
51
SRE-1A
SRE-1B
SRE-2A
SRE-2B
SRE-3A
SRE-3B
SRE-4A
SRE-4B
diag LED
O
O
O
O
O
O
O
O
O
Synchronous Rectifier Enable 1A
Synchronous Rectifier Enable 1B
Synchronous Rectifier Enable 2A
Synchronous Rectifier Enable 2B
Synchronous Rectifier Enable 3A
Synchronous Rectifier Enable 3B
Synchronous Rectifier Enable 4A
Synchronous Rectifier Enable 4B
Diagnostic LED
39
40
54
TMUX-0
TMUX-1
TMUX-2
O
O
O
Temperature multiplexer select S0
Temperature multiplexer select S1
Temperature multiplexer select S2
17
18
19
20
21
dPWM-1A
dPWM-1B
dPWM-2A
dPWM-2B
dPWM-3A
23
dPWM-4A
11
12
13
14
25
FAULT-1A
FAULT-1B
FAULT-2A
FAULT-2B
FAULT-3A
34
FAULT-4A
22
24
33
35
29
SRE-1A
SRE-1B
SRE-2A
SRE-2B
SRE-3A
30
SRE-4A
31
32
42
TMUX-0
TMUX-1
TMUX-2
I/O
ADCref
Description
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5
UCD9240
Digital Point of Load System Controller
41
FAN-PWM
SLUS766 – APRIL 2007
53
49
32
FAN-PWM
PowerGood
FAN-Tach
O
O
I
Fan control PWM output.
Power Good signal
Fan tachometer input
Sync_Out
Sync_In
NC
NC
NC
NC
NC
NC
O
I
O
I
O
I
I/O
I/O
Sync output from DPWM #?.
Sync input to DPWM #?.
No connect
DVss.
No connect
DVss.
No connect or DVss.
No connect or DVss
I
I/O
I/O
O
I
Low Active device reset input.
PMBus Clk (Must have pull-up to 3.3V)
PMBus Data (Must have pull-up to 3.3V)
PMBUS Alert
PMBUS Cntl
10
36
37
38
39
40
NC
FAN-Tach
Sync_Out
Sync_In
PowerGood
NC
30
31
14
44
45
46
47
48
9
15
16
27
28
nRESET
PMBus_Clk
PMBus_Data
PMBus_Alert
PMBus_Cntrl
13
19
20
35
36
nRESET
PMBus_Clk
PMBus_Data
PMBus_Alert
PMBus_Cntrl
58
46
45
7
44
47
V33FB
V33A
V33D
V33DIO
V33DIO
BPCap
70
58
57
8
56
59
V33FB
V33A
V33D
V33DIO
V33DIO
BPCap
I
I
I
I
I
I
3.3V linear regulator Feedback connection.
Analog 3.3 V supply
Digital Core 3.3V supply
Digital I/O 3.3V supply.
Digital I/O 3.3V supply.
1.8V Bypass Capacitor Connection.
49
48
64
8
26
43
AVss
AVss
AVss
DVss
DVss
DVss
61
60
80
9
34
55
AVss
AVss
AVss
DVss
DVss
DVss
I
I
I
I
I
I
Analog Ground.
Analog Ground.
Analog Ground.
Digital Ground.
Digital Ground.
Digital Ground.
6
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
ELECTRICAL SPECIFIACTIONS
Recommended operating conditions
MIN
NOM
MAX
UNIT
V33D,V33DIO,V33A
SYMBOL
Supply voltage during operation
PARAMETER
3.0
3.3
3.6
V
TA
Operating free-air temperature range
-40
125
C
Absolute Maximum Ratings1
Voltage applied at V33D to DVss
-0.3 V to 3.6 V
Voltage applied at V33A to AVss
-0.3 V to 3.6 V
Voltage applied to any pin (see NOTE)
-0.3 V to V33D + 0.3 V
Storage temperature, TSTG
-40C to 150C
Electrical Characteristics
Supply Current
SYMBOL
PARAMETER
TEST CONDITION
I33a
Supply current
V33A = 3.3V
I33dio
Supply current
V33DIO = 3.3V
I33d
Supply current
V33D = 3.3V
I33d
Supply current
V33D = 3.3V storing configuration
parameters in flash memory
MIN
NOM
MAX
UNIT
15
mΑ
mΑ
mΑ
mΑ
40
TBD
Regulator Inputs/Outputs
SYMBOL
PARAMETER
Vreg BPCap
Bypass Capacitor Voltage
V33
3.3V Linear Regulator
V33FB
3.3V linear Reg Feedback
I33FB
Series pass base drive
Beta
Series NPN pass device
TEST CONDITION
MIN
NOM
MAX
1.8
3.25
Vin = 12V
UNIT
V
3.3
3.35
V
4.0
4.6
V
10
mA
40
Bias Supply Generator
Two supply voltages, 3.3 and 1.8 V, are required. An internal series pass regulator generates 1.8 V from the 3.3 V
supply. It requires a 0.1 to 1 uF bypass capacitor from BPCap to ground. The 3.3 V can either be supplied from
an external source, or generated from Vin with regulation circuitry built into the UCD9240 that drives an external
series pass NPN transistor. Transistor beta must be at least 40. The typical application circuit shows the base of
1
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS.
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7
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
the external NPN connected to a pull up resistor and the VD33FB pin. The NPN emitter becomes the 3.3 V
supply for the chip and should be bypassed to ground with 4 to 5 uF.
Analog Inputs/Outputs
PARAMETER
EAPn, EANn
EAP-EAN
MIN
TYP
MAX
UNIT
Vsense Differential
Voltage Range
0.0
0.8
1.6
V
Maximum Vsense
excursion
-0.3
2.0
V
Small Signal Error voltage
resolution
Error Voltage Accuracy
TEST CONDITIONS
during start/stop ramp
during run mode
4.0
1.0
“DAC commanded to be 1V”
.99
Input impedance
ground reference
TBD
Input capacitance
differential
1
mV
mV
1.01
V
ohm
TBD
pF
9
11
uA
0.141
2.50
uA
IBIAS
Bias current
PMBus Addr pins
VADDR
PMBus Address
programming bins
VRANGE: CSxx
voltage range for current
sense input
0
2.5
V
VRANGE: Vin, Vtrack,
Vtemp
input voltage range
0
2.5
V
VOVERCURRENT:
CS1-A, CS2-A,
CS3-A, CS4-A
Analog Overcurrent
Threshold
2.0
CI2
Current Sense Input
capacitance
5
ADCRefIn
External Reference
(80-pin package)
See Table 2
V
10
V33A
pF
(Not currently supported in the Firmware!)
1.8
V
TEST CONDITIONS
MIN
TJ = 25C
100
Years
2
µS
Timing
PARAMETER
Tretention
Retention of configuration
parameters
t(reset)
Pulse length needed at
Reset
TYP
MAX
UNIT
Fault Detection Latency
2
8
t(FAULT)
time to disable PWM
output
High level on FAULT pin
20
nS
t(CLF)
time to disable PWM
output
Step change in CS voltage from 1.0V to
2.5V
20
nS
t(OC)
time to disable PWM
output due to overcurrrent
detection on average KKK
Step change in CS voltage from 50% of
PMBus programmed over-current threshold
to 150% of threshold
800
uS
Not production tested. Limits verified by design.
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
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9
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
Digital Inputs/Outputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Dgnd
+ 0.25
V
VOL
Low-level output voltage
IOH= +6 mA3, V33DIO = 3.0 V
VOH
High-level output voltage
IOH = -6 mA4, V33DIO = 3.0 V
V33dio
– 0.6
V
VIH
High-level input voltage
V33DIO = 3.0 V
2.1
V
VIL
Low-level input voltage
V33DIO = 3.5 V
1.0
V
PMBus/SMBus/I2C
2
The timing characteristics and timing diagram for the communications interface that supports I C, SMBus and
PMBus is shown below.
2
Table 1 I C/SMBus/PMBus Timing Characteristics
TA = -40°C to 85°C, 3.0V < VDD < 3.6V; Typical values at TA = 25°C and VCC = 2.5V (Unless otherwise noted)
PARAMETER
FSMB
SMBus/PMBus operating frequency
2
MIN
Slave mode, SMBC 50% duty cycle
10
10
FI2C
I C operating frequency
Slave mode, SCL 50% duty cycle
FMAS
SMBus master clock frequency
Master mode, No clock low slave extend
TYP
MAX
UNIT
100
kHz
400
kHz
51.2
kHz
t(BUF)
Bus free time between start and stop
4.7
us
t(HD:STA)
Hold time after (repeated) start
4.0
us
t(SU:STA)
Repeated start setup time
4.7
us
t(SU:STO)
Stop setup time
t(HD:DAT)
Data hold time
t(SU:DAT)
Data setup time
t(TIMEOUT)
Error signal/detect
t(LOW)
Clock low period
t(HIGH)
Clock high period
t(LOW:SEXT) Cumulative clock low slave extend time
3
TEST CONDITIONS
4.0
us
Receive Mode
0
ns
Transmit Mode
300
ns
250
See (5) below
25
ns
35
4.7
See (6) below
See (7) below
4.0
us
us
50
us
25
us
t(LOW:MEXT) Cumulative clock low master extend time
See (8) below
10
us
tf
Clock/data fall time
See (9) below
300
ns
tr
Clock/data rise time
See (10) below
1000
ns
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed +/-12 mA to hold the maximum voltage drop specified.
4 The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed +/-48 mA to hold the maximum voltage drop specified.
o
5
The UCD9110 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9110 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
7
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
8
t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
9
Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
10
Fall time tf = 0.9VDD to (VILMAX – 0.15)
6
10
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
The coefficients of the filter sections are generated thru modeling the power stage and load in the Power+
Designer. Several banks of filter coefficients can be downloaded to the device which can automatically switch
them based on on the operation of the power stage.
Figure 1 I2C/SMBus/PMBus Timing Diagram
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11
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
FUNCTION OVERVIEW
The UCD9240 contains four Fusion Power Peripherals (FPP). Each FPP can be configured to drive from one to
eight power stages. Each FPP consists of differential feedback input, circuits used to set the output regulation
voltage, error measurement circuits, digital hardware accelerated for a 3-pole/3-zero compensator and a digital
PWM engine. Each controller is configured through a PMBus serial interface.
PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
2
interface, which is built on I C physical specification. The UCD9240 supports the interface through dedicated
hardware and firmware in the ARM-7 digital supervisory processor.
The UCD9240 supports revision 1.1 of the PMBus standard. Wherever possible, standard PMBus commands are
used to support the function of the device. For unique features of the UCD9240, MFR_SPECIFIC commands are
defined to configure or activate those features.
The firmware for the UCD9240 is PMBus compliant, in accordance with the "Compliance" section of the PMBus
specification. The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus
ALERT function. The hardware can support either 100 kHz or 400 kHz signaling, though at present the firmware
defaults to 100 kHz.
PMBus Address Decode via ADC12 Reading
Two pins are allocated to decode the PMBus address. At power-up the device applies IBIAS to each address detect
pin and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is calculated as
follows.
PMBus Address = 12*bin(VAD01) + bin(VAD00)
Where bin(VAD0x) is the address bin for one of 12 address as shown in
12
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
Table 2
AddrSens0,
AddrSens1
pin
Vdd
IBIAS
On/Off Control
Resistor to
set PMBus
Address
To ADC Mux
Figure 2 PMBus Address Detection Method
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13
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
Table 2 PMBus Address bins
Address
12
11
10
9
8
7
6
5
4
3
2
1
0
Voltage
2.299
1.815
1.463
1.177
0.953
0.749
0.604
0.486
0.383
0.308
0.249
0.196
0.157
Resistor
209
165
133
107
86.6
68.1
54.9
44.2
34.8
28.0
22.6
17.8
14.3
A low impedance (short) on the address pin the produces a voltage below the minimum voltage will cause the
PMBus address to default to address 0x0B. A high impedance (open) on the address pin that produces a voltage
above the maximum voltage will also cause the PMBus address to default to address 0x0B.
Figure 3 PMBus Voltage Adjustment Methods
Output Voltage Adjustment
The Output Voltage is programmed by issuing VOUT_COMMAND, VOUT_TRIM or VOUT_MARGIN, …
commands on the PMBus..
Soft-Start, Soft-Stop and Normal Operation
During the soft-start or soft-stop the internal gain is changed to have +-8mV resolution This allows the ADC to
have a wider dynamic range during the start/stop ramp. During normal operation the gain is adjusted to +-1mv
resolution for tighter regulation.
14
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
Digital Compensator
Each voltage rail controller in the UCD9240 includes a digital compensator. The compensator is a digital filter
consisting of a second order infinite impulse response (IIR) filter section cascaded with a first order IIR filter
section. based design tool program:
The development tool for the UCD9240 comes with the "POWER+DESIGNER", which can be used to assist in
defining the compensator coefficients. The design tool allows the compensator to be described in terms of the
pole frequencies, zero frequencies and gain desired for the control loop. In addition, the Design Tool can be used
to characterize the power stage so that the compensator coefficients can be chosen based on the total loop gain
for each feedback system. The coefficients of the filter sections are generated thru modeling the power stage and
load in the Power+ Designer.
Additionally, the UCD9240 allows for several banks of filter coefficients which can be configured to switch
automatically based on the operation of the power stage.
The compensator also allows the minimum and maximum duty cycle to be programmed. This again is done by
issuing a PMBus command to the device.
PWM Engine
The output of the compensator feeds the high resolution PWM engine. The PWM engine produces the pulse width
modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle
as a 16-bit number representing a value from 0.0 to 1.0. This duty cycle value is multiplied by the period to
generate the duty period. The resolution of the duty period is 250 psec.
When the UCD9240 is configured to drive multiple power stage circuits from one compensator, each gate drive
output pulse width is adjusted to correct for current imbalance between the connected power stage sections. This
is done by monitoring the current using input on the current sense pins and increasing the pulse width of the PWM
signal driving the power stage with the lowest current and decreasing the pulse width of the PWM signal driving
the power stage with the highest measured current.
Each PWM engine can be synchronized to another PMW engine or to an external sync signal via the SYNC_IN
and SYNC_OUT pins. An input sync signal causes a PWM ramp timer to reset. Sync signal outputs from each of
the four PWM engines occur when the ramp timer crosses a programmed threshold. In this way the phase of
multiple power stage drive signals can be tightly controlled. The synchronization behavior is programmed through
a MFR_SPECIFIC PMBus command.
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15
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
PWM Engine (1 of 4)
SysClk
SyncIn
Clk high res
ramp
counter
reset
S
R
Switch period
PWM gate drive output
Current balance adj
Compensator output
EADC trigger
EADC trigger threshold
SyncOut
SyncOut phase
The switching frequency is set by issuing the FREQUENCY_SWITCH PMBus command.
Fault Handling
The UCD9240 has several fault handling features. The following faults are handled.
1. Vin is monitored for over-voltage or under-voltage.
2. A logic high signal from an external source, such as the gate driver IC will cause a fault and immediately
shut down the PWM engine. The response to the event is programmed through a PMBus command.
3. The device contains programmable internal analog comparators that monitor the current sense inputs. If
the current sense input exceeds the programmed threshold the PWM signal is shut down.
4. Monitoring and averaging the current sense inputs for each multiphase power stage that makes up an
output rail. Over current and under current (negative) thresholds are programmed via PMBus for each rail.
The response to the event is also programmed through a PMBus command.
5. Temperature is periodically measured and compared to the PMBus configured over-temperature
threshold.
Temperature Measurement
The UCD9240 has the ability to measure current and temperature in the controlled power stage. The pin Temp
and the select pins TMUX0-2 are used to control an external analog multiplexer which cycles through each of the
power stage temperature measurement signals. It can be programmed to accept the output from either a linear
device such as an LM20 temperature sensor or a diode forward voltage.
16
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
Figure 4 Temperature Mux (4-rail, 6-phase example)
Current Measurement
Pins CS1-A, CS1-B, CS2-A, CS2-B, CS3-A, CS3-B, CS4-A, and CS4-B are used to measure output or inductor
current in each of the controlled power stages. MFR_SPECIFIC PMBus commands are used to calibrate each
measurement. When the measured current exceeds either the over-current or undercurrent threshold a FAULT is
declared the UCD9240 performs the PMBus programmed fault recovery. ADC current measurements are digitally
filtered (averaged) before compared against the FAULT threshold.
In response to a PMBus request for a current reading, the device will return an average current value. When the
UCD9240 is configured to drive a multi-phase power converter, the device will add the average current
measurement for each of the power stages tied to a power rail.
Current Sense Detection
Several mechanisms are provide to sense output current. This allows for the design of power systems with
multiple layers of protection.
1. A logic high signal on the FAULT input will immediately drive the PWM signal for the associated page
(rail/output) low. The SRE signal will be driven low between TDB and TBD usec later. An intelligent gate
driver such as the UCD7230 can be used to generate the FAULT signal. The UCD7230 monitors the voltage
drop across the high side FET and if it exceeds a resistor programmed threshold, the UCD7230 activates the
CLF output and turns off the FET drives. The CLF can be used to drive the FAULT input on the UCD9240.
Typically, the FAULT input is used to monitor and protect against a short circuit in one of the switches or the
load. Therefore this threshold is set to the highest current setting of the multiple over-current settings.
2. Four of the current sense inputs are wired to an internal analog comparator, one for each page (rail/output).
The threshold for the current sense input is set to 2.0V. This input can be used to detect the output of a
current sense amplifier such as the amplifier in the UCD7230 which monitors the current in the power stage
inductor. If the current sense voltage exceeds 2.0V the corresponding PWM output is immediately driven low.
The SRE signal will be driven low between TDB and TBD usec later. The over-current threshold condition is
programmed by choosing the appropriate divider network on the input to the CSx.y pin. This forms the
"middle" level of over-current protection.
3. Each Current Sense input to the UCD9240 is also monitored by the 12-bit ADC. This measured value is
averaged and compared with a PMBus programmable threshold. This threshold is typically the lowest overcurrent setting and set closest to the maximum allowed current for the design.
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17
UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
PACKAGING
64-pin Package
Notes: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5-1994.
B. This drawing is subject to change without notice.
C. Quad Flatpack, no-leads (QFN) package configuration.
18
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UCD9240
Digital Point of Load System Controller
SLUS766 – APRIL 2007
80-pin Package
Notes: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Ordering Information
Part Number
Package
UCD9240PHR
80-pin QFP
UCD9240RHBR
64-pin QFN
Operating Temp. Range, TA
TBD
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19
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UCD9240RGCR
PREVIEW
QFN
RGC
64
2000
TBD
Call TI
Call TI
UCD9240RGCT
PREVIEW
QFN
RGC
64
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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