78P2241
E3/DS3/STS-1
Transceiver
October 2000
DESCRIPTION
FEATURES
The 78P2241 is a line interface transceiver IC for
E3, DS3, STS-1, NA T3 and ATM applications. It
includes clock recovery and transmitter pulse
shaping functions for applications using 75-ohm
coaxial cable at distances up to 1100 feet. These
applications include
DSLAMs, T3/E3 digital
multiplexers, SONET Add/Drop multiplexers, PDH
equipment, DS3 to Fiber optic and microwave
modems and ATM WAN access for routers and
switches.
•
•
•
•
•
The receiver recovers clock and data from a B3ZS
or HDB3 coded AMI signal. It can compensate for
over 12dB of cable and 6dB of flat loss. The
transmitter generates a signal that meets the
standard pulse shape requirements.
•
•
•
The 28-pin PLCC 78P2241 is pin and functionally
compatible to the 78P7200. It adds a B3ZS/HDB3
ENDEC, loop-back and clock polarity selection as
well as ability to receive a DSX3 monitor signal.
•
•
•
•
•
The 78P2241 is manufactured in an advanced
BICMOS process and operates at both 5V and
3.3 V power supply voltages. It consumes less than
95 mA of supply current.
Single chip transmit and receive interface for
E3, DS3 and STS-1 applications.
Interface to 75 ohm coaxial cable over 1100
feet at speeds up to 51.84 Mbps.
Compliant with ANSI T1.102-1993, Telcordia
GR-499-CORE and GR-253-CORE, ITU-T
G.703 and G.823 for jitter tolerance.
Compliant with ATM FORUM af-phy-0034 (E3
public UNI) and af-phy-0054 (DS3 public UNI).
Easily Interfaced to ATM framer ICs such as
PMC 7345 , 7346 QJET and 7321.
Unique clock recovery requires no reference
clock or crystal oscillator.
Receive DS3-high and DSX3 monitor signals
Includes diagnostic loop-back for AMI and
digital signals.
Includes a selectable B3ZS/HDB3 ENDEC.
Pin compatible to 78P7200 (28-lead PLCC).
28-lead PLCC and 48-lead TQFP packages
3.3 or 5 V operation, ICC<95mA
Input circuit works either Transformer or
Capacitor coupled
TXEN
LINP
LINN
Adaptive
Equalizer
Clock
Recovery
Biasing
Signal
Detector
MON
RCLK
Data
Slicer
LOS
B3ZS /
HDB3
Decoder
RFO
RPOS
RNEG
LOUTP
LOUTN
PULSE
SHAPER
LPBK
B3ZS /
HDB3
Encoder
LF
TPOS
TNEG
TCLK
LBO
LPBK
BLOCK DIAGRAM
78P2241
E3/DS3/STS-1
Transceiver
FUNCTIONAL DESCRIPTION
The AMI signal first enters a selectable fixed 20 dB
amplifier stage that compensates for very low
amplitude DSX3 monitor signal when MON pin is
held high. The signal then enters an equalizer and
AGC gain stage. The equalizer is designed to
overcome intersymbol interference caused by long
cable lengths. Because the equalizer is adaptive,
the circuit will work with all square shaped signals
such as DS3 high or 34 Mbit/s E3. The variable gain
differential amplifier maintains a constant voltage
level output regardless of the input voltage level.
The gain of the amplifier is adjusted by detecting the
peak of the signal and comparing it to a fixed
reference.
The 78P2241 is a single chip line interface IC
designed to work with a 51.84 Mbit/s STS-1, 44.736
Mbit/s DS3 or 34.368 Mbit/s E3 signal. The receiver
recovers clock, positive data and negative data from
an Alternate Mark Inversion (AMI) signal. The AMI
line input signal should be B3ZS or HDB3 coded.
The transmitter accepts clock, positive, and negative
data and converts them into an AMI signal to drive a
75 Ω coaxial cable. The shape of the transmitted
signal though any cable length of 0 to 450 feet
complies with the published templates of ANSI
T1.102-1993, Telcordia TR-NWT-000499 and GR253-CORE, ITU-T G.703. The 78P2241 is designed
to work with B3ZS or HDB3 coded signals. The
B3ZS or HDB3 encoding and decoding functions are
normally included in the framer ICs; however, a
selectable B3ZS/HDB3 ENDEC is included in the
78P2241 for interface to binary NRZ data. The
78P2241 is designed to easily connect to popular
ATM framer ICs such as PMC 7345 (SUNI-PDH),
PMC 7346 (QJET) and 7321.
Outputs of the data comparators are connected to
the clock recovery circuits. The clock recovery
system employs a phase locked loop with an
auxiliary frequency-sensitive acquisition loop. This
system permits the loop to independently lock to the
frequency and phase of the incoming data stream
without the need for an external, high precision
tuned circuits or reference clock signal.
The jitter tolerance of the 78P2241 meets the
requirements of Telcordia GR-499-CORE for
Category I equipment for DS3 rates and exceeds the
requirements of ITU-T G.823 for E3 rates.
OPERATION SPEED
Internal bias generators that are adjusted by the
value of the RFO set the 78P2241 PLL center
frequency and Transmitter amplitude for the different
standards. The E# pin controls the equalizer
response and the transmitter pulse shape and
amplitude. The following table shows the proper
settings.
Standard
E3
DS3
STS-1
RFO Value, kΩ
6.81
5.23
4.53
Pin 21
MON
Low
High
Low
High
E# pin setting
Low
High
Float
RECEIVER
The receiver input can be either transformer-coupled
or capacitor coupled to the AMI signal.
In
applications where the highest performance and
isolation is required, a 1:1 transformer is used on the
receiver path. In the applications, where isolation is
provided elsewhere in the circuit, an AC coupling can
be used.
The inputs to the IC are internally
referenced to Vcc. Since the input impedance of the
78P2241 is high, the AMI line must be terminated to
75 Ω . The input signal of the 78P2241 must be limited
to a maximum of three consecutive zeros using a
coding scheme such as B3ZS or HDB3.
2
Receive
Range
mVpk
90-850
25-80
104-1200
25-80
Mode
DS3/STS-1 normal
DS3 monitor
E3 normal
E3 monitor
78P2241
E3/DS3/STS-1
Transceiver
FUNCTIONAL DESCRIPTION (continued)
For E3 applications, the transmitted pulse for a short
cable meets the requirements of ITU-T G.703. The
E# pin is to be pulled low.
LOSS OF SIGNAL
Should the input signal fall below a minimum value,
the loss of signal indication, LOS goes low.
RCLK/TCLK polarity reversal:
To simplify the interface with framer circuitry, RCLK
and TCLK can be inverted with the ICKP pin.
B3ZS/HDB3 DECODER
The 78P2241 includes a selectable B3ZS/HDB3
Encoder/Decoder (ENDEC). When the ENDEC pin is
low, the ENDEC is selected and the receiver
generates a composite NRZ logic data following the
B3ZS (for DS3/STS-1) or HDB3 (for E3) substitution
codes via the RPOS/RNRZ pin as shown below.
Pin 20
ENDEC
High
Low
RPOS/RNRZ
Positive AMI
NRZ data
Pin 10
ICKP
Low
Float
High
TPOS/TNRZ
Positive AMI
NRZ data
TCLK
Normal
Invert
Normal
Normal
Invert
Invert
Loop-back modes:
RNEG
Negative AMI
No Connect
The following loop-back modes allow for the
diagnostic test of the PC board. This function is
controlled by the LPBK pin.
On the transmit side, NRZ input data is internally
converted to Positive and Negative logic data
following the B3ZS (for DS3/STS-1) or HDB3 (for E3)
substitution codes. The NRZ data is input to the
TPOS/TNRZ pin as shown below.
Pin 20
ENDEC
High
Low
RCLK
Pin 28
LPBK
Low
Float
High
TNEG
Negative AMI
No Connect
Loop-back
Local loop-back (LLB)
Remote loop-back (RLB)
Normal Operation
Local) loop-back:
When LPBK is low, the 78P2241 enters Local
loopback. In this mode, the LOUT+/- transmit signals
are internally routed to the receiver input circuit. The
incoming line receiver AMI signal on LIN+/- is
ignored. With the transmitter still tied to the cable,
this test mode can indicate a short circuit on the
transmitter external components or other problem in
the transmit path.
Remote loop-back:
TRANSMITTER
The transmitter accepts logic level clock (TCLK),
positive data (TPOS) and negative data (TNEG)
signals and generates current pulses on the LOUT+
and LOUT- pins. When properly connected to a
center-tapped 1:2 transformer, an AMI pulse is
generated which can drive a 75 Ω coaxial cable.
When LPBK pin is allowed to float, the 78P2241
enters remote loopback mode. The RPOS/RNEG
and RCLK pins are internally tied to the
TPOS/TNEG and TCLK so the same AMI signal that
is received by the framer is transmitted back to the
far end where a bit continuity test can be performed.
When the recommended transformer is used and the
E# pin is set high, the transmitted pulse shape at the
end of the 75Ω terminated cable of 0 to 450 feet will
fit the DS3 template in ANSI T1.102-1993 and
Telcordia GR-499-CORE standard documents.
For STS-1 applications, the transmitted pulse for a
short cable meets the requirements of Telcordia
GR-253-CORE. The E# pin should be allowed to
float.
Line Build-Out:
The Line Build-Out function controls the amplitude in
DS3 and STS-1 mode. The selection of LBO
depends on the amount of cable the transmitter is
connected to. When used with less than 225 ft of
cable the LBO pin should be pulled high. With 225ft
or more cable the LBO pin should be low.
3
78P2241
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: The 28-pin PLCC is compatible with 78P7200
NAME
PIN
TQFP
42
44
33
35
PIN
PLCC
1
3
23
25
TYPE
RNEG
34
24
O
LOS
39
27
O
LOUT+
LOUTTCLK
9
11
18
9
11
16
O
TPOS/
TNRZ
16
14
I
TNEG
17
15
I
LBO
13
12
I
E#
15
13
I3
TXEN
22
18
I
MON
28
21
I
ICKP
10
10
I3
LPBK
40
28
I3
VCC
5,6,20,
21,37,38
7,17,26
P
LIN+
LINRCLK
RPOS/
RNRZ
I
O
O
I
DESCRIPTION
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
Receive Clock: Recovered receive clock.
Receive Positive Data / NRZ Data: When ENDEC is high,
this pin indicates reception of a positive AMI pulse on the
coax cable. When ENDEC is low, it outputs decoded NRZ
data.
Receive Negative Data: When ENDEC is high, this pin indicates
reception of a negative AMI pulse on the coax. When ENDEC is
low this pin is at logic low.
Loss of Signal: logic low indicates that receiver signal (LIN±)
is below the threshold level. RPOS and RNEG are forced
low when LOS=0.
Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301Ω resistor.
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P2241.
Transmit Positive Data / Transmit NRZ: When ENDEC is
high, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time
that TNEG is high.
When ENDEC is low, data on this pin is encoded and
converted into positive and negative AMI pulses.
Transmit Negative Data: When ENDEC is high, a logic one on
this pin generates a negative AMI pulse on the coax. This pin
should not be high at the same time that TPOS/TNRZ is high.
When ENDEC is low, this pin is ignored.
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used with
less than 225ft of cable.
DS3, E3 and STS-1 Select: Set low for E# applications. Set
high for DS3, allow to float for STS-1 operation. Formerly
OPT! on the 78P7200.
Transmitter Enable: When high, enables transmitter. When
low, tri-states transmitter drivers, LOUT±. This pin was
called OPT@ on 78P7200.
DSX3 / E3 Monitor Select: When set high, an additional 20dB gain stage is added to the receiver gain. This pin was
tied to GND on the 78P7200.
Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set high,
the polarity of TCLK is inverted. When allowed to float, the
polarities of both RCLK and TCLK are inverted.
Loop-back Select: When high, neither loop-back is activated.
When allowed to float RPOS, RNEG and RCLK are looped
back onto TPOS, TNEG and TCLK. When low, LOUT± is
looped back onto LIN±.
Power Supply.
4
78P2241
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: The 28-pin PLCC is compatible with 78P7200 (continued)
NAME
PIN
PLCC
2,4,6,8,22
TYPE
P
Ground. Connecting all ground pins to a common ground
plane is recommended.
RFO
PIN
TQFP
1,3,4,7,8,12,14,
19,23,24,25,29,
30,31,32,36,41,
43,45,46,47,48
2
5
-
LF1
26
19
-
A resistor to GND sets the operational speed of the chip.
RFO= 5.23K for DS3, RFO=6.81K for E3 and RFO=4.53K
for STS-1.
Receiver PLL filter capacitor.
ENDEC
27
20
I
GND
DESCRIPTION
Encoder/Decoder: When set low, activates B3ZS/HDB3
ENDEC on receiver and transmitter logic signals.
Note 1: Pin type: I-input; I3-three level logic input; O-output; P-power supply. Advanced Data sheet pin
assignment and functions are subject to change.
5
78P2241
E3/DS3/STS-1
Transceiver
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Operation beyond these maximums rating may permanently damage the device.
PARAMETER
RATING
Positive supply, VCC
6V
Storage temperature
-65 to 150
Ambient operating temperature
-40 to +85 °C
Output Pin Voltage (LOUT+, LOUT-)
VCC -2 to VCC +2 V
Input Pin Voltage (LIN+, LIN-)
Input pin voltage, all other pins
VCC+0.3 to GND-0.3 V
DC CHARACTERISTICS: Ta = -40° to +85°C; positive supply voltage = 5V ±0.5V or 3.3V±0.3V
PARAMETER
PIN TYPE
CONDITION
MIN
TYP
MAX
UNIT
95
mA
Supply current ICC
Transmit and receive all
ones, VCC=5V or 3.3V
70
Supply current ICC
transmitter disabled,
TXEN=0
35
VIL
I
VIH
I
2.0
IIL, IIH
I
-10
VIL3
I3
ZIM3
I3
VIH3
I3
VCC-0.5
IIL3, IIH3
I3
-100
VOL
O
IOL=-0.1mA
VOH
O
IOL=+0.1mA
mA
0.8
Input Floating
8
VCC-0.5
6
V
V
10
+10
uA
0.5
V
20
kΩ
V
+100
uA
0.5
V
V
78P2241
E3/DS3/STS-1
Transceiver
E3 – RECEIVER (RFO = 6.81kΩ , E# is set low), receiver is transformer-coupled.
PARAMETER
CONDITION
MIN
Peak Differential Input
Amplitude, LIN+, LIN-
See Note 2
Peak Differential Input
Amplitude, LIN+, LIN-
MON=1
TYP
MAX
UNIT
104
1200
mVpk
25.5
85
mVpk
4
ns
Monitor Mode
Bit Error Ratio in the
presence of an Interfering
Signal at Receive Input
-9
Interfering signal power 20dB below
E3 signal power. Both are PRBS23
23
(2 -1) patterns.
RCLK rise/fall time TRCT
10
2
RCLK period, TRCF
29.10
RCLK clock duty cycle
45
RCLK pulse width TRC
55
14.55
RPOS/RNEG data setup
time TRDPS
CL=15 pF
7
RPOS/RNEG data hold time
TRDPH
CL=15 pF
7
ns
%
ns
ns
Note 2: 104 mVpk equals 950 mVP at the source with 1100 feet of cable (13.2dB loss).
Note 3: Meets the jitter tolerance requirement of ITU-T G.823.
Note 4: Measure the jitter’s 3dB fall off on RCLK. In order to meet jitter transfer function requirements with a lower
bandwidth, an external jitter attenuation circuit needs to be added.
7
78P2241
E3/DS3/STS-1
Transceiver
DS3/STS-1 RECEIVER (RFO = 5.23kΩ for DS3 and 4.53kΩ for STS-1, E# pin is set high or allowed to float),
Input is transformer coupled
PARAMETER
Peak Differential Input
Amplitude, LIN+ and LIN(see Note 5)
Peak Differential Input
Amplitude, LIN+ and LINPeak Differential Input
Amplitude, LIN+ and LIN-
CONDITION
MON=0. Signal at DSX is 360-850mVP
(see Note 6)
Bit Error Ratio in the presence of
an Interfering Signal (IS) at
LIN+,LIN-
IS is a sinusoidal tone, 22.368 MHz
for DS3 or 25.92MHz for STS-1. Data
15
is a PRBS15 (2 -1) pattern. IS power
is 10dB below data signal power.
Cl=25pf
DS3
STS-1
DS3
STS-1
CL=15 pF
7
ns
CL=15 pF
7
ns
RCLK rise/fall time TRCT
RCLK period
TRCF
RCLK pulse width
TRC
RPOS/RNEG data setup time
TRDPS
RPOS/RNEG data hold time
TRPDH
MIN
90
TYP
MAX
850
UNIT
mVP
Mon=1
25
80
mVP
Mon=0. DS3 HIGH (see Note 7)
90
1200
mVP
10-9
5
22.35
19.29
12.24
9.65
ns
ns
ns
Note 5:
Signal source should meet DS3 template of ANSI-T102.1993 Figure 4 and STS-1 template of ANSIT102.1993 Figure 5, Loss characteristics of the WE728A or RG 59B cable should be better than Figure
C2 of ANSI-T102.1993.
Note 6:
Receiver can handle up to 450 feet of cable loss (5.5dB) from the DSX cross-connect.
Note 7:
Case where test signal is fed directly into receiver with fast rise times violates DS3 template and normal
maximum. In this mode no noise, jitter, or interfering tone impairments will be added.
Note 8:
This is performed in digital loop-back mode. Jitter is supplied by a Bit Error Rate Tester and bit errors
are measured. Jitter is specified in terms of UI (Unit Interval) and frequency, is summed with DS3
PRBS15 data through 450 feet of cable.
8
78P2241
E3/DS3/STS-1
Transceiver
TIMING DIAGRAM: Receive Waveforms (E3/DS3/STS-1)
9
78P2241
E3/DS3/STS-1
Transceiver
RECEIVER JITTER TOLERANCE
E3 and DS3 jitter tolerance specifications are in ITU-T G.823 and G.824. The E3 specification is the tighter of
the two for frequencies greater than 20 kHz. Receive jitter tolerance is not tested during production test.
100
10
E3
1
DS3
0.1
0.01
1.E-05
1.E-03
1.E-01
1.E+01 1.E+03
1.E+05
1.E+07
PARAMETER
CONDITION
MIN
Receiver Jitter Tolerance
12µHz to 2.78 Hz
18
10Hz to 600Hz
5
20 kHz to 800 kHz
0.15
10
NOM
MAX
UNIT
UI
78P2241
E3/DS3/STS-1
Transceiver
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop filter characteristics are such that the receiver has the following transfer
function. The corner frequency of the PLL is approximately 50 kHz. Receiver jitter transfer function is not tested
during production test.
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
1.E+01
1.E+02
1.E+03
PARAMETER
CONDITION
Receiver Jitter transfer function
below 59.6 kHz
1.E+04
1.E+05
MIN
Jitter transfer function roll-off
1.E+06
NOM
20
11
MAX
UNIT
0.1
dB
dB per
decade
78P2241
E3/DS3/STS-1
Transceiver
E3 – TRANSMITTER (RFO = 6.81kΩ , E# = LOW)
PARAMETER
CONDITION (see timing diagram)
MIN
TYP
MAX
UNIT
Transmitter amplitude
LOUT+ and LOUT-
950
1000
1050
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse centers
0.95
1.05
Transmitter width mismatch
TTPL/TTHL
Ratio of widths of positive and
negative pulses measured at
pulse half amplitude
0.95
1.05
Transmitter Pulse width TTPL,
TTPN
LOUT+ and LOUT40
Transmitter clock duty cycle,
TTC/TTCF
Transmitter clock period
14.55
ns
60
%
TTCF
29.10
ns
Transmitter clock pulse width , TTC
14.55
ns
Transmitter clock transition time,
Rising and falling CPTT/CNTT
0.8
Data setup time
TTDRS
2.5
ns
Data hold time
TTDHS
2.5
ns
12
3
5
ns
78P2241
E3/DS3/STS-1
Transceiver
DS3/STS-1 TRANSMITTER (E # = High)
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmitter Amplitude
LOUT+ and LOUT-
750
800
850
mVP
Transmitter Amplitude Mismatch
Ratio of amplitudes of positive
and negative pulses measured at
pulse peaks.
0.9
1.1
Transmitter power
DS3 only - All ones, 3kHz
bandwidth
-1.8
+5.7
dBm
DS3 only - All ones, 3kHz
bandwidth
-21.8
-14.3
dBm
40
60
%
At 22.368 MHz
Transmitter power
At 44.736 MHz
Transmitter clock duty cycle,
TTC/TTCF
Transmitter clock period
TTCF
DS3
22.35
ns
STS-1
19.29
ns
Transmitter clock period
TTCF
Data setup time
TTPDS
2.5
ns
Data hold time
TTPDH
2.5
ns
0.8
Transmitter clock transition time,
Rising and falling TTCPT,TTCNT
13
2
4
ns
78P2241
E3/DS3/STS-1
Transceiver
TIMINGING DIAGRAM: Transmitter Waveforms (E3/DS3/STS-1)
14
78P2241
E3/DS3/STS-1
Transceiver
E3 TRANSMIT TEMPLATE
17 ns
0.2
0.1
1.0
8.65 ns
0.1
0.2
14.55 ns
0.5
12.1 ns
24.5 ns
0.1
0.1
0
0.1
0.1
0.2
29.1 ns
15
78P2241
E3/DS3/STS-1
Transceiver
DS3 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
1
Time, Unit Intervals
Time axis range (UI)
Normalized amplitude equation
Upper Curve
-0.85 < T < -0.68
0.03
-0.68 < T < 0.36
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.36 < T < 1.4
0.08+0.407 e-1.84(T-0.36)
Lower Curve
-0.85 < T < -0.36
-0.03
-.0.36 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
16
1.5
78P2241
E3/DS3/STS-1
Transceiver
STS-1 TRANSMIT PULSE TEMPLATE
1.2
1
Normalized Amplitude
0.8
0.6
0.4
0.2
0
-0.2
-1
-0.5
0
0.5
Time, Unit Intervals
STS-1 (Transmit template specs)
Time axis range (T)
Normalized amplitude equation (A)
Upper Curve
-0.85 < T < -0.68
0.03
-0.68 < T < 0.26
0.03 + 0.5{1+sin[(pi/2)(1+T/0.34)]}
0.26 < T < 1.4
0.1+0.61 e-2.4(T-0.26)
Lower Curve
-0.85 < T < -0.38
-0.03
-0.38 < T < 0.36
-0.03 + 0.5{1+sin[(pi/2)(1 + T/0.18)]}
0.36 < T < 1.4
-0.03
17
1
1.5
78P2241
E3/DS3/STS-1
Transceiver
TRANSMITTER OUTPUT JITTER
The transmit jitter specification ensures compliance with ITU-T G.823 and G.824, and ANSI T1.102-199 for all
supported rates. Transmit output jitter is not tested during production test.
Jitter
Detector
Measured Jitter
Amplitude
20dB/decade
Transmitter
Output
10Hz
PARAMETER
CONDITION
Transmitter Output Jitter
10 Hz to 800 kHz
800kHz
MIN
18
NOM
MAX
UNIT
0.1
UI
78P2241
E3/DS3/STS-1
Transceiver
E3/DS3/STS-1 Example Circuit
VCC
F1
Ferrite Bead
VCC
0.1uF
0.001uF
17
U1
1
TR
75
2
3
4
LIN+
LPBK(CPD)
LOS(LOWSIG
VCC
GND
RPOS/RNRZ
RNEG
RCLK
RFO
MON(NCD1)
7
Loop Back Select
27
26
VCC 0.1uF
LIN-
F2
VCC
28
GND
RFO
5
10K
VCC
J1
BNC
25
24
23
21
Framer/
Deframer
MON
VCC
VCC
Ferrite Bead
0.001uF
0.1uF
78P2241
J2
BNC
10K
9
TT
LOUT+
ENDEC(LF2)
VCC
20
Endec Select
301
11
10
LBO
Speed Select
12
13
VCC
LF1
0.047uF
19
ICKP(NCT)
RT
LBO
TCLK
TNEG
TPOS/TNRZ
E3(OPT1)
TXEN(OPT2)
16
15
14
8
6
22
18
CLF
LOUT-
GND
GND
GND
1:2ct
Note 9: Pin names in ( ) denote pin names from 78P7200. Pin numbers refer to 28 PLCC package. Default
settings used to simulate 78P7200.
Note 10: Resistors on TCLK, TNEG, TPOS are optional but recommmeded. Clock pulse shapes at the inputs to
the 78P2241 are dependent on board layout and will dictate the need for such added resistors.
Note 11. Adding a series Ferrite Bead on VCC pins may be required for some pc board layout.
EXTERNAL COMPONENTS (Common to E3/DS3/STS-1)
Component
Receiver Termination Resistor
Receiver Transformer Turns Ratio
Transmitter Termination Resistor
Transmitter Transformer Turns Ratio
Tolerance
Value
Unit
RTR
1%
75
Ω
TR
3%
1:1
---
RTT
1%
301
Ω
TT
3%
1:2ct
---
EXTERNAL COMPONENTS (Dependant on speed, nominal value)
Component
Tolerance
STS-1
DS3
E3
Unit
Loop Filter Capacitor
CLF
10%
0.047
0.047
0.047
µF
Bias Resistor
RFO
1%
4.53
5.23
6.81
kΩ
Note 11: Advanced Data sheet pin assignment ,functions and external component values are subject to change.
19
78P2241
E3/DS3/STS-1
Transceiver
78P2241 Replacement for Existing 78P7200 Designs
VCC
LVCC
C1
L1
U1
17
RVCC
J1
T1
R1
1
R2
C2
L2
RTR
2
CPD
VCC
BNC
LIN+
LPBK(CPD)
LOS(LOWSIG
28
27
LOW_SIG
GND
LVCC
3
LIN-
VCC
26
VCC
C3
4
GND
RFO
5
RPOS/RNRZ
RNEG
RCLK
RFO
25
24
23
RPOS
RNEG
RCLK
RVCC
VCC
MON(NCD1)
LVCC
7
21
RVCC
VCC
78P2241
J2
BNC
9
TT
RLF2
LOUT+
ENDEC(LF2)
VCC
20
CTT
RTT
RLF1
TCLK
TNEG
TPOS/TNRZ
E3(OPT1)
TXEN(OPT2)
8
OPT2 18
19
CLF
LBO
RT
16
15
14
TCLK
TNEG
TPOS
GND
OPT1 13
LF1
ICKP(NCT)
GND
12
GND
10
LBO
LOUT-
22
11
6
1:2ct
Note 12: 78P7200 components (such as transmitter transformer) which are not shown here are not modified.
Component Variation for Existing 78P7200 Designs
INPUT FILTER
COMPONENT
R1,R2
78P7200
78P2241
75Ω
82p
6.8u
0.47u
1000p
0.01
1:2
SHORT (0Ω)
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
NOT INSTALLED
1:1
422Ω
0.22u
75Ω
CPD
RLF2
100k Ω
RLF1
CLF1
RTT
6.04k Ω
0.22u
DS3
CTT
E3
DS3
LVCC
E3
4.7uH
C2
L2
L1
C1
C3
T1
RTR
PLL FILTER
TRANSMITTER
POWER SUPPLY
20
SHORT (0Ω)
NOT INSTALLED
NOT INSTALLED
0.047u
301Ω
301Ω
604Ω
5-15pF
3pF
301Ω
NOT INSTALLED
NOT INSTALLED
SHORT (0Ω) or Ferrite
Bead
78P2241
E3/DS3/STS-1
Transceiver
PACKAGE PIN DESIGNATIONS
(Top View)
78P2241
28-Pin PLCC
MECHANICAL DRAWING
28-Pin PLCC
21
78P2241
E3/DS3/STS-1
Transceiver
CAUTION: Use handling procedures necessary for
a static sensitive component.
PACKAGE PIN DESIGNATIONS
(Top View)
48-Pin TQFP
(NOT pin-compatible to 78P7200)
22
78P2241
E3/DS3/STS-1
Transceiver
MECHANICAL DRAWING
48-Pin TQFP
ORDERING INFORMATION
PART DESCRIPTION
ORDER NUMBER
PACKAGE MARK
28-pin PLCC
78P2241-IH
78P2241-IH
48-pin TQFP
78P2241-IGT
78P2241-IGT
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks
or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK
Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the
reader is cautioned to verify that the data sheet is current before placing orders.
TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877
TDK Semiconductor Corporation
10/06/00 - rev . B
23