Data sheet acquired from Harris Semiconductor SCHS249A CD54AC273, CD74AC273 CD54ACT273, CD74ACT273 Octal D Flip-Flop with Reset August 1998 - Revised April 2000 Features Description • Buffered Inputs The ’AC273 and ’ACT273 devices are octal D-type flip-flops with reset that utilize advanced CMOS logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. • Typical Propagation Delay - 6.5ns at VCC = 5V, TA = 25oC, CL = 50pF • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 • SCR-Latchup-Resistant CMOS Process and Circuit Design Ordering Information • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption PART NUMBER • Balanced Propagation Delays • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines TEMPERATURE RANGE PACKAGE CD74AC273E -40oC to 85oC 20 Ld PDIP CD54AC273F3A -55oC to 125oC 20 Ld CDIP CD74ACT273E -40oC to 85oC 20 Ld PDIP CD54ACT273F3A -55oC to 125oC 20 Ld CDIP CD74AC273M -40oC to 85oC 20 Ld SOIC CD74ACT273M -40oC to 85oC 20 Ld SOIC NOTES: Pinout 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. CD54AC273, CD54ACT273 (CDIP) CD74AC273, CD74ACT273 (PDIP, SOIC) TOP VIEW MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated 1 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Functional Diagram CLOCK CP DATA INPUTS D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 DATA OUTPUTS RESET MR TRUTH TABLE INPUTS OUTPUTS RESET (MR) CLOCK CP DATA Dn Qn L X X L H ↑ H H H ↑ L L H L X Q0 H = High level (steady state), L = Low level (steady state), X = Irrelevant, ↑ = Transition from Low to High level, Q0 = The level of Q before the indicated steady-state input conditions were established. 2 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance, θJA (Typical, Note 5) E Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69oC/W M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58oC/W Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA CD54AC273, CD54ACT273 . . . . . . . . . . . . . . . . . -55oC to 125oC CD74AC273, CD74ACT273 . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. The package thermal impedance is calculated in accordance with JESD 51. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V - 3 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD Dn 0.5 MR 0.57 CP 1 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Prerequisite For Switching Function PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX UNITS tSU 1.5 2 - 2 - ns 3.3 (Note 9) 2 - 2 - ns 5 (Note 10) 2 - 2 - ns 1.5 2 - 2 - ns 3.3 2 - 2 - ns 5 2 - 2 - ns 1.5 2 - 2 - ns 3.3 2 - 2 - ns 5 2 - 2 - ns 1.5 55 - 63 - ns 3.3 6.1 - 7 - ns 5 4.4 - 5 - ns 1.5 55 - 63 - ns 3.3 6.1 - 7 - ns 5 4.4 - 5 - ns 1.5 9 - 8 - MHz 3.3 81 - 71 - MHz 5 114 - 100 - MHz AC TYPES Data to CP Set-Up Time Hold Time tH Removal Time, MR to CP tREM MR Pulse Width tW CP Pulse Width tW CP Frequency fMAX ACT TYPES Data to CP Set-Up Time tSU 5 (Note 10) 2 - 2 - ns Hold Time tH 5 2 - 2 - ns tREM 5 2 - 2 - ns MR Pulse Width tW 5 4.4 - 5 - ns CP Pulse Width tW 5 5.3 - 6 - ns fMAX 5 97 - 85 - MHz Removal Time MR to CP CP Frequency Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 154 - - 169 ns 3.3 (Note 9) 4.9 - 17.2 4.7 - 18.9 ns 5 (Note 10) 3.5 - 12.3 3.4 - 13.5 ns AC TYPES Propagation Delay, CP to Qn 5 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 154 - - 169 ns 3.3 4.9 - 17.2 4.7 - 18.9 ns 5 3.5 - 12.3 3.4 - 13.5 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 45 - - 45 - pF Propagation Delay, CP to Qn tPLH, tPHL 5 (Note 10) 3.5 - 12.3 3.4 - 13.5 ns Propagation Delay, MR to Qn tPLH, tPHL 5 3.5 - 12.3 3.4 - 13.5 ns Input Capacitance CI - - - 10 - - 10 pF CPD (Note 11) - - 45 - - 45 - pF PARAMETER Propagation Delay, MR to Qn Input Capacitance Power Dissipation Capacitance ACT TYPES Power Dissipation Capacitance NOTES: 8. Limits tested 100%. 9. 3.3V Min is at 3.6V, Max is at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V. 11. CPD is used to determine the dynamic power consumption per flip-flop. AC: PD = CPD VCC2 fi = ∑ (CL VCC2 fo) ACT: PD = CPD VCC2 fi + ∑ (CL VCC2 fo) + VCC ∆ICC where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. INPUT LEVEL INPUT LEVEL CP 10% tr tf 90% VS VS 10% MR VS INPUT tW tPLH tPHL Q VS VS Q FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK PULSE WIDTH tREM tW CP (Q) VS VS GND VS tPLH VS FIGURE 2. PREREQUISITE AND PROPAGATION DELAY TIMES FOR MASTER RESET 6 CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 OUTPUT LEVEL D VS VS VS VS tH (L) tH (H) tSU (L) CP tSU (H) VS VS FIGURE 3. PREREQUISITE FOR CLOCK OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. AC ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 4. 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