BH2222FV Standard ICs 8bit 20ch D/A converter BH2222FV BH2222FV is an 8bit D/A converter for electronic adjustment. The 20-channel output voltage can be independently controlled by three-wire serial interface from micro-controller. The built-in power on reset circuit keeps the output state Low after the power is on. 4-channel have data register function. Two kinds of set voltage can be retained, and output voltage can be switched by SEL pin. !Applications The voltage adjustment for DVC, DSC etc. !Features 1) 8bit 20-channel D/A converters adopting R-2R system. 2) 3-wire + 1-wire 16-bit serial interface. 3) POWER ON RESET circuit. 4) The full scale output voltage range : 2.7 ~ 5.5V. 5) It is possible to set the two output full scale level independently. 6) 4-channel date Register extension function. 7) SSOP-B28 package. !Absolute maximum ratings (Ta=25°C) Parameter Symbol Limits Power supply voltage VCC −0.3~+7.0 V Maximum output voltage VIN −0.3~VCC V Tstg −55~+125 640 ∗ mW Storage temperature Power dissipation Pd Unit °C ∗Reduced by 6.4mW for each increase in Ta of 1°C over 25°C. This product is not designed for protection against radioactive rays. !Recommended operating conditions (Ta=25°C) Symbol Min. Typ. Max. Unit VCC supply voltage Parameter VCC 4.5 − 5.5 V VDD1 supply voltage VDD1 2.7 − VCC V VDD2 supply voltage VDD2 2.7 − VCC V Analog output source current IOL − − 1.0 mA Analog output sink current IOH − − 1.0 mA Operating temperature range Clock frequency Limit load capacitance Topr −20 − 85 °C FSCLK − 1.0 − MHz CL − − 0.47 µF Please set to VCC ≥ VDD1, VDD2. 1/7 BH2222FV Standard ICs !Block diagram VCC 1 VDD2 2 POWER_ON RESET 28 CLK Serial interface VCC AO2 6 AO3 7 AO4 8 AO5 9 AO6 10 AO7 11 AO8 12 VDD1 13 GND 14 EXD 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC R-2R DAC 8bitREG + DEC 8bitREG + DEC R-2R DAC VDD1 26 EX4 25 EX3 24 AO16 23 AO15 22 AO14 21 AO13 20 AO12 VCC 5 EXD 8bitREG + DEC R-2R DAC VDD1 AO1 R-2R DAC VCC 4 EXD 8bitREG + DEC VCC EX2 R-2R DAC EXD 8bitREG + DEC VDD1 3 VCC EX1 27 DI VDD2 VDD2 VDD2 19 AO11 18 AO10 17 AO9 16 SEL 15 LD 2/7 BH2222FV Standard ICs !Pin descriptions Pin No. Pin name In / Out Power supply − − Power supply pin − − Power supply pin OUT VDD2 Functions 1 VCC 2 VDD2 3 EX1 4 EX2 OUT VDD2 5 AO1 OUT VDD2 6 AO2 OUT VDD2 7 AO3 OUT VDD2 8 AO4 OUT VDD1 9 AO5 OUT VDD1 10 AO6 OUT VDD1 11 AO7 OUT VDD1 12 AO8 OUT VDD1 13 VDD1 − − 14 GND − − Common GND pin 15 LD IN − Serial Load input pin Select extended data register pin Analog output pins (Register extension) Analog output pins Power supply pin 16 SEL IN − 17 AO9 OUT VDD1 18 AO10 OUT VDD1 19 AO11 OUT VDD1 20 AO12 OUT VDD1 21 AO13 OUT VDD1 22 AO14 OUT VDD2 23 AO15 OUT VDD2 24 AO16 OUT VDD2 25 EX3 OUT VDD2 26 EX4 OUT VDD2 27 DI IN − Serial Data input pin 28 CLK IN − Serial Clock input pin Analog output pins Analog output pins (Register extension) 3/7 BH2222FV Standard ICs !Electrical characteristics (unless otherwise noted, Ta=25°C, VCC=VDD2=5.0V, VDD1=3.0V, RL=OPEN, CL=0pF) Parameter Symbol Min. Typ. Max. Unit Conditions VCC system ICC − 1.1 2.5 mA VDD1 system IDD1 − 1.0 2.0 mA VDD2 system IDD2 − 1.5 3.0 mA Input low voltage VIL GND − 0.6 V Input high voltage VIH 2.4 − VCC V Input low current IIL − − 10 µA Input high current IIH − − 10 µA ZS1 GND − 0.1 V 00H set IOH=0.0mA ZS2 GND − 0.2 V 00H set IOH=0.5mA ZS3 GND − 0.3 V 00H set IOH=1.0mA FS1 VCC −0.1 − VCC V FFH set IOL=0.0mA FS2 VCC −0.2 − VCC V FFH set IOL=0.5mA FS3 VCC −0.3 − VCC V FFH set IOL=1.0mA Resolution RES − 8 − bit Differential nonlinearity error DNL −1.0 − 1.0 LSB Input code 02H~FDH Nonlinearity error INL −1.5 − 1.5 LSB Input code 02H~FDH <Operating current> (80H set) CLK=1MHz <Logic interface> <Buffer amplifier> Minimum output voltage Maximum output voltage <DAC accuracy> !Circuit operation (1) Power on reset This LSI has a power on reset circuit that sets an analog output to low level in VCC power stand-up. Please be sure that the time constant meets below condition, because the output is undefined when VCC power stand up too rapidly. Parameter VCC supply voltage rise time Power on reset voltage Symbol Min. trVCC 10 VPOR − Typ. Max. Unit − − ms 2.1 − V Conditions VCC=0→4.5V 4/7 BH2222FV Standard ICs (2) Conditions of operating timing (unless otherwise noted,Ta=25°C, VCC=5.0V, VDD1=3.0V, VDD2=5.0V) Symbol Min. Typ. Max. Unit CLK L level pulse width tCLKL 200 − − ns CLK H level pulse width tCLKH 200 − − ns tsDI 30 − − ns Parameter DI setup time DI hold time thDI 60 − − ns LD setup time tsLD 200 − − ns LD hold time thLD 100 − − ns LD "H" level pulse width tLDH 100 − − ns Analog output delay time tOUT − − 200 µs tCLKL Conditions CL=50pF, RL=10kΩ tCLKH CLK DI LAST DATA tsDI LD thDI tLDH thLD tsLD OUTPUT tOUT 5/7 BH2222FV Standard ICs (3) Command sending Control command is 3+1wire 16bit serial interface. (LSB first) Data is taken in with the rise edge of the CLK and output data is fixed in the LD high section. Data is maintained in the LD low section. Please change SEL mode in the LD low section. MSB (LAST) LSB (FIRST) Data set D15 Channel select D14 D13 D12 D11 D10 D9 D8 D7 D6 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 GND 0 0 0 0 0 0 0 1 (VDD1, 2-GND) / 256×1 0 0 0 0 0 0 1 0 (VDD1, 2-GND) / 256×2 1 1 1 1 1 1 1 0 ((VDD1, 2-GND) / 256×254 1 1 1 1 1 1 1 1 ((VDD1, 2-GND) / 256×255 D5 D4 D3 D2 D1 D0 •Data set Analog output voltage level •Channel select D7 D6 D5 D4 D3 D2 D1 D0 × × × 0 0 0 0 0 Don't Care × × × × × 0 0 0 0 1 AO1 × AO1 × × × 1 0 0 0 0 AO16 × AO16 × × × 1 0 0 0 1 EX1_0 0 EX1 × × × 1 0 1 0 0 EX4_0 0 EX4 × × × 1 0 1 0 1 EX1_1 1 EX1 × × × 1 1 0 0 0 EX4_1 1 EX4 × × × 1 1 0 0 1 Don't Care × × × × × 1 1 1 1 1 Don't Care × × Function SEL Output pin × : Don't Care 6/7 BH2222FV Standard ICs !Operation notes (1) Regarding to the DNL & INL This item is guaranteed under below condition. Input code 02H∼FDH (2) Regarding to the early stage condition With the power on reset, the output is fixed to low level in power stand-up. But the output is undefined when only LD signal is inputted. Input the LD signal after setting data. (3) Regarding to the setting of the each voltage Set the VCC, VDD1, VDD2 to become the following condition. When not satisfied, unnecessary current flows. VCC ≥ VDD1, VDD2 (4) Regarding to the power on reset function This function operates detecting the voltage level of the VCC. So, if the voltage level of the VCC become less than power on reset voltage when working, it is a possibility that the outputs become reset condition. !External dimensions (Units : mm) 10.0±0.2 15 1 14 1.15±0.1 0.1 0.3Min. 7.6±0.3 5.6±0.2 28 0.65 0.15±0.1 0.1 0.22±0.1 SSOP-B28 7/7 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.