ETC CH7001C-V

CH7001C
CHRONTEL
VGA to NTSC/PAL Encoder
Features
Description
• Enhanced bandwidth and signal-to-noise ratio for
higher video performance
• Integrated triple video rate 8-bit analog to digital
converters for input RGB
• 3-line digital vertical filtering with pinprogrammable characteristics for optimum antiflicker and resolution
• On-chip phase-locked loop generates sampling
clock from VGA horizontal sync
• Enhanced power management for selective circuit
power-down
• Simultaneous composite/S-video output
• Horizontal and vertical position control
• Pin-programmable underscan/overscan mode
• On-chip reference generation and loop filter
• CMOS technology in 44-pin PLCC
• 5V supply
Chrontel’s CH7001C VGA to NTSC/PAL encoder is a
stand-alone integrated circuit that converts analog VGA
inputs directly into 525-line (M) NTSC or 625-line
(B, D, G, H, I) PAL composite video and S-video
outputs.
This circuit integrates a digital NTSC/PAL encoder
with 8-bit ADC and DAC interfaces, a 3-line vertical
filter and low-jitter phase-locked loop to create
outstanding quality video with 24-bits-per-pixel processing throughout the entire signal path.
A high level of integration and performance makes the
CH7001C ideal for a variety of stand-alone and systemlevel integration solutions, including notebook
computers and PC add-on graphics cards.
HORIZONTAL, VERTICAL
POSITION CONTROL
STROBE
CLKOUT CLKEN*
NTSC/PAL*
PD[1:0]
VDD
DVDD AVDD
RSET
VREF1
RSET
VREF
BLANKING
UNDERSCAN
H,V SYNC
GENERATOR
MS[1:0]
R
ADC
G
ADC
B
VREF2
Y
FILTER
M
U
X
Σ
VERTICAL
SCAN-RATE
FILTER
CONVERTER
DAC
Y
DAC
CVBS
DAC
C
COLOR
SPACE
U
FILTER
CONVERTER
M
U
X
Σ
X
ADC
V
FILTER
H
SYSTEM CLOCKS
PLL
M
U
X
BLANKING COLOR-BURST
CONTROL
X
SIN + COSINE
GENERATOR
OSC
V
Figure 1: Functional Block Diagram
201-0000-028 Rev 3.0, 6/2/99
1
AGND
VREF1
AGND
41
40
AGND
1
42
G
2
AVDD
AVDD
3
43
R
4
B
AGND
5
44
STROBE
CH7001C
6
CHRONTEL
CLKEN*
7
39
VREF2
CLKOUT
8
38
AVDD
DVDD
9
37
PD0
DGND
10
36
TEST*
MS0
11
35
H
MS1
12
34
V
DVDD
13
33
UNDERSCAN
DGND
14
32
DVDD
XI
15
31
DGND
XO/FIN
16
30
NTSC/PAL*
PDI
17
29
RIGHT
18
19
20
21
22
23
24
25
26
27
28
VDD
RSET
GND
Y
CVBS
C
GND
VDD
UP
DOWN
LEFT
CHRONTEL
CH7001C
Figure 2: 44-pin PLCC
2
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CHRONTEL
CH7001C
Table 1 • Pin Description
Pin
Type
Symbol
Description
Analog ground
These pins provide the ground reference for the analog section of
CH7001C, and MUST be connected to the system ground to
prevent latchup. Please refer to Application Note AN-11 for
information on proper supply decoupling.
1, 5, 40, 42
Power
AGND
2, 4, 44
In
G, R, B
3, 38, 43
Power
AVDD
6
In
STROBE
7
In
CLKEN*
8
Out
CLKOUT
9, 13, 32
Power
DVDD
10, 14, 31
Power
DGND
11, 12
In
MS0, MS1
15
16
Note:
In
In
VGA Inputs 1
These pins should be terminated with 75Ω resistors and isolated
from switching digital signals and video output pins.
Analog Supply Voltage
These pins supply the 5V power to the analog section of the
CH7001C. For information on proper supply decoupling, please
refer to Application Note AN-11.
Strobe Input (active high, internal pull-up)
A logical HIGH input to this pin keeps chip mode pins (CLKEN*,
UNDERSCAN, MS[1:0], UP, DOWN, LEFT, and RIGHT) active.
These input signals are internally sampled on the high-to-low
transition of the STROBE signal. This allows the chip state to be
maintained while rendering these mode pins inactive.
Clock Enable (active low, internal pull-up)
A logical LOW input to this pin enables CLKOUT. CLKEN* should
be hardwired to ground to enable CLKOUT. Otherwise, CLKEN*
should be left unconnected or connected to VDD.
Clock Output
This pin defaults to 14.31818 MHz upon power-up. Further toggling
of the CLKEN* pin causes CLKOUT to output other internal test
clocks. When disabled (i.e., CLKEN*=1), this output is a logic LOW.
Setting the PD* pin low also causes CLKOUT to be logic LOW.
Digital Supply Voltage
These pins supply the 5V power to the digital section of CH7001C.
For information on proper supply decoupling, please refer to
Application Note AN-11.
Digital Ground
These pins provide the ground reference for the digital section of
CH7001C, and MUST be connected to the system ground to
prevent latchup. For information on proper supply decoupling,
please refer to Application Note AN-11.
Anti-flicker Mode Select Pins
These two pins are used to select one of four possible anti-flicker
vertical filter modes.
XI
Crystal Input 2
A 14.31818 MHz parallel resonance (± 50 ppm) crystal should be
attached between XI and XO/FIN. However, if an external CMOS
clock is attached to XO/FIN, XI should be connected to ground.
XO/FIN
Crystal Output or External FREF Input 2
A 14.31818 MHz (± 50 ppm) crystal may be attached between
XO/FIN and XI. An external CMOS compatible clock can be
connected to XO/FIN as an alternative.
1 The Typical Connection Diagram (Figure 4 on page 6) shows the VGA input configured for applications that do not require
RGB buffering before the monitor. In this configuration, 75 Ω input termination must be guaranteed either by termination by the
monitor connection, by discrete 75 Ω resistors on the PCB, or by a dummy 75 Ω termination connector. The total RGB trace on
the PCB must be kept as short as possible to avoid cable reflection problems. For further information, request a copy of
Application Note AN-11, “PC Board Layout Considerations for CH7001C. ”
2 Please refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance value for the
tuning capacitor should be obtained from the crystal manufacturer. For further information, request a copy of Application Note
AN-19, “Tuning Clock Outputs. ”
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CHRONTEL
CH7001C
Table 1 • Pin Description (continued)
Pin
4
Type
Symbol
Description
Power Down Inputs (active low, internal pull-up)
Asserting these signals place CH7001C into different power-down
states. (Refer to section on Power Management). Note: Use of
these pins is optional. Leaving these two pins floating will maintain
normal operating mode.
DAC Power Supply
These pins supply power to CH7001C’s internal DACs. Please refer
to Application Note AN-11 for information on proper supply
decoupling.
Reference Resistor
A 330Ω resistor with short and wide traces should be attached
between RSET and ground. No other connections should be made
to this pin.
DAC Ground
These pins provide the ground reference for CH7001C’s internal
DACs. For information on proper supply decoupling, please refer to
Application Note AN-11.
Luminance Output
A 75Ω termination resistor with short traces should be attached
between Y and ground for optimum performance. An optional low
pass filter circuit, shown in Figure 3 on page 5, may be used as an
alternative to the ferrite bead shown in Figure 4 on page 6.
Composite Output
A 75Ω termination resistor with short traces should be attached
between CVBS and ground for optimum performance. An optional
low pass filter circuit shown in Figure 3 on page 5, may be used as
an alternative to the ferrite bead shown in Figure 4 on page 6.
Chrominance Output
A 75Ω termination resistor with short traces should be attached
between C and ground for optimum performance. An optional low
pass filter circuit shown in Figure 3 on page 5, may be used as an
alternative to the ferrite bead shown on Figure 4 on page 6.
Up Position Control (active low, internal pull-up)
UP allows the screen display position to be moved up incrementally
for every toggle of this pin to ground. An internal schmitt trigger
minimizes switch bounce problems. UP may be connected directly
to the power supply or ground.
Down Position Control (active low, internal pull-up)
DOWN allows the screen display position to be moved down
incrementally for every toggle of this pin to ground. An internal
schmitt trigger minimizes switch bounce problems. DOWN may be
connected directly to the power supply or ground.
Left Position Control (active low, internal pull-up)
LEFT allows the screen display position to be moved to the left
incrementally for every toggle of this pin to ground. An internal
schmitt trigger minimizes switch bounce problems. LEFT may be
connected directly to the power supply or ground.
Right Position Control (active low, internal pull-up)
RIGHT allows the screen display position to be moved to the right
incrementally for every toggle of this pin to ground. An internal
schmitt trigger minimizes switch bounce problems. RIGHT may be
connected directly to the power supply or ground.
NTSC/PAL Mode Select Input (internal pull-up)
A logical HIGH input NTSC/PAL* pin selects NTSC operation. A
logical LOW input to NTSC/PAL* selects PAL operation. NTSC/PAL*
accepts CMOS logic level inputs and may be connected directly to
the power supply or ground.
17, 37
In
PDI, PD0
18, 25
Power
VDD
19
In
RSET
20, 24
Power
GND
21
Out
Y
22
Out
CVBS
23
Out
C
26
In
UP
27
In
DOWN
28
In
LEFT
29
In
RIGHT
30
In
NTSC / PAL*
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CHRONTEL
CH7001C
Table 1 • Pin Description (continued)
Pin
Type
Symbol
33
In
UNDERSCAN
34
In
V
35
In
H
36
—
TEST*
39
In
VREF2
41
In
VREF1
Description
Underscan Enable Pin (active high, internal pull-up)
A logical HIGH input to UNDERSCAN results to an output screen
that has approximately 12.5% horizontal underscan. This pin may
be connected directly to the power supply or ground.
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The
capacitive loading on this pin should kept to a minimum.
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should kept to a minimum. Please
refer to Application Note 11 “PC Board Layout Considerations
for CH7001C.”
Test Pin (active low, internal pull-up)
Connect a capacitor in the range of 2.2uF - 4.7uF from this pin
to GND to ensure proper functionality of the UNDERSCAN/
OVERSCAN feature.
Internal Voltage Reference
VREF2 provides a typical 2.5V reference that is used as an internal
bias to the ADCs. A 0.1 µF decoupling capacitor should be
connected between VREF2 and ground.
ADC Voltage Reference Input / Output
VREF1 provides a typical 1.235V reference that sets the RGB input
full scale at 0.75V. A 0.1 µF decoupling capacitor should be
connected between VREF1 and ground. VREF1 may also be forced
by external reference.
Optional Output Filter
47pF
1.2uH
1.2uH
Y,C, CVBS
OUTPUT
75 Ohms
150pF
270pF
1
Figure 3: Optional Output Filter
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5
CHRONTEL
CH7001C
Ferrite Bead
+5V
Ferrite Bead
0.1uF
0.1uF
Ferrite Bead
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF +
3
AVDD
34
VGA
Card
18
25
VDD
VDD
9
13
DVDD
DVDD
32
DVDD
41
H
VREF1
0.1uF
V
39
4
VREF2
R
2
0.1uF
G
8
44
CLKOUT
75 Ohms
75 Ohms
To MONITOR or
TERMINATION
RESISTORS
75 Ohms
B
21
26
75 Ohms
UP
Switch
23
27 DOWN
28
Switch
Ferrite Bead
Y
Ferrite Bead
C
LEFT
75 Ohms
CH7001C
29 RIGHT
(PLCC pinout)
12, 11
MS [1:0]
33
22
Ferrite Bead
CVBS
UNDERSCAN
30
75 Ohms
NTSC/PAL*
7
(1)
S-VIDEO
CONNECTOR
7404 7404
43
AVDD
COMPOSITE
CONNECTOR
35
38
AVDD
CLKEN*
37,17
PD [0:1]
6
STROBE
36
2.2uF-4.7uF (2)
TEST*
RSET
16
XO/FIN
14.31818
MHz
15
19
330 Ohms
XI
AGND
1
5
GND
40
42
20
DGND
24
10
14
31
Figure 4: CH7001C Typical Connection Diagram
Note: 1 If the CLKOUT signal is not used, either connect CLKEN* to VDD, or leave it unconnected.
Note: 2 An external pull-up resistor should not be connected to the TEST* pin.
6
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CHRONTEL
CH7001C
General Description
The CH7001C is a fully integrated solution for converting analog RGB and synchronization signals from a standard
VGA source into high-quality NTSC or PAL video signals. All essential circuitry for this conversion (memory,
memory control, PLL, ADC, DAC, digital filters, digital NTSC/PAL encoder) are present in this IC. All internal
signal processing, including NTSC/PAL encoding, is performed using digital techniques to ensure that the highquality video signals are not affected by drift issues associated with analog components. No additional adjustment
is required during manufacturing.
CH7001C is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support
components (passive components, 14.31818 MHz crystal) are required for full operation. The CH7001C easily
integrates into notebook computers and PC add-on graphics cards.
Functional Description
The analog RGB inputs are digitized on a pixel-by-pixel basis by three 8-bit video A/D converters. The digitized
RGB inputs are fed to a block where scan-rate conversion and programmable 3-line vertical filtering are performed.
The vertical filter eliminates flicker at the output, while the scan-rate converter transforms the VGA horizontal scanrate to either NTSC or PAL scan-rates.
The digitized RGB inputs are encoded into luminance (Y) and color-difference (U,V) signals through the color
space converter. The resulting YUV signals are filtered through digital filters to minimize aliasing problems (the
frequency response is shown in Figure 5 on page 8). The digital encoder receives the filtered signals and transforms
them to composite and S-video outputs, which are converted by the three 8-bit DACs into analog outputs. Highquality video is ensured by using 24 bits per pixel processing throughout the entire signal path.
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CHRONTEL
CH7001C
General Description (continued)
Figure 5: U,V, and Y Filter Response
Y_SV
CH7001C Detailed Frequency Response
Y_CV
-0
UV
-2
dB
-4
-6
-8
-10
0
1
2
3
4
5
6
Freq (MHz)
CH7001C Frequency Response
-0
-10
dB
-20
-30
-40
-50
0
1
2
3
4
5
6
7
8
9
10
11
12
Freq (MHz)
8
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CHRONTEL
CH7001C
General Description (continued)
Clock Generation and Video Timing
All clock signals of the CH7001C are generated from the VGA synchronization inputs by a low-jitter, PLL circuit.
The VGA input and sync timing are illustrated in Figures 6 and 7 below. The VGA pixel clock is generated
internally, using the VGA horizontal sync signal, and is used for sampling the RGB inputs pixel-by-pixel, which
aids in preventing aliasing artifacts.
All synchronization and color burst envelope pulses are internally generated using only the timing signals provided
by the VGA synchronization inputs.
31.78 µs
H
25.42 µs
R,G,B
DATA
3.81 µs
ACTIVE VIDEO
1.91 µs
0.64 µs
Note: The timing diagram shown is for 640 x 480, 60 Hz VGA mode
Figure 6: Typical VGA Input Timing
31.78 µs
H
63.56 µs
V*
(ACTIVE LOW)
Figure 7: VGA Horizontal and Vertical Sync Timing
Internal Voltage Reference
The on-chip generated ADC voltage references are brought out to pins VREF1 and VREF2 for decoupling purposes.
VREF1 and VREF2 should each have a 0.1 µF decoupling capacitor between each pin and ground. VREF2
provides a typical 2.5V reference, used for setting the internal bias to the ADCs, and VREF1 provides a typical
1.235V reference, used for setting the RGB input full scale at 0.75V. VREF1 can be forced by an external voltage
reference in order to accommodate different RGB input ranges. An additional on-chip bandgap circuit is used in the
DAC to generate a reference voltage which, in conjunction with a reference resistor at pin RSET, sets the output
ranges of the DACs.
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CHRONTEL
CH7001C
General Description (continued)
Strobing
The CH7001C programmable pins (MS[1:0], UNDERSCAN, NTSC/PAL*, LEFT, RIGHT, UP, and DOWN) may
be connected to shared signal lines and then strobed in using the STROBE pin. By asserting the STROBE pin high,
the state of the programmable pins is internally sampled during the STROBE signal’s high-to-low transition. A
logical low input to the STROBE pin allows the chip state to be maintained, while rendering the programmable pins
inactive.
Power Management
The CH7001C supports four operating states including Normal (On), Power Down, S-Video Off, and Composite
Off) in order to provide optimal power consumption for the application involved. Using pins PD0 and PD1, the
CH7001C ay be placed in either Normal state or any of the three power managed states as listed below:
PD1
1
PD0
1
Operating State
Normal (On)
Functional Description
All functions and pins are active (default state with inputs floating.)
0
1
Power Down
Most pins and cicruitry are disabled. This reduces power to only 1%
1
0
S-Video Off
of normal operating power.
Power is shut off to the unused DACs associated with Y and C outputs.
Composite Off
This reduces power to 81% of normal operating power.
Power is shut off to the unused DAC associated with CVBS output.
0
0
This reduces power to 89% of normal operating power.
Color Burst Accuracy*
The CH7001C employs a proprietary technique for generating the color sub-carrier frequency. This method allows
the sub-carrier frequency to be accurately generated from a 14.31818 MHz crystal oscillator, leaving the accuracy of
the sub-carrier frequency independent of the sampling rate. As a result, the CH7001C is compatible with any VGA
card, since the CH7001C sub-carrier frequency is not dependent on the pixel rates of VGA card manufacturers.
This feature is a significant benefit, since even a ± 0.01% sub-carrier frequency variation may be enough to cause
some television monitors to lose color lock.
10
*Patent number 5,874,846
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CHRONTEL
CH7001C
Programmability
All operational modes of the CH7001C are accessed directly through the package pins, making the CH7001C
programmable without the use of an additional microcontroller. Some of the programmable features are: horizontal
overscan/underscan control, NTSC or PAL operation, selectable anti-flicker filter modes, and adjustable horizontal
and vertical display positioning capabilities.
Horizontal Overscan/Underscan
Horizontal underscan mode is enabled via the UNDERSCAN pin. By setting this pin high, the resulting output
screen experiences a 12.5% horizontal underscan.
The CH7001C also implements an overscan/underscan mode that is controllable through the PC. Software control
is available only when the underscan input is inactive (i.e., UNDERSCAN = 0) and is accomplished by
programming the length (in VGA line periods) of the vertical sync pulse.
When the CH7001C detects the vertical sync pulse as having fewer than eight VGA line periods, the device operates
in overscan mode; when it detects the vertical sync pulse as having more than eight VGA line periods, it operates in
underscan mode. The CH7001C determines the number of VGA line periods through an internal circuitry that
continuously analyzes the width of the VGA vertical sync input.
Software control is overridden if the underscan input is set high.
NTSC or PAL Operation
Composite and S-video outputs are supported in either NTSC or PAL format, as shown in Figures 8 through 10.
These outputs can be conveniently switched to either format via the NTSC/PAL* pin. If the NTSC/PAL* pin is set
low, PAL output format is selected. If the NTSC/PAL* is set high, NTSC output format is selected. See Figures 11
through 16 on pages 14 through 16 for illustrations of the composite and S-video output waveforms.
A
B
C
D
E
F
G
H
Figure 8: NTSC / PAL Composite Output
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CHRONTEL
CH7001C
General Description (continued)
Table 2 • NTSC/PAL Composite Output Timing Parameters (in µS)
Symbol
Description
A
NTSC
PAL
OVERSCAN
UNDERSCAN
OVERSCAN
UNDERSCAN
Front Porch
1.35
1.20
1.35
1.20
B
Horizontal Sync
4.69
4.70
4.69
4.70
C
Breezeway
0.64
0.57
0.56
0.49
D
Color Burst
2.66
2.37
2.39
2.12
E
Back Porch
1.47
1.31
1.83
1.63
F
Black
2.38
5.10
2.37
5.11
G
Active Video
50.51
45.19
50.51
45.19
H
Black
0.00
3.12
0.00
3.12
START
OF
VSYNC
ANALOG
FIELD 1
520
521
522
523
524
525
1
2
3
4
5
6
7
8
9
ANALOG
FIELD 2
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
LINE RATE = HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480)
FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480)
Figure 9: Interlaced NTSC Video Timing
12
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CHRONTEL
CH7001C
General Description (continued)
START
OF
VSYNC
ANALOG
FIELD 1
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
ANALOG
FIELD 2
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
ANALOG
FIELD 3
620
621
622
623
624
625
1
2
3
4
5
6
7
8
9
10
ANALOG
FIELD 4
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
Figure 10: Interlaced PAL Video Timing
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13
15.23
16.99
13.49
14.93
0.571
0.637
0.506
0.560
Blue
Black
Blank
10.49
11.59
8.74
9.69
8.26
7.49
0.393
0.435
0.327
0.363
0.281
0.310
Sync
0.50
0.640
0.019
0.024
Note:
100% amplitude, 100% saturation color bars are shown
Note:
VREF1 = 1.235V, RSET = 330Ω, 75Ω doubly terminated load.
BLACK
Magenta
Red
BLUE
0.745
0.828
0.679
0.750
BLACK
19.85
22.08
18.11
20.01
RED
Cyan
Green
COLOR BARS :
BLUE
0.922
1.030
0.857
0.953
MAGENTA
24.60
27.48
22.85
25.41
RED
White
Yellow
GREEN
V
MAGENTA
mA
CYAN
Color / Level
YELLOW
CH7001C
WHITE
CHRONTEL
White
Yellow
26.05
24.60
24.00
22.85
0.977
0.922
0.900
0.857
Cyan
Green
20.67
19.85
18.59
18.11
0.775
0.745
0.697
0.679
Magenta
Red
15.57
15.23
13.52
13.49
0.584
0.571
0.507
0.506
Blue
Black
Blank
10.19
10.49
8.74
7.49
8.26
0.393
0.382
0.327
0.281
0.310
Sync
0.50
0.640
0.019
0.024
COLOR BARS :
Note:
100% amplitude, 100% saturation color bars are shown
Note:
VREF1 = 1.235V, RSET = 330Ω, 75Ω doubly terminated load.
GREEN
V
CYAN
mA
YELLOW
Color / Level
WHITE
Figure 11: NTSC Y (Luminance) Output Waveform
Figure 12: PAL Y (Luminance) Video Output Waveform
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CHRONTEL
CH7001C
BLACK
BLUE
RED
MAGENTA
COLOR BARS :
GREEN
VV
CYAN
mA
mA
YELLOW
Color / Level
WHITE
General Description (continued)
Cyan / Red
22.60 0.994/1.000
0.848
26.51/26.66
Green / Magenta 25.89/25.89
21.85 0.971/0.971
0.819
Yellow / Blue
19.61 0.877/0.877
0.735
23.39/23.39
Peak Burst
15.98
19.34
0.599
0.725
Blank
12.49
15.59
0.468
0.585
Peak Burst
11.85
8.99
0.444
0.337
3.579545 MHz Color Burst
(9 cycles)
Yellow / Blue
Green / Magenta
Cyan / Red
5.37
7.8/7.8
0.201
0.292/0.292
5.3/5.3
3.12 0.199/0.199
0.117
2.37 0.175/0.170
0.089
4.68/4.52
Note: 1 100% amplitude, 100% saturation color bars are shown
Note: 2 VREF1 = 1.235V, RSET = 330Ω, 75Ω doubly terminated load.
Cyan / Red
Green / Magenta
0.994/1.000
26.51/26.66
22.60
0.848
25.89/25.89
0.971/0.971
21.85
0.819
Yellow / Blue
23.39/23.39
0.877/0.877
19.61
0.735
Peak Burst
16.23
19.34
0.609
0.725
Blank
12.49
15.59
0.468
0.585
11.85
8.74
0.444
0.328
Peak Burst
BLACK
BLUE
RED
MAGENTA
COLOR BARS :
GREEN
V V
CYAN
mA
YELLOW
Color / Level
WHITE
Figure 13: NTSC C (Chrominance) Video Output Waveform
4.433619 MHz Color Burst
(10 cycles)
Yellow / Blue
Green / Magenta
Cyan / Red
5.37
7.8/7.8
0.201
0.292/0.292
5.3/5.3
3.12
0.117
0.199/0.199
4.68/4.52
2.37
0.089
0.175/0.170
Note: 1 100% amplitude, 100% saturation color bars are shown
Figure 14: PAL C (Chrominance) Video Output Waveform
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15
CHRONTEL
CH7001C
BLACK
1.026
1.030
BLUE
27.37
27.47
BLUE
White
COLOR BARS :
RED
1.271
1.246
RED
33.89
33.23
MAGENTA
Peak Chroma
GREEN
V
CYAN
mA
YELLOW
Color / Level
WHITE
General Description (continued)
3.579545 MHz
Color Burst
(9 Cycles)
Peak Burst
Black
Blank
12.00
12.03
9.68
9.62
8.27
8.16
0.450
0.451
0.363
0.360
0.310
0.306
Peak Burst
4.32
4.53
0.162
0.170
Sync
0.50
0.640
0.019
0.024
Note: VREF1=1.235V, RSET=330Ω, 75Ω, doubly terminated load.
1.271
1.193
White
26.05
27.37
1.026
0.977
COLOR BARS :
BLACK
31.81
33.89
MAGENTA
Peak Chroma
GREEN
V
CYAN
mA
YELLOW
Color / Level
WHITE
Figure 15: Composite NTSC Video Output Waveform
4.433619 MHz
Color Burst
(10 Cycles)
Peak Burst
12.00
12.03
0.450
0.451
Blank/Black
8.26
8.64
0.310
0.324
Peak Burst
4.53
4.58
0.171
0.170
Sync
0.643
0.50
0.019
0.024
Note: VREF1=1.235V, RSET=330W, 75W, doubly terminated load.
Figure 16: Composite PAL Video Output Waveform
16
201-0000-028 Rev 3.0, 6/2/99
CHRONTEL
CH7001C
General Description (continued)
Anti-Flicker Filter Modes
The CH7001C integrates a 3-line vertical filter circuitry to help eliminate the flicker associated with interlaced
displays. The CH7001C provides four anti-flicker filter modes programmable via the anti-flicker mode select pins
MS[1:0]. For a list of the filter modes available, please refer to Table 3 below.
Table 3 • Anti-Flicker Filter Modes
MS1
0
0
1
1
MS0
0
1
0
1
Filter Modes
0:1:0 averaging
1:3:1 averaging
1:2:1 averaging
1:1:1 averaging
Programmability
Display Position Control
UP, DOWN, LEFT, and RIGHT are dedicated inut pins controlling the NTSC or PAL display position. Upon power
up, the internal position registers for a typical VGA input center the display on the television screen. With each
toggle of any position pin to ground, the display will shift four pixels in the respective direction. For example, if the
LEFT pin is toggled to ground once, the screen display will move four pixels to the left. Similarly, if the RIGHT pin
is toggled to ground once, the screen display will move four pixels to the right. The shift of the display occurs
during the low-to-high transition of the position pin. Toggling conflicting pins, such as the LEFT and RIGHT pins
for example, simultaneously is not allowed. The minimum time required for the display position pins to be held low
is 40 ns.Electrical Specifications
Table 4 • Absolute Maximum Ratings
Symbol
TSC
TAMB
TSTOR
TJ
TVPS
PMAX
Description
VDD relative to GND
Input voltage of all digital pins1
Analog output short circuit duration
Ambient operating temperature
Storage temperature
Junction temperature
Vapor phase soldering (one minute)
Maximum Power dissipation
Min
- 0.5
GND - 0.5
Typ
Max
7.0
VDD + 0.5
Indefinite
- 55
- 65
125
150
150
220
TBD
Units
V
V
Sec
°C
°C
°C
°C
W
Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are
stress ratings only. Functional operation of device at these or any other conditions above those indicated under the normal
operating conditions section of this specification is not recommended, Exposure to absolute maximum rating conditions for
extended periods may affect relaibility.
The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device.
Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup.
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17
CHRONTEL
CH7001C
Table 5 • Recommended Operating Conditions
Symbol
VDD
AVDD
DVDD
TA
RL
VREF1
VREF2
Description
DAC power supply voltage
Analog supply voltage
Digital supply voltage
Ambient operating temperature
Output load to DAC outputs
ADC voltage reference input/output
Internal voltage reference
Min
4.75
0
1.20
Table 6 • Electrical Characteristics (Operating Conditions: T
Symbol
IREF1
Note:
Description
Video D/A resolution
Full scale output current
Video level error
using external reference
using internal reference
VREF1 input current (VREF1 = 1.235V)
Total Current Consumption
(both S-video & composite outputs are On)
Typ
5.00
5.00
5.00
25
37.5
1.235
2.5
Min
8
A
Max
5.25
Units
V
70
°C
Ω
V
V
1.32
– 70° C, VDD = 5V ± 5%)
=0
Typ
8
33.89
Max
8
Unit
Bits
mA
5
10
%
%
µA
mA
10
340
As applied to Tables 4, 5, and 6, Recommended Operating Conditions are used as test conditions unless otherwise specified.
Table 7 • Digital Inputs / Outputs
Symbol
VOH
VOL
VIH
VIL
IPU
ILK
CDIN
CDOUT
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input internal pull-up current
Input leakage current
Input capacitance
Output capacitance
Test Condition @ T A = 25
IOH = - 400 µA
IOL = 3.2 mA
Min
2.4
Typ
2.0
GND - 0.5
5
-10
f = 1 MHz, VIN = 2.4V
7
10
Max
Units
V
0.4
V
VDD + 0.5
V
0.8
V
25
µA
10
µA
pF
pF
ORDERING INFORMATION
18
Part number
Package type
Number of pins
Voltage supply
CH7001C-V
PLCC
44
5V
201-0000-028 Rev 3.0, 6/2/99