High-Level Design Technology Used to Integrate a Microcontroller and a CD DSP on a Single Chip Microcontroller with On-Chip CD DSP CXP401 Sony is committed to creating a wide range of products combining various peripheral functions around a high-performance CPU base, and have developed a product line of microcontrollers optimal for specific applications. Now, these efforts have progressed to the point where this area could be called the ASIC microcontroller field. The product of this release corresponds to an all-out effort at chip set integration aimed at achieving an ASIC microcontroller optimal for CD audio applications, and achieves the integration of both a DSP and a microcontroller on a single chip. The newly-developed CXP401 adopts the latest audio DSP as its DSP and an SPC500 Series CPU core, which has an extensive track record, as its CPU. As a result, the CXP401 can contribute to the creation of even more compact CD players. CPU Block The CPU used in the CXP401 is the CPU core from the SPC500 Series redesigned for use as an ASIC core. The ROM and RAM capacities were chosen, based on experience developing CD players, to be 6 KB of ROM and 400 words of RAM. In particular, these are capacities that are adequate for the implementation of popularly-priced CD players. By providing an on-chip LCD controller/driver as a display function, the CXP401 increases the reusability of software developed in the past for SPC500 Series microcontrollers. Since connection between the internal V O I C E When we were considering integrating a microprocessor and a DSP on a single chip, we had a serious argument over the pins. A microcontroller has 64 pins and a DSP has 100 pins, so simple arithmetic would result in a 164pin product. This many pins would be completely impractical. We analyzed the functions and usage of each pin, and merged pins with common functions wherever possible. Somehow, we managed to reduce the count to 112 pins. Still, achieving this amount of functionality in a 100-pin product remains a goal for our next design effort. n n n n n n n DSP and the CPU uses port-type I/O, applications can be developed using the same concepts as software developed previously. DSP Block The built-in DSP is the latest DSP, and includes digital filters, a D/A converter, and low-pass filters for audio signals and, despite being a popularly-priced product, provides characteristics equivalent to high-end audio. In particular, it also includes wide capture and digital bass boost functions as added functionality. When the wide capture function is used, playback can continue without fluctuations in the audio even if there are variations in the disc speed. The digital bass boost function has the characteristics shown in table 1, and allows the playback characteristics to be modified without any additional external components. Piggyback/Evaluator Chip for Program Development Sony provides the CXP401Z piggyback/evaluator chip for program development, similar to that provided for the SPC500 and SPC700 Series microcontrollers. The assembler, debugger, and emulator for the SPC500 Series can be used directly as a software development environment for the CXP401. SPC500 Series CPU core 6-KB ROM, 400-word RAM LCD controller/driver on chip DSP block: Includes digital filter, D/A converter, and low-pass filter circuits D/A converter performance: 8fs, 100 dB or better Wide capture and digital bass boost functions provided CXP401Z piggyback/evaluator chip available for program development System Structure By integrating a microcontroller and a DSP on a single chip, the CXP401 allows a CD system to be formed from three chips, the CXP401 itself, an SSP (the CXA2542), and a motor driver, as shown in figure 1. CXP401 RF Amp. + SSP CXA2542Q DSP Block 1-bit D/A LPF Audio Out CPU Block Driver Speaker Key LCD LCD Controller/Driver SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 Servo Auto Sequencer SPC500 CPU Core RAM T/C EPROM Collector Analog Out AVSS AVDD AOUT2 AIN2 LOUT2 AVSS XVSS XTAO XTAI XVDD AVSS LOUT1 AIN1 AOUT1 AVDD AVSS BCKI BCK PCMOI PCMO LRCKI LRCK RMC XRST PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 n Figure 2 CXP401 Block Diagram 10.00 Normal DBB MID DBB MAX 6.00 4.00 2.00 [dB] 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 3 1e + 02 1-bit DAC Digital Filter RST 8.00 3 1e + 03 3 1e + 04 Digital bass boost frequency response [Hz] n Figure 3 Digital Bass Boost Characteristics Asymmetry Collector D/A I/F RMC Port –14.00 1e + 01 Digital PLL 16K RAM SIO PA0 PA1 PA2 PA3 Digital CLV EFM Demodulator Port CPU I/F ROM DATO XLTO CLKO SEIN CNIN SBSO EXCK LOCK MON MOS MOP C4M VPCO1 VPCO2 VCK1 V16M VCTL PCO FILI FILO AVSS CLTV AVDD BIAS RF ASYI ASYO SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VCL1 VCL2 VCL3 SCOR EMPHI XRSTO FOK GFS n Figure 1 System Structure 3 Test Circuit WFCK QTOP XPCK RFCK C2PO XROF MNT0 MNT1 MNT3 DOUT TEST1 TEST2 DSPTEST CPUTEST VDD VSS VDD VSS VDD VSS