ADVANCE INFORMATION DRX 3960A Digital Receiver Front-end Edition Feb. 8, 2001 6251-510-2AI MICRONAS DRX 3960A ADVANCE INFORMATION Contents Page Section Title 4 4 5 6 7 7 7 7 1. 1.1. 1.2. 1.3. 1.3.1. 1.3.2. 1.3.3. 1.3.4. Introduction Features Quick Reference Data Analog TV Application Initialization for Analog TV Multistandard Configuration for B/G, L, I, D/K and M/N Multistandard Configuration for L’ FM Radio 8 8 8 8 8 8 8 8 8 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. Functional Description Input Amplifier with TOP Setting Carrier Recovery Channel Filtering and Audio/Video Splitting Video and Tuner AGC Group Delay Equalizing Peaking SIF AGC Output Ports 9 9 9 10 10 10 3. 3.1. 3.2. 3.3. 3.4. 3.5. Standard Specific Filter Curves Standard B Standard G Standard D/K, I, L/L’ Standard M/N Standard FM 11 11 11 12 13 14 14 14 14 14 15 15 15 16 18 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.4.1. 4.1.4.2. 4.1.4.3. 4.2. 4.3. 4.4. 4.4.1. 4.4.2. 4.4.3. Control Interface I2C Bus Interface Device and Subaddresses Description of CONTROL Register Protocol Description Proposals for General DRX 3960A I2C Telegrams Symbols Write Telegrams Read Telegrams List of Control Registers List of Status Registers Description of User Registers Write Register on I2C Subaddress 03hex Write Register on I2C Subaddress 10hex Read Register on I2C Subaddress 11hex 19 19 19 21 22 23 5. 5.1. 5.2. 5.3. 5.4. 5.5. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configuration Electrical Characteristics 2 Micronas ADVANCE INFORMATION DRX 3960A Contents, continued Page Section Title 23 23 24 24 24 5.5.1. 5.5.2. 5.5.3. 5.5.4. 5.6. Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Recommended Tuner Characteristics Characteristics 28 6. Application Circuit 30 7. Data Sheet History Micronas 3 DRX 3960A ADVANCE INFORMATION Digital Receiver Front-end Release Note: Revision bars indicate significant changes to the previous edition. 1. Introduction The Digital Receiver Front-end DRX 3960A performs the entire multistandard Quasi Split Sound (QSS) TV IF processing, AGC, video demodulation, and generation of the second sound IF (SIF) with only one SAW filter. The IC is designed for applications in TV sets, VCRs, PC cards, and TV tuners. The alignment-free DRX 3960A needs no special external components. All control functions and status registers are accessible via I2C bus interface. Therefore, it simplifies the design of high-quality, highly standardized IF stages. Due to its mixed signal structure and the digital demodulation, the IC offers unique features and is prepared for digital TV. – Standard specific digital picture carrier recovery: • alignment-free • quartz-stable and accurate • stable frequency lock at 100% modulation and overmodulation up to 150% • quartz-accurate AFC information – Programmable standard specific digital group delay equalizing – Automatically frequency-adjusted Nyquist slope, therefore optimal picture and sound performance over complete lock in frequency range – Standard-specific digital AGC and delayed tuner AGC with programmable tuner Take Over Point – Fast AGC due to linear structure – Adaptive back porch control, therefore fast positive modulation AGC – No sound traps needed at video output – Second SIF output with standard dependent pre-filtering and amplitude controlled output level – Optimal sound SNR due to carrier recovery without quadrature distortions 1.1. Features – FM radio capability without external components and with standard TV tuner – Multistandard QSS IF processing with a single SAW – Highly reduced amount of external components (no tank circuit, no potentiometers, no SAW switching) – Prepared for digital TV (DVB-C, DVB-T, ATSC) – Programmable IF frequency (38.9 MHz, 45.75 MHz, 32.9 MHz, 36.125 MHz etc.) – I2C bus interface – Digital IF processing for the following standards: B/G, D/K, I, L/L’, and M/N – Standard specific digital post filtering – Standard specific digital video/audio splitting fref DSP Clock Generation D Filtering A TOP Carrier Recovery IF In TAGC VAGC AAGC Tuner AGC D A EQU D CVBS A D 2nd SIF A I2C Fig. 1–1: Block diagram of the DRX 3960A 4 Micronas DRX 3960A ADVANCE INFORMATION 1.2. Quick Reference Data Parameter Min. Typ. Max. Unit Supply voltage, analog 5 V Current consumption, analog 110 mA Supply voltage, digital 3.3 V Current consumption, digital 60 mA Input frequency 30 Maximum wanted signal input voltage minimum TOP gain: maximum TOP gain: 47 200 20 Remarks MHz mVpp mVpp Lock in range 0.8 1.0 MHz MHz direction adjacent channel direction own channel center freq. quartz stable Intermodulation ratio α1.07 65 dB blue picture, PSC1=−13dB, no sound shelf Weighted video S/N (CCIR567, 10 kHz...5 MHz) 56 58 dB Unweighted video S/N (10 kHz...5 MHz) 49 51 dB Weighted sound S/N (black, CCIR468 quasi peak, SC1/SC2) 62/58 dB dev. = 27 kHz Weighted sound S/N (FuBK, CCIR468 quasi peak, SC1/SC2) 55/50 dB dev. = 27 kHz CVBS output voltage 2 Vpp programmable Second IF output voltage 0.8 Vpp programmable Delayed Tuner AGC external voltage Micronas 8 V 5 DRX 3960A ADVANCE INFORMATION 1.3. Analog TV Application The Digital Receiver Front-end DRX 3960A is able to replace a conventional IF IC including several SAWs. Nevertheless, quasi split sound processing is performed with standard specific internal filtering and group delay equalizing. The input signal of the DRX 3960A is the TV IF with its carrier at: – 38.9 MHz (B/G, D/K, I, L, and M/N in multistandard applications) – 32.9 MHz (L’) After the desired standard information is transferred into the DRX 3960A, the following standard specific procedures are performed: – Adjacent channel suppression – Carrier locking including AFC information generation – Nyquist slope adjustment – Video/sound splitting – Video AGC, including delayed tuner AGC – Group delay post distortion – Video and sound frequency shaping – 45.75 MHz (M/N in single standard applications) – other frequencies are also programmable – Video demodulation – Second SIF generation and AGC – 36.125 MHz (DVB-C or DVB-T in further versions) These signals are available from conventional tuners. For pre-filtering, one 8-MHz channel SAW filter must be used, e.g. the Epcos X6966M. Nevertheless, the entire multistandard processing is performed. The prefilter limits the signal bandwidth to 8 MHz and suppresses major parts of the adjacent channels. Similar to conventional analog front-ends, the tuner gain is controlled by the DRX 3960A. New AGC algorithms have been implemented for superior level tracking for both positive and negative video modulation. The demodulated CVBS signal and the second sound IF (SIF) are available as analog output signals. If an FM radio channel is transferred to the IF inputs, down-mixed by means of a standard TV tuner, it can be preselected and further down-mixed by the DRX 3960A. Thus, a succeeding sound demodulator, e.g. the MSP, will be able to demodulate that channel. The DRX 3960A operates with its own quartz or with appropriate external clocks, e.g.: – 13.5, 20.25, 27 MHz from an employed video IC – 1, 4 MHz from the tuner CVBS Tuner SAW VPC/VCT DRX 3960A 2nd SIF Delayed Tuner AGC MSP I2C Fig. 1–2: Multistandard video and sound IF processing with DRX 3960A 6 Micronas ADVANCE INFORMATION DRX 3960A 1.3.1. Initialization for Analog TV The DRX 3960A is able to operate with different reference frequencies. If 20.25 MHz is used, REF_SW has to be connected to ground; additionally, if a lower frequency is used, SYN_REF (control register) has to be set accordingly. If a higher frequency is used, REF_SW has to be connected to VDVDD and SYN_REF has to be set accordingly. In the 20.25 MHz case, no I2C command is needed. The standard which should be processed has to be set via I2C bus. Additional controlling is only needed if the default values for the remaining write registers are not applicable. 1.3.2. Multistandard Configuration for B/G, L, I, D/K and M/N In multistandard applications for B/G, L, I, D/K, and M/N, the picture carrier frequency at the tuner output should be 38.9 MHz. The sound carrier frequencies are below in a distance corresponding to the transmission standard. Thus, all wanted channel components are within the passband of the SAW and forwarded to the DRX 3960A. The demodulated and filtered video signal will be available at the CVBS output and the downconverted sound carriers will be available at the 2nd SIF output. 1.3.3. Multistandard Configuration for L’ In the L standard, the band 1 channels (40 MHz to 65 MHz) have a different frequency configuration. Their sound carriers are below the according picture carrier. This sub-standard is called L’. In that case, the picture carrier frequency at the tuner output should be 32.9 MHz. Using conventional tuners, the sound carrier frequencies in L’ at the tuner output are above the picture carrier. Thus, again all wanted channel components are within the passband of the SAW. 1.3.4. FM Radio In FM radio applications, the tuner has to down-convert the wanted channel to 32.4 MHz. Therefore, the lower slope of the SAW frequency response rejects adjacent carriers on one side of that channel. The DRX 3960A further down-converts the wanted channel to 5.5 MHz. After additional filtering, the signal is fed to the 2nd SIF output. Micronas 7 DRX 3960A 2. Functional Description ADVANCE INFORMATION is higher than 38% of the CVBS amplitude, or lower than 17%, it is set to the according limit. 2.1. Input Amplifier with TOP Setting The first block of the DRX 3960A is a low-noise preamplifier. It has a setable gain between 0 and 20 dB for setting the Tuner take Over Point voltage (TOP). This adjustment is responsible for optimal tuner operation. Note: The TOP is the tuner input voltage at which the IF circuit (e.g. the DRX 3960A) begins to reduce the tuner gain. Thus, above this voltage the tuner output voltage remains nearly constant. Of course, the gain of the tuner is only allowed to be reduced if the S/N is sufficiently high. A level of 60...70 dBµV at the antenna input is a typical value for the starting point of gain reduction. If the video AGC gain is to low, the tuner AGC increases its output current. Thus, the tuner reduces its gain. The actual gain value of both control loops can be read out (VID_GAIN, TAGC_I) as information about the input signal strength. 2.5. Group Delay Equalizing The group delay is set to compensate the pre-distortion of the transmitter. Additionally, the standard settings can be changed by means of four coefficients to optimize the complete signal path (EQU_0, EQU_1, EQU_2, EQU_3). 2.2. Carrier Recovery A digital PLL performs the tracking of the picture carrier and therefore synchronous demodulation. The lock in range refers to the desired IF frequency which is chosen according to the programmed TV standard (e.g. 32.9 MHz at L’ or 38.9 MHz at all other standards). The PLL incorporates its own AFC function and provides the frequency offset from the desired IF frequency for external use (CR_FREQ). A special digital validation algorithm allows long frequency lock at 100% modulation. Additionally, the PLL aligns the digital calculated Nyquist slope to the picture carrier frequency. 2.6. Peaking To shape the frequency response, a peaking filter is implemented. The following figure indicates the possible frequency responses: Video Response [dB] 10 7.5 5 2.5 0 -2.5 -5 Due to its digital implementation, the carrier recovery is absolutely offset-free, alignment-free, drift-free, and quartz-accurate. 2.3. Channel Filtering and Audio/Video Splitting According to the selected standard, channel filtering (suppression of not wanted signals) is performed internally by digital filters. These filters additionally separate the video and sound components of the desired channel and transfer them to the according output. The processing is competitive to conventional QSS systems. 2.4. Video and Tuner AGC The video AGC controls the CVBS amplitude to a given value (VID_AMP). This value may be set via I2C bus. In positive modulation mode, an adaptive back porch control (BPC) is activated. If the detected BP reference 8 -7.5 1 2 3 4 5 Frequency [MHz] Fig. 2–1: Peaking filter frequency response The peaking value is setable via I2C (VID_PEAK). 2.7. SIF AGC The SIF AGC controls the level of the sound carrier output. Four different reference amplitude values are available (SIF_REF) . The actual gain (SIF_GAIN) can be read out and set via I2C. According to the standard, the time constant is switched to FM/NICAM (fast AGC) or AM (slow AGC). 2.8. Output Ports Six general purpose output ports can be switched to high or low level. Micronas DRX 3960A ADVANCE INFORMATION 3. Standard Specific Filter Curves The external SAW only performes a coarse attenuation of major parts of adjacent channels. The main filtering is done by means of the DSP. The following figures indicate the overall filter curves of the DRX 3960A including the SAW. 3.1. Standard B 3.2. Standard G Video Response [dB] Video Response [dB] 10 10 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 2 4 6 8 10 2 4 6 SIF Response [dB] SIF Response [dB] 10 10 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 4 6 8 10 Frequency [MHz] Micronas 10 Frequency [MHz] Frequency [MHz] 2 8 2 4 6 8 10 Frequency [MHz] 9 DRX 3960A ADVANCE INFORMATION 3.3. Standard D/K, I, L/L’ 3.4. Standard M/N Video Response [dB] Video Response [dB] 10 10 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 2 4 6 8 10 2 4 6 Frequency [MHz] SIF Response [dB] 10 Frequency [MHz] SIF Response [dB] 10 10 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 2 8 4 6 8 10 Frequency [MHz] 2 4 6 8 10 Frequency [MHz] 3.5. Standard FM SIF Response [dB] 10 0 -10 -20 -30 -40 -50 -60 2 4 6 8 10 Frequency [MHz] 10 Micronas DRX 3960A ADVANCE INFORMATION 4. Control Interface 4.1. I2C Bus Interface 4.1.1. Device and Subaddresses The DRX 3960A is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the DRX 3960A device addresses. In order to allow up to three ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the DRX 3960A responds to different device addresses. A device address pair is defined as a write address and a read address. Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Due to the internal architecture of the DRX 3960A, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the DRX 3960A cannot accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line low to force the transmitter into a wait state. The maximum wait period during normal operation mode is less than 1 ms. Table 4–1: I2C Bus Device Addresses ADR_SEL Low High Left Open Mode Write Read Write Read Write Read Device address 82hex 83hex 86hex 87hex 8Ahex 8Bhex Table 4–2: I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Read/Write Write Read PORT 0000 0011 03 Write output port address WR_DRX 0001 0000 10 Write write address RD_DRX 0001 0001 11 Write read address Micronas : Software reset of DRX : Hardware error status of DRX 11 DRX 3960A ADVANCE INFORMATION 4.1.2. Description of CONTROL Register Table 4–3: CONTROL as a Write Register Name Subaddress Bit[15] (MSB) Bits[14:0] CONTROL 00hex 1 : RESET 0 : normal 0 Table 4–4: CONTROL as a Read Register Name Subaddress Bit[15] (MSB) Bit>@ BitV>@ CONTROL 00hex Reset status after last reading of CONTROL: 0 : no reset occurred 1 : reset occurred Internal hardware status: 0 : no error occurred 1 : internal error occurred not of interest Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset. 12 Micronas DRX 3960A ADVANCE INFORMATION 4.1.3. Protocol Description Write protocol S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P high low high low Read protocol S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low Write to Control or Test Registers S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low Write to Port Registers S Wait write device address Note: S = P= ACK = NAK = Wait = ACK sub-addr ACK data-byte ACK P I2C bus Start Condition from master I2C bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= DRX, light gray) or master (= controller dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from DRX indicating internal error state I2C clock line is held low, while the DRX is processing the I2C command. This waiting time is max. 1 ms 1 0 I2C_DA S P I2C_CL Fig. 4–1: I2C bus protocol (MSB first; data must be stable while clock is high) Micronas 13 DRX 3960A ADVANCE INFORMATION 4.1.4. Proposals for General DRX 3960A I2C Telegrams 4.1.4.1. Symbols daw dar < > aa dd write device address (82hex, 86hex or 8Ahex) read device address (83hex, 87hex or 8Bhex) Start Condition Stop Condition Address Byte Data Byte 4.1.4.2. Write Telegrams <daw 00 d0 00> <daw 10 aa aa dd dd> write to CONTROL register write data into DRX 4.1.4.3. Read Telegrams <daw 11 aa aa <dar dd dd> read data from DRX 4.2. List of Control Registers Table 4–5: List of Control Registers Write Register Address (hex) Bits Description Reset (hex) Output level of Ports 0 01 03 I2C Subaddress = 03hex ; Register is not readable. Output ports no [5:0] I2C Subaddress = 10hex ; Register are not readable. Standard select 00 20 [11:0] Transmission standard Level settings 10 01 [9:0] [VID_PEAK, SIF_REF, VID_AMP] Reference divider 10 10 [8:0] [for 4 MHz, 13 MHz, 20.25 MHz, 27 MHz or other REF_SW = high REF_SW = low] 10D 0CA Tuner take over point 10 12 [3:0] [0 dB ... 20 dB] 3 Equalizer Coe. 0 10 70 [9:0] Equalizer coefficient 025 Equalizer Coe. 1 10 71 [8:0] Equalizer coefficient 197 Equalizer Coe. 2 10 72 [8:0] Equalizer coefficient 0C5 Equalizer Coe. 3 10 73 [8:0] Equalizer coefficient 12E 14 Micronas DRX 3960A ADVANCE INFORMATION 4.3. List of Status Registers Table 4–6: List of Status Registers Read Register Address (hex) Bits Description I2C Subaddress = 11hex ; Register are not writable VIDEO_GAIN 10 05 [10:0] Actual gain of the video AGC TAGC_I 10 06 [11:0] Actual tuner current SIF_GAIN 10 0A [10:0] Internal actual gain of the SIF AGC CR_FREQ 10 0B [8:1] Frequency deviation referred to reference IF frequency 4.4. Description of User Registers 4.4.1. Write Register on I2C Subaddress 03hex Table 4–7: Write Register on I2C Subaddress 03hex I2C-Subaddress (hex) Function Name no Output Port Level PORT bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] Micronas Level at output port 5 Level at output port 4 Level at output port 3 Level at output port 2 Level at output port 1 Level at output port 0 15 DRX 3960A ADVANCE INFORMATION 4.4.2. Write Register on I2C Subaddress 10hex Table 4–8: Write Register on I2C Subaddress 10hex I2C-Subaddress (hex) Function Name 00 20 Standard select STANDARD_SEL Defines TV standard which is to be processed bit[15:0] 10 01 00 00hex 00 01hex 00 02hex 01 03hex 00 03hex 00 04hex 00 09hex 01 09hex 00 0Ahex 00 40hex reserved reserved M/N B (default) G D/K L L’ I FM Level settings Defines the different output levels and frequency response 16 bit[4:0]Video frequency response deviation at 5 MHz −8 −11.0 dB −7 −9.0 dB ... ... −2 −2.1 dB −1 −1.0 dB 0 0 dB 1 0.8 dB (default) 2 1.5 dB 3 2.1 dB ... ... 14 8.1 dB 15 8.3 dB VID_PEAK bit[6:5] Reference value for SIF maximum amplitude: 0 1000 mVpp(default) 1 700 mVpp 2 500 mVpp 3 350 mVpp SIF_REF bit[8:7] Reference value for video amplitude 0 2.0 V (default) 1 1.5 V 2 1.0 V 3 0.7 V VID_AMP Micronas DRX 3960A ADVANCE INFORMATION Table 4–8: Write Register on I2C Subaddress 10hex I2C-Subaddress (hex) Function Name 10 10 Reference divider setting SYN_REF The DRX 3960A is able to operate with different reference frequencies. The reference divider has to be set to the value which divides the reference frequency to 100 kHz. To prevent malfunction after POR, the default value is set for fref = 27 MHz, if the pin REF_SW is connected to VDVDD or set for fref = 20.25 MHz, if the pin REF_SW is connected to GND. bit[8:0] 10 12 External_Ref_Freq / 100 kHz 27 MHz 10Dhex 20.25 MHz CAhex 4 MHz 28hex Tuner Take Over Point (TOP) setting TOP_SET Defines the gain of the internal preamplifier to set the TOP bit[3:0] 10 70 Equalizer coefficient 0 bit[9:1] bit[0] 10 71 Micronas do not update coefficients update coefficients EQU_1 EQU_2 Coefficient Equalizer coefficient 3 bit[8:0] EQU_0 Coefficient Equalizer coefficient 2 bit[8:0] 10 73 Coefficient Update bit 0 1 Equalizer coefficient 1 bit[8:0] 10 72 Gain of Preamplifier 0 0 dB 1 1.33 dB 2 2.67 dB ... 8 10 dB (default) ... 14 18.67 dB 15 20 dB EQU_3 Coefficient 17 DRX 3960A ADVANCE INFORMATION 4.4.3. Read Register on I2C Subaddress 11hex Table 4–9: Read Register on I2C Subaddress 11hex I2C-Subaddress (hex) Function Name 10 05 Actual gain of video AGC VID_GAIN bit[10:0] 10 06 Tuner current 0.4 µA/LSB SIF_GAIN SIF gain 0.05 dB/LSB 0dB = C8hex CR_FREQ Frequency deviation10 kHz/LSB Lock bit: 1 : Carrier Recovery locked 0 : Carrier Recovery unlocked Lock Quality bit[10:0] 18 TAGC_I AFC bit[8:1] bit[0] 10 0C 0dB = C8hex Actual gain of SIF AGC bit[10:0] 10 0B 0.05 dB/LSB Actual gain of tuner AGC bit[10:0] 10 0A Video gain CR_LOCK < 080hex strong signal 080hex...700hex weak signal > 700hex no signal Micronas DRX 3960A ADVANCE INFORMATION 5. Specifications 5.1. Outline Dimensions 10 x 0.8 = 8 ± 0.1 0.17 ± 0.06 0.8 23 10 ± 0.1 0.34 ± 0.05 13.2 ± 0.2 12 44 0.8 22 34 10 x 0.8 = 8 ± 0.1 33 1 11 2.0 ± 0.1 13.2 ± 0.2 2.15 ± 0.2 10 ± 0.1 0.1 SPGS706000-5(P44)/1E Fig. 5–1: 44-Pin Plastic Metric Quad Flat Pack (PMQFP44) Weight approximately 0.4 g Dimensions in mm 5.2. Pin Connections and Short Descriptions NC = not connected, leave vacant LV = if not used, leave vacant DVSS = if not used, connect to DVSS Pin No. Pin Name Type X = obligatory; connect as described in circuit diagram AHVSS = connect to AHVSS Supply Voltage Connection Short Description (If not used) 1 AVSS_ADC X Analog ground for ADC 2 AVDD_ADC X Analog supply for ADC (+5 V) 3 ANATSTX I/O AVDD_FE8 GND Test pin 4 ANATSTY I/O AVDD_FE8 GND Test pin 5 AVDD_FE8 X 2nd analog supply for the front-end 6 AVSS_FE8 X 2nd analog ground for the front-end 7 AVSS_FE40 X 1st analog ground for the front-end 8 IFINX X IF input 9 AVDD_FE40 X 1st analog supply for the front-end (+5 V) 10 IFINY X IF input 11 AVSS_FE40 X 1st analog ground for the front-end 12 AVDD_SYN X Analog supply for synthesizer (+5 V) 13 AVSS_SYN X Analog ground for synthesizer 14 SHIELD X Shield GND Micronas IN IN IN AVDD_FE40 AVDD_FE40 19 DRX 3960A Pin No. Pin Name ADVANCE INFORMATION Type Supply Voltage Connection Short Description (If not used) 15 TEST0 IN AVDD_DAC GND Test Pin 16 TEST1 IN AVDD_DAC GND Test Pin 17 TEST2 IN AVDD_DAC GND Test Pin 18 CVBS OUT AVDD_DAC X CVBS output 19 REF_SW IN AVDD_DAC X Reference frequency switch 20 SIF OUT AVDD_DAC X 2nd SIF output 21 AVDD_DAC X DAC supply (+5 V) 22 AVSS_DAC X DAC ground 23 TEST_EN IN DVDD GND Test enable 24 RESETQ IN DVDD X Reset 25 I2C_SDA I/O DVDD X I2C data 26 I2C_SCL I/O DVDD X I2C clock 27 DVDD_CAP X Digital supply capacitor 28 DVDD X Digital supply (+3.3 V) 29 DVSS X Digital ground 30 DVSS_CAP X Digital capacitor ground 31 PORT0 OUT DVDD LV Digital output port 32 PORT1 OUT DVDD LV Digital output port 33 TUNER_AGC OUT DVDD X Tuner AGC current output 34 PORT2 OUT DVDD LV Digital output port 35 PORT3 OUT DVDD LV Digital output port 36 PORT4 OUT DVDD LV Digital output port 37 ADR_SEL IN DVDD X Address select 38 PORT5 OUT DVDD LV Digital output port 39 DVDD_ADC X Digital supply for ADC (+3.3 V) 40 DVSS_ADC X Digital ground for ADC 41 XTAL_IN IN AVDD_ADC X Crystal oscillator 42 XTAL_OUT I/O AVDD_ADC X Crystal oscillator / external reference frequency 43 VREF AVDD_ADC X ADC reference voltage 44 SGND AVDD_ADC X ADC reference ground 20 Micronas ADVANCE INFORMATION DRX 3960A 5.3. Pin Descriptions Pin 1, AVSS_ADC − Analog ground for ADC Pin 2, AVDD_ADC − Analog supply for ADC This pin must be connected to 5 V. Pin 3, ANATSTX − Reserved for test This pin should be connected to analog ground. Pin 4, ANATSTY − Reserved for test This pin should be connected to analog ground. Pin 5, AVDD_FE8 − Analog supply for analog frontend This pin must be connected to 5 V. Pin 6, AVSS_FE8 − Analog ground for analog frontend Pin 7, AVSS_FE40 − Analog ground for IF input circuitry. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 8, IFINX − Balanced IF input X This pin must be connected to SAW output. SAW has to be placed as close as possible. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 9, AVDD_FE40 − Analog supply for IF input circuitry This pin must be connected to 5 V. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 10, IFINX − Balanced IF input Y This pin must be connected to SAW output. SAW has to be placed as close as possible. The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 11, AVSS_FE40 − Analog ground for IF input circuitry The layout of the IF input should be symmetrical with respect to AVDD_FE40. Pin 12, AVDD_SYN − Analog supply for clock synthesizer. This pin must be connected to 5 V. Pin 13, AVSS_SYN − Analog ground for clock synthesizer. Pin 14, SHIELD − Analog ground for shielding analog from digital part. Pin 15,16,17, TEST0 1 2 − Pins for factory test Micronas Pin 18, CVBS − Video output Output level is set via I2C-Bus. An appropriate video processor (e.g. VPC etc.) has to be connected to that pin. Pin 19, REF_SW− Reference frequency switch. This input defines the default setting of the reference divider after POR. For 20.25 MHz applications it has to be connected to ground, for applications with higher frequencies than 20.25 MHz it must be connected to 3.3 V. Pin 20, SIF − 2nd sound IF ouput Output level is set via I2C-Bus. An appropriate sound processor (e.g. MSP) has to be connected to that pin. Pin 21, AVDD_DAC − Analog supply for the analog output DACs This pin must be connected to 5 V. Pin 22, AVSS_DAC − Analog Ground for the analog output DACs This pin must be connected to ground. Pin 23, TEST_EN − Test Enable pin This pin enables factory test modes. For normal operation it must be connected to ground. Pin 24, RESET − Reset input For normal operation, a high level is required. A low level resets the DRX 3960A. Pin 25, 26, I2C_SDA, I2C_SCL− I2C control bus data and clock Pin 27, DVDD_CAP − Digital supply pin This pin has to be connected to 3.3 V according to the application circuit. Pin 28, DVDD − Digital supply pin This pin has to be connected to 3.3 V according to the application circuit. Pin 29, DVSS − Digital ground pin This pin has to be connected to digital ground according to the application circuit. Pin 30, DVSS_CAP − Digital ground pin This pin has to be connected according to the application circuit. Pin 31, 32, 34, 35, 36, 38, PORT0 1 2 3 4 5 − General purpose output ports Their states are controlled via I2C bus. Pin 33, TUNER_AGC − This pin controls the delayed tuner AGC. As it is a noise-shaped-I-DAC output, it has to be connected according to the application circuit. 21 DRX 3960A Pin 37, ADR_SEL − I2C Bus address select By means of this pin, one of three device addresses can be selected. ADVANCE INFORMATION 5.4. Pin Configuration DVDD Pin 39, DVDD_ADC − Digital supply pin for ADC This pin has to be connected to 3.3 V. DVSS DVDD_CAP DVSS_CAP I2C_SCL PORT0 Pin 40, DVSS_ADC − Digital ground pin for ADC. This pin has to be connected to digital ground. Pin 41, XTAL_IN − Crystal input pin If an external clock is used this pin should be left open. A crystal should be placed as close as possible to this pin. External capacitors at each crystal pin to ground are required. It should be verified by layout, that no supply current is flowing through the ground connection point. Pin 42, XTAL_OUT − Crystal output pin If an external clock is used, it has to be connected to this pin. A crystal should be placed as close as possible to this pin. External capacitors at each crystal pin to ground are required. It should be verified by layout, that no supply current is flowing through the ground connection point. I2C_SDA PORT1 RESETQ TUNER_AGC TEST_EN 33 32 31 30 29 28 27 26 25 24 23 PORT2 34 22 AVSS_DAC PORT3 35 21 AVDD_DAC PORT4 36 20 SIF ADR_SEL 37 19 REF_SW PORT5 38 18 CVBS DVDD_ADC 39 17 TEST2 DVSS_ADC 40 16 TEST1 XTAL_IN 41 15 TEST0 XTAL_OUT 42 14 SHIELD VREF 43 13 AVSS_SYN SGND 44 12 AVDD_SYN DRX 3960A 1 2 3 4 5 6 7 8 9 AVSS_ADC AVSS_FE40 AVDD_ADC IFINY AVDD_FE40 ANATSTX Pin 43, VREF − Analog reference voltage This pin must be connected to SGND via a circuitry according to the application circuit. Pin 43, SGND − Reference for analog ground This pin must be connected separately to a single ground point. 22 10 11 ANATSTY IFINX AVDD_FE8 AVSS_FE40 AVSS_FE8 Fig. 5–2: 44-pin PMQFP package Micronas DRX 3960A ADVANCE INFORMATION 5.5. Electrical Characteristics 5.5.1. Absolute Maximum Ratings Symbol Parameter TA Min. Max. Unit Ambient Operating Temperature 0 70 °C PTOT Maximum Power Dissipation – 833 mW TS Storage Temperature –40 125 °C VSUPmax Supply Voltage, all Supply Inputs –0.3 6 V Vmax External Voltage, all VASUP Pins, (without TUNER_AGC) –0.3 VASUP+0.3 V External Voltage, all VDSUP Pins –0.3 VDSUP+0.3 V VSUP-tun Pin Name External Voltage, I2C I2C_SDA I2C_SCL −0.3 6 V TUNER_AGC Voltage TUNER_AGC – 8 V Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 5.5.2. Recommended Operating Conditions Symbol Parameter Pin Name Min. Typ. Max. Unit VASUP Voltage, Analog Supply Pins AVDD_ADC AVDD_FE8 AVDD_FE40 AVDD_SYN AVDD_DAC 4.75 5.0 5.25 V VDSUP Voltage, Digital Supply Pins DVDD DVDD_CAP 3.0 3.3 3.6 V VDSUP_ADC Voltage, Digital Supply Pins, ADC DVDD_ADC 3.0 3.3 3.6 V Vext_I2C External Voltage I2C I2C_SDA I2C_SCL 0.0 – 5.5 V fXTAL Clock Frequency XTAL_IN/ OUT – 20.25 – MHz fexternal External Clock Frequency Range XTAL_IN 1 20.25 30 MHz fssbnoise SSB-Phase noise of External Clock Frequency fratio = 20*Log10 (40.5 MHz/fexternal) XTAL_IN –90 fratio dBc fm = 1 kHz The values given under “Characteristics” are valid for these “Recommended Operating Conditions”. Micronas 23 DRX 3960A ADVANCE INFORMATION 5.5.3. Recommended Crystal Characteristics Symbol Parameter Min. Typ. Max. Unit TA Operating Ambient Temperature 0 – 70 °C fP Parallel Resonance Frequency with Load Capacitance CL = 13 pF – 20.250000 – MHz ∆fP/fP Accuracy of Adjustment – – ±100 ppm ∆fP/fP Frequency Temperature Drift – – ±30 ppm RR Series Resistance – – 25 Ω C0 Shunt Capacitance 3 – 7 pF Typ. Max. Unit 5.5.4. Recommended Tuner Characteristics Symbol Parameter Min. atuner Minimum Gain Control Range 40 Stuner AGC Control Voltage Sensitivity dB 50 dB/V 5.6. Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Supply Idig Current Consumption, digital 60 mA Iana Current Consumption, analog 110 mA Ptot Total Power Consumption 750 mW Digital Input Levels VDIGIL Digital Input Low Voltage VDIGIH Digital Input High Voltage ZDIGI Input Impedance IDLEAK Digital Input Leakage Current VDIGIL Digital Input Low Voltage VDIGIH Digital Input High Voltage 0.8 IADRSEL Input Current Address Select Pin −500 TEST_EN REF_SW 0.2 0.8 VDVDD −1 ADR_SEL 5 pF 1 µA 0.2 VDVDD 0 V < VINPUT< VDVDD VDVDD −220 220 24 VDVDD 500 µA VADR_SEL= VDVSS µA VADR_SEL= VDVDD Micronas DRX 3960A ADVANCE INFORMATION Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions 0.4 V IPORT = 1.6 mA V IPORT = −1.6 mA Digital Output Levels VPORTL Digital Output Low Voltage VPORTH Digital Output High Voltage VDVDD 0.4 IPORT Digital Output Current −2 PORT 0, 1, 2, 3, 4, 5 2 mA Reset VRHL Reset High Low transition RESET 1.1 V VRLH Reset Low High transition RESET 2.1 V VI2CIL I2C-Bus Input Low Voltage I2C_CL, I2C_DA VI2CIH I2C-Bus Input High Voltage 0.6 VDVDD tI2C1 I2C Start Condition Setup Time 120 ns tI2C2 I2C Stop Condition Setup Time 120 ns tI2C5 I2C-Data Setup Time before Rising Edge of Clock 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns tI2C3 I2C-Clock Low Pulse Time 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns fI2C I2C-Bus Frequency VI2COL I2C-Data Output Low Voltage II2COH I2C-Data Output High Leakage Current tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns I2C-Bus I2C_CL 0.3 I2C_CL, I2C_DA VDVDD 1.0 MHz 0.4 V II2COL = 3 mA 1.0 µA VI2COH = 5 V fI2C = 1 MHz IF Input Differential Input Impedance R C IFINX, IFINY fin Input Frequency IFINX, IFINY Vwanted Maximum wanted Signal Input Voltage TOP = 0 IFINX, IFINY Zin TOP = 15 SIF Micronas Sensitivity (S/N unweighted = 26 dB) IFINX, IFINY 1.6 1 2 2.4 4 kΩ pF 38.9 47 MHz FS 200 97 mVpp dBuV 20 77 mVpp dBuV 1 mV fin = 38.9 MHz, TOP gain = 10 dB 25 DRX 3960A Symbol Parameter ADVANCE INFORMATION Pin Name Min. Typ. Max. Unit Test Conditions Low Noise Preamplifier (with Tuner Take Over Point Setting) TOPmin Minimum Gain 0 dB TOPmax Maximum Gain 20 dB TOPstep Stepsize of Gain 1.33 dB Analog Front-end Gtol Total Gain Tolerance ±1 dB 50 kHz matched inputs Carrier Recovery DAFC Frequency Tolerance = AFC Accuracy flock Lock in range = frequency true demodulation range 0.8 1.0 MHz MHz direction: adjacent channel direction: own channel VIF AGC fVAGC Control Bandwidth BWn negative modulation 200 Hz BWp positive modulation 1 Hz BWpinc positive modulation increasing signal (white picture) 200 Hz BWbp positive modulation back porch control 200 Hz Tuner AGC, Current Output ITAGC Maximum Output Sink Current Vsup_tun Maximum Output Voltage TUNER_ AGC 680 800 920 µA 8 V 90 % FS Video Output Vsync Sync Level (minimum DAC value) Vvidmax CVBS 1.2 1.4 1.6 V Maximum Level (maximum DAC value) 3.8 2.9 2.4 2.0 4.0 3.3 2.7 2.3 4.2 3.7 3.0 2.6 V @ VID_AMP=0 @ VID_AMP=1 @ VID_AMP=2 @ VID_AMP=3 Vvidpp Full Scale Voltage 2.4 1.7 1.2 0.8 2.6 1.9 1.3 0.9 2.8 2.1 1.4 1.0 Vpp @ VID_AMP=0 @ VID_AMP=1 @ VID_AMP=2 @ VID_AMP=3 f-1dBvid Cutoff Frequency 6 MHz CLoad < 30 pF, RLoad_AC > 1 kΩ Routvid Output Resistance Ω f < 6 MHz SNRvidw Weighted Video S/N 56 58 dB Weighted video S/N (CCIR567, 10 kHz...5 MHz) SNRvidu Unweighted Video S/N 49 51 dB Unweighted video S/N (10 kHz...5 MHz) α1.07 Intermodulation ratio 65 dB blue picture, PSC1=-13dB, no sound shelf 50 α1.07= PCC-P1.07 +3dB 26 Micronas DRX 3960A ADVANCE INFORMATION Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Vpp @ SIF_REF=0 @ SIF_REF=1 @ SIF_REF=2 @ SIF_REF=3 MHz CLoad < 30 pF, RLoad_AC > 1 kΩ Ω f < 6 MHz Sound IF Output Vsifpp Full Scale Voltage f-1dBsif Cutoff Frequency f-1dB Routsif Output Resistance SNRb Weighted Sound S/N SC1/SC2 62/58 dB black picture, CCIR 468 SNRw Weighted Sound S/N SC1/SC2 62/58 dB white picture, CCIR 468 SNRfubk Weighted Sound S/N SC1/SC2 55/50 dB FuBK picture, CCIR 468 Micronas SIF 1.5 1.1 0.8 0.6 6 50 27 DRX 3960A ADVANCE INFORMATION 6. Application Circuit REF_SW 28 Micronas ADVANCE INFORMATION Micronas DRX 3960A 29 DRX 3960A ADVANCE INFORMATION 7. Data Sheet History 1. Advance Information: “DRX 3960A Digital Receiver Front-end”, Aug. 10, 2000, 6251-510-1AI. First release of the advance information. 2. Advance Information: “DRX 3960A Digital Receiver Front-end”, Feb. 8, 2001, 6251-510-2AI. Second release of the advance information. Major changes: – reduction of front-end gain – positive detection bit removed – output level setting changed – lock detection bit added Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: [email protected] Internet: www.micronas.com Printed in Germany Order No. 6251-510-2AI 30 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH. Micronas